arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  14 #include <dt-bindings/interconnect/qcom,sdm845.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  20 #include <dt-bindings/soc/qcom,apr.h>
  21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  22 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         aliases {
  32                 i2c0 = &i2c0;
  33                 i2c1 = &i2c1;
  34                 i2c2 = &i2c2;
  35                 i2c3 = &i2c3;
  36                 i2c4 = &i2c4;
  37                 i2c5 = &i2c5;
  38                 i2c6 = &i2c6;
  39                 i2c7 = &i2c7;
  40                 i2c8 = &i2c8;
  41                 i2c9 = &i2c9;
  42                 i2c10 = &i2c10;
  43                 i2c11 = &i2c11;
  44                 i2c12 = &i2c12;
  45                 i2c13 = &i2c13;
  46                 i2c14 = &i2c14;
  47                 i2c15 = &i2c15;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi2 = &spi2;
  51                 spi3 = &spi3;
  52                 spi4 = &spi4;
  53                 spi5 = &spi5;
  54                 spi6 = &spi6;
  55                 spi7 = &spi7;
  56                 spi8 = &spi8;
  57                 spi9 = &spi9;
  58                 spi10 = &spi10;
  59                 spi11 = &spi11;
  60                 spi12 = &spi12;
  61                 spi13 = &spi13;
  62                 spi14 = &spi14;
  63                 spi15 = &spi15;
  64         };
  65
  66         chosen { };
  67
  68         memory@80000000 {
  69                 device_type = "memory";
  70                 /* We expect the bootloader to fill in the size */
  71                 reg = <0 0x80000000 0 0>;
  72         };
  73
  74         reserved-memory {
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 ranges;
  78
  79                 hyp_mem: memory@85700000 {
  80                         reg = <0 0x85700000 0 0x600000>;
  81                         no-map;
  82                 };
  83
  84                 xbl_mem: memory@85e00000 {
  85                         reg = <0 0x85e00000 0 0x100000>;
  86                         no-map;
  87                 };
  88
  89                 aop_mem: memory@85fc0000 {
  90                         reg = <0 0x85fc0000 0 0x20000>;
  91                         no-map;
  92                 };
  93
  94                 aop_cmd_db_mem: memory@85fe0000 {
  95                         compatible = "qcom,cmd-db";
  96                         reg = <0x0 0x85fe0000 0 0x20000>;
  97                         no-map;
  98                 };
  99
 100                 smem_mem: memory@86000000 {
 101                         reg = <0x0 0x86000000 0 0x200000>;
 102                         no-map;
 103                 };
 104
 105                 tz_mem: memory@86200000 {
 106                         reg = <0 0x86200000 0 0x2d00000>;
 107                         no-map;
 108                 };
 109
 110                 rmtfs_mem: memory@88f00000 {
 111                         compatible = "qcom,rmtfs-mem";
 112                         reg = <0 0x88f00000 0 0x200000>;
 113                         no-map;
 114
 115                         qcom,client-id = <1>;
 116                         qcom,vmid = <15>;
 117                 };
 118
 119                 qseecom_mem: memory@8ab00000 {
 120                         reg = <0 0x8ab00000 0 0x1400000>;
 121                         no-map;
 122                 };
 123
 124                 camera_mem: memory@8bf00000 {
 125                         reg = <0 0x8bf00000 0 0x500000>;
 126                         no-map;
 127                 };
 128
 129                 ipa_fw_mem: memory@8c400000 {
 130                         reg = <0 0x8c400000 0 0x10000>;
 131                         no-map;
 132                 };
 133
 134                 ipa_gsi_mem: memory@8c410000 {
 135                         reg = <0 0x8c410000 0 0x5000>;
 136                         no-map;
 137                 };
 138
 139                 gpu_mem: memory@8c415000 {
 140                         reg = <0 0x8c415000 0 0x2000>;
 141                         no-map;
 142                 };
 143
 144                 adsp_mem: memory@8c500000 {
 145                         reg = <0 0x8c500000 0 0x1a00000>;
 146                         no-map;
 147                 };
 148
 149                 wlan_msa_mem: memory@8df00000 {
 150                         reg = <0 0x8df00000 0 0x100000>;
 151                         no-map;
 152                 };
 153
 154                 mpss_region: memory@8e000000 {
 155                         reg = <0 0x8e000000 0 0x7800000>;
 156                         no-map;
 157                 };
 158
 159                 venus_mem: memory@95800000 {
 160                         reg = <0 0x95800000 0 0x500000>;
 161                         no-map;
 162                 };
 163
 164                 cdsp_mem: memory@95d00000 {
 165                         reg = <0 0x95d00000 0 0x800000>;
 166                         no-map;
 167                 };
 168
 169                 mba_region: memory@96500000 {
 170                         reg = <0 0x96500000 0 0x200000>;
 171                         no-map;
 172                 };
 173
 174                 slpi_mem: memory@96700000 {
 175                         reg = <0 0x96700000 0 0x1400000>;
 176                         no-map;
 177                 };
 178
 179                 spss_mem: memory@97b00000 {
 180                         reg = <0 0x97b00000 0 0x100000>;
 181                         no-map;
 182                 };
 183         };
 184
 185         cpus {
 186                 #address-cells = <2>;
 187                 #size-cells = <0>;
 188
 189                 CPU0: cpu@0 {
 190                         device_type = "cpu";
 191                         compatible = "qcom,kryo385";
 192                         reg = <0x0 0x0>;
 193                         enable-method = "psci";
 194                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 195                                            &LITTLE_CPU_SLEEP_1
 196                                            &CLUSTER_SLEEP_0>;
 197                         capacity-dmips-mhz = <607>;
 198                         dynamic-power-coefficient = <100>;
 199                         qcom,freq-domain = <&cpufreq_hw 0>;
 200                         #cooling-cells = <2>;
 201                         next-level-cache = <&L2_0>;
 202                         L2_0: l2-cache {
 203                                 compatible = "cache";
 204                                 next-level-cache = <&L3_0>;
 205                                 L3_0: l3-cache {
 206                                       compatible = "cache";
 207                                 };
 208                         };
 209                 };
 210
 211                 CPU1: cpu@100 {
 212                         device_type = "cpu";
 213                         compatible = "qcom,kryo385";
 214                         reg = <0x0 0x100>;
 215                         enable-method = "psci";
 216                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 217                                            &LITTLE_CPU_SLEEP_1
 218                                            &CLUSTER_SLEEP_0>;
 219                         capacity-dmips-mhz = <607>;
 220                         dynamic-power-coefficient = <100>;
 221                         qcom,freq-domain = <&cpufreq_hw 0>;
 222                         #cooling-cells = <2>;
 223                         next-level-cache = <&L2_100>;
 224                         L2_100: l2-cache {
 225                                 compatible = "cache";
 226                                 next-level-cache = <&L3_0>;
 227                         };
 228                 };
 229
 230                 CPU2: cpu@200 {
 231                         device_type = "cpu";
 232                         compatible = "qcom,kryo385";
 233                         reg = <0x0 0x200>;
 234                         enable-method = "psci";
 235                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 236                                            &LITTLE_CPU_SLEEP_1
 237                                            &CLUSTER_SLEEP_0>;
 238                         capacity-dmips-mhz = <607>;
 239                         dynamic-power-coefficient = <100>;
 240                         qcom,freq-domain = <&cpufreq_hw 0>;
 241                         #cooling-cells = <2>;
 242                         next-level-cache = <&L2_200>;
 243                         L2_200: l2-cache {
 244                                 compatible = "cache";
 245                                 next-level-cache = <&L3_0>;
 246                         };
 247                 };
 248
 249                 CPU3: cpu@300 {
 250                         device_type = "cpu";
 251                         compatible = "qcom,kryo385";
 252                         reg = <0x0 0x300>;
 253                         enable-method = "psci";
 254                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 255                                            &LITTLE_CPU_SLEEP_1
 256                                            &CLUSTER_SLEEP_0>;
 257                         capacity-dmips-mhz = <607>;
 258                         dynamic-power-coefficient = <100>;
 259                         qcom,freq-domain = <&cpufreq_hw 0>;
 260                         #cooling-cells = <2>;
 261                         next-level-cache = <&L2_300>;
 262                         L2_300: l2-cache {
 263                                 compatible = "cache";
 264                                 next-level-cache = <&L3_0>;
 265                         };
 266                 };
 267
 268                 CPU4: cpu@400 {
 269                         device_type = "cpu";
 270                         compatible = "qcom,kryo385";
 271                         reg = <0x0 0x400>;
 272                         enable-method = "psci";
 273                         capacity-dmips-mhz = <1024>;
 274                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 275                                            &BIG_CPU_SLEEP_1
 276                                            &CLUSTER_SLEEP_0>;
 277                         dynamic-power-coefficient = <396>;
 278                         qcom,freq-domain = <&cpufreq_hw 1>;
 279                         #cooling-cells = <2>;
 280                         next-level-cache = <&L2_400>;
 281                         L2_400: l2-cache {
 282                                 compatible = "cache";
 283                                 next-level-cache = <&L3_0>;
 284                         };
 285                 };
 286
 287                 CPU5: cpu@500 {
 288                         device_type = "cpu";
 289                         compatible = "qcom,kryo385";
 290                         reg = <0x0 0x500>;
 291                         enable-method = "psci";
 292                         capacity-dmips-mhz = <1024>;
 293                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 294                                            &BIG_CPU_SLEEP_1
 295                                            &CLUSTER_SLEEP_0>;
 296                         dynamic-power-coefficient = <396>;
 297                         qcom,freq-domain = <&cpufreq_hw 1>;
 298                         #cooling-cells = <2>;
 299                         next-level-cache = <&L2_500>;
 300                         L2_500: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 CPU6: cpu@600 {
 307                         device_type = "cpu";
 308                         compatible = "qcom,kryo385";
 309                         reg = <0x0 0x600>;
 310                         enable-method = "psci";
 311                         capacity-dmips-mhz = <1024>;
 312                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 313                                            &BIG_CPU_SLEEP_1
 314                                            &CLUSTER_SLEEP_0>;
 315                         dynamic-power-coefficient = <396>;
 316                         qcom,freq-domain = <&cpufreq_hw 1>;
 317                         #cooling-cells = <2>;
 318                         next-level-cache = <&L2_600>;
 319                         L2_600: l2-cache {
 320                                 compatible = "cache";
 321                                 next-level-cache = <&L3_0>;
 322                         };
 323                 };
 324
 325                 CPU7: cpu@700 {
 326                         device_type = "cpu";
 327                         compatible = "qcom,kryo385";
 328                         reg = <0x0 0x700>;
 329                         enable-method = "psci";
 330                         capacity-dmips-mhz = <1024>;
 331                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 332                                            &BIG_CPU_SLEEP_1
 333                                            &CLUSTER_SLEEP_0>;
 334                         dynamic-power-coefficient = <396>;
 335                         qcom,freq-domain = <&cpufreq_hw 1>;
 336                         #cooling-cells = <2>;
 337                         next-level-cache = <&L2_700>;
 338                         L2_700: l2-cache {
 339                                 compatible = "cache";
 340                                 next-level-cache = <&L3_0>;
 341                         };
 342                 };
 343
 344                 cpu-map {
 345                         cluster0 {
 346                                 core0 {
 347                                         cpu = <&CPU0>;
 348                                 };
 349
 350                                 core1 {
 351                                         cpu = <&CPU1>;
 352                                 };
 353
 354                                 core2 {
 355                                         cpu = <&CPU2>;
 356                                 };
 357
 358                                 core3 {
 359                                         cpu = <&CPU3>;
 360                                 };
 361
 362                                 core4 {
 363                                         cpu = <&CPU4>;
 364                                 };
 365
 366                                 core5 {
 367                                         cpu = <&CPU5>;
 368                                 };
 369
 370                                 core6 {
 371                                         cpu = <&CPU6>;
 372                                 };
 373
 374                                 core7 {
 375                                         cpu = <&CPU7>;
 376                                 };
 377                         };
 378                 };
 379
 380                 idle-states {
 381                         entry-method = "psci";
 382
 383                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 384                                 compatible = "arm,idle-state";
 385                                 idle-state-name = "little-power-down";
 386                                 arm,psci-suspend-param = <0x40000003>;
 387                                 entry-latency-us = <350>;
 388                                 exit-latency-us = <461>;
 389                                 min-residency-us = <1890>;
 390                                 local-timer-stop;
 391                         };
 392
 393                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 394                                 compatible = "arm,idle-state";
 395                                 idle-state-name = "little-rail-power-down";
 396                                 arm,psci-suspend-param = <0x40000004>;
 397                                 entry-latency-us = <360>;
 398                                 exit-latency-us = <531>;
 399                                 min-residency-us = <3934>;
 400                                 local-timer-stop;
 401                         };
 402
 403                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 404                                 compatible = "arm,idle-state";
 405                                 idle-state-name = "big-power-down";
 406                                 arm,psci-suspend-param = <0x40000003>;
 407                                 entry-latency-us = <264>;
 408                                 exit-latency-us = <621>;
 409                                 min-residency-us = <952>;
 410                                 local-timer-stop;
 411                         };
 412
 413                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 414                                 compatible = "arm,idle-state";
 415                                 idle-state-name = "big-rail-power-down";
 416                                 arm,psci-suspend-param = <0x40000004>;
 417                                 entry-latency-us = <702>;
 418                                 exit-latency-us = <1061>;
 419                                 min-residency-us = <4488>;
 420                                 local-timer-stop;
 421                         };
 422
 423                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 424                                 compatible = "arm,idle-state";
 425                                 idle-state-name = "cluster-power-down";
 426                                 arm,psci-suspend-param = <0x400000F4>;
 427                                 entry-latency-us = <3263>;
 428                                 exit-latency-us = <6562>;
 429                                 min-residency-us = <9987>;
 430                                 local-timer-stop;
 431                         };
 432                 };
 433         };
 434
 435         pmu {
 436                 compatible = "arm,armv8-pmuv3";
 437                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 438         };
 439
 440         timer {
 441                 compatible = "arm,armv8-timer";
 442                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 443                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 444                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 445                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 446         };
 447
 448         clocks {
 449                 xo_board: xo-board {
 450                         compatible = "fixed-clock";
 451                         #clock-cells = <0>;
 452                         clock-frequency = <38400000>;
 453                         clock-output-names = "xo_board";
 454                 };
 455
 456                 sleep_clk: sleep-clk {
 457                         compatible = "fixed-clock";
 458                         #clock-cells = <0>;
 459                         clock-frequency = <32764>;
 460                 };
 461         };
 462
 463         firmware {
 464                 scm {
 465                         compatible = "qcom,scm-sdm845", "qcom,scm";
 466                 };
 467         };
 468
 469         adsp_pas: remoteproc-adsp {
 470                 compatible = "qcom,sdm845-adsp-pas";
 471
 472                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 473                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 474                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 475                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 476                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 477                 interrupt-names = "wdog", "fatal", "ready",
 478                                   "handover", "stop-ack";
 479
 480                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 481                 clock-names = "xo";
 482
 483                 memory-region = <&adsp_mem>;
 484
 485                 qcom,smem-states = <&adsp_smp2p_out 0>;
 486                 qcom,smem-state-names = "stop";
 487
 488                 status = "disabled";
 489
 490                 glink-edge {
 491                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 492                         label = "lpass";
 493                         qcom,remote-pid = <2>;
 494                         mboxes = <&apss_shared 8>;
 495
 496                         apr {
 497                                 compatible = "qcom,apr-v2";
 498                                 qcom,glink-channels = "apr_audio_svc";
 499                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
 500                                 #address-cells = <1>;
 501                                 #size-cells = <0>;
 502                                 qcom,intents = <512 20>;
 503
 504                                 apr-service@3 {
 505                                         reg = <APR_SVC_ADSP_CORE>;
 506                                         compatible = "qcom,q6core";
 507                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 508                                 };
 509
 510                                 q6afe: apr-service@4 {
 511                                         compatible = "qcom,q6afe";
 512                                         reg = <APR_SVC_AFE>;
 513                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 514                                         q6afedai: dais {
 515                                                 compatible = "qcom,q6afe-dais";
 516                                                 #address-cells = <1>;
 517                                                 #size-cells = <0>;
 518                                                 #sound-dai-cells = <1>;
 519                                         };
 520                                 };
 521
 522                                 q6asm: apr-service@7 {
 523                                         compatible = "qcom,q6asm";
 524                                         reg = <APR_SVC_ASM>;
 525                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 526                                         q6asmdai: dais {
 527                                                 compatible = "qcom,q6asm-dais";
 528                                                 #address-cells = <1>;
 529                                                 #size-cells = <0>;
 530                                                 #sound-dai-cells = <1>;
 531                                                 iommus = <&apps_smmu 0x1821 0x0>;
 532                                         };
 533                                 };
 534
 535                                 q6adm: apr-service@8 {
 536                                         compatible = "qcom,q6adm";
 537                                         reg = <APR_SVC_ADM>;
 538                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 539                                         q6routing: routing {
 540                                                 compatible = "qcom,q6adm-routing";
 541                                                 #sound-dai-cells = <0>;
 542                                         };
 543                                 };
 544                         };
 545
 546                         fastrpc {
 547                                 compatible = "qcom,fastrpc";
 548                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 549                                 label = "adsp";
 550                                 #address-cells = <1>;
 551                                 #size-cells = <0>;
 552
 553                                 compute-cb@3 {
 554                                         compatible = "qcom,fastrpc-compute-cb";
 555                                         reg = <3>;
 556                                         iommus = <&apps_smmu 0x1823 0x0>;
 557                                 };
 558
 559                                 compute-cb@4 {
 560                                         compatible = "qcom,fastrpc-compute-cb";
 561                                         reg = <4>;
 562                                         iommus = <&apps_smmu 0x1824 0x0>;
 563                                 };
 564                         };
 565                 };
 566         };
 567
 568         cdsp_pas: remoteproc-cdsp {
 569                 compatible = "qcom,sdm845-cdsp-pas";
 570
 571                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 572                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 573                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 574                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 575                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 576                 interrupt-names = "wdog", "fatal", "ready",
 577                                   "handover", "stop-ack";
 578
 579                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 580                 clock-names = "xo";
 581
 582                 memory-region = <&cdsp_mem>;
 583
 584                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 585                 qcom,smem-state-names = "stop";
 586
 587                 status = "disabled";
 588
 589                 glink-edge {
 590                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 591                         label = "turing";
 592                         qcom,remote-pid = <5>;
 593                         mboxes = <&apss_shared 4>;
 594                         fastrpc {
 595                                 compatible = "qcom,fastrpc";
 596                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 597                                 label = "cdsp";
 598                                 #address-cells = <1>;
 599                                 #size-cells = <0>;
 600
 601                                 compute-cb@1 {
 602                                         compatible = "qcom,fastrpc-compute-cb";
 603                                         reg = <1>;
 604                                         iommus = <&apps_smmu 0x1401 0x30>;
 605                                 };
 606
 607                                 compute-cb@2 {
 608                                         compatible = "qcom,fastrpc-compute-cb";
 609                                         reg = <2>;
 610                                         iommus = <&apps_smmu 0x1402 0x30>;
 611                                 };
 612
 613                                 compute-cb@3 {
 614                                         compatible = "qcom,fastrpc-compute-cb";
 615                                         reg = <3>;
 616                                         iommus = <&apps_smmu 0x1403 0x30>;
 617                                 };
 618
 619                                 compute-cb@4 {
 620                                         compatible = "qcom,fastrpc-compute-cb";
 621                                         reg = <4>;
 622                                         iommus = <&apps_smmu 0x1404 0x30>;
 623                                 };
 624
 625                                 compute-cb@5 {
 626                                         compatible = "qcom,fastrpc-compute-cb";
 627                                         reg = <5>;
 628                                         iommus = <&apps_smmu 0x1405 0x30>;
 629                                 };
 630
 631                                 compute-cb@6 {
 632                                         compatible = "qcom,fastrpc-compute-cb";
 633                                         reg = <6>;
 634                                         iommus = <&apps_smmu 0x1406 0x30>;
 635                                 };
 636
 637                                 compute-cb@7 {
 638                                         compatible = "qcom,fastrpc-compute-cb";
 639                                         reg = <7>;
 640                                         iommus = <&apps_smmu 0x1407 0x30>;
 641                                 };
 642
 643                                 compute-cb@8 {
 644                                         compatible = "qcom,fastrpc-compute-cb";
 645                                         reg = <8>;
 646                                         iommus = <&apps_smmu 0x1408 0x30>;
 647                                 };
 648                         };
 649                 };
 650         };
 651
 652         tcsr_mutex: hwlock {
 653                 compatible = "qcom,tcsr-mutex";
 654                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 655                 #hwlock-cells = <1>;
 656         };
 657
 658         smem {
 659                 compatible = "qcom,smem";
 660                 memory-region = <&smem_mem>;
 661                 hwlocks = <&tcsr_mutex 3>;
 662         };
 663
 664         smp2p-cdsp {
 665                 compatible = "qcom,smp2p";
 666                 qcom,smem = <94>, <432>;
 667
 668                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 669
 670                 mboxes = <&apss_shared 6>;
 671
 672                 qcom,local-pid = <0>;
 673                 qcom,remote-pid = <5>;
 674
 675                 cdsp_smp2p_out: master-kernel {
 676                         qcom,entry-name = "master-kernel";
 677                         #qcom,smem-state-cells = <1>;
 678                 };
 679
 680                 cdsp_smp2p_in: slave-kernel {
 681                         qcom,entry-name = "slave-kernel";
 682
 683                         interrupt-controller;
 684                         #interrupt-cells = <2>;
 685                 };
 686         };
 687
 688         smp2p-lpass {
 689                 compatible = "qcom,smp2p";
 690                 qcom,smem = <443>, <429>;
 691
 692                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 693
 694                 mboxes = <&apss_shared 10>;
 695
 696                 qcom,local-pid = <0>;
 697                 qcom,remote-pid = <2>;
 698
 699                 adsp_smp2p_out: master-kernel {
 700                         qcom,entry-name = "master-kernel";
 701                         #qcom,smem-state-cells = <1>;
 702                 };
 703
 704                 adsp_smp2p_in: slave-kernel {
 705                         qcom,entry-name = "slave-kernel";
 706
 707                         interrupt-controller;
 708                         #interrupt-cells = <2>;
 709                 };
 710         };
 711
 712         smp2p-mpss {
 713                 compatible = "qcom,smp2p";
 714                 qcom,smem = <435>, <428>;
 715                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 716                 mboxes = <&apss_shared 14>;
 717                 qcom,local-pid = <0>;
 718                 qcom,remote-pid = <1>;
 719
 720                 modem_smp2p_out: master-kernel {
 721                         qcom,entry-name = "master-kernel";
 722                         #qcom,smem-state-cells = <1>;
 723                 };
 724
 725                 modem_smp2p_in: slave-kernel {
 726                         qcom,entry-name = "slave-kernel";
 727                         interrupt-controller;
 728                         #interrupt-cells = <2>;
 729                 };
 730         };
 731
 732         smp2p-slpi {
 733                 compatible = "qcom,smp2p";
 734                 qcom,smem = <481>, <430>;
 735                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 736                 mboxes = <&apss_shared 26>;
 737                 qcom,local-pid = <0>;
 738                 qcom,remote-pid = <3>;
 739
 740                 slpi_smp2p_out: master-kernel {
 741                         qcom,entry-name = "master-kernel";
 742                         #qcom,smem-state-cells = <1>;
 743                 };
 744
 745                 slpi_smp2p_in: slave-kernel {
 746                         qcom,entry-name = "slave-kernel";
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749                 };
 750         };
 751
 752         psci {
 753                 compatible = "arm,psci-1.0";
 754                 method = "smc";
 755         };
 756
 757         soc: soc@0 {
 758                 #address-cells = <2>;
 759                 #size-cells = <2>;
 760                 ranges = <0 0 0 0 0x10 0>;
 761                 dma-ranges = <0 0 0 0 0x10 0>;
 762                 compatible = "simple-bus";
 763
 764                 gcc: clock-controller@100000 {
 765                         compatible = "qcom,gcc-sdm845";
 766                         reg = <0 0x00100000 0 0x1f0000>;
 767                         #clock-cells = <1>;
 768                         #reset-cells = <1>;
 769                         #power-domain-cells = <1>;
 770                 };
 771
 772                 qfprom@784000 {
 773                         compatible = "qcom,qfprom";
 774                         reg = <0 0x00784000 0 0x8ff>;
 775                         #address-cells = <1>;
 776                         #size-cells = <1>;
 777
 778                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
 779                                 reg = <0x1eb 0x1>;
 780                                 bits = <1 4>;
 781                         };
 782
 783                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
 784                                 reg = <0x1eb 0x2>;
 785                                 bits = <6 4>;
 786                         };
 787                 };
 788
 789                 rng: rng@793000 {
 790                         compatible = "qcom,prng-ee";
 791                         reg = <0 0x00793000 0 0x1000>;
 792                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 793                         clock-names = "core";
 794                 };
 795
 796                 qupv3_id_0: geniqup@8c0000 {
 797                         compatible = "qcom,geni-se-qup";
 798                         reg = <0 0x008c0000 0 0x6000>;
 799                         clock-names = "m-ahb", "s-ahb";
 800                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 801                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 802                         #address-cells = <2>;
 803                         #size-cells = <2>;
 804                         ranges;
 805                         status = "disabled";
 806
 807                         i2c0: i2c@880000 {
 808                                 compatible = "qcom,geni-i2c";
 809                                 reg = <0 0x00880000 0 0x4000>;
 810                                 clock-names = "se";
 811                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 812                                 pinctrl-names = "default";
 813                                 pinctrl-0 = <&qup_i2c0_default>;
 814                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 815                                 #address-cells = <1>;
 816                                 #size-cells = <0>;
 817                                 status = "disabled";
 818                         };
 819
 820                         spi0: spi@880000 {
 821                                 compatible = "qcom,geni-spi";
 822                                 reg = <0 0x00880000 0 0x4000>;
 823                                 clock-names = "se";
 824                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 825                                 pinctrl-names = "default";
 826                                 pinctrl-0 = <&qup_spi0_default>;
 827                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 828                                 #address-cells = <1>;
 829                                 #size-cells = <0>;
 830                                 status = "disabled";
 831                         };
 832
 833                         uart0: serial@880000 {
 834                                 compatible = "qcom,geni-uart";
 835                                 reg = <0 0x00880000 0 0x4000>;
 836                                 clock-names = "se";
 837                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 838                                 pinctrl-names = "default";
 839                                 pinctrl-0 = <&qup_uart0_default>;
 840                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 841                                 status = "disabled";
 842                         };
 843
 844                         i2c1: i2c@884000 {
 845                                 compatible = "qcom,geni-i2c";
 846                                 reg = <0 0x00884000 0 0x4000>;
 847                                 clock-names = "se";
 848                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 849                                 pinctrl-names = "default";
 850                                 pinctrl-0 = <&qup_i2c1_default>;
 851                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 852                                 #address-cells = <1>;
 853                                 #size-cells = <0>;
 854                                 status = "disabled";
 855                         };
 856
 857                         spi1: spi@884000 {
 858                                 compatible = "qcom,geni-spi";
 859                                 reg = <0 0x00884000 0 0x4000>;
 860                                 clock-names = "se";
 861                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 862                                 pinctrl-names = "default";
 863                                 pinctrl-0 = <&qup_spi1_default>;
 864                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 865                                 #address-cells = <1>;
 866                                 #size-cells = <0>;
 867                                 status = "disabled";
 868                         };
 869
 870                         uart1: serial@884000 {
 871                                 compatible = "qcom,geni-uart";
 872                                 reg = <0 0x00884000 0 0x4000>;
 873                                 clock-names = "se";
 874                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 875                                 pinctrl-names = "default";
 876                                 pinctrl-0 = <&qup_uart1_default>;
 877                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 878                                 status = "disabled";
 879                         };
 880
 881                         i2c2: i2c@888000 {
 882                                 compatible = "qcom,geni-i2c";
 883                                 reg = <0 0x00888000 0 0x4000>;
 884                                 clock-names = "se";
 885                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 886                                 pinctrl-names = "default";
 887                                 pinctrl-0 = <&qup_i2c2_default>;
 888                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 status = "disabled";
 892                         };
 893
 894                         spi2: spi@888000 {
 895                                 compatible = "qcom,geni-spi";
 896                                 reg = <0 0x00888000 0 0x4000>;
 897                                 clock-names = "se";
 898                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 899                                 pinctrl-names = "default";
 900                                 pinctrl-0 = <&qup_spi2_default>;
 901                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 status = "disabled";
 905                         };
 906
 907                         uart2: serial@888000 {
 908                                 compatible = "qcom,geni-uart";
 909                                 reg = <0 0x00888000 0 0x4000>;
 910                                 clock-names = "se";
 911                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&qup_uart2_default>;
 914                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 915                                 status = "disabled";
 916                         };
 917
 918                         i2c3: i2c@88c000 {
 919                                 compatible = "qcom,geni-i2c";
 920                                 reg = <0 0x0088c000 0 0x4000>;
 921                                 clock-names = "se";
 922                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 923                                 pinctrl-names = "default";
 924                                 pinctrl-0 = <&qup_i2c3_default>;
 925                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 926                                 #address-cells = <1>;
 927                                 #size-cells = <0>;
 928                                 status = "disabled";
 929                         };
 930
 931                         spi3: spi@88c000 {
 932                                 compatible = "qcom,geni-spi";
 933                                 reg = <0 0x0088c000 0 0x4000>;
 934                                 clock-names = "se";
 935                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 936                                 pinctrl-names = "default";
 937                                 pinctrl-0 = <&qup_spi3_default>;
 938                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 939                                 #address-cells = <1>;
 940                                 #size-cells = <0>;
 941                                 status = "disabled";
 942                         };
 943
 944                         uart3: serial@88c000 {
 945                                 compatible = "qcom,geni-uart";
 946                                 reg = <0 0x0088c000 0 0x4000>;
 947                                 clock-names = "se";
 948                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&qup_uart3_default>;
 951                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 952                                 status = "disabled";
 953                         };
 954
 955                         i2c4: i2c@890000 {
 956                                 compatible = "qcom,geni-i2c";
 957                                 reg = <0 0x00890000 0 0x4000>;
 958                                 clock-names = "se";
 959                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 960                                 pinctrl-names = "default";
 961                                 pinctrl-0 = <&qup_i2c4_default>;
 962                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 963                                 #address-cells = <1>;
 964                                 #size-cells = <0>;
 965                                 status = "disabled";
 966                         };
 967
 968                         spi4: spi@890000 {
 969                                 compatible = "qcom,geni-spi";
 970                                 reg = <0 0x00890000 0 0x4000>;
 971                                 clock-names = "se";
 972                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 973                                 pinctrl-names = "default";
 974                                 pinctrl-0 = <&qup_spi4_default>;
 975                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978                                 status = "disabled";
 979                         };
 980
 981                         uart4: serial@890000 {
 982                                 compatible = "qcom,geni-uart";
 983                                 reg = <0 0x00890000 0 0x4000>;
 984                                 clock-names = "se";
 985                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 986                                 pinctrl-names = "default";
 987                                 pinctrl-0 = <&qup_uart4_default>;
 988                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 989                                 status = "disabled";
 990                         };
 991
 992                         i2c5: i2c@894000 {
 993                                 compatible = "qcom,geni-i2c";
 994                                 reg = <0 0x00894000 0 0x4000>;
 995                                 clock-names = "se";
 996                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 997                                 pinctrl-names = "default";
 998                                 pinctrl-0 = <&qup_i2c5_default>;
 999                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002                                 status = "disabled";
1003                         };
1004
1005                         spi5: spi@894000 {
1006                                 compatible = "qcom,geni-spi";
1007                                 reg = <0 0x00894000 0 0x4000>;
1008                                 clock-names = "se";
1009                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1010                                 pinctrl-names = "default";
1011                                 pinctrl-0 = <&qup_spi5_default>;
1012                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015                                 status = "disabled";
1016                         };
1017
1018                         uart5: serial@894000 {
1019                                 compatible = "qcom,geni-uart";
1020                                 reg = <0 0x00894000 0 0x4000>;
1021                                 clock-names = "se";
1022                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1023                                 pinctrl-names = "default";
1024                                 pinctrl-0 = <&qup_uart5_default>;
1025                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1026                                 status = "disabled";
1027                         };
1028
1029                         i2c6: i2c@898000 {
1030                                 compatible = "qcom,geni-i2c";
1031                                 reg = <0 0x00898000 0 0x4000>;
1032                                 clock-names = "se";
1033                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1034                                 pinctrl-names = "default";
1035                                 pinctrl-0 = <&qup_i2c6_default>;
1036                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1037                                 #address-cells = <1>;
1038                                 #size-cells = <0>;
1039                                 status = "disabled";
1040                         };
1041
1042                         spi6: spi@898000 {
1043                                 compatible = "qcom,geni-spi";
1044                                 reg = <0 0x00898000 0 0x4000>;
1045                                 clock-names = "se";
1046                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1047                                 pinctrl-names = "default";
1048                                 pinctrl-0 = <&qup_spi6_default>;
1049                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1050                                 #address-cells = <1>;
1051                                 #size-cells = <0>;
1052                                 status = "disabled";
1053                         };
1054
1055                         uart6: serial@898000 {
1056                                 compatible = "qcom,geni-uart";
1057                                 reg = <0 0x00898000 0 0x4000>;
1058                                 clock-names = "se";
1059                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1060                                 pinctrl-names = "default";
1061                                 pinctrl-0 = <&qup_uart6_default>;
1062                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1063                                 status = "disabled";
1064                         };
1065
1066                         i2c7: i2c@89c000 {
1067                                 compatible = "qcom,geni-i2c";
1068                                 reg = <0 0x0089c000 0 0x4000>;
1069                                 clock-names = "se";
1070                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1071                                 pinctrl-names = "default";
1072                                 pinctrl-0 = <&qup_i2c7_default>;
1073                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1074                                 #address-cells = <1>;
1075                                 #size-cells = <0>;
1076                                 status = "disabled";
1077                         };
1078
1079                         spi7: spi@89c000 {
1080                                 compatible = "qcom,geni-spi";
1081                                 reg = <0 0x0089c000 0 0x4000>;
1082                                 clock-names = "se";
1083                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1084                                 pinctrl-names = "default";
1085                                 pinctrl-0 = <&qup_spi7_default>;
1086                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1087                                 #address-cells = <1>;
1088                                 #size-cells = <0>;
1089                                 status = "disabled";
1090                         };
1091
1092                         uart7: serial@89c000 {
1093                                 compatible = "qcom,geni-uart";
1094                                 reg = <0 0x0089c000 0 0x4000>;
1095                                 clock-names = "se";
1096                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1097                                 pinctrl-names = "default";
1098                                 pinctrl-0 = <&qup_uart7_default>;
1099                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1100                                 status = "disabled";
1101                         };
1102                 };
1103
1104                 qupv3_id_1: geniqup@ac0000 {
1105                         compatible = "qcom,geni-se-qup";
1106                         reg = <0 0x00ac0000 0 0x6000>;
1107                         clock-names = "m-ahb", "s-ahb";
1108                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1109                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1110                         #address-cells = <2>;
1111                         #size-cells = <2>;
1112                         ranges;
1113                         status = "disabled";
1114
1115                         i2c8: i2c@a80000 {
1116                                 compatible = "qcom,geni-i2c";
1117                                 reg = <0 0x00a80000 0 0x4000>;
1118                                 clock-names = "se";
1119                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&qup_i2c8_default>;
1122                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 status = "disabled";
1126                         };
1127
1128                         spi8: spi@a80000 {
1129                                 compatible = "qcom,geni-spi";
1130                                 reg = <0 0x00a80000 0 0x4000>;
1131                                 clock-names = "se";
1132                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1133                                 pinctrl-names = "default";
1134                                 pinctrl-0 = <&qup_spi8_default>;
1135                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 status = "disabled";
1139                         };
1140
1141                         uart8: serial@a80000 {
1142                                 compatible = "qcom,geni-uart";
1143                                 reg = <0 0x00a80000 0 0x4000>;
1144                                 clock-names = "se";
1145                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1146                                 pinctrl-names = "default";
1147                                 pinctrl-0 = <&qup_uart8_default>;
1148                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1149                                 status = "disabled";
1150                         };
1151
1152                         i2c9: i2c@a84000 {
1153                                 compatible = "qcom,geni-i2c";
1154                                 reg = <0 0x00a84000 0 0x4000>;
1155                                 clock-names = "se";
1156                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1157                                 pinctrl-names = "default";
1158                                 pinctrl-0 = <&qup_i2c9_default>;
1159                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1160                                 #address-cells = <1>;
1161                                 #size-cells = <0>;
1162                                 status = "disabled";
1163                         };
1164
1165                         spi9: spi@a84000 {
1166                                 compatible = "qcom,geni-spi";
1167                                 reg = <0 0x00a84000 0 0x4000>;
1168                                 clock-names = "se";
1169                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1170                                 pinctrl-names = "default";
1171                                 pinctrl-0 = <&qup_spi9_default>;
1172                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1173                                 #address-cells = <1>;
1174                                 #size-cells = <0>;
1175                                 status = "disabled";
1176                         };
1177
1178                         uart9: serial@a84000 {
1179                                 compatible = "qcom,geni-debug-uart";
1180                                 reg = <0 0x00a84000 0 0x4000>;
1181                                 clock-names = "se";
1182                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1183                                 pinctrl-names = "default";
1184                                 pinctrl-0 = <&qup_uart9_default>;
1185                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1186                                 status = "disabled";
1187                         };
1188
1189                         i2c10: i2c@a88000 {
1190                                 compatible = "qcom,geni-i2c";
1191                                 reg = <0 0x00a88000 0 0x4000>;
1192                                 clock-names = "se";
1193                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1194                                 pinctrl-names = "default";
1195                                 pinctrl-0 = <&qup_i2c10_default>;
1196                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1197                                 #address-cells = <1>;
1198                                 #size-cells = <0>;
1199                                 status = "disabled";
1200                         };
1201
1202                         spi10: spi@a88000 {
1203                                 compatible = "qcom,geni-spi";
1204                                 reg = <0 0x00a88000 0 0x4000>;
1205                                 clock-names = "se";
1206                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1207                                 pinctrl-names = "default";
1208                                 pinctrl-0 = <&qup_spi10_default>;
1209                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1210                                 #address-cells = <1>;
1211                                 #size-cells = <0>;
1212                                 status = "disabled";
1213                         };
1214
1215                         uart10: serial@a88000 {
1216                                 compatible = "qcom,geni-uart";
1217                                 reg = <0 0x00a88000 0 0x4000>;
1218                                 clock-names = "se";
1219                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1220                                 pinctrl-names = "default";
1221                                 pinctrl-0 = <&qup_uart10_default>;
1222                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1223                                 status = "disabled";
1224                         };
1225
1226                         i2c11: i2c@a8c000 {
1227                                 compatible = "qcom,geni-i2c";
1228                                 reg = <0 0x00a8c000 0 0x4000>;
1229                                 clock-names = "se";
1230                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1231                                 pinctrl-names = "default";
1232                                 pinctrl-0 = <&qup_i2c11_default>;
1233                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1234                                 #address-cells = <1>;
1235                                 #size-cells = <0>;
1236                                 status = "disabled";
1237                         };
1238
1239                         spi11: spi@a8c000 {
1240                                 compatible = "qcom,geni-spi";
1241                                 reg = <0 0x00a8c000 0 0x4000>;
1242                                 clock-names = "se";
1243                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1244                                 pinctrl-names = "default";
1245                                 pinctrl-0 = <&qup_spi11_default>;
1246                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1247                                 #address-cells = <1>;
1248                                 #size-cells = <0>;
1249                                 status = "disabled";
1250                         };
1251
1252                         uart11: serial@a8c000 {
1253                                 compatible = "qcom,geni-uart";
1254                                 reg = <0 0x00a8c000 0 0x4000>;
1255                                 clock-names = "se";
1256                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1257                                 pinctrl-names = "default";
1258                                 pinctrl-0 = <&qup_uart11_default>;
1259                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1260                                 status = "disabled";
1261                         };
1262
1263                         i2c12: i2c@a90000 {
1264                                 compatible = "qcom,geni-i2c";
1265                                 reg = <0 0x00a90000 0 0x4000>;
1266                                 clock-names = "se";
1267                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1268                                 pinctrl-names = "default";
1269                                 pinctrl-0 = <&qup_i2c12_default>;
1270                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273                                 status = "disabled";
1274                         };
1275
1276                         spi12: spi@a90000 {
1277                                 compatible = "qcom,geni-spi";
1278                                 reg = <0 0x00a90000 0 0x4000>;
1279                                 clock-names = "se";
1280                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1281                                 pinctrl-names = "default";
1282                                 pinctrl-0 = <&qup_spi12_default>;
1283                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1284                                 #address-cells = <1>;
1285                                 #size-cells = <0>;
1286                                 status = "disabled";
1287                         };
1288
1289                         uart12: serial@a90000 {
1290                                 compatible = "qcom,geni-uart";
1291                                 reg = <0 0x00a90000 0 0x4000>;
1292                                 clock-names = "se";
1293                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1294                                 pinctrl-names = "default";
1295                                 pinctrl-0 = <&qup_uart12_default>;
1296                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1297                                 status = "disabled";
1298                         };
1299
1300                         i2c13: i2c@a94000 {
1301                                 compatible = "qcom,geni-i2c";
1302                                 reg = <0 0x00a94000 0 0x4000>;
1303                                 clock-names = "se";
1304                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1305                                 pinctrl-names = "default";
1306                                 pinctrl-0 = <&qup_i2c13_default>;
1307                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1308                                 #address-cells = <1>;
1309                                 #size-cells = <0>;
1310                                 status = "disabled";
1311                         };
1312
1313                         spi13: spi@a94000 {
1314                                 compatible = "qcom,geni-spi";
1315                                 reg = <0 0x00a94000 0 0x4000>;
1316                                 clock-names = "se";
1317                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1318                                 pinctrl-names = "default";
1319                                 pinctrl-0 = <&qup_spi13_default>;
1320                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1321                                 #address-cells = <1>;
1322                                 #size-cells = <0>;
1323                                 status = "disabled";
1324                         };
1325
1326                         uart13: serial@a94000 {
1327                                 compatible = "qcom,geni-uart";
1328                                 reg = <0 0x00a94000 0 0x4000>;
1329                                 clock-names = "se";
1330                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1331                                 pinctrl-names = "default";
1332                                 pinctrl-0 = <&qup_uart13_default>;
1333                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1334                                 status = "disabled";
1335                         };
1336
1337                         i2c14: i2c@a98000 {
1338                                 compatible = "qcom,geni-i2c";
1339                                 reg = <0 0x00a98000 0 0x4000>;
1340                                 clock-names = "se";
1341                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1342                                 pinctrl-names = "default";
1343                                 pinctrl-0 = <&qup_i2c14_default>;
1344                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1345                                 #address-cells = <1>;
1346                                 #size-cells = <0>;
1347                                 status = "disabled";
1348                         };
1349
1350                         spi14: spi@a98000 {
1351                                 compatible = "qcom,geni-spi";
1352                                 reg = <0 0x00a98000 0 0x4000>;
1353                                 clock-names = "se";
1354                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1355                                 pinctrl-names = "default";
1356                                 pinctrl-0 = <&qup_spi14_default>;
1357                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1358                                 #address-cells = <1>;
1359                                 #size-cells = <0>;
1360                                 status = "disabled";
1361                         };
1362
1363                         uart14: serial@a98000 {
1364                                 compatible = "qcom,geni-uart";
1365                                 reg = <0 0x00a98000 0 0x4000>;
1366                                 clock-names = "se";
1367                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_uart14_default>;
1370                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1371                                 status = "disabled";
1372                         };
1373
1374                         i2c15: i2c@a9c000 {
1375                                 compatible = "qcom,geni-i2c";
1376                                 reg = <0 0x00a9c000 0 0x4000>;
1377                                 clock-names = "se";
1378                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1379                                 pinctrl-names = "default";
1380                                 pinctrl-0 = <&qup_i2c15_default>;
1381                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1382                                 #address-cells = <1>;
1383                                 #size-cells = <0>;
1384                                 status = "disabled";
1385                         };
1386
1387                         spi15: spi@a9c000 {
1388                                 compatible = "qcom,geni-spi";
1389                                 reg = <0 0x00a9c000 0 0x4000>;
1390                                 clock-names = "se";
1391                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1392                                 pinctrl-names = "default";
1393                                 pinctrl-0 = <&qup_spi15_default>;
1394                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1395                                 #address-cells = <1>;
1396                                 #size-cells = <0>;
1397                                 status = "disabled";
1398                         };
1399
1400                         uart15: serial@a9c000 {
1401                                 compatible = "qcom,geni-uart";
1402                                 reg = <0 0x00a9c000 0 0x4000>;
1403                                 clock-names = "se";
1404                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1405                                 pinctrl-names = "default";
1406                                 pinctrl-0 = <&qup_uart15_default>;
1407                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1408                                 status = "disabled";
1409                         };
1410                 };
1411
1412                 system-cache-controller@1100000 {
1413                         compatible = "qcom,sdm845-llcc";
1414                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1415                         reg-names = "llcc_base", "llcc_broadcast_base";
1416                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1417                 };
1418
1419                 pcie0: pci@1c00000 {
1420                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1421                         reg = <0 0x01c00000 0 0x2000>,
1422                               <0 0x60000000 0 0xf1d>,
1423                               <0 0x60000f20 0 0xa8>,
1424                               <0 0x60100000 0 0x100000>;
1425                         reg-names = "parf", "dbi", "elbi", "config";
1426                         device_type = "pci";
1427                         linux,pci-domain = <0>;
1428                         bus-range = <0x00 0xff>;
1429                         num-lanes = <1>;
1430
1431                         #address-cells = <3>;
1432                         #size-cells = <2>;
1433
1434                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1435                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1436
1437                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1438                         interrupt-names = "msi";
1439                         #interrupt-cells = <1>;
1440                         interrupt-map-mask = <0 0 0 0x7>;
1441                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1442                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1443                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1444                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1445
1446                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1447                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1448                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1449                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1450                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1451                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1452                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1453                         clock-names = "pipe",
1454                                       "aux",
1455                                       "cfg",
1456                                       "bus_master",
1457                                       "bus_slave",
1458                                       "slave_q2a",
1459                                       "tbu";
1460
1461                         iommus = <&apps_smmu 0x1c10 0xf>;
1462                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
1463                                     <0x100 &apps_smmu 0x1c11 0x1>,
1464                                     <0x200 &apps_smmu 0x1c12 0x1>,
1465                                     <0x300 &apps_smmu 0x1c13 0x1>,
1466                                     <0x400 &apps_smmu 0x1c14 0x1>,
1467                                     <0x500 &apps_smmu 0x1c15 0x1>,
1468                                     <0x600 &apps_smmu 0x1c16 0x1>,
1469                                     <0x700 &apps_smmu 0x1c17 0x1>,
1470                                     <0x800 &apps_smmu 0x1c18 0x1>,
1471                                     <0x900 &apps_smmu 0x1c19 0x1>,
1472                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
1473                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
1474                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
1475                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
1476                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
1477                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
1478
1479                         resets = <&gcc GCC_PCIE_0_BCR>;
1480                         reset-names = "pci";
1481
1482                         power-domains = <&gcc PCIE_0_GDSC>;
1483
1484                         phys = <&pcie0_lane>;
1485                         phy-names = "pciephy";
1486
1487                         status = "disabled";
1488                 };
1489
1490                 pcie0_phy: phy@1c06000 {
1491                         compatible = "qcom,sdm845-qmp-pcie-phy";
1492                         reg = <0 0x01c06000 0 0x18c>;
1493                         #address-cells = <2>;
1494                         #size-cells = <2>;
1495                         ranges;
1496                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1497                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1498                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1499                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1500                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1501
1502                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1503                         reset-names = "phy";
1504
1505                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1506                         assigned-clock-rates = <100000000>;
1507
1508                         status = "disabled";
1509
1510                         pcie0_lane: lanes@1c06200 {
1511                                 reg = <0 0x01c06200 0 0x128>,
1512                                       <0 0x01c06400 0 0x1fc>,
1513                                       <0 0x01c06800 0 0x218>,
1514                                       <0 0x01c06600 0 0x70>;
1515                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1516                                 clock-names = "pipe0";
1517
1518                                 #phy-cells = <0>;
1519                                 clock-output-names = "pcie_0_pipe_clk";
1520                         };
1521                 };
1522
1523                 pcie1: pci@1c08000 {
1524                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1525                         reg = <0 0x01c08000 0 0x2000>,
1526                               <0 0x40000000 0 0xf1d>,
1527                               <0 0x40000f20 0 0xa8>,
1528                               <0 0x40100000 0 0x100000>;
1529                         reg-names = "parf", "dbi", "elbi", "config";
1530                         device_type = "pci";
1531                         linux,pci-domain = <1>;
1532                         bus-range = <0x00 0xff>;
1533                         num-lanes = <1>;
1534
1535                         #address-cells = <3>;
1536                         #size-cells = <2>;
1537
1538                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1539                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1540
1541                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1542                         interrupt-names = "msi";
1543                         #interrupt-cells = <1>;
1544                         interrupt-map-mask = <0 0 0 0x7>;
1545                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1546                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1547                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1548                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1549
1550                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1551                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1552                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1553                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1554                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1555                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1556                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1557                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1558                         clock-names = "pipe",
1559                                       "aux",
1560                                       "cfg",
1561                                       "bus_master",
1562                                       "bus_slave",
1563                                       "slave_q2a",
1564                                       "ref",
1565                                       "tbu";
1566
1567                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1568                         assigned-clock-rates = <19200000>;
1569
1570                         iommus = <&apps_smmu 0x1c00 0xf>;
1571                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1572                                     <0x100 &apps_smmu 0x1c01 0x1>,
1573                                     <0x200 &apps_smmu 0x1c02 0x1>,
1574                                     <0x300 &apps_smmu 0x1c03 0x1>,
1575                                     <0x400 &apps_smmu 0x1c04 0x1>,
1576                                     <0x500 &apps_smmu 0x1c05 0x1>,
1577                                     <0x600 &apps_smmu 0x1c06 0x1>,
1578                                     <0x700 &apps_smmu 0x1c07 0x1>,
1579                                     <0x800 &apps_smmu 0x1c08 0x1>,
1580                                     <0x900 &apps_smmu 0x1c09 0x1>,
1581                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
1582                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
1583                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
1584                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
1585                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
1586                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
1587
1588                         resets = <&gcc GCC_PCIE_1_BCR>;
1589                         reset-names = "pci";
1590
1591                         power-domains = <&gcc PCIE_1_GDSC>;
1592
1593                         phys = <&pcie1_lane>;
1594                         phy-names = "pciephy";
1595
1596                         status = "disabled";
1597                 };
1598
1599                 pcie1_phy: phy@1c0a000 {
1600                         compatible = "qcom,sdm845-qhp-pcie-phy";
1601                         reg = <0 0x01c0a000 0 0x800>;
1602                         #address-cells = <2>;
1603                         #size-cells = <2>;
1604                         ranges;
1605                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1606                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1607                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1608                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1609                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1610
1611                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1612                         reset-names = "phy";
1613
1614                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1615                         assigned-clock-rates = <100000000>;
1616
1617                         status = "disabled";
1618
1619                         pcie1_lane: lanes@1c06200 {
1620                                 reg = <0 0x01c0a800 0 0x800>,
1621                                       <0 0x01c0a800 0 0x800>,
1622                                       <0 0x01c0b800 0 0x400>;
1623                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1624                                 clock-names = "pipe0";
1625
1626                                 #phy-cells = <0>;
1627                                 clock-output-names = "pcie_1_pipe_clk";
1628                         };
1629                 };
1630
1631                 mem_noc: interconnect@1380000 {
1632                         compatible = "qcom,sdm845-mem-noc";
1633                         reg = <0 0x01380000 0 0x27200>;
1634                         #interconnect-cells = <1>;
1635                         qcom,bcm-voters = <&apps_bcm_voter>;
1636                 };
1637
1638                 dc_noc: interconnect@14e0000 {
1639                         compatible = "qcom,sdm845-dc-noc";
1640                         reg = <0 0x014e0000 0 0x400>;
1641                         #interconnect-cells = <1>;
1642                         qcom,bcm-voters = <&apps_bcm_voter>;
1643                 };
1644
1645                 config_noc: interconnect@1500000 {
1646                         compatible = "qcom,sdm845-config-noc";
1647                         reg = <0 0x01500000 0 0x5080>;
1648                         #interconnect-cells = <1>;
1649                         qcom,bcm-voters = <&apps_bcm_voter>;
1650                 };
1651
1652                 system_noc: interconnect@1620000 {
1653                         compatible = "qcom,sdm845-system-noc";
1654                         reg = <0 0x01620000 0 0x18080>;
1655                         #interconnect-cells = <1>;
1656                         qcom,bcm-voters = <&apps_bcm_voter>;
1657                 };
1658
1659                 aggre1_noc: interconnect@16e0000 {
1660                         compatible = "qcom,sdm845-aggre1-noc";
1661                         reg = <0 0x016e0000 0 0x15080>;
1662                         #interconnect-cells = <1>;
1663                         qcom,bcm-voters = <&apps_bcm_voter>;
1664                 };
1665
1666                 aggre2_noc: interconnect@1700000 {
1667                         compatible = "qcom,sdm845-aggre2-noc";
1668                         reg = <0 0x01700000 0 0x1f300>;
1669                         #interconnect-cells = <1>;
1670                         qcom,bcm-voters = <&apps_bcm_voter>;
1671                 };
1672
1673                 mmss_noc: interconnect@1740000 {
1674                         compatible = "qcom,sdm845-mmss-noc";
1675                         reg = <0 0x01740000 0 0x1c100>;
1676                         #interconnect-cells = <1>;
1677                         qcom,bcm-voters = <&apps_bcm_voter>;
1678                 };
1679
1680                 ufs_mem_hc: ufshc@1d84000 {
1681                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1682                                      "jedec,ufs-2.0";
1683                         reg = <0 0x01d84000 0 0x2500>;
1684                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1685                         phys = <&ufs_mem_phy_lanes>;
1686                         phy-names = "ufsphy";
1687                         lanes-per-direction = <2>;
1688                         power-domains = <&gcc UFS_PHY_GDSC>;
1689                         #reset-cells = <1>;
1690                         resets = <&gcc GCC_UFS_PHY_BCR>;
1691                         reset-names = "rst";
1692
1693                         iommus = <&apps_smmu 0x100 0xf>;
1694
1695                         clock-names =
1696                                 "core_clk",
1697                                 "bus_aggr_clk",
1698                                 "iface_clk",
1699                                 "core_clk_unipro",
1700                                 "ref_clk",
1701                                 "tx_lane0_sync_clk",
1702                                 "rx_lane0_sync_clk",
1703                                 "rx_lane1_sync_clk";
1704                         clocks =
1705                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1706                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1707                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1708                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1709                                 <&rpmhcc RPMH_CXO_CLK>,
1710                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1711                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1712                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1713                         freq-table-hz =
1714                                 <50000000 200000000>,
1715                                 <0 0>,
1716                                 <0 0>,
1717                                 <37500000 150000000>,
1718                                 <0 0>,
1719                                 <0 0>,
1720                                 <0 0>,
1721                                 <0 0>;
1722
1723                         status = "disabled";
1724                 };
1725
1726                 ufs_mem_phy: phy@1d87000 {
1727                         compatible = "qcom,sdm845-qmp-ufs-phy";
1728                         reg = <0 0x01d87000 0 0x18c>;
1729                         #address-cells = <2>;
1730                         #size-cells = <2>;
1731                         ranges;
1732                         clock-names = "ref",
1733                                       "ref_aux";
1734                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1735                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1736
1737                         resets = <&ufs_mem_hc 0>;
1738                         reset-names = "ufsphy";
1739                         status = "disabled";
1740
1741                         ufs_mem_phy_lanes: lanes@1d87400 {
1742                                 reg = <0 0x01d87400 0 0x108>,
1743                                       <0 0x01d87600 0 0x1e0>,
1744                                       <0 0x01d87c00 0 0x1dc>,
1745                                       <0 0x01d87800 0 0x108>,
1746                                       <0 0x01d87a00 0 0x1e0>;
1747                                 #phy-cells = <0>;
1748                         };
1749                 };
1750
1751                 tcsr_mutex_regs: syscon@1f40000 {
1752                         compatible = "syscon";
1753                         reg = <0 0x01f40000 0 0x40000>;
1754                 };
1755
1756                 tlmm: pinctrl@3400000 {
1757                         compatible = "qcom,sdm845-pinctrl";
1758                         reg = <0 0x03400000 0 0xc00000>;
1759                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1760                         gpio-controller;
1761                         #gpio-cells = <2>;
1762                         interrupt-controller;
1763                         #interrupt-cells = <2>;
1764                         gpio-ranges = <&tlmm 0 0 150>;
1765                         wakeup-parent = <&pdc_intc>;
1766
1767                         qspi_clk: qspi-clk {
1768                                 pinmux {
1769                                         pins = "gpio95";
1770                                         function = "qspi_clk";
1771                                 };
1772                         };
1773
1774                         qspi_cs0: qspi-cs0 {
1775                                 pinmux {
1776                                         pins = "gpio90";
1777                                         function = "qspi_cs";
1778                                 };
1779                         };
1780
1781                         qspi_cs1: qspi-cs1 {
1782                                 pinmux {
1783                                         pins = "gpio89";
1784                                         function = "qspi_cs";
1785                                 };
1786                         };
1787
1788                         qspi_data01: qspi-data01 {
1789                                 pinmux-data {
1790                                         pins = "gpio91", "gpio92";
1791                                         function = "qspi_data";
1792                                 };
1793                         };
1794
1795                         qspi_data12: qspi-data12 {
1796                                 pinmux-data {
1797                                         pins = "gpio93", "gpio94";
1798                                         function = "qspi_data";
1799                                 };
1800                         };
1801
1802                         qup_i2c0_default: qup-i2c0-default {
1803                                 pinmux {
1804                                         pins = "gpio0", "gpio1";
1805                                         function = "qup0";
1806                                 };
1807                         };
1808
1809                         qup_i2c1_default: qup-i2c1-default {
1810                                 pinmux {
1811                                         pins = "gpio17", "gpio18";
1812                                         function = "qup1";
1813                                 };
1814                         };
1815
1816                         qup_i2c2_default: qup-i2c2-default {
1817                                 pinmux {
1818                                         pins = "gpio27", "gpio28";
1819                                         function = "qup2";
1820                                 };
1821                         };
1822
1823                         qup_i2c3_default: qup-i2c3-default {
1824                                 pinmux {
1825                                         pins = "gpio41", "gpio42";
1826                                         function = "qup3";
1827                                 };
1828                         };
1829
1830                         qup_i2c4_default: qup-i2c4-default {
1831                                 pinmux {
1832                                         pins = "gpio89", "gpio90";
1833                                         function = "qup4";
1834                                 };
1835                         };
1836
1837                         qup_i2c5_default: qup-i2c5-default {
1838                                 pinmux {
1839                                         pins = "gpio85", "gpio86";
1840                                         function = "qup5";
1841                                 };
1842                         };
1843
1844                         qup_i2c6_default: qup-i2c6-default {
1845                                 pinmux {
1846                                         pins = "gpio45", "gpio46";
1847                                         function = "qup6";
1848                                 };
1849                         };
1850
1851                         qup_i2c7_default: qup-i2c7-default {
1852                                 pinmux {
1853                                         pins = "gpio93", "gpio94";
1854                                         function = "qup7";
1855                                 };
1856                         };
1857
1858                         qup_i2c8_default: qup-i2c8-default {
1859                                 pinmux {
1860                                         pins = "gpio65", "gpio66";
1861                                         function = "qup8";
1862                                 };
1863                         };
1864
1865                         qup_i2c9_default: qup-i2c9-default {
1866                                 pinmux {
1867                                         pins = "gpio6", "gpio7";
1868                                         function = "qup9";
1869                                 };
1870                         };
1871
1872                         qup_i2c10_default: qup-i2c10-default {
1873                                 pinmux {
1874                                         pins = "gpio55", "gpio56";
1875                                         function = "qup10";
1876                                 };
1877                         };
1878
1879                         qup_i2c11_default: qup-i2c11-default {
1880                                 pinmux {
1881                                         pins = "gpio31", "gpio32";
1882                                         function = "qup11";
1883                                 };
1884                         };
1885
1886                         qup_i2c12_default: qup-i2c12-default {
1887                                 pinmux {
1888                                         pins = "gpio49", "gpio50";
1889                                         function = "qup12";
1890                                 };
1891                         };
1892
1893                         qup_i2c13_default: qup-i2c13-default {
1894                                 pinmux {
1895                                         pins = "gpio105", "gpio106";
1896                                         function = "qup13";
1897                                 };
1898                         };
1899
1900                         qup_i2c14_default: qup-i2c14-default {
1901                                 pinmux {
1902                                         pins = "gpio33", "gpio34";
1903                                         function = "qup14";
1904                                 };
1905                         };
1906
1907                         qup_i2c15_default: qup-i2c15-default {
1908                                 pinmux {
1909                                         pins = "gpio81", "gpio82";
1910                                         function = "qup15";
1911                                 };
1912                         };
1913
1914                         qup_spi0_default: qup-spi0-default {
1915                                 pinmux {
1916                                         pins = "gpio0", "gpio1",
1917                                                "gpio2", "gpio3";
1918                                         function = "qup0";
1919                                 };
1920                         };
1921
1922                         qup_spi1_default: qup-spi1-default {
1923                                 pinmux {
1924                                         pins = "gpio17", "gpio18",
1925                                                "gpio19", "gpio20";
1926                                         function = "qup1";
1927                                 };
1928                         };
1929
1930                         qup_spi2_default: qup-spi2-default {
1931                                 pinmux {
1932                                         pins = "gpio27", "gpio28",
1933                                                "gpio29", "gpio30";
1934                                         function = "qup2";
1935                                 };
1936                         };
1937
1938                         qup_spi3_default: qup-spi3-default {
1939                                 pinmux {
1940                                         pins = "gpio41", "gpio42",
1941                                                "gpio43", "gpio44";
1942                                         function = "qup3";
1943                                 };
1944                         };
1945
1946                         qup_spi4_default: qup-spi4-default {
1947                                 pinmux {
1948                                         pins = "gpio89", "gpio90",
1949                                                "gpio91", "gpio92";
1950                                         function = "qup4";
1951                                 };
1952                         };
1953
1954                         qup_spi5_default: qup-spi5-default {
1955                                 pinmux {
1956                                         pins = "gpio85", "gpio86",
1957                                                "gpio87", "gpio88";
1958                                         function = "qup5";
1959                                 };
1960                         };
1961
1962                         qup_spi6_default: qup-spi6-default {
1963                                 pinmux {
1964                                         pins = "gpio45", "gpio46",
1965                                                "gpio47", "gpio48";
1966                                         function = "qup6";
1967                                 };
1968                         };
1969
1970                         qup_spi7_default: qup-spi7-default {
1971                                 pinmux {
1972                                         pins = "gpio93", "gpio94",
1973                                                "gpio95", "gpio96";
1974                                         function = "qup7";
1975                                 };
1976                         };
1977
1978                         qup_spi8_default: qup-spi8-default {
1979                                 pinmux {
1980                                         pins = "gpio65", "gpio66",
1981                                                "gpio67", "gpio68";
1982                                         function = "qup8";
1983                                 };
1984                         };
1985
1986                         qup_spi9_default: qup-spi9-default {
1987                                 pinmux {
1988                                         pins = "gpio6", "gpio7",
1989                                                "gpio4", "gpio5";
1990                                         function = "qup9";
1991                                 };
1992                         };
1993
1994                         qup_spi10_default: qup-spi10-default {
1995                                 pinmux {
1996                                         pins = "gpio55", "gpio56",
1997                                                "gpio53", "gpio54";
1998                                         function = "qup10";
1999                                 };
2000                         };
2001
2002                         qup_spi11_default: qup-spi11-default {
2003                                 pinmux {
2004                                         pins = "gpio31", "gpio32",
2005                                                "gpio33", "gpio34";
2006                                         function = "qup11";
2007                                 };
2008                         };
2009
2010                         qup_spi12_default: qup-spi12-default {
2011                                 pinmux {
2012                                         pins = "gpio49", "gpio50",
2013                                                "gpio51", "gpio52";
2014                                         function = "qup12";
2015                                 };
2016                         };
2017
2018                         qup_spi13_default: qup-spi13-default {
2019                                 pinmux {
2020                                         pins = "gpio105", "gpio106",
2021                                                "gpio107", "gpio108";
2022                                         function = "qup13";
2023                                 };
2024                         };
2025
2026                         qup_spi14_default: qup-spi14-default {
2027                                 pinmux {
2028                                         pins = "gpio33", "gpio34",
2029                                                "gpio31", "gpio32";
2030                                         function = "qup14";
2031                                 };
2032                         };
2033
2034                         qup_spi15_default: qup-spi15-default {
2035                                 pinmux {
2036                                         pins = "gpio81", "gpio82",
2037                                                "gpio83", "gpio84";
2038                                         function = "qup15";
2039                                 };
2040                         };
2041
2042                         qup_uart0_default: qup-uart0-default {
2043                                 pinmux {
2044                                         pins = "gpio2", "gpio3";
2045                                         function = "qup0";
2046                                 };
2047                         };
2048
2049                         qup_uart1_default: qup-uart1-default {
2050                                 pinmux {
2051                                         pins = "gpio19", "gpio20";
2052                                         function = "qup1";
2053                                 };
2054                         };
2055
2056                         qup_uart2_default: qup-uart2-default {
2057                                 pinmux {
2058                                         pins = "gpio29", "gpio30";
2059                                         function = "qup2";
2060                                 };
2061                         };
2062
2063                         qup_uart3_default: qup-uart3-default {
2064                                 pinmux {
2065                                         pins = "gpio43", "gpio44";
2066                                         function = "qup3";
2067                                 };
2068                         };
2069
2070                         qup_uart4_default: qup-uart4-default {
2071                                 pinmux {
2072                                         pins = "gpio91", "gpio92";
2073                                         function = "qup4";
2074                                 };
2075                         };
2076
2077                         qup_uart5_default: qup-uart5-default {
2078                                 pinmux {
2079                                         pins = "gpio87", "gpio88";
2080                                         function = "qup5";
2081                                 };
2082                         };
2083
2084                         qup_uart6_default: qup-uart6-default {
2085                                 pinmux {
2086                                         pins = "gpio47", "gpio48";
2087                                         function = "qup6";
2088                                 };
2089                         };
2090
2091                         qup_uart7_default: qup-uart7-default {
2092                                 pinmux {
2093                                         pins = "gpio95", "gpio96";
2094                                         function = "qup7";
2095                                 };
2096                         };
2097
2098                         qup_uart8_default: qup-uart8-default {
2099                                 pinmux {
2100                                         pins = "gpio67", "gpio68";
2101                                         function = "qup8";
2102                                 };
2103                         };
2104
2105                         qup_uart9_default: qup-uart9-default {
2106                                 pinmux {
2107                                         pins = "gpio4", "gpio5";
2108                                         function = "qup9";
2109                                 };
2110                         };
2111
2112                         qup_uart10_default: qup-uart10-default {
2113                                 pinmux {
2114                                         pins = "gpio53", "gpio54";
2115                                         function = "qup10";
2116                                 };
2117                         };
2118
2119                         qup_uart11_default: qup-uart11-default {
2120                                 pinmux {
2121                                         pins = "gpio33", "gpio34";
2122                                         function = "qup11";
2123                                 };
2124                         };
2125
2126                         qup_uart12_default: qup-uart12-default {
2127                                 pinmux {
2128                                         pins = "gpio51", "gpio52";
2129                                         function = "qup12";
2130                                 };
2131                         };
2132
2133                         qup_uart13_default: qup-uart13-default {
2134                                 pinmux {
2135                                         pins = "gpio107", "gpio108";
2136                                         function = "qup13";
2137                                 };
2138                         };
2139
2140                         qup_uart14_default: qup-uart14-default {
2141                                 pinmux {
2142                                         pins = "gpio31", "gpio32";
2143                                         function = "qup14";
2144                                 };
2145                         };
2146
2147                         qup_uart15_default: qup-uart15-default {
2148                                 pinmux {
2149                                         pins = "gpio83", "gpio84";
2150                                         function = "qup15";
2151                                 };
2152                         };
2153
2154                         quat_mi2s_sleep: quat_mi2s_sleep {
2155                                 mux {
2156                                         pins = "gpio58", "gpio59";
2157                                         function = "gpio";
2158                                 };
2159
2160                                 config {
2161                                         pins = "gpio58", "gpio59";
2162                                         drive-strength = <2>;
2163                                         bias-pull-down;
2164                                         input-enable;
2165                                 };
2166                         };
2167
2168                         quat_mi2s_active: quat_mi2s_active {
2169                                 mux {
2170                                         pins = "gpio58", "gpio59";
2171                                         function = "qua_mi2s";
2172                                 };
2173
2174                                 config {
2175                                         pins = "gpio58", "gpio59";
2176                                         drive-strength = <8>;
2177                                         bias-disable;
2178                                         output-high;
2179                                 };
2180                         };
2181
2182                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2183                                 mux {
2184                                         pins = "gpio60";
2185                                         function = "gpio";
2186                                 };
2187
2188                                 config {
2189                                         pins = "gpio60";
2190                                         drive-strength = <2>;
2191                                         bias-pull-down;
2192                                         input-enable;
2193                                 };
2194                         };
2195
2196                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2197                                 mux {
2198                                         pins = "gpio60";
2199                                         function = "qua_mi2s";
2200                                 };
2201
2202                                 config {
2203                                         pins = "gpio60";
2204                                         drive-strength = <8>;
2205                                         bias-disable;
2206                                 };
2207                         };
2208
2209                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2210                                 mux {
2211                                         pins = "gpio61";
2212                                         function = "gpio";
2213                                 };
2214
2215                                 config {
2216                                         pins = "gpio61";
2217                                         drive-strength = <2>;
2218                                         bias-pull-down;
2219                                         input-enable;
2220                                 };
2221                         };
2222
2223                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2224                                 mux {
2225                                         pins = "gpio61";
2226                                         function = "qua_mi2s";
2227                                 };
2228
2229                                 config {
2230                                         pins = "gpio61";
2231                                         drive-strength = <8>;
2232                                         bias-disable;
2233                                 };
2234                         };
2235
2236                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2237                                 mux {
2238                                         pins = "gpio62";
2239                                         function = "gpio";
2240                                 };
2241
2242                                 config {
2243                                         pins = "gpio62";
2244                                         drive-strength = <2>;
2245                                         bias-pull-down;
2246                                         input-enable;
2247                                 };
2248                         };
2249
2250                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2251                                 mux {
2252                                         pins = "gpio62";
2253                                         function = "qua_mi2s";
2254                                 };
2255
2256                                 config {
2257                                         pins = "gpio62";
2258                                         drive-strength = <8>;
2259                                         bias-disable;
2260                                 };
2261                         };
2262
2263                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2264                                 mux {
2265                                         pins = "gpio63";
2266                                         function = "gpio";
2267                                 };
2268
2269                                 config {
2270                                         pins = "gpio63";
2271                                         drive-strength = <2>;
2272                                         bias-pull-down;
2273                                         input-enable;
2274                                 };
2275                         };
2276
2277                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2278                                 mux {
2279                                         pins = "gpio63";
2280                                         function = "qua_mi2s";
2281                                 };
2282
2283                                 config {
2284                                         pins = "gpio63";
2285                                         drive-strength = <8>;
2286                                         bias-disable;
2287                                 };
2288                         };
2289                 };
2290
2291                 mss_pil: remoteproc@4080000 {
2292                         compatible = "qcom,sdm845-mss-pil";
2293                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2294                         reg-names = "qdsp6", "rmb";
2295
2296                         interrupts-extended =
2297                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2298                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2299                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2300                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2301                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2302                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2303                         interrupt-names = "wdog", "fatal", "ready",
2304                                           "handover", "stop-ack",
2305                                           "shutdown-ack";
2306
2307                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2308                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2309                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2310                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2311                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2312                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2313                                  <&gcc GCC_PRNG_AHB_CLK>,
2314                                  <&rpmhcc RPMH_CXO_CLK>;
2315                         clock-names = "iface", "bus", "mem", "gpll0_mss",
2316                                       "snoc_axi", "mnoc_axi", "prng", "xo";
2317
2318                         qcom,smem-states = <&modem_smp2p_out 0>;
2319                         qcom,smem-state-names = "stop";
2320
2321                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2322                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2323                         reset-names = "mss_restart", "pdc_reset";
2324
2325                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2326
2327                         power-domains = <&aoss_qmp 2>,
2328                                         <&rpmhpd SDM845_CX>,
2329                                         <&rpmhpd SDM845_MX>,
2330                                         <&rpmhpd SDM845_MSS>;
2331                         power-domain-names = "load_state", "cx", "mx", "mss";
2332
2333                         mba {
2334                                 memory-region = <&mba_region>;
2335                         };
2336
2337                         mpss {
2338                                 memory-region = <&mpss_region>;
2339                         };
2340
2341                         glink-edge {
2342                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2343                                 label = "modem";
2344                                 qcom,remote-pid = <1>;
2345                                 mboxes = <&apss_shared 12>;
2346                         };
2347                 };
2348
2349                 gpucc: clock-controller@5090000 {
2350                         compatible = "qcom,sdm845-gpucc";
2351                         reg = <0 0x05090000 0 0x9000>;
2352                         #clock-cells = <1>;
2353                         #reset-cells = <1>;
2354                         #power-domain-cells = <1>;
2355                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2356                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2357                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2358                         clock-names = "bi_tcxo",
2359                                       "gcc_gpu_gpll0_clk_src",
2360                                       "gcc_gpu_gpll0_div_clk_src";
2361                 };
2362
2363                 stm@6002000 {
2364                         compatible = "arm,coresight-stm", "arm,primecell";
2365                         reg = <0 0x06002000 0 0x1000>,
2366                               <0 0x16280000 0 0x180000>;
2367                         reg-names = "stm-base", "stm-stimulus-base";
2368
2369                         clocks = <&aoss_qmp>;
2370                         clock-names = "apb_pclk";
2371
2372                         out-ports {
2373                                 port {
2374                                         stm_out: endpoint {
2375                                                 remote-endpoint =
2376                                                   <&funnel0_in7>;
2377                                         };
2378                                 };
2379                         };
2380                 };
2381
2382                 funnel@6041000 {
2383                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2384                         reg = <0 0x06041000 0 0x1000>;
2385
2386                         clocks = <&aoss_qmp>;
2387                         clock-names = "apb_pclk";
2388
2389                         out-ports {
2390                                 port {
2391                                         funnel0_out: endpoint {
2392                                                 remote-endpoint =
2393                                                   <&merge_funnel_in0>;
2394                                         };
2395                                 };
2396                         };
2397
2398                         in-ports {
2399                                 #address-cells = <1>;
2400                                 #size-cells = <0>;
2401
2402                                 port@7 {
2403                                         reg = <7>;
2404                                         funnel0_in7: endpoint {
2405                                                 remote-endpoint = <&stm_out>;
2406                                         };
2407                                 };
2408                         };
2409                 };
2410
2411                 funnel@6043000 {
2412                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2413                         reg = <0 0x06043000 0 0x1000>;
2414
2415                         clocks = <&aoss_qmp>;
2416                         clock-names = "apb_pclk";
2417
2418                         out-ports {
2419                                 port {
2420                                         funnel2_out: endpoint {
2421                                                 remote-endpoint =
2422                                                   <&merge_funnel_in2>;
2423                                         };
2424                                 };
2425                         };
2426
2427                         in-ports {
2428                                 #address-cells = <1>;
2429                                 #size-cells = <0>;
2430
2431                                 port@5 {
2432                                         reg = <5>;
2433                                         funnel2_in5: endpoint {
2434                                                 remote-endpoint =
2435                                                   <&apss_merge_funnel_out>;
2436                                         };
2437                                 };
2438                         };
2439                 };
2440
2441                 funnel@6045000 {
2442                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2443                         reg = <0 0x06045000 0 0x1000>;
2444
2445                         clocks = <&aoss_qmp>;
2446                         clock-names = "apb_pclk";
2447
2448                         out-ports {
2449                                 port {
2450                                         merge_funnel_out: endpoint {
2451                                                 remote-endpoint = <&etf_in>;
2452                                         };
2453                                 };
2454                         };
2455
2456                         in-ports {
2457                                 #address-cells = <1>;
2458                                 #size-cells = <0>;
2459
2460                                 port@0 {
2461                                         reg = <0>;
2462                                         merge_funnel_in0: endpoint {
2463                                                 remote-endpoint =
2464                                                   <&funnel0_out>;
2465                                         };
2466                                 };
2467
2468                                 port@2 {
2469                                         reg = <2>;
2470                                         merge_funnel_in2: endpoint {
2471                                                 remote-endpoint =
2472                                                   <&funnel2_out>;
2473                                         };
2474                                 };
2475                         };
2476                 };
2477
2478                 replicator@6046000 {
2479                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2480                         reg = <0 0x06046000 0 0x1000>;
2481
2482                         clocks = <&aoss_qmp>;
2483                         clock-names = "apb_pclk";
2484
2485                         out-ports {
2486                                 port {
2487                                         replicator_out: endpoint {
2488                                                 remote-endpoint = <&etr_in>;
2489                                         };
2490                                 };
2491                         };
2492
2493                         in-ports {
2494                                 port {
2495                                         replicator_in: endpoint {
2496                                                 remote-endpoint = <&etf_out>;
2497                                         };
2498                                 };
2499                         };
2500                 };
2501
2502                 etf@6047000 {
2503                         compatible = "arm,coresight-tmc", "arm,primecell";
2504                         reg = <0 0x06047000 0 0x1000>;
2505
2506                         clocks = <&aoss_qmp>;
2507                         clock-names = "apb_pclk";
2508
2509                         out-ports {
2510                                 port {
2511                                         etf_out: endpoint {
2512                                                 remote-endpoint =
2513                                                   <&replicator_in>;
2514                                         };
2515                                 };
2516                         };
2517
2518                         in-ports {
2519                                 #address-cells = <1>;
2520                                 #size-cells = <0>;
2521
2522                                 port@1 {
2523                                         reg = <1>;
2524                                         etf_in: endpoint {
2525                                                 remote-endpoint =
2526                                                   <&merge_funnel_out>;
2527                                         };
2528                                 };
2529                         };
2530                 };
2531
2532                 etr@6048000 {
2533                         compatible = "arm,coresight-tmc", "arm,primecell";
2534                         reg = <0 0x06048000 0 0x1000>;
2535
2536                         clocks = <&aoss_qmp>;
2537                         clock-names = "apb_pclk";
2538                         arm,scatter-gather;
2539
2540                         in-ports {
2541                                 port {
2542                                         etr_in: endpoint {
2543                                                 remote-endpoint =
2544                                                   <&replicator_out>;
2545                                         };
2546                                 };
2547                         };
2548                 };
2549
2550                 etm@7040000 {
2551                         compatible = "arm,coresight-etm4x", "arm,primecell";
2552                         reg = <0 0x07040000 0 0x1000>;
2553
2554                         cpu = <&CPU0>;
2555
2556                         clocks = <&aoss_qmp>;
2557                         clock-names = "apb_pclk";
2558
2559                         out-ports {
2560                                 port {
2561                                         etm0_out: endpoint {
2562                                                 remote-endpoint =
2563                                                   <&apss_funnel_in0>;
2564                                         };
2565                                 };
2566                         };
2567                 };
2568
2569                 etm@7140000 {
2570                         compatible = "arm,coresight-etm4x", "arm,primecell";
2571                         reg = <0 0x07140000 0 0x1000>;
2572
2573                         cpu = <&CPU1>;
2574
2575                         clocks = <&aoss_qmp>;
2576                         clock-names = "apb_pclk";
2577
2578                         out-ports {
2579                                 port {
2580                                         etm1_out: endpoint {
2581                                                 remote-endpoint =
2582                                                   <&apss_funnel_in1>;
2583                                         };
2584                                 };
2585                         };
2586                 };
2587
2588                 etm@7240000 {
2589                         compatible = "arm,coresight-etm4x", "arm,primecell";
2590                         reg = <0 0x07240000 0 0x1000>;
2591
2592                         cpu = <&CPU2>;
2593
2594                         clocks = <&aoss_qmp>;
2595                         clock-names = "apb_pclk";
2596
2597                         out-ports {
2598                                 port {
2599                                         etm2_out: endpoint {
2600                                                 remote-endpoint =
2601                                                   <&apss_funnel_in2>;
2602                                         };
2603                                 };
2604                         };
2605                 };
2606
2607                 etm@7340000 {
2608                         compatible = "arm,coresight-etm4x", "arm,primecell";
2609                         reg = <0 0x07340000 0 0x1000>;
2610
2611                         cpu = <&CPU3>;
2612
2613                         clocks = <&aoss_qmp>;
2614                         clock-names = "apb_pclk";
2615
2616                         out-ports {
2617                                 port {
2618                                         etm3_out: endpoint {
2619                                                 remote-endpoint =
2620                                                   <&apss_funnel_in3>;
2621                                         };
2622                                 };
2623                         };
2624                 };
2625
2626                 etm@7440000 {
2627                         compatible = "arm,coresight-etm4x", "arm,primecell";
2628                         reg = <0 0x07440000 0 0x1000>;
2629
2630                         cpu = <&CPU4>;
2631
2632                         clocks = <&aoss_qmp>;
2633                         clock-names = "apb_pclk";
2634
2635                         out-ports {
2636                                 port {
2637                                         etm4_out: endpoint {
2638                                                 remote-endpoint =
2639                                                   <&apss_funnel_in4>;
2640                                         };
2641                                 };
2642                         };
2643                 };
2644
2645                 etm@7540000 {
2646                         compatible = "arm,coresight-etm4x", "arm,primecell";
2647                         reg = <0 0x07540000 0 0x1000>;
2648
2649                         cpu = <&CPU5>;
2650
2651                         clocks = <&aoss_qmp>;
2652                         clock-names = "apb_pclk";
2653
2654                         out-ports {
2655                                 port {
2656                                         etm5_out: endpoint {
2657                                                 remote-endpoint =
2658                                                   <&apss_funnel_in5>;
2659                                         };
2660                                 };
2661                         };
2662                 };
2663
2664                 etm@7640000 {
2665                         compatible = "arm,coresight-etm4x", "arm,primecell";
2666                         reg = <0 0x07640000 0 0x1000>;
2667
2668                         cpu = <&CPU6>;
2669
2670                         clocks = <&aoss_qmp>;
2671                         clock-names = "apb_pclk";
2672
2673                         out-ports {
2674                                 port {
2675                                         etm6_out: endpoint {
2676                                                 remote-endpoint =
2677                                                   <&apss_funnel_in6>;
2678                                         };
2679                                 };
2680                         };
2681                 };
2682
2683                 etm@7740000 {
2684                         compatible = "arm,coresight-etm4x", "arm,primecell";
2685                         reg = <0 0x07740000 0 0x1000>;
2686
2687                         cpu = <&CPU7>;
2688
2689                         clocks = <&aoss_qmp>;
2690                         clock-names = "apb_pclk";
2691
2692                         out-ports {
2693                                 port {
2694                                         etm7_out: endpoint {
2695                                                 remote-endpoint =
2696                                                   <&apss_funnel_in7>;
2697                                         };
2698                                 };
2699                         };
2700                 };
2701
2702                 funnel@7800000 { /* APSS Funnel */
2703                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2704                         reg = <0 0x07800000 0 0x1000>;
2705
2706                         clocks = <&aoss_qmp>;
2707                         clock-names = "apb_pclk";
2708
2709                         out-ports {
2710                                 port {
2711                                         apss_funnel_out: endpoint {
2712                                                 remote-endpoint =
2713                                                   <&apss_merge_funnel_in>;
2714                                         };
2715                                 };
2716                         };
2717
2718                         in-ports {
2719                                 #address-cells = <1>;
2720                                 #size-cells = <0>;
2721
2722                                 port@0 {
2723                                         reg = <0>;
2724                                         apss_funnel_in0: endpoint {
2725                                                 remote-endpoint =
2726                                                   <&etm0_out>;
2727                                         };
2728                                 };
2729
2730                                 port@1 {
2731                                         reg = <1>;
2732                                         apss_funnel_in1: endpoint {
2733                                                 remote-endpoint =
2734                                                   <&etm1_out>;
2735                                         };
2736                                 };
2737
2738                                 port@2 {
2739                                         reg = <2>;
2740                                         apss_funnel_in2: endpoint {
2741                                                 remote-endpoint =
2742                                                   <&etm2_out>;
2743                                         };
2744                                 };
2745
2746                                 port@3 {
2747                                         reg = <3>;
2748                                         apss_funnel_in3: endpoint {
2749                                                 remote-endpoint =
2750                                                   <&etm3_out>;
2751                                         };
2752                                 };
2753
2754                                 port@4 {
2755                                         reg = <4>;
2756                                         apss_funnel_in4: endpoint {
2757                                                 remote-endpoint =
2758                                                   <&etm4_out>;
2759                                         };
2760                                 };
2761
2762                                 port@5 {
2763                                         reg = <5>;
2764                                         apss_funnel_in5: endpoint {
2765                                                 remote-endpoint =
2766                                                   <&etm5_out>;
2767                                         };
2768                                 };
2769
2770                                 port@6 {
2771                                         reg = <6>;
2772                                         apss_funnel_in6: endpoint {
2773                                                 remote-endpoint =
2774                                                   <&etm6_out>;
2775                                         };
2776                                 };
2777
2778                                 port@7 {
2779                                         reg = <7>;
2780                                         apss_funnel_in7: endpoint {
2781                                                 remote-endpoint =
2782                                                   <&etm7_out>;
2783                                         };
2784                                 };
2785                         };
2786                 };
2787
2788                 funnel@7810000 {
2789                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2790                         reg = <0 0x07810000 0 0x1000>;
2791
2792                         clocks = <&aoss_qmp>;
2793                         clock-names = "apb_pclk";
2794
2795                         out-ports {
2796                                 port {
2797                                         apss_merge_funnel_out: endpoint {
2798                                                 remote-endpoint =
2799                                                   <&funnel2_in5>;
2800                                         };
2801                                 };
2802                         };
2803
2804                         in-ports {
2805                                 port {
2806                                         apss_merge_funnel_in: endpoint {
2807                                                 remote-endpoint =
2808                                                   <&apss_funnel_out>;
2809                                         };
2810                                 };
2811                         };
2812                 };
2813
2814                 sdhc_2: sdhci@8804000 {
2815                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
2816                         reg = <0 0x08804000 0 0x1000>;
2817
2818                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2819                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2820                         interrupt-names = "hc_irq", "pwr_irq";
2821
2822                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2823                                  <&gcc GCC_SDCC2_APPS_CLK>;
2824                         clock-names = "iface", "core";
2825                         iommus = <&apps_smmu 0xa0 0xf>;
2826
2827                         status = "disabled";
2828                 };
2829
2830                 qspi: spi@88df000 {
2831                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
2832                         reg = <0 0x088df000 0 0x600>;
2833                         #address-cells = <1>;
2834                         #size-cells = <0>;
2835                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2836                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2837                                  <&gcc GCC_QSPI_CORE_CLK>;
2838                         clock-names = "iface", "core";
2839                         status = "disabled";
2840                 };
2841
2842                 slim: slim@171c0000 {
2843                         compatible = "qcom,slim-ngd-v2.1.0";
2844                         reg = <0 0x171c0000 0 0x2c000>;
2845                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
2846
2847                         qcom,apps-ch-pipes = <0x780000>;
2848                         qcom,ea-pc = <0x270>;
2849                         status = "okay";
2850                         dmas =  <&slimbam 3>, <&slimbam 4>,
2851                                 <&slimbam 5>, <&slimbam 6>;
2852                         dma-names = "rx", "tx", "tx2", "rx2";
2853
2854                         iommus = <&apps_smmu 0x1806 0x0>;
2855                         #address-cells = <1>;
2856                         #size-cells = <0>;
2857
2858                         ngd@1 {
2859                                 reg = <1>;
2860                                 #address-cells = <2>;
2861                                 #size-cells = <0>;
2862
2863                                 wcd9340_ifd: ifd@0{
2864                                         compatible = "slim217,250";
2865                                         reg  = <0 0>;
2866                                 };
2867
2868                                 wcd9340: codec@1{
2869                                         compatible = "slim217,250";
2870                                         reg  = <1 0>;
2871                                         slim-ifc-dev  = <&wcd9340_ifd>;
2872
2873                                         #sound-dai-cells = <1>;
2874
2875                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
2876                                         interrupt-controller;
2877                                         #interrupt-cells = <1>;
2878
2879                                         #clock-cells = <0>;
2880                                         clock-frequency = <9600000>;
2881                                         clock-output-names = "mclk";
2882                                         qcom,micbias1-millivolt = <1800>;
2883                                         qcom,micbias2-millivolt = <1800>;
2884                                         qcom,micbias3-millivolt = <1800>;
2885                                         qcom,micbias4-millivolt = <1800>;
2886
2887                                         #address-cells = <1>;
2888                                         #size-cells = <1>;
2889
2890                                         wcdgpio: gpio-controller@42 {
2891                                                 compatible = "qcom,wcd9340-gpio";
2892                                                 gpio-controller;
2893                                                 #gpio-cells = <2>;
2894                                                 reg = <0x42 0x2>;
2895                                         };
2896
2897                                         swm: swm@c85 {
2898                                                 compatible = "qcom,soundwire-v1.3.0";
2899                                                 reg = <0xc85 0x40>;
2900                                                 interrupts-extended = <&wcd9340 20>;
2901
2902                                                 qcom,dout-ports = <6>;
2903                                                 qcom,din-ports  = <2>;
2904                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
2905                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
2906                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
2907
2908                                                 #sound-dai-cells = <1>;
2909                                                 clocks = <&wcd9340>;
2910                                                 clock-names = "iface";
2911                                                 #address-cells = <2>;
2912                                                 #size-cells = <0>;
2913
2914
2915                                         };
2916                                 };
2917                         };
2918                 };
2919
2920                 sound: sound {
2921                 };
2922
2923                 usb_1_hsphy: phy@88e2000 {
2924                         compatible = "qcom,sdm845-qusb2-phy";
2925                         reg = <0 0x088e2000 0 0x400>;
2926                         status = "disabled";
2927                         #phy-cells = <0>;
2928
2929                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2930                                  <&rpmhcc RPMH_CXO_CLK>;
2931                         clock-names = "cfg_ahb", "ref";
2932
2933                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2934
2935                         nvmem-cells = <&qusb2p_hstx_trim>;
2936                 };
2937
2938                 usb_2_hsphy: phy@88e3000 {
2939                         compatible = "qcom,sdm845-qusb2-phy";
2940                         reg = <0 0x088e3000 0 0x400>;
2941                         status = "disabled";
2942                         #phy-cells = <0>;
2943
2944                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2945                                  <&rpmhcc RPMH_CXO_CLK>;
2946                         clock-names = "cfg_ahb", "ref";
2947
2948                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2949
2950                         nvmem-cells = <&qusb2s_hstx_trim>;
2951                 };
2952
2953                 usb_1_qmpphy: phy@88e9000 {
2954                         compatible = "qcom,sdm845-qmp-usb3-phy";
2955                         reg = <0 0x088e9000 0 0x18c>,
2956                               <0 0x088e8000 0 0x10>;
2957                         reg-names = "reg-base", "dp_com";
2958                         status = "disabled";
2959                         #clock-cells = <1>;
2960                         #address-cells = <2>;
2961                         #size-cells = <2>;
2962                         ranges;
2963
2964                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2965                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2966                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2967                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2968                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2969
2970                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2971                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2972                         reset-names = "phy", "common";
2973
2974                         usb_1_ssphy: lanes@88e9200 {
2975                                 reg = <0 0x088e9200 0 0x128>,
2976                                       <0 0x088e9400 0 0x200>,
2977                                       <0 0x088e9c00 0 0x218>,
2978                                       <0 0x088e9600 0 0x128>,
2979                                       <0 0x088e9800 0 0x200>,
2980                                       <0 0x088e9a00 0 0x100>;
2981                                 #phy-cells = <0>;
2982                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2983                                 clock-names = "pipe0";
2984                                 clock-output-names = "usb3_phy_pipe_clk_src";
2985                         };
2986                 };
2987
2988                 usb_2_qmpphy: phy@88eb000 {
2989                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
2990                         reg = <0 0x088eb000 0 0x18c>;
2991                         status = "disabled";
2992                         #clock-cells = <1>;
2993                         #address-cells = <2>;
2994                         #size-cells = <2>;
2995                         ranges;
2996
2997                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2998                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2999                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3000                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3001                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3002
3003                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3004                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3005                         reset-names = "phy", "common";
3006
3007                         usb_2_ssphy: lane@88eb200 {
3008                                 reg = <0 0x088eb200 0 0x128>,
3009                                       <0 0x088eb400 0 0x1fc>,
3010                                       <0 0x088eb800 0 0x218>,
3011                                       <0 0x088eb600 0 0x70>;
3012                                 #phy-cells = <0>;
3013                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3014                                 clock-names = "pipe0";
3015                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3016                         };
3017                 };
3018
3019                 usb_1: usb@a6f8800 {
3020                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3021                         reg = <0 0x0a6f8800 0 0x400>;
3022                         status = "disabled";
3023                         #address-cells = <2>;
3024                         #size-cells = <2>;
3025                         ranges;
3026                         dma-ranges;
3027
3028                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3029                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3030                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3031                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3032                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3033                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3034                                       "sleep";
3035
3036                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038                         assigned-clock-rates = <19200000>, <150000000>;
3039
3040                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3041                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3042                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3043                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3044                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3045                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3046
3047                         power-domains = <&gcc USB30_PRIM_GDSC>;
3048
3049                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3050
3051                         usb_1_dwc3: dwc3@a600000 {
3052                                 compatible = "snps,dwc3";
3053                                 reg = <0 0x0a600000 0 0xcd00>;
3054                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3055                                 iommus = <&apps_smmu 0x740 0>;
3056                                 snps,dis_u2_susphy_quirk;
3057                                 snps,dis_enblslpm_quirk;
3058                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3059                                 phy-names = "usb2-phy", "usb3-phy";
3060                         };
3061                 };
3062
3063                 usb_2: usb@a8f8800 {
3064                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3065                         reg = <0 0x0a8f8800 0 0x400>;
3066                         status = "disabled";
3067                         #address-cells = <2>;
3068                         #size-cells = <2>;
3069                         ranges;
3070                         dma-ranges;
3071
3072                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3073                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3074                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3075                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3076                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3077                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3078                                       "sleep";
3079
3080                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3081                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3082                         assigned-clock-rates = <19200000>, <150000000>;
3083
3084                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3085                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3086                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3087                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3088                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3089                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3090
3091                         power-domains = <&gcc USB30_SEC_GDSC>;
3092
3093                         resets = <&gcc GCC_USB30_SEC_BCR>;
3094
3095                         usb_2_dwc3: dwc3@a800000 {
3096                                 compatible = "snps,dwc3";
3097                                 reg = <0 0x0a800000 0 0xcd00>;
3098                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3099                                 iommus = <&apps_smmu 0x760 0>;
3100                                 snps,dis_u2_susphy_quirk;
3101                                 snps,dis_enblslpm_quirk;
3102                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3103                                 phy-names = "usb2-phy", "usb3-phy";
3104                         };
3105                 };
3106
3107                 venus: video-codec@aa00000 {
3108                         compatible = "qcom,sdm845-venus-v2";
3109                         reg = <0 0x0aa00000 0 0xff000>;
3110                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3111                         power-domains = <&videocc VENUS_GDSC>,
3112                                         <&videocc VCODEC0_GDSC>,
3113                                         <&videocc VCODEC1_GDSC>;
3114                         power-domain-names = "venus", "vcodec0", "vcodec1";
3115                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3116                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3117                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3118                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3119                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3120                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3121                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3122                         clock-names = "core", "iface", "bus",
3123                                       "vcodec0_core", "vcodec0_bus",
3124                                       "vcodec1_core", "vcodec1_bus";
3125                         iommus = <&apps_smmu 0x10a0 0x8>,
3126                                  <&apps_smmu 0x10b0 0x0>;
3127                         memory-region = <&venus_mem>;
3128
3129                         video-core0 {
3130                                 compatible = "venus-decoder";
3131                         };
3132
3133                         video-core1 {
3134                                 compatible = "venus-encoder";
3135                         };
3136                 };
3137
3138                 videocc: clock-controller@ab00000 {
3139                         compatible = "qcom,sdm845-videocc";
3140                         reg = <0 0x0ab00000 0 0x10000>;
3141                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3142                         clock-names = "bi_tcxo";
3143                         #clock-cells = <1>;
3144                         #power-domain-cells = <1>;
3145                         #reset-cells = <1>;
3146                 };
3147
3148                 mdss: mdss@ae00000 {
3149                         compatible = "qcom,sdm845-mdss";
3150                         reg = <0 0x0ae00000 0 0x1000>;
3151                         reg-names = "mdss";
3152
3153                         power-domains = <&dispcc MDSS_GDSC>;
3154
3155                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3156                                  <&gcc GCC_DISP_AXI_CLK>,
3157                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3158                         clock-names = "iface", "bus", "core";
3159
3160                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
3161                         assigned-clock-rates = <300000000>;
3162
3163                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3164                         interrupt-controller;
3165                         #interrupt-cells = <1>;
3166
3167                         iommus = <&apps_smmu 0x880 0x8>,
3168                                  <&apps_smmu 0xc80 0x8>;
3169
3170                         status = "disabled";
3171
3172                         #address-cells = <2>;
3173                         #size-cells = <2>;
3174                         ranges;
3175
3176                         mdss_mdp: mdp@ae01000 {
3177                                 compatible = "qcom,sdm845-dpu";
3178                                 reg = <0 0x0ae01000 0 0x8f000>,
3179                                       <0 0x0aeb0000 0 0x2008>;
3180                                 reg-names = "mdp", "vbif";
3181
3182                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3183                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
3184                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3185                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3186                                 clock-names = "iface", "bus", "core", "vsync";
3187
3188                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3189                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3190                                 assigned-clock-rates = <300000000>,
3191                                                        <19200000>;
3192
3193                                 interrupt-parent = <&mdss>;
3194                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3195
3196                                 status = "disabled";
3197
3198                                 ports {
3199                                         #address-cells = <1>;
3200                                         #size-cells = <0>;
3201
3202                                         port@0 {
3203                                                 reg = <0>;
3204                                                 dpu_intf1_out: endpoint {
3205                                                         remote-endpoint = <&dsi0_in>;
3206                                                 };
3207                                         };
3208
3209                                         port@1 {
3210                                                 reg = <1>;
3211                                                 dpu_intf2_out: endpoint {
3212                                                         remote-endpoint = <&dsi1_in>;
3213                                                 };
3214                                         };
3215                                 };
3216                         };
3217
3218                         dsi0: dsi@ae94000 {
3219                                 compatible = "qcom,mdss-dsi-ctrl";
3220                                 reg = <0 0x0ae94000 0 0x400>;
3221                                 reg-names = "dsi_ctrl";
3222
3223                                 interrupt-parent = <&mdss>;
3224                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
3225
3226                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3227                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3228                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3229                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3230                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3231                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
3232                                 clock-names = "byte",
3233                                               "byte_intf",
3234                                               "pixel",
3235                                               "core",
3236                                               "iface",
3237                                               "bus";
3238
3239                                 phys = <&dsi0_phy>;
3240                                 phy-names = "dsi";
3241
3242                                 status = "disabled";
3243
3244                                 ports {
3245                                         #address-cells = <1>;
3246                                         #size-cells = <0>;
3247
3248                                         port@0 {
3249                                                 reg = <0>;
3250                                                 dsi0_in: endpoint {
3251                                                         remote-endpoint = <&dpu_intf1_out>;
3252                                                 };
3253                                         };
3254
3255                                         port@1 {
3256                                                 reg = <1>;
3257                                                 dsi0_out: endpoint {
3258                                                 };
3259                                         };
3260                                 };
3261                         };
3262
3263                         dsi0_phy: dsi-phy@ae94400 {
3264                                 compatible = "qcom,dsi-phy-10nm";
3265                                 reg = <0 0x0ae94400 0 0x200>,
3266                                       <0 0x0ae94600 0 0x280>,
3267                                       <0 0x0ae94a00 0 0x1e0>;
3268                                 reg-names = "dsi_phy",
3269                                             "dsi_phy_lane",
3270                                             "dsi_pll";
3271
3272                                 #clock-cells = <1>;
3273                                 #phy-cells = <0>;
3274
3275                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3276                                          <&rpmhcc RPMH_CXO_CLK>;
3277                                 clock-names = "iface", "ref";
3278
3279                                 status = "disabled";
3280                         };
3281
3282                         dsi1: dsi@ae96000 {
3283                                 compatible = "qcom,mdss-dsi-ctrl";
3284                                 reg = <0 0x0ae96000 0 0x400>;
3285                                 reg-names = "dsi_ctrl";
3286
3287                                 interrupt-parent = <&mdss>;
3288                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
3289
3290                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3291                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3292                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3293                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3294                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3295                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
3296                                 clock-names = "byte",
3297                                               "byte_intf",
3298                                               "pixel",
3299                                               "core",
3300                                               "iface",
3301                                               "bus";
3302
3303                                 phys = <&dsi1_phy>;
3304                                 phy-names = "dsi";
3305
3306                                 status = "disabled";
3307
3308                                 ports {
3309                                         #address-cells = <1>;
3310                                         #size-cells = <0>;
3311
3312                                         port@0 {
3313                                                 reg = <0>;
3314                                                 dsi1_in: endpoint {
3315                                                         remote-endpoint = <&dpu_intf2_out>;
3316                                                 };
3317                                         };
3318
3319                                         port@1 {
3320                                                 reg = <1>;
3321                                                 dsi1_out: endpoint {
3322                                                 };
3323                                         };
3324                                 };
3325                         };
3326
3327                         dsi1_phy: dsi-phy@ae96400 {
3328                                 compatible = "qcom,dsi-phy-10nm";
3329                                 reg = <0 0x0ae96400 0 0x200>,
3330                                       <0 0x0ae96600 0 0x280>,
3331                                       <0 0x0ae96a00 0 0x10e>;
3332                                 reg-names = "dsi_phy",
3333                                             "dsi_phy_lane",
3334                                             "dsi_pll";
3335
3336                                 #clock-cells = <1>;
3337                                 #phy-cells = <0>;
3338
3339                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3340                                          <&rpmhcc RPMH_CXO_CLK>;
3341                                 clock-names = "iface", "ref";
3342
3343                                 status = "disabled";
3344                         };
3345                 };
3346
3347                 gpu: gpu@5000000 {
3348                         compatible = "qcom,adreno-630.2", "qcom,adreno";
3349                         #stream-id-cells = <16>;
3350
3351                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
3352                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
3353
3354                         /*
3355                          * Look ma, no clocks! The GPU clocks and power are
3356                          * controlled entirely by the GMU
3357                          */
3358
3359                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3360
3361                         iommus = <&adreno_smmu 0>;
3362
3363                         operating-points-v2 = <&gpu_opp_table>;
3364
3365                         qcom,gmu = <&gmu>;
3366
3367                         gpu_opp_table: opp-table {
3368                                 compatible = "operating-points-v2";
3369
3370                                 opp-710000000 {
3371                                         opp-hz = /bits/ 64 <710000000>;
3372                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3373                                 };
3374
3375                                 opp-675000000 {
3376                                         opp-hz = /bits/ 64 <675000000>;
3377                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3378                                 };
3379
3380                                 opp-596000000 {
3381                                         opp-hz = /bits/ 64 <596000000>;
3382                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3383                                 };
3384
3385                                 opp-520000000 {
3386                                         opp-hz = /bits/ 64 <520000000>;
3387                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3388                                 };
3389
3390                                 opp-414000000 {
3391                                         opp-hz = /bits/ 64 <414000000>;
3392                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3393                                 };
3394
3395                                 opp-342000000 {
3396                                         opp-hz = /bits/ 64 <342000000>;
3397                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3398                                 };
3399
3400                                 opp-257000000 {
3401                                         opp-hz = /bits/ 64 <257000000>;
3402                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3403                                 };
3404                         };
3405                 };
3406
3407                 adreno_smmu: iommu@5040000 {
3408                         compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
3409                         reg = <0 0x5040000 0 0x10000>;
3410                         #iommu-cells = <1>;
3411                         #global-interrupts = <2>;
3412                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
3413                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
3414                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
3415                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
3416                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
3417                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
3418                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
3419                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
3420                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
3421                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
3422                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3423                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
3424                         clock-names = "bus", "iface";
3425
3426                         power-domains = <&gpucc GPU_CX_GDSC>;
3427                 };
3428
3429                 gmu: gmu@506a000 {
3430                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
3431
3432                         reg = <0 0x506a000 0 0x30000>,
3433                               <0 0xb280000 0 0x10000>,
3434                               <0 0xb480000 0 0x10000>;
3435                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
3436
3437                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3438                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3439                         interrupt-names = "hfi", "gmu";
3440
3441                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
3442                                  <&gpucc GPU_CC_CXO_CLK>,
3443                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3444                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3445                         clock-names = "gmu", "cxo", "axi", "memnoc";
3446
3447                         power-domains = <&gpucc GPU_CX_GDSC>,
3448                                         <&gpucc GPU_GX_GDSC>;
3449                         power-domain-names = "cx", "gx";
3450
3451                         iommus = <&adreno_smmu 5>;
3452
3453                         operating-points-v2 = <&gmu_opp_table>;
3454
3455                         gmu_opp_table: opp-table {
3456                                 compatible = "operating-points-v2";
3457
3458                                 opp-400000000 {
3459                                         opp-hz = /bits/ 64 <400000000>;
3460                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3461                                 };
3462
3463                                 opp-200000000 {
3464                                         opp-hz = /bits/ 64 <200000000>;
3465                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3466                                 };
3467                         };
3468                 };
3469
3470                 dispcc: clock-controller@af00000 {
3471                         compatible = "qcom,sdm845-dispcc";
3472                         reg = <0 0x0af00000 0 0x10000>;
3473                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3474                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3475                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
3476                                  <&dsi0_phy 0>,
3477                                  <&dsi0_phy 1>,
3478                                  <&dsi1_phy 0>,
3479                                  <&dsi1_phy 1>,
3480                                  <0>,
3481                                  <0>;
3482                         clock-names = "bi_tcxo",
3483                                       "gcc_disp_gpll0_clk_src",
3484                                       "gcc_disp_gpll0_div_clk_src",
3485                                       "dsi0_phy_pll_out_byteclk",
3486                                       "dsi0_phy_pll_out_dsiclk",
3487                                       "dsi1_phy_pll_out_byteclk",
3488                                       "dsi1_phy_pll_out_dsiclk",
3489                                       "dp_link_clk_divsel_ten",
3490                                       "dp_vco_divided_clk_src_mux";
3491                         #clock-cells = <1>;
3492                         #reset-cells = <1>;
3493                         #power-domain-cells = <1>;
3494                 };
3495
3496                 pdc_intc: interrupt-controller@b220000 {
3497                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
3498                         reg = <0 0x0b220000 0 0x30000>;
3499                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
3500                         #interrupt-cells = <2>;
3501                         interrupt-parent = <&intc>;
3502                         interrupt-controller;
3503                 };
3504
3505                 pdc_reset: reset-controller@b2e0000 {
3506                         compatible = "qcom,sdm845-pdc-global";
3507                         reg = <0 0x0b2e0000 0 0x20000>;
3508                         #reset-cells = <1>;
3509                 };
3510
3511                 tsens0: thermal-sensor@c263000 {
3512                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
3513                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3514                               <0 0x0c222000 0 0x1ff>; /* SROT */
3515                         #qcom,sensors = <13>;
3516                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3517                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3518                         interrupt-names = "uplow", "critical";
3519                         #thermal-sensor-cells = <1>;
3520                 };
3521
3522                 tsens1: thermal-sensor@c265000 {
3523                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
3524                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3525                               <0 0x0c223000 0 0x1ff>; /* SROT */
3526                         #qcom,sensors = <8>;
3527                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3528                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3529                         interrupt-names = "uplow", "critical";
3530                         #thermal-sensor-cells = <1>;
3531                 };
3532
3533                 aoss_reset: reset-controller@c2a0000 {
3534                         compatible = "qcom,sdm845-aoss-cc";
3535                         reg = <0 0x0c2a0000 0 0x31000>;
3536                         #reset-cells = <1>;
3537                 };
3538
3539                 aoss_qmp: qmp@c300000 {
3540                         compatible = "qcom,sdm845-aoss-qmp";
3541                         reg = <0 0x0c300000 0 0x100000>;
3542                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3543                         mboxes = <&apss_shared 0>;
3544
3545                         #clock-cells = <0>;
3546                         #power-domain-cells = <1>;
3547
3548                         cx_cdev: cx {
3549                                 #cooling-cells = <2>;
3550                         };
3551
3552                         ebi_cdev: ebi {
3553                                 #cooling-cells = <2>;
3554                         };
3555                 };
3556
3557                 spmi_bus: spmi@c440000 {
3558                         compatible = "qcom,spmi-pmic-arb";
3559                         reg = <0 0x0c440000 0 0x1100>,
3560                               <0 0x0c600000 0 0x2000000>,
3561                               <0 0x0e600000 0 0x100000>,
3562                               <0 0x0e700000 0 0xa0000>,
3563                               <0 0x0c40a000 0 0x26000>;
3564                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3565                         interrupt-names = "periph_irq";
3566                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3567                         qcom,ee = <0>;
3568                         qcom,channel = <0>;
3569                         #address-cells = <2>;
3570                         #size-cells = <0>;
3571                         interrupt-controller;
3572                         #interrupt-cells = <4>;
3573                         cell-index = <0>;
3574                 };
3575
3576                 apps_smmu: iommu@15000000 {
3577                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
3578                         reg = <0 0x15000000 0 0x80000>;
3579                         #iommu-cells = <2>;
3580                         #global-interrupts = <1>;
3581                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3582                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3583                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3584                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3585                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3586                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3587                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3588                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3589                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3590                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3591                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3592                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3593                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3594                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3595                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3596                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3597                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3598                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3599                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3600                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3601                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3602                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3603                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3604                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3605                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3606                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3607                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3608                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3609                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3610                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3611                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3612                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3613                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3614                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3615                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3616                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3617                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3618                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3619                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3620                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3621                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3622                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3623                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3624                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3625                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3626                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3627                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3628                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3629                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3630                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3631                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3632                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3633                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3634                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3635                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3636                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3637                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3638                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3639                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3640                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3641                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3642                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3643                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3644                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3645                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
3646                 };
3647
3648                 lpasscc: clock-controller@17014000 {
3649                         compatible = "qcom,sdm845-lpasscc";
3650                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
3651                         reg-names = "cc", "qdsp6ss";
3652                         #clock-cells = <1>;
3653                         status = "disabled";
3654                 };
3655
3656                 gladiator_noc: interconnect@17900000 {
3657                         compatible = "qcom,sdm845-gladiator-noc";
3658                         reg = <0 0x17900000 0 0xd080>;
3659                         #interconnect-cells = <1>;
3660                         qcom,bcm-voters = <&apps_bcm_voter>;
3661                 };
3662
3663                 watchdog@17980000 {
3664                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
3665                         reg = <0 0x17980000 0 0x1000>;
3666                         clocks = <&sleep_clk>;
3667                 };
3668
3669                 apss_shared: mailbox@17990000 {
3670                         compatible = "qcom,sdm845-apss-shared";
3671                         reg = <0 0x17990000 0 0x1000>;
3672                         #mbox-cells = <1>;
3673                 };
3674
3675                 apps_rsc: rsc@179c0000 {
3676                         label = "apps_rsc";
3677                         compatible = "qcom,rpmh-rsc";
3678                         reg = <0 0x179c0000 0 0x10000>,
3679                               <0 0x179d0000 0 0x10000>,
3680                               <0 0x179e0000 0 0x10000>;
3681                         reg-names = "drv-0", "drv-1", "drv-2";
3682                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3683                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3684                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3685                         qcom,tcs-offset = <0xd00>;
3686                         qcom,drv-id = <2>;
3687                         qcom,tcs-config = <ACTIVE_TCS  2>,
3688                                           <SLEEP_TCS   3>,
3689                                           <WAKE_TCS    3>,
3690                                           <CONTROL_TCS 1>;
3691
3692                         apps_bcm_voter: bcm-voter {
3693                                 compatible = "qcom,bcm-voter";
3694                         };
3695
3696                         rpmhcc: clock-controller {
3697                                 compatible = "qcom,sdm845-rpmh-clk";
3698                                 #clock-cells = <1>;
3699                                 clock-names = "xo";
3700                                 clocks = <&xo_board>;
3701                         };
3702
3703                         rpmhpd: power-controller {
3704                                 compatible = "qcom,sdm845-rpmhpd";
3705                                 #power-domain-cells = <1>;
3706                                 operating-points-v2 = <&rpmhpd_opp_table>;
3707
3708                                 rpmhpd_opp_table: opp-table {
3709                                         compatible = "operating-points-v2";
3710
3711                                         rpmhpd_opp_ret: opp1 {
3712                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3713                                         };
3714
3715                                         rpmhpd_opp_min_svs: opp2 {
3716                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3717                                         };
3718
3719                                         rpmhpd_opp_low_svs: opp3 {
3720                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3721                                         };
3722
3723                                         rpmhpd_opp_svs: opp4 {
3724                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3725                                         };
3726
3727                                         rpmhpd_opp_svs_l1: opp5 {
3728                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3729                                         };
3730
3731                                         rpmhpd_opp_nom: opp6 {
3732                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3733                                         };
3734
3735                                         rpmhpd_opp_nom_l1: opp7 {
3736                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3737                                         };
3738
3739                                         rpmhpd_opp_nom_l2: opp8 {
3740                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3741                                         };
3742
3743                                         rpmhpd_opp_turbo: opp9 {
3744                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3745                                         };
3746
3747                                         rpmhpd_opp_turbo_l1: opp10 {
3748                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3749                                         };
3750                                 };
3751                         };
3752                 };
3753
3754                 intc: interrupt-controller@17a00000 {
3755                         compatible = "arm,gic-v3";
3756                         #address-cells = <2>;
3757                         #size-cells = <2>;
3758                         ranges;
3759                         #interrupt-cells = <3>;
3760                         interrupt-controller;
3761                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3762                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3763                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3764
3765                         msi-controller@17a40000 {
3766                                 compatible = "arm,gic-v3-its";
3767                                 msi-controller;
3768                                 #msi-cells = <1>;
3769                                 reg = <0 0x17a40000 0 0x20000>;
3770                                 status = "disabled";
3771                         };
3772                 };
3773
3774                 slimbam: dma@17184000 {
3775                         compatible = "qcom,bam-v1.7.0";
3776                         qcom,controlled-remotely;
3777                         reg = <0 0x17184000 0 0x2a000>;
3778                         num-channels  = <31>;
3779                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3780                         #dma-cells = <1>;
3781                         qcom,ee = <1>;
3782                         qcom,num-ees = <2>;
3783                         iommus = <&apps_smmu 0x1806 0x0>;
3784                 };
3785
3786                 timer@17c90000 {
3787                         #address-cells = <2>;
3788                         #size-cells = <2>;
3789                         ranges;
3790                         compatible = "arm,armv7-timer-mem";
3791                         reg = <0 0x17c90000 0 0x1000>;
3792
3793                         frame@17ca0000 {
3794                                 frame-number = <0>;
3795                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
3796                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3797                                 reg = <0 0x17ca0000 0 0x1000>,
3798                                       <0 0x17cb0000 0 0x1000>;
3799                         };
3800
3801                         frame@17cc0000 {
3802                                 frame-number = <1>;
3803                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
3804                                 reg = <0 0x17cc0000 0 0x1000>;
3805                                 status = "disabled";
3806                         };
3807
3808                         frame@17cd0000 {
3809                                 frame-number = <2>;
3810                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3811                                 reg = <0 0x17cd0000 0 0x1000>;
3812                                 status = "disabled";
3813                         };
3814
3815                         frame@17ce0000 {
3816                                 frame-number = <3>;
3817                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3818                                 reg = <0 0x17ce0000 0 0x1000>;
3819                                 status = "disabled";
3820                         };
3821
3822                         frame@17cf0000 {
3823                                 frame-number = <4>;
3824                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3825                                 reg = <0 0x17cf0000 0 0x1000>;
3826                                 status = "disabled";
3827                         };
3828
3829                         frame@17d00000 {
3830                                 frame-number = <5>;
3831                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3832                                 reg = <0 0x17d00000 0 0x1000>;
3833                                 status = "disabled";
3834                         };
3835
3836                         frame@17d10000 {
3837                                 frame-number = <6>;
3838                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3839                                 reg = <0 0x17d10000 0 0x1000>;
3840                                 status = "disabled";
3841                         };
3842                 };
3843
3844                 osm_l3: interconnect@17d41000 {
3845                         compatible = "qcom,sdm845-osm-l3";
3846                         reg = <0 0x17d41000 0 0x1400>;
3847
3848                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3849                         clock-names = "xo", "alternate";
3850
3851                         #interconnect-cells = <1>;
3852                 };
3853
3854                 cpufreq_hw: cpufreq@17d43000 {
3855                         compatible = "qcom,cpufreq-hw";
3856                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
3857                         reg-names = "freq-domain0", "freq-domain1";
3858
3859                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3860                         clock-names = "xo", "alternate";
3861
3862                         #freq-domain-cells = <1>;
3863                 };
3864
3865                 wifi: wifi@18800000 {
3866                         compatible = "qcom,wcn3990-wifi";
3867                         status = "disabled";
3868                         reg = <0 0x18800000 0 0x800000>;
3869                         reg-names = "membase";
3870                         memory-region = <&wlan_msa_mem>;
3871                         clock-names = "cxo_ref_clk_pin";
3872                         clocks = <&rpmhcc RPMH_RF_CLK2>;
3873                         interrupts =
3874                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3875                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3876                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3877                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3878                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3879                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3880                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3881                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3882                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3883                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3884                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3885                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3886                         iommus = <&apps_smmu 0x0040 0x1>;
3887                 };
3888         };
3889
3890         thermal-zones {
3891                 cpu0-thermal {
3892                         polling-delay-passive = <250>;
3893                         polling-delay = <1000>;
3894
3895                         thermal-sensors = <&tsens0 1>;
3896
3897                         trips {
3898                                 cpu0_alert0: trip-point0 {
3899                                         temperature = <90000>;
3900                                         hysteresis = <2000>;
3901                                         type = "passive";
3902                                 };
3903
3904                                 cpu0_alert1: trip-point1 {
3905                                         temperature = <95000>;
3906                                         hysteresis = <2000>;
3907                                         type = "passive";
3908                                 };
3909
3910                                 cpu0_crit: cpu_crit {
3911                                         temperature = <110000>;
3912                                         hysteresis = <1000>;
3913                                         type = "critical";
3914                                 };
3915                         };
3916
3917                         cooling-maps {
3918                                 map0 {
3919                                         trip = <&cpu0_alert0>;
3920                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3921                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3922                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3923                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3924                                 };
3925                                 map1 {
3926                                         trip = <&cpu0_alert1>;
3927                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3928                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3929                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3930                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3931                                 };
3932                         };
3933                 };
3934
3935                 cpu1-thermal {
3936                         polling-delay-passive = <250>;
3937                         polling-delay = <1000>;
3938
3939                         thermal-sensors = <&tsens0 2>;
3940
3941                         trips {
3942                                 cpu1_alert0: trip-point0 {
3943                                         temperature = <90000>;
3944                                         hysteresis = <2000>;
3945                                         type = "passive";
3946                                 };
3947
3948                                 cpu1_alert1: trip-point1 {
3949                                         temperature = <95000>;
3950                                         hysteresis = <2000>;
3951                                         type = "passive";
3952                                 };
3953
3954                                 cpu1_crit: cpu_crit {
3955                                         temperature = <110000>;
3956                                         hysteresis = <1000>;
3957                                         type = "critical";
3958                                 };
3959                         };
3960
3961                         cooling-maps {
3962                                 map0 {
3963                                         trip = <&cpu1_alert0>;
3964                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3965                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3966                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3967                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3968                                 };
3969                                 map1 {
3970                                         trip = <&cpu1_alert1>;
3971                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3972                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3973                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3974                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3975                                 };
3976                         };
3977                 };
3978
3979                 cpu2-thermal {
3980                         polling-delay-passive = <250>;
3981                         polling-delay = <1000>;
3982
3983                         thermal-sensors = <&tsens0 3>;
3984
3985                         trips {
3986                                 cpu2_alert0: trip-point0 {
3987                                         temperature = <90000>;
3988                                         hysteresis = <2000>;
3989                                         type = "passive";
3990                                 };
3991
3992                                 cpu2_alert1: trip-point1 {
3993                                         temperature = <95000>;
3994                                         hysteresis = <2000>;
3995                                         type = "passive";
3996                                 };
3997
3998                                 cpu2_crit: cpu_crit {
3999                                         temperature = <110000>;
4000                                         hysteresis = <1000>;
4001                                         type = "critical";
4002                                 };
4003                         };
4004
4005                         cooling-maps {
4006                                 map0 {
4007                                         trip = <&cpu2_alert0>;
4008                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4009                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4010                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4011                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4012                                 };
4013                                 map1 {
4014                                         trip = <&cpu2_alert1>;
4015                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4016                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4017                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4018                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4019                                 };
4020                         };
4021                 };
4022
4023                 cpu3-thermal {
4024                         polling-delay-passive = <250>;
4025                         polling-delay = <1000>;
4026
4027                         thermal-sensors = <&tsens0 4>;
4028
4029                         trips {
4030                                 cpu3_alert0: trip-point0 {
4031                                         temperature = <90000>;
4032                                         hysteresis = <2000>;
4033                                         type = "passive";
4034                                 };
4035
4036                                 cpu3_alert1: trip-point1 {
4037                                         temperature = <95000>;
4038                                         hysteresis = <2000>;
4039                                         type = "passive";
4040                                 };
4041
4042                                 cpu3_crit: cpu_crit {
4043                                         temperature = <110000>;
4044                                         hysteresis = <1000>;
4045                                         type = "critical";
4046                                 };
4047                         };
4048
4049                         cooling-maps {
4050                                 map0 {
4051                                         trip = <&cpu3_alert0>;
4052                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4053                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4054                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4055                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4056                                 };
4057                                 map1 {
4058                                         trip = <&cpu3_alert1>;
4059                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4060                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4061                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4062                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4063                                 };
4064                         };
4065                 };
4066
4067                 cpu4-thermal {
4068                         polling-delay-passive = <250>;
4069                         polling-delay = <1000>;
4070
4071                         thermal-sensors = <&tsens0 7>;
4072
4073                         trips {
4074                                 cpu4_alert0: trip-point0 {
4075                                         temperature = <90000>;
4076                                         hysteresis = <2000>;
4077                                         type = "passive";
4078                                 };
4079
4080                                 cpu4_alert1: trip-point1 {
4081                                         temperature = <95000>;
4082                                         hysteresis = <2000>;
4083                                         type = "passive";
4084                                 };
4085
4086                                 cpu4_crit: cpu_crit {
4087                                         temperature = <110000>;
4088                                         hysteresis = <1000>;
4089                                         type = "critical";
4090                                 };
4091                         };
4092
4093                         cooling-maps {
4094                                 map0 {
4095                                         trip = <&cpu4_alert0>;
4096                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4097                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4098                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4099                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4100                                 };
4101                                 map1 {
4102                                         trip = <&cpu4_alert1>;
4103                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4104                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4105                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4106                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4107                                 };
4108                         };
4109                 };
4110
4111                 cpu5-thermal {
4112                         polling-delay-passive = <250>;
4113                         polling-delay = <1000>;
4114
4115                         thermal-sensors = <&tsens0 8>;
4116
4117                         trips {
4118                                 cpu5_alert0: trip-point0 {
4119                                         temperature = <90000>;
4120                                         hysteresis = <2000>;
4121                                         type = "passive";
4122                                 };
4123
4124                                 cpu5_alert1: trip-point1 {
4125                                         temperature = <95000>;
4126                                         hysteresis = <2000>;
4127                                         type = "passive";
4128                                 };
4129
4130                                 cpu5_crit: cpu_crit {
4131                                         temperature = <110000>;
4132                                         hysteresis = <1000>;
4133                                         type = "critical";
4134                                 };
4135                         };
4136
4137                         cooling-maps {
4138                                 map0 {
4139                                         trip = <&cpu5_alert0>;
4140                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4141                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4142                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4143                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4144                                 };
4145                                 map1 {
4146                                         trip = <&cpu5_alert1>;
4147                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4148                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4149                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4150                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4151                                 };
4152                         };
4153                 };
4154
4155                 cpu6-thermal {
4156                         polling-delay-passive = <250>;
4157                         polling-delay = <1000>;
4158
4159                         thermal-sensors = <&tsens0 9>;
4160
4161                         trips {
4162                                 cpu6_alert0: trip-point0 {
4163                                         temperature = <90000>;
4164                                         hysteresis = <2000>;
4165                                         type = "passive";
4166                                 };
4167
4168                                 cpu6_alert1: trip-point1 {
4169                                         temperature = <95000>;
4170                                         hysteresis = <2000>;
4171                                         type = "passive";
4172                                 };
4173
4174                                 cpu6_crit: cpu_crit {
4175                                         temperature = <110000>;
4176                                         hysteresis = <1000>;
4177                                         type = "critical";
4178                                 };
4179                         };
4180
4181                         cooling-maps {
4182                                 map0 {
4183                                         trip = <&cpu6_alert0>;
4184                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4185                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4186                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4187                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4188                                 };
4189                                 map1 {
4190                                         trip = <&cpu6_alert1>;
4191                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4192                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4193                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4194                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4195                                 };
4196                         };
4197                 };
4198
4199                 cpu7-thermal {
4200                         polling-delay-passive = <250>;
4201                         polling-delay = <1000>;
4202
4203                         thermal-sensors = <&tsens0 10>;
4204
4205                         trips {
4206                                 cpu7_alert0: trip-point0 {
4207                                         temperature = <90000>;
4208                                         hysteresis = <2000>;
4209                                         type = "passive";
4210                                 };
4211
4212                                 cpu7_alert1: trip-point1 {
4213                                         temperature = <95000>;
4214                                         hysteresis = <2000>;
4215                                         type = "passive";
4216                                 };
4217
4218                                 cpu7_crit: cpu_crit {
4219                                         temperature = <110000>;
4220                                         hysteresis = <1000>;
4221                                         type = "critical";
4222                                 };
4223                         };
4224
4225                         cooling-maps {
4226                                 map0 {
4227                                         trip = <&cpu7_alert0>;
4228                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4229                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4230                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4231                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4232                                 };
4233                                 map1 {
4234                                         trip = <&cpu7_alert1>;
4235                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4236                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4237                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4238                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4239                                 };
4240                         };
4241                 };
4242
4243                 aoss0-thermal {
4244                         polling-delay-passive = <250>;
4245                         polling-delay = <1000>;
4246
4247                         thermal-sensors = <&tsens0 0>;
4248
4249                         trips {
4250                                 aoss0_alert0: trip-point0 {
4251                                         temperature = <90000>;
4252                                         hysteresis = <2000>;
4253                                         type = "hot";
4254                                 };
4255                         };
4256                 };
4257
4258                 cluster0-thermal {
4259                         polling-delay-passive = <250>;
4260                         polling-delay = <1000>;
4261
4262                         thermal-sensors = <&tsens0 5>;
4263
4264                         trips {
4265                                 cluster0_alert0: trip-point0 {
4266                                         temperature = <90000>;
4267                                         hysteresis = <2000>;
4268                                         type = "hot";
4269                                 };
4270                                 cluster0_crit: cluster0_crit {
4271                                         temperature = <110000>;
4272                                         hysteresis = <2000>;
4273                                         type = "critical";
4274                                 };
4275                         };
4276                 };
4277
4278                 cluster1-thermal {
4279                         polling-delay-passive = <250>;
4280                         polling-delay = <1000>;
4281
4282                         thermal-sensors = <&tsens0 6>;
4283
4284                         trips {
4285                                 cluster1_alert0: trip-point0 {
4286                                         temperature = <90000>;
4287                                         hysteresis = <2000>;
4288                                         type = "hot";
4289                                 };
4290                                 cluster1_crit: cluster1_crit {
4291                                         temperature = <110000>;
4292                                         hysteresis = <2000>;
4293                                         type = "critical";
4294                                 };
4295                         };
4296                 };
4297
4298                 gpu-thermal-top {
4299                         polling-delay-passive = <250>;
4300                         polling-delay = <1000>;
4301
4302                         thermal-sensors = <&tsens0 11>;
4303
4304                         trips {
4305                                 gpu1_alert0: trip-point0 {
4306                                         temperature = <90000>;
4307                                         hysteresis = <2000>;
4308                                         type = "hot";
4309                                 };
4310                         };
4311                 };
4312
4313                 gpu-thermal-bottom {
4314                         polling-delay-passive = <250>;
4315                         polling-delay = <1000>;
4316
4317                         thermal-sensors = <&tsens0 12>;
4318
4319                         trips {
4320                                 gpu2_alert0: trip-point0 {
4321                                         temperature = <90000>;
4322                                         hysteresis = <2000>;
4323                                         type = "hot";
4324                                 };
4325                         };
4326                 };
4327
4328                 aoss1-thermal {
4329                         polling-delay-passive = <250>;
4330                         polling-delay = <1000>;
4331
4332                         thermal-sensors = <&tsens1 0>;
4333
4334                         trips {
4335                                 aoss1_alert0: trip-point0 {
4336                                         temperature = <90000>;
4337                                         hysteresis = <2000>;
4338                                         type = "hot";
4339                                 };
4340                         };
4341                 };
4342
4343                 q6-modem-thermal {
4344                         polling-delay-passive = <250>;
4345                         polling-delay = <1000>;
4346
4347                         thermal-sensors = <&tsens1 1>;
4348
4349                         trips {
4350                                 q6_modem_alert0: trip-point0 {
4351                                         temperature = <90000>;
4352                                         hysteresis = <2000>;
4353                                         type = "hot";
4354                                 };
4355                         };
4356                 };
4357
4358                 mem-thermal {
4359                         polling-delay-passive = <250>;
4360                         polling-delay = <1000>;
4361
4362                         thermal-sensors = <&tsens1 2>;
4363
4364                         trips {
4365                                 mem_alert0: trip-point0 {
4366                                         temperature = <90000>;
4367                                         hysteresis = <2000>;
4368                                         type = "hot";
4369                                 };
4370                         };
4371                 };
4372
4373                 wlan-thermal {
4374                         polling-delay-passive = <250>;
4375                         polling-delay = <1000>;
4376
4377                         thermal-sensors = <&tsens1 3>;
4378
4379                         trips {
4380                                 wlan_alert0: trip-point0 {
4381                                         temperature = <90000>;
4382                                         hysteresis = <2000>;
4383                                         type = "hot";
4384                                 };
4385                         };
4386                 };
4387
4388                 q6-hvx-thermal {
4389                         polling-delay-passive = <250>;
4390                         polling-delay = <1000>;
4391
4392                         thermal-sensors = <&tsens1 4>;
4393
4394                         trips {
4395                                 q6_hvx_alert0: trip-point0 {
4396                                         temperature = <90000>;
4397                                         hysteresis = <2000>;
4398                                         type = "hot";
4399                                 };
4400                         };
4401                 };
4402
4403                 camera-thermal {
4404                         polling-delay-passive = <250>;
4405                         polling-delay = <1000>;
4406
4407                         thermal-sensors = <&tsens1 5>;
4408
4409                         trips {
4410                                 camera_alert0: trip-point0 {
4411                                         temperature = <90000>;
4412                                         hysteresis = <2000>;
4413                                         type = "hot";
4414                                 };
4415                         };
4416                 };
4417
4418                 video-thermal {
4419                         polling-delay-passive = <250>;
4420                         polling-delay = <1000>;
4421
4422                         thermal-sensors = <&tsens1 6>;
4423
4424                         trips {
4425                                 video_alert0: trip-point0 {
4426                                         temperature = <90000>;
4427                                         hysteresis = <2000>;
4428                                         type = "hot";
4429                                 };
4430                         };
4431                 };
4432
4433                 modem-thermal {
4434                         polling-delay-passive = <250>;
4435                         polling-delay = <1000>;
4436
4437                         thermal-sensors = <&tsens1 7>;
4438
4439                         trips {
4440                                 modem_alert0: trip-point0 {
4441                                         temperature = <90000>;
4442                                         hysteresis = <2000>;
4443                                         type = "hot";
4444                                 };
4445                         };
4446                 };
4447         };
4448 };