1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sdm845.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qusb2.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
22 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
23 #include <dt-bindings/soc/qcom,apr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
72 device_type = "memory";
73 /* We expect the bootloader to fill in the size */
74 reg = <0 0x80000000 0 0>;
82 hyp_mem: memory@85700000 {
83 reg = <0 0x85700000 0 0x600000>;
87 xbl_mem: memory@85e00000 {
88 reg = <0 0x85e00000 0 0x100000>;
92 aop_mem: memory@85fc0000 {
93 reg = <0 0x85fc0000 0 0x20000>;
97 aop_cmd_db_mem: memory@85fe0000 {
98 compatible = "qcom,cmd-db";
99 reg = <0x0 0x85fe0000 0 0x20000>;
104 compatible = "qcom,smem";
105 reg = <0x0 0x86000000 0 0x200000>;
107 hwlocks = <&tcsr_mutex 3>;
110 tz_mem: memory@86200000 {
111 reg = <0 0x86200000 0 0x2d00000>;
115 rmtfs_mem: memory@88f00000 {
116 compatible = "qcom,rmtfs-mem";
117 reg = <0 0x88f00000 0 0x200000>;
120 qcom,client-id = <1>;
124 qseecom_mem: memory@8ab00000 {
125 reg = <0 0x8ab00000 0 0x1400000>;
129 camera_mem: memory@8bf00000 {
130 reg = <0 0x8bf00000 0 0x500000>;
134 ipa_fw_mem: memory@8c400000 {
135 reg = <0 0x8c400000 0 0x10000>;
139 ipa_gsi_mem: memory@8c410000 {
140 reg = <0 0x8c410000 0 0x5000>;
144 gpu_mem: memory@8c415000 {
145 reg = <0 0x8c415000 0 0x2000>;
149 adsp_mem: memory@8c500000 {
150 reg = <0 0x8c500000 0 0x1a00000>;
154 wlan_msa_mem: memory@8df00000 {
155 reg = <0 0x8df00000 0 0x100000>;
159 mpss_region: memory@8e000000 {
160 reg = <0 0x8e000000 0 0x7800000>;
164 venus_mem: memory@95800000 {
165 reg = <0 0x95800000 0 0x500000>;
169 cdsp_mem: memory@95d00000 {
170 reg = <0 0x95d00000 0 0x800000>;
174 mba_region: memory@96500000 {
175 reg = <0 0x96500000 0 0x200000>;
179 slpi_mem: memory@96700000 {
180 reg = <0 0x96700000 0 0x1400000>;
184 spss_mem: memory@97b00000 {
185 reg = <0 0x97b00000 0 0x100000>;
191 #address-cells = <2>;
196 compatible = "qcom,kryo385";
198 enable-method = "psci";
199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
202 capacity-dmips-mhz = <607>;
203 dynamic-power-coefficient = <100>;
204 qcom,freq-domain = <&cpufreq_hw 0>;
205 operating-points-v2 = <&cpu0_opp_table>;
206 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_0>;
211 compatible = "cache";
212 next-level-cache = <&L3_0>;
214 compatible = "cache";
221 compatible = "qcom,kryo385";
223 enable-method = "psci";
224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
227 capacity-dmips-mhz = <607>;
228 dynamic-power-coefficient = <100>;
229 qcom,freq-domain = <&cpufreq_hw 0>;
230 operating-points-v2 = <&cpu0_opp_table>;
231 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
233 #cooling-cells = <2>;
234 next-level-cache = <&L2_100>;
236 compatible = "cache";
237 next-level-cache = <&L3_0>;
243 compatible = "qcom,kryo385";
245 enable-method = "psci";
246 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
249 capacity-dmips-mhz = <607>;
250 dynamic-power-coefficient = <100>;
251 qcom,freq-domain = <&cpufreq_hw 0>;
252 operating-points-v2 = <&cpu0_opp_table>;
253 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 #cooling-cells = <2>;
256 next-level-cache = <&L2_200>;
258 compatible = "cache";
259 next-level-cache = <&L3_0>;
265 compatible = "qcom,kryo385";
267 enable-method = "psci";
268 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
271 capacity-dmips-mhz = <607>;
272 dynamic-power-coefficient = <100>;
273 qcom,freq-domain = <&cpufreq_hw 0>;
274 operating-points-v2 = <&cpu0_opp_table>;
275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
277 #cooling-cells = <2>;
278 next-level-cache = <&L2_300>;
280 compatible = "cache";
281 next-level-cache = <&L3_0>;
287 compatible = "qcom,kryo385";
289 enable-method = "psci";
290 capacity-dmips-mhz = <1024>;
291 cpu-idle-states = <&BIG_CPU_SLEEP_0
294 dynamic-power-coefficient = <396>;
295 qcom,freq-domain = <&cpufreq_hw 1>;
296 operating-points-v2 = <&cpu4_opp_table>;
297 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
298 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
299 #cooling-cells = <2>;
300 next-level-cache = <&L2_400>;
302 compatible = "cache";
303 next-level-cache = <&L3_0>;
309 compatible = "qcom,kryo385";
311 enable-method = "psci";
312 capacity-dmips-mhz = <1024>;
313 cpu-idle-states = <&BIG_CPU_SLEEP_0
316 dynamic-power-coefficient = <396>;
317 qcom,freq-domain = <&cpufreq_hw 1>;
318 operating-points-v2 = <&cpu4_opp_table>;
319 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
320 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
321 #cooling-cells = <2>;
322 next-level-cache = <&L2_500>;
324 compatible = "cache";
325 next-level-cache = <&L3_0>;
331 compatible = "qcom,kryo385";
333 enable-method = "psci";
334 capacity-dmips-mhz = <1024>;
335 cpu-idle-states = <&BIG_CPU_SLEEP_0
338 dynamic-power-coefficient = <396>;
339 qcom,freq-domain = <&cpufreq_hw 1>;
340 operating-points-v2 = <&cpu4_opp_table>;
341 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
342 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
343 #cooling-cells = <2>;
344 next-level-cache = <&L2_600>;
346 compatible = "cache";
347 next-level-cache = <&L3_0>;
353 compatible = "qcom,kryo385";
355 enable-method = "psci";
356 capacity-dmips-mhz = <1024>;
357 cpu-idle-states = <&BIG_CPU_SLEEP_0
360 dynamic-power-coefficient = <396>;
361 qcom,freq-domain = <&cpufreq_hw 1>;
362 operating-points-v2 = <&cpu4_opp_table>;
363 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
364 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
365 #cooling-cells = <2>;
366 next-level-cache = <&L2_700>;
368 compatible = "cache";
369 next-level-cache = <&L3_0>;
410 entry-method = "psci";
412 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
413 compatible = "arm,idle-state";
414 idle-state-name = "little-power-down";
415 arm,psci-suspend-param = <0x40000003>;
416 entry-latency-us = <350>;
417 exit-latency-us = <461>;
418 min-residency-us = <1890>;
422 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
423 compatible = "arm,idle-state";
424 idle-state-name = "little-rail-power-down";
425 arm,psci-suspend-param = <0x40000004>;
426 entry-latency-us = <360>;
427 exit-latency-us = <531>;
428 min-residency-us = <3934>;
432 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
433 compatible = "arm,idle-state";
434 idle-state-name = "big-power-down";
435 arm,psci-suspend-param = <0x40000003>;
436 entry-latency-us = <264>;
437 exit-latency-us = <621>;
438 min-residency-us = <952>;
442 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
443 compatible = "arm,idle-state";
444 idle-state-name = "big-rail-power-down";
445 arm,psci-suspend-param = <0x40000004>;
446 entry-latency-us = <702>;
447 exit-latency-us = <1061>;
448 min-residency-us = <4488>;
452 CLUSTER_SLEEP_0: cluster-sleep-0 {
453 compatible = "arm,idle-state";
454 idle-state-name = "cluster-power-down";
455 arm,psci-suspend-param = <0x400000F4>;
456 entry-latency-us = <3263>;
457 exit-latency-us = <6562>;
458 min-residency-us = <9987>;
464 cpu0_opp_table: cpu0_opp_table {
465 compatible = "operating-points-v2";
468 cpu0_opp1: opp-300000000 {
469 opp-hz = /bits/ 64 <300000000>;
470 opp-peak-kBps = <800000 4800000>;
473 cpu0_opp2: opp-403200000 {
474 opp-hz = /bits/ 64 <403200000>;
475 opp-peak-kBps = <800000 4800000>;
478 cpu0_opp3: opp-480000000 {
479 opp-hz = /bits/ 64 <480000000>;
480 opp-peak-kBps = <800000 6451200>;
483 cpu0_opp4: opp-576000000 {
484 opp-hz = /bits/ 64 <576000000>;
485 opp-peak-kBps = <800000 6451200>;
488 cpu0_opp5: opp-652800000 {
489 opp-hz = /bits/ 64 <652800000>;
490 opp-peak-kBps = <800000 7680000>;
493 cpu0_opp6: opp-748800000 {
494 opp-hz = /bits/ 64 <748800000>;
495 opp-peak-kBps = <1804000 9216000>;
498 cpu0_opp7: opp-825600000 {
499 opp-hz = /bits/ 64 <825600000>;
500 opp-peak-kBps = <1804000 9216000>;
503 cpu0_opp8: opp-902400000 {
504 opp-hz = /bits/ 64 <902400000>;
505 opp-peak-kBps = <1804000 10444800>;
508 cpu0_opp9: opp-979200000 {
509 opp-hz = /bits/ 64 <979200000>;
510 opp-peak-kBps = <1804000 11980800>;
513 cpu0_opp10: opp-1056000000 {
514 opp-hz = /bits/ 64 <1056000000>;
515 opp-peak-kBps = <1804000 11980800>;
518 cpu0_opp11: opp-1132800000 {
519 opp-hz = /bits/ 64 <1132800000>;
520 opp-peak-kBps = <2188000 13516800>;
523 cpu0_opp12: opp-1228800000 {
524 opp-hz = /bits/ 64 <1228800000>;
525 opp-peak-kBps = <2188000 15052800>;
528 cpu0_opp13: opp-1324800000 {
529 opp-hz = /bits/ 64 <1324800000>;
530 opp-peak-kBps = <2188000 16588800>;
533 cpu0_opp14: opp-1420800000 {
534 opp-hz = /bits/ 64 <1420800000>;
535 opp-peak-kBps = <3072000 18124800>;
538 cpu0_opp15: opp-1516800000 {
539 opp-hz = /bits/ 64 <1516800000>;
540 opp-peak-kBps = <3072000 19353600>;
543 cpu0_opp16: opp-1612800000 {
544 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <4068000 19353600>;
548 cpu0_opp17: opp-1689600000 {
549 opp-hz = /bits/ 64 <1689600000>;
550 opp-peak-kBps = <4068000 20889600>;
553 cpu0_opp18: opp-1766400000 {
554 opp-hz = /bits/ 64 <1766400000>;
555 opp-peak-kBps = <4068000 22425600>;
559 cpu4_opp_table: cpu4_opp_table {
560 compatible = "operating-points-v2";
563 cpu4_opp1: opp-300000000 {
564 opp-hz = /bits/ 64 <300000000>;
565 opp-peak-kBps = <800000 4800000>;
568 cpu4_opp2: opp-403200000 {
569 opp-hz = /bits/ 64 <403200000>;
570 opp-peak-kBps = <800000 4800000>;
573 cpu4_opp3: opp-480000000 {
574 opp-hz = /bits/ 64 <480000000>;
575 opp-peak-kBps = <1804000 4800000>;
578 cpu4_opp4: opp-576000000 {
579 opp-hz = /bits/ 64 <576000000>;
580 opp-peak-kBps = <1804000 4800000>;
583 cpu4_opp5: opp-652800000 {
584 opp-hz = /bits/ 64 <652800000>;
585 opp-peak-kBps = <1804000 4800000>;
588 cpu4_opp6: opp-748800000 {
589 opp-hz = /bits/ 64 <748800000>;
590 opp-peak-kBps = <1804000 4800000>;
593 cpu4_opp7: opp-825600000 {
594 opp-hz = /bits/ 64 <825600000>;
595 opp-peak-kBps = <2188000 9216000>;
598 cpu4_opp8: opp-902400000 {
599 opp-hz = /bits/ 64 <902400000>;
600 opp-peak-kBps = <2188000 9216000>;
603 cpu4_opp9: opp-979200000 {
604 opp-hz = /bits/ 64 <979200000>;
605 opp-peak-kBps = <2188000 9216000>;
608 cpu4_opp10: opp-1056000000 {
609 opp-hz = /bits/ 64 <1056000000>;
610 opp-peak-kBps = <3072000 9216000>;
613 cpu4_opp11: opp-1132800000 {
614 opp-hz = /bits/ 64 <1132800000>;
615 opp-peak-kBps = <3072000 11980800>;
618 cpu4_opp12: opp-1209600000 {
619 opp-hz = /bits/ 64 <1209600000>;
620 opp-peak-kBps = <4068000 11980800>;
623 cpu4_opp13: opp-1286400000 {
624 opp-hz = /bits/ 64 <1286400000>;
625 opp-peak-kBps = <4068000 11980800>;
628 cpu4_opp14: opp-1363200000 {
629 opp-hz = /bits/ 64 <1363200000>;
630 opp-peak-kBps = <4068000 15052800>;
633 cpu4_opp15: opp-1459200000 {
634 opp-hz = /bits/ 64 <1459200000>;
635 opp-peak-kBps = <4068000 15052800>;
638 cpu4_opp16: opp-1536000000 {
639 opp-hz = /bits/ 64 <1536000000>;
640 opp-peak-kBps = <5412000 15052800>;
643 cpu4_opp17: opp-1612800000 {
644 opp-hz = /bits/ 64 <1612800000>;
645 opp-peak-kBps = <5412000 15052800>;
648 cpu4_opp18: opp-1689600000 {
649 opp-hz = /bits/ 64 <1689600000>;
650 opp-peak-kBps = <5412000 19353600>;
653 cpu4_opp19: opp-1766400000 {
654 opp-hz = /bits/ 64 <1766400000>;
655 opp-peak-kBps = <6220000 19353600>;
658 cpu4_opp20: opp-1843200000 {
659 opp-hz = /bits/ 64 <1843200000>;
660 opp-peak-kBps = <6220000 19353600>;
663 cpu4_opp21: opp-1920000000 {
664 opp-hz = /bits/ 64 <1920000000>;
665 opp-peak-kBps = <7216000 19353600>;
668 cpu4_opp22: opp-1996800000 {
669 opp-hz = /bits/ 64 <1996800000>;
670 opp-peak-kBps = <7216000 20889600>;
673 cpu4_opp23: opp-2092800000 {
674 opp-hz = /bits/ 64 <2092800000>;
675 opp-peak-kBps = <7216000 20889600>;
678 cpu4_opp24: opp-2169600000 {
679 opp-hz = /bits/ 64 <2169600000>;
680 opp-peak-kBps = <7216000 20889600>;
683 cpu4_opp25: opp-2246400000 {
684 opp-hz = /bits/ 64 <2246400000>;
685 opp-peak-kBps = <7216000 20889600>;
688 cpu4_opp26: opp-2323200000 {
689 opp-hz = /bits/ 64 <2323200000>;
690 opp-peak-kBps = <7216000 20889600>;
693 cpu4_opp27: opp-2400000000 {
694 opp-hz = /bits/ 64 <2400000000>;
695 opp-peak-kBps = <7216000 22425600>;
698 cpu4_opp28: opp-2476800000 {
699 opp-hz = /bits/ 64 <2476800000>;
700 opp-peak-kBps = <7216000 22425600>;
703 cpu4_opp29: opp-2553600000 {
704 opp-hz = /bits/ 64 <2553600000>;
705 opp-peak-kBps = <7216000 22425600>;
708 cpu4_opp30: opp-2649600000 {
709 opp-hz = /bits/ 64 <2649600000>;
710 opp-peak-kBps = <7216000 22425600>;
713 cpu4_opp31: opp-2745600000 {
714 opp-hz = /bits/ 64 <2745600000>;
715 opp-peak-kBps = <7216000 25497600>;
718 cpu4_opp32: opp-2803200000 {
719 opp-hz = /bits/ 64 <2803200000>;
720 opp-peak-kBps = <7216000 25497600>;
725 compatible = "arm,armv8-pmuv3";
726 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
730 compatible = "arm,armv8-timer";
731 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
732 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
733 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
734 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
739 compatible = "fixed-clock";
741 clock-frequency = <38400000>;
742 clock-output-names = "xo_board";
745 sleep_clk: sleep-clk {
746 compatible = "fixed-clock";
748 clock-frequency = <32764>;
754 compatible = "qcom,scm-sdm845", "qcom,scm";
758 adsp_pas: remoteproc-adsp {
759 compatible = "qcom,sdm845-adsp-pas";
761 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
762 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
763 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
764 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
765 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
766 interrupt-names = "wdog", "fatal", "ready",
767 "handover", "stop-ack";
769 clocks = <&rpmhcc RPMH_CXO_CLK>;
772 memory-region = <&adsp_mem>;
774 qcom,qmp = <&aoss_qmp>;
776 qcom,smem-states = <&adsp_smp2p_out 0>;
777 qcom,smem-state-names = "stop";
782 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
784 qcom,remote-pid = <2>;
785 mboxes = <&apss_shared 8>;
788 compatible = "qcom,apr-v2";
789 qcom,glink-channels = "apr_audio_svc";
790 qcom,apr-domain = <APR_DOMAIN_ADSP>;
791 #address-cells = <1>;
793 qcom,intents = <512 20>;
796 reg = <APR_SVC_ADSP_CORE>;
797 compatible = "qcom,q6core";
798 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
801 q6afe: apr-service@4 {
802 compatible = "qcom,q6afe";
804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
806 compatible = "qcom,q6afe-dais";
807 #address-cells = <1>;
809 #sound-dai-cells = <1>;
813 q6asm: apr-service@7 {
814 compatible = "qcom,q6asm";
816 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
818 compatible = "qcom,q6asm-dais";
819 #address-cells = <1>;
821 #sound-dai-cells = <1>;
822 iommus = <&apps_smmu 0x1821 0x0>;
826 q6adm: apr-service@8 {
827 compatible = "qcom,q6adm";
829 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
831 compatible = "qcom,q6adm-routing";
832 #sound-dai-cells = <0>;
838 compatible = "qcom,fastrpc";
839 qcom,glink-channels = "fastrpcglink-apps-dsp";
841 #address-cells = <1>;
845 compatible = "qcom,fastrpc-compute-cb";
847 iommus = <&apps_smmu 0x1823 0x0>;
851 compatible = "qcom,fastrpc-compute-cb";
853 iommus = <&apps_smmu 0x1824 0x0>;
859 cdsp_pas: remoteproc-cdsp {
860 compatible = "qcom,sdm845-cdsp-pas";
862 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
863 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
864 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
865 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
866 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
867 interrupt-names = "wdog", "fatal", "ready",
868 "handover", "stop-ack";
870 clocks = <&rpmhcc RPMH_CXO_CLK>;
873 memory-region = <&cdsp_mem>;
875 qcom,qmp = <&aoss_qmp>;
877 qcom,smem-states = <&cdsp_smp2p_out 0>;
878 qcom,smem-state-names = "stop";
883 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
885 qcom,remote-pid = <5>;
886 mboxes = <&apss_shared 4>;
888 compatible = "qcom,fastrpc";
889 qcom,glink-channels = "fastrpcglink-apps-dsp";
891 #address-cells = <1>;
895 compatible = "qcom,fastrpc-compute-cb";
897 iommus = <&apps_smmu 0x1401 0x30>;
901 compatible = "qcom,fastrpc-compute-cb";
903 iommus = <&apps_smmu 0x1402 0x30>;
907 compatible = "qcom,fastrpc-compute-cb";
909 iommus = <&apps_smmu 0x1403 0x30>;
913 compatible = "qcom,fastrpc-compute-cb";
915 iommus = <&apps_smmu 0x1404 0x30>;
919 compatible = "qcom,fastrpc-compute-cb";
921 iommus = <&apps_smmu 0x1405 0x30>;
925 compatible = "qcom,fastrpc-compute-cb";
927 iommus = <&apps_smmu 0x1406 0x30>;
931 compatible = "qcom,fastrpc-compute-cb";
933 iommus = <&apps_smmu 0x1407 0x30>;
937 compatible = "qcom,fastrpc-compute-cb";
939 iommus = <&apps_smmu 0x1408 0x30>;
946 compatible = "qcom,tcsr-mutex";
947 syscon = <&tcsr_mutex_regs 0 0x1000>;
952 compatible = "qcom,smp2p";
953 qcom,smem = <94>, <432>;
955 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
957 mboxes = <&apss_shared 6>;
959 qcom,local-pid = <0>;
960 qcom,remote-pid = <5>;
962 cdsp_smp2p_out: master-kernel {
963 qcom,entry-name = "master-kernel";
964 #qcom,smem-state-cells = <1>;
967 cdsp_smp2p_in: slave-kernel {
968 qcom,entry-name = "slave-kernel";
970 interrupt-controller;
971 #interrupt-cells = <2>;
976 compatible = "qcom,smp2p";
977 qcom,smem = <443>, <429>;
979 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
981 mboxes = <&apss_shared 10>;
983 qcom,local-pid = <0>;
984 qcom,remote-pid = <2>;
986 adsp_smp2p_out: master-kernel {
987 qcom,entry-name = "master-kernel";
988 #qcom,smem-state-cells = <1>;
991 adsp_smp2p_in: slave-kernel {
992 qcom,entry-name = "slave-kernel";
994 interrupt-controller;
995 #interrupt-cells = <2>;
1000 compatible = "qcom,smp2p";
1001 qcom,smem = <435>, <428>;
1002 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1003 mboxes = <&apss_shared 14>;
1004 qcom,local-pid = <0>;
1005 qcom,remote-pid = <1>;
1007 modem_smp2p_out: master-kernel {
1008 qcom,entry-name = "master-kernel";
1009 #qcom,smem-state-cells = <1>;
1012 modem_smp2p_in: slave-kernel {
1013 qcom,entry-name = "slave-kernel";
1014 interrupt-controller;
1015 #interrupt-cells = <2>;
1018 ipa_smp2p_out: ipa-ap-to-modem {
1019 qcom,entry-name = "ipa";
1020 #qcom,smem-state-cells = <1>;
1023 ipa_smp2p_in: ipa-modem-to-ap {
1024 qcom,entry-name = "ipa";
1025 interrupt-controller;
1026 #interrupt-cells = <2>;
1031 compatible = "qcom,smp2p";
1032 qcom,smem = <481>, <430>;
1033 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1034 mboxes = <&apss_shared 26>;
1035 qcom,local-pid = <0>;
1036 qcom,remote-pid = <3>;
1038 slpi_smp2p_out: master-kernel {
1039 qcom,entry-name = "master-kernel";
1040 #qcom,smem-state-cells = <1>;
1043 slpi_smp2p_in: slave-kernel {
1044 qcom,entry-name = "slave-kernel";
1045 interrupt-controller;
1046 #interrupt-cells = <2>;
1051 compatible = "arm,psci-1.0";
1056 #address-cells = <2>;
1058 ranges = <0 0 0 0 0x10 0>;
1059 dma-ranges = <0 0 0 0 0x10 0>;
1060 compatible = "simple-bus";
1062 gcc: clock-controller@100000 {
1063 compatible = "qcom,gcc-sdm845";
1064 reg = <0 0x00100000 0 0x1f0000>;
1065 clocks = <&rpmhcc RPMH_CXO_CLK>,
1066 <&rpmhcc RPMH_CXO_CLK_A>,
1070 clock-names = "bi_tcxo",
1077 #power-domain-cells = <1>;
1081 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1082 reg = <0 0x00784000 0 0x8ff>;
1083 #address-cells = <1>;
1086 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1091 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1098 compatible = "qcom,prng-ee";
1099 reg = <0 0x00793000 0 0x1000>;
1100 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1101 clock-names = "core";
1104 qup_opp_table: qup-opp-table {
1105 compatible = "operating-points-v2";
1108 opp-hz = /bits/ 64 <50000000>;
1109 required-opps = <&rpmhpd_opp_min_svs>;
1113 opp-hz = /bits/ 64 <75000000>;
1114 required-opps = <&rpmhpd_opp_low_svs>;
1118 opp-hz = /bits/ 64 <100000000>;
1119 required-opps = <&rpmhpd_opp_svs>;
1123 opp-hz = /bits/ 64 <128000000>;
1124 required-opps = <&rpmhpd_opp_nom>;
1128 qupv3_id_0: geniqup@8c0000 {
1129 compatible = "qcom,geni-se-qup";
1130 reg = <0 0x008c0000 0 0x6000>;
1131 clock-names = "m-ahb", "s-ahb";
1132 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1133 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1134 iommus = <&apps_smmu 0x3 0x0>;
1135 #address-cells = <2>;
1138 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1139 interconnect-names = "qup-core";
1140 status = "disabled";
1143 compatible = "qcom,geni-i2c";
1144 reg = <0 0x00880000 0 0x4000>;
1146 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&qup_i2c0_default>;
1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1150 #address-cells = <1>;
1152 power-domains = <&rpmhpd SDM845_CX>;
1153 operating-points-v2 = <&qup_opp_table>;
1154 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1156 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1157 interconnect-names = "qup-core", "qup-config", "qup-memory";
1158 status = "disabled";
1162 compatible = "qcom,geni-spi";
1163 reg = <0 0x00880000 0 0x4000>;
1165 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_spi0_default>;
1168 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1169 #address-cells = <1>;
1171 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1172 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1173 interconnect-names = "qup-core", "qup-config";
1174 status = "disabled";
1177 uart0: serial@880000 {
1178 compatible = "qcom,geni-uart";
1179 reg = <0 0x00880000 0 0x4000>;
1181 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&qup_uart0_default>;
1184 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1185 power-domains = <&rpmhpd SDM845_CX>;
1186 operating-points-v2 = <&qup_opp_table>;
1187 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1188 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1189 interconnect-names = "qup-core", "qup-config";
1190 status = "disabled";
1194 compatible = "qcom,geni-i2c";
1195 reg = <0 0x00884000 0 0x4000>;
1197 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_i2c1_default>;
1200 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1201 #address-cells = <1>;
1203 power-domains = <&rpmhpd SDM845_CX>;
1204 operating-points-v2 = <&qup_opp_table>;
1205 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1206 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1207 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 status = "disabled";
1213 compatible = "qcom,geni-spi";
1214 reg = <0 0x00884000 0 0x4000>;
1216 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1217 pinctrl-names = "default";
1218 pinctrl-0 = <&qup_spi1_default>;
1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1220 #address-cells = <1>;
1222 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1223 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1224 interconnect-names = "qup-core", "qup-config";
1225 status = "disabled";
1228 uart1: serial@884000 {
1229 compatible = "qcom,geni-uart";
1230 reg = <0 0x00884000 0 0x4000>;
1232 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_uart1_default>;
1235 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains = <&rpmhpd SDM845_CX>;
1237 operating-points-v2 = <&qup_opp_table>;
1238 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1239 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1240 interconnect-names = "qup-core", "qup-config";
1241 status = "disabled";
1245 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00888000 0 0x4000>;
1248 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_i2c2_default>;
1251 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cells = <1>;
1254 power-domains = <&rpmhpd SDM845_CX>;
1255 operating-points-v2 = <&qup_opp_table>;
1256 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1257 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1258 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1259 interconnect-names = "qup-core", "qup-config", "qup-memory";
1260 status = "disabled";
1264 compatible = "qcom,geni-spi";
1265 reg = <0 0x00888000 0 0x4000>;
1267 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&qup_spi2_default>;
1270 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1271 #address-cells = <1>;
1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1274 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1275 interconnect-names = "qup-core", "qup-config";
1276 status = "disabled";
1279 uart2: serial@888000 {
1280 compatible = "qcom,geni-uart";
1281 reg = <0 0x00888000 0 0x4000>;
1283 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_uart2_default>;
1286 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287 power-domains = <&rpmhpd SDM845_CX>;
1288 operating-points-v2 = <&qup_opp_table>;
1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1291 interconnect-names = "qup-core", "qup-config";
1292 status = "disabled";
1296 compatible = "qcom,geni-i2c";
1297 reg = <0 0x0088c000 0 0x4000>;
1299 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&qup_i2c3_default>;
1302 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303 #address-cells = <1>;
1305 power-domains = <&rpmhpd SDM845_CX>;
1306 operating-points-v2 = <&qup_opp_table>;
1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1309 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1310 interconnect-names = "qup-core", "qup-config", "qup-memory";
1311 status = "disabled";
1315 compatible = "qcom,geni-spi";
1316 reg = <0 0x0088c000 0 0x4000>;
1318 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_spi3_default>;
1321 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1322 #address-cells = <1>;
1324 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1325 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1326 interconnect-names = "qup-core", "qup-config";
1327 status = "disabled";
1330 uart3: serial@88c000 {
1331 compatible = "qcom,geni-uart";
1332 reg = <0 0x0088c000 0 0x4000>;
1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&qup_uart3_default>;
1337 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1338 power-domains = <&rpmhpd SDM845_CX>;
1339 operating-points-v2 = <&qup_opp_table>;
1340 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1341 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1342 interconnect-names = "qup-core", "qup-config";
1343 status = "disabled";
1347 compatible = "qcom,geni-i2c";
1348 reg = <0 0x00890000 0 0x4000>;
1350 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&qup_i2c4_default>;
1353 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1354 #address-cells = <1>;
1356 power-domains = <&rpmhpd SDM845_CX>;
1357 operating-points-v2 = <&qup_opp_table>;
1358 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1359 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1360 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1361 interconnect-names = "qup-core", "qup-config", "qup-memory";
1362 status = "disabled";
1366 compatible = "qcom,geni-spi";
1367 reg = <0 0x00890000 0 0x4000>;
1369 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_spi4_default>;
1372 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1373 #address-cells = <1>;
1375 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1376 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1377 interconnect-names = "qup-core", "qup-config";
1378 status = "disabled";
1381 uart4: serial@890000 {
1382 compatible = "qcom,geni-uart";
1383 reg = <0 0x00890000 0 0x4000>;
1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1386 pinctrl-names = "default";
1387 pinctrl-0 = <&qup_uart4_default>;
1388 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1389 power-domains = <&rpmhpd SDM845_CX>;
1390 operating-points-v2 = <&qup_opp_table>;
1391 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1392 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1393 interconnect-names = "qup-core", "qup-config";
1394 status = "disabled";
1398 compatible = "qcom,geni-i2c";
1399 reg = <0 0x00894000 0 0x4000>;
1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1402 pinctrl-names = "default";
1403 pinctrl-0 = <&qup_i2c5_default>;
1404 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1405 #address-cells = <1>;
1407 power-domains = <&rpmhpd SDM845_CX>;
1408 operating-points-v2 = <&qup_opp_table>;
1409 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1410 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1411 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 status = "disabled";
1417 compatible = "qcom,geni-spi";
1418 reg = <0 0x00894000 0 0x4000>;
1420 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1421 pinctrl-names = "default";
1422 pinctrl-0 = <&qup_spi5_default>;
1423 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1424 #address-cells = <1>;
1426 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1427 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1428 interconnect-names = "qup-core", "qup-config";
1429 status = "disabled";
1432 uart5: serial@894000 {
1433 compatible = "qcom,geni-uart";
1434 reg = <0 0x00894000 0 0x4000>;
1436 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&qup_uart5_default>;
1439 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1440 power-domains = <&rpmhpd SDM845_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1444 interconnect-names = "qup-core", "qup-config";
1445 status = "disabled";
1449 compatible = "qcom,geni-i2c";
1450 reg = <0 0x00898000 0 0x4000>;
1452 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1453 pinctrl-names = "default";
1454 pinctrl-0 = <&qup_i2c6_default>;
1455 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1456 #address-cells = <1>;
1458 power-domains = <&rpmhpd SDM845_CX>;
1459 operating-points-v2 = <&qup_opp_table>;
1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1463 interconnect-names = "qup-core", "qup-config", "qup-memory";
1464 status = "disabled";
1468 compatible = "qcom,geni-spi";
1469 reg = <0 0x00898000 0 0x4000>;
1471 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_spi6_default>;
1474 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1475 #address-cells = <1>;
1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1479 interconnect-names = "qup-core", "qup-config";
1480 status = "disabled";
1483 uart6: serial@898000 {
1484 compatible = "qcom,geni-uart";
1485 reg = <0 0x00898000 0 0x4000>;
1487 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&qup_uart6_default>;
1490 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1491 power-domains = <&rpmhpd SDM845_CX>;
1492 operating-points-v2 = <&qup_opp_table>;
1493 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1494 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1495 interconnect-names = "qup-core", "qup-config";
1496 status = "disabled";
1500 compatible = "qcom,geni-i2c";
1501 reg = <0 0x0089c000 0 0x4000>;
1503 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1504 pinctrl-names = "default";
1505 pinctrl-0 = <&qup_i2c7_default>;
1506 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1507 #address-cells = <1>;
1509 power-domains = <&rpmhpd SDM845_CX>;
1510 operating-points-v2 = <&qup_opp_table>;
1511 status = "disabled";
1515 compatible = "qcom,geni-spi";
1516 reg = <0 0x0089c000 0 0x4000>;
1518 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1519 pinctrl-names = "default";
1520 pinctrl-0 = <&qup_spi7_default>;
1521 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1522 #address-cells = <1>;
1524 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1525 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1526 interconnect-names = "qup-core", "qup-config";
1527 status = "disabled";
1530 uart7: serial@89c000 {
1531 compatible = "qcom,geni-uart";
1532 reg = <0 0x0089c000 0 0x4000>;
1534 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1535 pinctrl-names = "default";
1536 pinctrl-0 = <&qup_uart7_default>;
1537 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1538 power-domains = <&rpmhpd SDM845_CX>;
1539 operating-points-v2 = <&qup_opp_table>;
1540 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1541 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1542 interconnect-names = "qup-core", "qup-config";
1543 status = "disabled";
1547 qupv3_id_1: geniqup@ac0000 {
1548 compatible = "qcom,geni-se-qup";
1549 reg = <0 0x00ac0000 0 0x6000>;
1550 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1552 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1553 iommus = <&apps_smmu 0x6c3 0x0>;
1554 #address-cells = <2>;
1557 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1558 interconnect-names = "qup-core";
1559 status = "disabled";
1562 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00a80000 0 0x4000>;
1565 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1566 pinctrl-names = "default";
1567 pinctrl-0 = <&qup_i2c8_default>;
1568 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cells = <1>;
1571 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-points-v2 = <&qup_opp_table>;
1573 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1574 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1575 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 status = "disabled";
1581 compatible = "qcom,geni-spi";
1582 reg = <0 0x00a80000 0 0x4000>;
1584 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&qup_spi8_default>;
1587 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1588 #address-cells = <1>;
1590 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1591 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1592 interconnect-names = "qup-core", "qup-config";
1593 status = "disabled";
1596 uart8: serial@a80000 {
1597 compatible = "qcom,geni-uart";
1598 reg = <0 0x00a80000 0 0x4000>;
1600 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1601 pinctrl-names = "default";
1602 pinctrl-0 = <&qup_uart8_default>;
1603 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1604 power-domains = <&rpmhpd SDM845_CX>;
1605 operating-points-v2 = <&qup_opp_table>;
1606 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1607 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1608 interconnect-names = "qup-core", "qup-config";
1609 status = "disabled";
1613 compatible = "qcom,geni-i2c";
1614 reg = <0 0x00a84000 0 0x4000>;
1616 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&qup_i2c9_default>;
1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1620 #address-cells = <1>;
1622 power-domains = <&rpmhpd SDM845_CX>;
1623 operating-points-v2 = <&qup_opp_table>;
1624 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1625 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1626 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1627 interconnect-names = "qup-core", "qup-config", "qup-memory";
1628 status = "disabled";
1632 compatible = "qcom,geni-spi";
1633 reg = <0 0x00a84000 0 0x4000>;
1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1636 pinctrl-names = "default";
1637 pinctrl-0 = <&qup_spi9_default>;
1638 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1639 #address-cells = <1>;
1641 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1642 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1643 interconnect-names = "qup-core", "qup-config";
1644 status = "disabled";
1647 uart9: serial@a84000 {
1648 compatible = "qcom,geni-debug-uart";
1649 reg = <0 0x00a84000 0 0x4000>;
1651 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1652 pinctrl-names = "default";
1653 pinctrl-0 = <&qup_uart9_default>;
1654 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1655 power-domains = <&rpmhpd SDM845_CX>;
1656 operating-points-v2 = <&qup_opp_table>;
1657 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1658 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1659 interconnect-names = "qup-core", "qup-config";
1660 status = "disabled";
1664 compatible = "qcom,geni-i2c";
1665 reg = <0 0x00a88000 0 0x4000>;
1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1668 pinctrl-names = "default";
1669 pinctrl-0 = <&qup_i2c10_default>;
1670 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1671 #address-cells = <1>;
1673 power-domains = <&rpmhpd SDM845_CX>;
1674 operating-points-v2 = <&qup_opp_table>;
1675 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1676 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1677 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1678 interconnect-names = "qup-core", "qup-config", "qup-memory";
1679 status = "disabled";
1683 compatible = "qcom,geni-spi";
1684 reg = <0 0x00a88000 0 0x4000>;
1686 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_spi10_default>;
1689 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1690 #address-cells = <1>;
1692 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1693 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1694 interconnect-names = "qup-core", "qup-config";
1695 status = "disabled";
1698 uart10: serial@a88000 {
1699 compatible = "qcom,geni-uart";
1700 reg = <0 0x00a88000 0 0x4000>;
1702 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&qup_uart10_default>;
1705 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1706 power-domains = <&rpmhpd SDM845_CX>;
1707 operating-points-v2 = <&qup_opp_table>;
1708 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1709 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1710 interconnect-names = "qup-core", "qup-config";
1711 status = "disabled";
1715 compatible = "qcom,geni-i2c";
1716 reg = <0 0x00a8c000 0 0x4000>;
1718 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1719 pinctrl-names = "default";
1720 pinctrl-0 = <&qup_i2c11_default>;
1721 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1722 #address-cells = <1>;
1724 power-domains = <&rpmhpd SDM845_CX>;
1725 operating-points-v2 = <&qup_opp_table>;
1726 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1727 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1728 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1729 interconnect-names = "qup-core", "qup-config", "qup-memory";
1730 status = "disabled";
1734 compatible = "qcom,geni-spi";
1735 reg = <0 0x00a8c000 0 0x4000>;
1737 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&qup_spi11_default>;
1740 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1741 #address-cells = <1>;
1743 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1744 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1745 interconnect-names = "qup-core", "qup-config";
1746 status = "disabled";
1749 uart11: serial@a8c000 {
1750 compatible = "qcom,geni-uart";
1751 reg = <0 0x00a8c000 0 0x4000>;
1753 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1754 pinctrl-names = "default";
1755 pinctrl-0 = <&qup_uart11_default>;
1756 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1757 power-domains = <&rpmhpd SDM845_CX>;
1758 operating-points-v2 = <&qup_opp_table>;
1759 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1760 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1761 interconnect-names = "qup-core", "qup-config";
1762 status = "disabled";
1766 compatible = "qcom,geni-i2c";
1767 reg = <0 0x00a90000 0 0x4000>;
1769 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1770 pinctrl-names = "default";
1771 pinctrl-0 = <&qup_i2c12_default>;
1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1773 #address-cells = <1>;
1775 power-domains = <&rpmhpd SDM845_CX>;
1776 operating-points-v2 = <&qup_opp_table>;
1777 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1778 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1779 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1780 interconnect-names = "qup-core", "qup-config", "qup-memory";
1781 status = "disabled";
1785 compatible = "qcom,geni-spi";
1786 reg = <0 0x00a90000 0 0x4000>;
1788 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1789 pinctrl-names = "default";
1790 pinctrl-0 = <&qup_spi12_default>;
1791 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1792 #address-cells = <1>;
1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1796 interconnect-names = "qup-core", "qup-config";
1797 status = "disabled";
1800 uart12: serial@a90000 {
1801 compatible = "qcom,geni-uart";
1802 reg = <0 0x00a90000 0 0x4000>;
1804 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1805 pinctrl-names = "default";
1806 pinctrl-0 = <&qup_uart12_default>;
1807 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1808 power-domains = <&rpmhpd SDM845_CX>;
1809 operating-points-v2 = <&qup_opp_table>;
1810 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1811 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1812 interconnect-names = "qup-core", "qup-config";
1813 status = "disabled";
1817 compatible = "qcom,geni-i2c";
1818 reg = <0 0x00a94000 0 0x4000>;
1820 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1821 pinctrl-names = "default";
1822 pinctrl-0 = <&qup_i2c13_default>;
1823 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1824 #address-cells = <1>;
1826 power-domains = <&rpmhpd SDM845_CX>;
1827 operating-points-v2 = <&qup_opp_table>;
1828 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1830 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1831 interconnect-names = "qup-core", "qup-config", "qup-memory";
1832 status = "disabled";
1836 compatible = "qcom,geni-spi";
1837 reg = <0 0x00a94000 0 0x4000>;
1839 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1840 pinctrl-names = "default";
1841 pinctrl-0 = <&qup_spi13_default>;
1842 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1843 #address-cells = <1>;
1845 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1846 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1847 interconnect-names = "qup-core", "qup-config";
1848 status = "disabled";
1851 uart13: serial@a94000 {
1852 compatible = "qcom,geni-uart";
1853 reg = <0 0x00a94000 0 0x4000>;
1855 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1856 pinctrl-names = "default";
1857 pinctrl-0 = <&qup_uart13_default>;
1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1859 power-domains = <&rpmhpd SDM845_CX>;
1860 operating-points-v2 = <&qup_opp_table>;
1861 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1862 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1863 interconnect-names = "qup-core", "qup-config";
1864 status = "disabled";
1868 compatible = "qcom,geni-i2c";
1869 reg = <0 0x00a98000 0 0x4000>;
1871 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1872 pinctrl-names = "default";
1873 pinctrl-0 = <&qup_i2c14_default>;
1874 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1875 #address-cells = <1>;
1877 power-domains = <&rpmhpd SDM845_CX>;
1878 operating-points-v2 = <&qup_opp_table>;
1879 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1880 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1881 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1882 interconnect-names = "qup-core", "qup-config", "qup-memory";
1883 status = "disabled";
1887 compatible = "qcom,geni-spi";
1888 reg = <0 0x00a98000 0 0x4000>;
1890 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1891 pinctrl-names = "default";
1892 pinctrl-0 = <&qup_spi14_default>;
1893 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1894 #address-cells = <1>;
1896 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1897 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1898 interconnect-names = "qup-core", "qup-config";
1899 status = "disabled";
1902 uart14: serial@a98000 {
1903 compatible = "qcom,geni-uart";
1904 reg = <0 0x00a98000 0 0x4000>;
1906 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1907 pinctrl-names = "default";
1908 pinctrl-0 = <&qup_uart14_default>;
1909 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1910 power-domains = <&rpmhpd SDM845_CX>;
1911 operating-points-v2 = <&qup_opp_table>;
1912 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1913 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1914 interconnect-names = "qup-core", "qup-config";
1915 status = "disabled";
1919 compatible = "qcom,geni-i2c";
1920 reg = <0 0x00a9c000 0 0x4000>;
1922 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1923 pinctrl-names = "default";
1924 pinctrl-0 = <&qup_i2c15_default>;
1925 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1926 #address-cells = <1>;
1928 power-domains = <&rpmhpd SDM845_CX>;
1929 operating-points-v2 = <&qup_opp_table>;
1930 status = "disabled";
1931 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1932 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1933 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1934 interconnect-names = "qup-core", "qup-config", "qup-memory";
1938 compatible = "qcom,geni-spi";
1939 reg = <0 0x00a9c000 0 0x4000>;
1941 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1942 pinctrl-names = "default";
1943 pinctrl-0 = <&qup_spi15_default>;
1944 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1945 #address-cells = <1>;
1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1949 interconnect-names = "qup-core", "qup-config";
1950 status = "disabled";
1953 uart15: serial@a9c000 {
1954 compatible = "qcom,geni-uart";
1955 reg = <0 0x00a9c000 0 0x4000>;
1957 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1958 pinctrl-names = "default";
1959 pinctrl-0 = <&qup_uart15_default>;
1960 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1961 power-domains = <&rpmhpd SDM845_CX>;
1962 operating-points-v2 = <&qup_opp_table>;
1963 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1964 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1965 interconnect-names = "qup-core", "qup-config";
1966 status = "disabled";
1970 system-cache-controller@1100000 {
1971 compatible = "qcom,sdm845-llcc";
1972 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1973 reg-names = "llcc_base", "llcc_broadcast_base";
1974 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1977 pcie0: pci@1c00000 {
1978 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1979 reg = <0 0x01c00000 0 0x2000>,
1980 <0 0x60000000 0 0xf1d>,
1981 <0 0x60000f20 0 0xa8>,
1982 <0 0x60100000 0 0x100000>;
1983 reg-names = "parf", "dbi", "elbi", "config";
1984 device_type = "pci";
1985 linux,pci-domain = <0>;
1986 bus-range = <0x00 0xff>;
1989 #address-cells = <3>;
1992 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1993 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1995 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1996 interrupt-names = "msi";
1997 #interrupt-cells = <1>;
1998 interrupt-map-mask = <0 0 0 0x7>;
1999 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2000 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2001 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2002 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2004 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2005 <&gcc GCC_PCIE_0_AUX_CLK>,
2006 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2007 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2008 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2009 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2010 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2011 clock-names = "pipe",
2019 iommus = <&apps_smmu 0x1c10 0xf>;
2020 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2021 <0x100 &apps_smmu 0x1c11 0x1>,
2022 <0x200 &apps_smmu 0x1c12 0x1>,
2023 <0x300 &apps_smmu 0x1c13 0x1>,
2024 <0x400 &apps_smmu 0x1c14 0x1>,
2025 <0x500 &apps_smmu 0x1c15 0x1>,
2026 <0x600 &apps_smmu 0x1c16 0x1>,
2027 <0x700 &apps_smmu 0x1c17 0x1>,
2028 <0x800 &apps_smmu 0x1c18 0x1>,
2029 <0x900 &apps_smmu 0x1c19 0x1>,
2030 <0xa00 &apps_smmu 0x1c1a 0x1>,
2031 <0xb00 &apps_smmu 0x1c1b 0x1>,
2032 <0xc00 &apps_smmu 0x1c1c 0x1>,
2033 <0xd00 &apps_smmu 0x1c1d 0x1>,
2034 <0xe00 &apps_smmu 0x1c1e 0x1>,
2035 <0xf00 &apps_smmu 0x1c1f 0x1>;
2037 resets = <&gcc GCC_PCIE_0_BCR>;
2038 reset-names = "pci";
2040 power-domains = <&gcc PCIE_0_GDSC>;
2042 phys = <&pcie0_lane>;
2043 phy-names = "pciephy";
2045 status = "disabled";
2048 pcie0_phy: phy@1c06000 {
2049 compatible = "qcom,sdm845-qmp-pcie-phy";
2050 reg = <0 0x01c06000 0 0x18c>;
2051 #address-cells = <2>;
2054 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2055 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2056 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2057 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2058 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2060 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2061 reset-names = "phy";
2063 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2064 assigned-clock-rates = <100000000>;
2066 status = "disabled";
2068 pcie0_lane: phy@1c06200 {
2069 reg = <0 0x01c06200 0 0x128>,
2070 <0 0x01c06400 0 0x1fc>,
2071 <0 0x01c06800 0 0x218>,
2072 <0 0x01c06600 0 0x70>;
2073 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2074 clock-names = "pipe0";
2078 clock-output-names = "pcie_0_pipe_clk";
2082 pcie1: pci@1c08000 {
2083 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2084 reg = <0 0x01c08000 0 0x2000>,
2085 <0 0x40000000 0 0xf1d>,
2086 <0 0x40000f20 0 0xa8>,
2087 <0 0x40100000 0 0x100000>;
2088 reg-names = "parf", "dbi", "elbi", "config";
2089 device_type = "pci";
2090 linux,pci-domain = <1>;
2091 bus-range = <0x00 0xff>;
2094 #address-cells = <3>;
2097 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2098 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2100 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2101 interrupt-names = "msi";
2102 #interrupt-cells = <1>;
2103 interrupt-map-mask = <0 0 0 0x7>;
2104 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2105 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2106 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2107 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2110 <&gcc GCC_PCIE_1_AUX_CLK>,
2111 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2112 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2113 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2114 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2115 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2116 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2117 clock-names = "pipe",
2126 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2127 assigned-clock-rates = <19200000>;
2129 iommus = <&apps_smmu 0x1c00 0xf>;
2130 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2131 <0x100 &apps_smmu 0x1c01 0x1>,
2132 <0x200 &apps_smmu 0x1c02 0x1>,
2133 <0x300 &apps_smmu 0x1c03 0x1>,
2134 <0x400 &apps_smmu 0x1c04 0x1>,
2135 <0x500 &apps_smmu 0x1c05 0x1>,
2136 <0x600 &apps_smmu 0x1c06 0x1>,
2137 <0x700 &apps_smmu 0x1c07 0x1>,
2138 <0x800 &apps_smmu 0x1c08 0x1>,
2139 <0x900 &apps_smmu 0x1c09 0x1>,
2140 <0xa00 &apps_smmu 0x1c0a 0x1>,
2141 <0xb00 &apps_smmu 0x1c0b 0x1>,
2142 <0xc00 &apps_smmu 0x1c0c 0x1>,
2143 <0xd00 &apps_smmu 0x1c0d 0x1>,
2144 <0xe00 &apps_smmu 0x1c0e 0x1>,
2145 <0xf00 &apps_smmu 0x1c0f 0x1>;
2147 resets = <&gcc GCC_PCIE_1_BCR>;
2148 reset-names = "pci";
2150 power-domains = <&gcc PCIE_1_GDSC>;
2152 phys = <&pcie1_lane>;
2153 phy-names = "pciephy";
2155 status = "disabled";
2158 pcie1_phy: phy@1c0a000 {
2159 compatible = "qcom,sdm845-qhp-pcie-phy";
2160 reg = <0 0x01c0a000 0 0x800>;
2161 #address-cells = <2>;
2164 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2165 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2166 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2167 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2168 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2170 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2171 reset-names = "phy";
2173 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2174 assigned-clock-rates = <100000000>;
2176 status = "disabled";
2178 pcie1_lane: phy@1c06200 {
2179 reg = <0 0x01c0a800 0 0x800>,
2180 <0 0x01c0a800 0 0x800>,
2181 <0 0x01c0b800 0 0x400>;
2182 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2183 clock-names = "pipe0";
2187 clock-output-names = "pcie_1_pipe_clk";
2191 mem_noc: interconnect@1380000 {
2192 compatible = "qcom,sdm845-mem-noc";
2193 reg = <0 0x01380000 0 0x27200>;
2194 #interconnect-cells = <2>;
2195 qcom,bcm-voters = <&apps_bcm_voter>;
2198 dc_noc: interconnect@14e0000 {
2199 compatible = "qcom,sdm845-dc-noc";
2200 reg = <0 0x014e0000 0 0x400>;
2201 #interconnect-cells = <2>;
2202 qcom,bcm-voters = <&apps_bcm_voter>;
2205 config_noc: interconnect@1500000 {
2206 compatible = "qcom,sdm845-config-noc";
2207 reg = <0 0x01500000 0 0x5080>;
2208 #interconnect-cells = <2>;
2209 qcom,bcm-voters = <&apps_bcm_voter>;
2212 system_noc: interconnect@1620000 {
2213 compatible = "qcom,sdm845-system-noc";
2214 reg = <0 0x01620000 0 0x18080>;
2215 #interconnect-cells = <2>;
2216 qcom,bcm-voters = <&apps_bcm_voter>;
2219 aggre1_noc: interconnect@16e0000 {
2220 compatible = "qcom,sdm845-aggre1-noc";
2221 reg = <0 0x016e0000 0 0x15080>;
2222 #interconnect-cells = <2>;
2223 qcom,bcm-voters = <&apps_bcm_voter>;
2226 aggre2_noc: interconnect@1700000 {
2227 compatible = "qcom,sdm845-aggre2-noc";
2228 reg = <0 0x01700000 0 0x1f300>;
2229 #interconnect-cells = <2>;
2230 qcom,bcm-voters = <&apps_bcm_voter>;
2233 mmss_noc: interconnect@1740000 {
2234 compatible = "qcom,sdm845-mmss-noc";
2235 reg = <0 0x01740000 0 0x1c100>;
2236 #interconnect-cells = <2>;
2237 qcom,bcm-voters = <&apps_bcm_voter>;
2240 ufs_mem_hc: ufshc@1d84000 {
2241 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2243 reg = <0 0x01d84000 0 0x2500>,
2244 <0 0x01d90000 0 0x8000>;
2245 reg-names = "std", "ice";
2246 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2247 phys = <&ufs_mem_phy_lanes>;
2248 phy-names = "ufsphy";
2249 lanes-per-direction = <2>;
2250 power-domains = <&gcc UFS_PHY_GDSC>;
2252 resets = <&gcc GCC_UFS_PHY_BCR>;
2253 reset-names = "rst";
2255 iommus = <&apps_smmu 0x100 0xf>;
2263 "tx_lane0_sync_clk",
2264 "rx_lane0_sync_clk",
2265 "rx_lane1_sync_clk",
2268 <&gcc GCC_UFS_PHY_AXI_CLK>,
2269 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2270 <&gcc GCC_UFS_PHY_AHB_CLK>,
2271 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2272 <&rpmhcc RPMH_CXO_CLK>,
2273 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2274 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2275 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2276 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2278 <50000000 200000000>,
2281 <37500000 150000000>,
2288 status = "disabled";
2291 ufs_mem_phy: phy@1d87000 {
2292 compatible = "qcom,sdm845-qmp-ufs-phy";
2293 reg = <0 0x01d87000 0 0x18c>;
2294 #address-cells = <2>;
2297 clock-names = "ref",
2299 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2300 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2302 resets = <&ufs_mem_hc 0>;
2303 reset-names = "ufsphy";
2304 status = "disabled";
2306 ufs_mem_phy_lanes: phy@1d87400 {
2307 reg = <0 0x01d87400 0 0x108>,
2308 <0 0x01d87600 0 0x1e0>,
2309 <0 0x01d87c00 0 0x1dc>,
2310 <0 0x01d87800 0 0x108>,
2311 <0 0x01d87a00 0 0x1e0>;
2316 cryptobam: dma-controller@1dc4000 {
2317 compatible = "qcom,bam-v1.7.0";
2318 reg = <0 0x01dc4000 0 0x24000>;
2319 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2320 clocks = <&rpmhcc RPMH_CE_CLK>;
2321 clock-names = "bam_clk";
2324 qcom,controlled-remotely;
2325 iommus = <&apps_smmu 0x704 0x1>,
2326 <&apps_smmu 0x706 0x1>,
2327 <&apps_smmu 0x714 0x1>,
2328 <&apps_smmu 0x716 0x1>;
2331 crypto: crypto@1dfa000 {
2332 compatible = "qcom,crypto-v5.4";
2333 reg = <0 0x01dfa000 0 0x6000>;
2334 clocks = <&gcc GCC_CE1_AHB_CLK>,
2335 <&gcc GCC_CE1_AXI_CLK>,
2336 <&rpmhcc RPMH_CE_CLK>;
2337 clock-names = "iface", "bus", "core";
2338 dmas = <&cryptobam 6>, <&cryptobam 7>;
2339 dma-names = "rx", "tx";
2340 iommus = <&apps_smmu 0x704 0x1>,
2341 <&apps_smmu 0x706 0x1>,
2342 <&apps_smmu 0x714 0x1>,
2343 <&apps_smmu 0x716 0x1>;
2347 compatible = "qcom,sdm845-ipa";
2349 iommus = <&apps_smmu 0x720 0x0>,
2350 <&apps_smmu 0x722 0x0>;
2351 reg = <0 0x1e40000 0 0x7000>,
2352 <0 0x1e47000 0 0x2000>,
2353 <0 0x1e04000 0 0x2c000>;
2354 reg-names = "ipa-reg",
2358 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2359 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2360 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2361 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2362 interrupt-names = "ipa",
2367 clocks = <&rpmhcc RPMH_IPA_CLK>;
2368 clock-names = "core";
2370 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2371 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2372 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2373 interconnect-names = "memory",
2377 qcom,smem-states = <&ipa_smp2p_out 0>,
2379 qcom,smem-state-names = "ipa-clock-enabled-valid",
2380 "ipa-clock-enabled";
2382 status = "disabled";
2385 tcsr_mutex_regs: syscon@1f40000 {
2386 compatible = "syscon";
2387 reg = <0 0x01f40000 0 0x40000>;
2390 tlmm: pinctrl@3400000 {
2391 compatible = "qcom,sdm845-pinctrl";
2392 reg = <0 0x03400000 0 0xc00000>;
2393 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2396 interrupt-controller;
2397 #interrupt-cells = <2>;
2398 gpio-ranges = <&tlmm 0 0 151>;
2399 wakeup-parent = <&pdc_intc>;
2401 cci0_default: cci0-default {
2403 pins = "gpio17", "gpio18";
2404 function = "cci_i2c";
2407 drive-strength = <2>; /* 2 mA */
2410 cci0_sleep: cci0-sleep {
2412 pins = "gpio17", "gpio18";
2413 function = "cci_i2c";
2415 drive-strength = <2>; /* 2 mA */
2419 cci1_default: cci1-default {
2421 pins = "gpio19", "gpio20";
2422 function = "cci_i2c";
2425 drive-strength = <2>; /* 2 mA */
2428 cci1_sleep: cci1-sleep {
2430 pins = "gpio19", "gpio20";
2431 function = "cci_i2c";
2433 drive-strength = <2>; /* 2 mA */
2437 qspi_clk: qspi-clk {
2440 function = "qspi_clk";
2444 qspi_cs0: qspi-cs0 {
2447 function = "qspi_cs";
2451 qspi_cs1: qspi-cs1 {
2454 function = "qspi_cs";
2458 qspi_data01: qspi-data01 {
2460 pins = "gpio91", "gpio92";
2461 function = "qspi_data";
2465 qspi_data12: qspi-data12 {
2467 pins = "gpio93", "gpio94";
2468 function = "qspi_data";
2472 qup_i2c0_default: qup-i2c0-default {
2474 pins = "gpio0", "gpio1";
2479 qup_i2c1_default: qup-i2c1-default {
2481 pins = "gpio17", "gpio18";
2486 qup_i2c2_default: qup-i2c2-default {
2488 pins = "gpio27", "gpio28";
2493 qup_i2c3_default: qup-i2c3-default {
2495 pins = "gpio41", "gpio42";
2500 qup_i2c4_default: qup-i2c4-default {
2502 pins = "gpio89", "gpio90";
2507 qup_i2c5_default: qup-i2c5-default {
2509 pins = "gpio85", "gpio86";
2514 qup_i2c6_default: qup-i2c6-default {
2516 pins = "gpio45", "gpio46";
2521 qup_i2c7_default: qup-i2c7-default {
2523 pins = "gpio93", "gpio94";
2528 qup_i2c8_default: qup-i2c8-default {
2530 pins = "gpio65", "gpio66";
2535 qup_i2c9_default: qup-i2c9-default {
2537 pins = "gpio6", "gpio7";
2542 qup_i2c10_default: qup-i2c10-default {
2544 pins = "gpio55", "gpio56";
2549 qup_i2c11_default: qup-i2c11-default {
2551 pins = "gpio31", "gpio32";
2556 qup_i2c12_default: qup-i2c12-default {
2558 pins = "gpio49", "gpio50";
2563 qup_i2c13_default: qup-i2c13-default {
2565 pins = "gpio105", "gpio106";
2570 qup_i2c14_default: qup-i2c14-default {
2572 pins = "gpio33", "gpio34";
2577 qup_i2c15_default: qup-i2c15-default {
2579 pins = "gpio81", "gpio82";
2584 qup_spi0_default: qup-spi0-default {
2586 pins = "gpio0", "gpio1",
2592 qup_spi1_default: qup-spi1-default {
2594 pins = "gpio17", "gpio18",
2600 qup_spi2_default: qup-spi2-default {
2602 pins = "gpio27", "gpio28",
2608 qup_spi3_default: qup-spi3-default {
2610 pins = "gpio41", "gpio42",
2616 qup_spi4_default: qup-spi4-default {
2618 pins = "gpio89", "gpio90",
2624 qup_spi5_default: qup-spi5-default {
2626 pins = "gpio85", "gpio86",
2632 qup_spi6_default: qup-spi6-default {
2634 pins = "gpio45", "gpio46",
2640 qup_spi7_default: qup-spi7-default {
2642 pins = "gpio93", "gpio94",
2648 qup_spi8_default: qup-spi8-default {
2650 pins = "gpio65", "gpio66",
2656 qup_spi9_default: qup-spi9-default {
2658 pins = "gpio6", "gpio7",
2664 qup_spi10_default: qup-spi10-default {
2666 pins = "gpio55", "gpio56",
2672 qup_spi11_default: qup-spi11-default {
2674 pins = "gpio31", "gpio32",
2680 qup_spi12_default: qup-spi12-default {
2682 pins = "gpio49", "gpio50",
2688 qup_spi13_default: qup-spi13-default {
2690 pins = "gpio105", "gpio106",
2691 "gpio107", "gpio108";
2696 qup_spi14_default: qup-spi14-default {
2698 pins = "gpio33", "gpio34",
2704 qup_spi15_default: qup-spi15-default {
2706 pins = "gpio81", "gpio82",
2712 qup_uart0_default: qup-uart0-default {
2714 pins = "gpio2", "gpio3";
2719 qup_uart1_default: qup-uart1-default {
2721 pins = "gpio19", "gpio20";
2726 qup_uart2_default: qup-uart2-default {
2728 pins = "gpio29", "gpio30";
2733 qup_uart3_default: qup-uart3-default {
2735 pins = "gpio43", "gpio44";
2740 qup_uart4_default: qup-uart4-default {
2742 pins = "gpio91", "gpio92";
2747 qup_uart5_default: qup-uart5-default {
2749 pins = "gpio87", "gpio88";
2754 qup_uart6_default: qup-uart6-default {
2756 pins = "gpio47", "gpio48";
2761 qup_uart7_default: qup-uart7-default {
2763 pins = "gpio95", "gpio96";
2768 qup_uart8_default: qup-uart8-default {
2770 pins = "gpio67", "gpio68";
2775 qup_uart9_default: qup-uart9-default {
2777 pins = "gpio4", "gpio5";
2782 qup_uart10_default: qup-uart10-default {
2784 pins = "gpio53", "gpio54";
2789 qup_uart11_default: qup-uart11-default {
2791 pins = "gpio33", "gpio34";
2796 qup_uart12_default: qup-uart12-default {
2798 pins = "gpio51", "gpio52";
2803 qup_uart13_default: qup-uart13-default {
2805 pins = "gpio107", "gpio108";
2810 qup_uart14_default: qup-uart14-default {
2812 pins = "gpio31", "gpio32";
2817 qup_uart15_default: qup-uart15-default {
2819 pins = "gpio83", "gpio84";
2824 quat_mi2s_sleep: quat_mi2s_sleep {
2826 pins = "gpio58", "gpio59";
2831 pins = "gpio58", "gpio59";
2832 drive-strength = <2>;
2838 quat_mi2s_active: quat_mi2s_active {
2840 pins = "gpio58", "gpio59";
2841 function = "qua_mi2s";
2845 pins = "gpio58", "gpio59";
2846 drive-strength = <8>;
2852 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2860 drive-strength = <2>;
2866 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2869 function = "qua_mi2s";
2874 drive-strength = <8>;
2879 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2887 drive-strength = <2>;
2893 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2896 function = "qua_mi2s";
2901 drive-strength = <8>;
2906 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2914 drive-strength = <2>;
2920 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2923 function = "qua_mi2s";
2928 drive-strength = <8>;
2933 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2941 drive-strength = <2>;
2947 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2950 function = "qua_mi2s";
2955 drive-strength = <8>;
2961 mss_pil: remoteproc@4080000 {
2962 compatible = "qcom,sdm845-mss-pil";
2963 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2964 reg-names = "qdsp6", "rmb";
2966 interrupts-extended =
2967 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2968 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2969 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2970 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2971 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2972 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2973 interrupt-names = "wdog", "fatal", "ready",
2974 "handover", "stop-ack",
2977 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2978 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2979 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2980 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2981 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2982 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2983 <&gcc GCC_PRNG_AHB_CLK>,
2984 <&rpmhcc RPMH_CXO_CLK>;
2985 clock-names = "iface", "bus", "mem", "gpll0_mss",
2986 "snoc_axi", "mnoc_axi", "prng", "xo";
2988 qcom,qmp = <&aoss_qmp>;
2990 qcom,smem-states = <&modem_smp2p_out 0>;
2991 qcom,smem-state-names = "stop";
2993 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2994 <&pdc_reset PDC_MODEM_SYNC_RESET>;
2995 reset-names = "mss_restart", "pdc_reset";
2997 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2999 power-domains = <&rpmhpd SDM845_CX>,
3000 <&rpmhpd SDM845_MX>,
3001 <&rpmhpd SDM845_MSS>;
3002 power-domain-names = "cx", "mx", "mss";
3004 status = "disabled";
3007 memory-region = <&mba_region>;
3011 memory-region = <&mpss_region>;
3015 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3017 qcom,remote-pid = <1>;
3018 mboxes = <&apss_shared 12>;
3022 gpucc: clock-controller@5090000 {
3023 compatible = "qcom,sdm845-gpucc";
3024 reg = <0 0x05090000 0 0x9000>;
3027 #power-domain-cells = <1>;
3028 clocks = <&rpmhcc RPMH_CXO_CLK>,
3029 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3030 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3031 clock-names = "bi_tcxo",
3032 "gcc_gpu_gpll0_clk_src",
3033 "gcc_gpu_gpll0_div_clk_src";
3037 compatible = "arm,coresight-stm", "arm,primecell";
3038 reg = <0 0x06002000 0 0x1000>,
3039 <0 0x16280000 0 0x180000>;
3040 reg-names = "stm-base", "stm-stimulus-base";
3042 clocks = <&aoss_qmp>;
3043 clock-names = "apb_pclk";
3056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3057 reg = <0 0x06041000 0 0x1000>;
3059 clocks = <&aoss_qmp>;
3060 clock-names = "apb_pclk";
3064 funnel0_out: endpoint {
3066 <&merge_funnel_in0>;
3072 #address-cells = <1>;
3077 funnel0_in7: endpoint {
3078 remote-endpoint = <&stm_out>;
3085 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3086 reg = <0 0x06043000 0 0x1000>;
3088 clocks = <&aoss_qmp>;
3089 clock-names = "apb_pclk";
3093 funnel2_out: endpoint {
3095 <&merge_funnel_in2>;
3101 #address-cells = <1>;
3106 funnel2_in5: endpoint {
3108 <&apss_merge_funnel_out>;
3115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3116 reg = <0 0x06045000 0 0x1000>;
3118 clocks = <&aoss_qmp>;
3119 clock-names = "apb_pclk";
3123 merge_funnel_out: endpoint {
3124 remote-endpoint = <&etf_in>;
3130 #address-cells = <1>;
3135 merge_funnel_in0: endpoint {
3143 merge_funnel_in2: endpoint {
3151 replicator@6046000 {
3152 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3153 reg = <0 0x06046000 0 0x1000>;
3155 clocks = <&aoss_qmp>;
3156 clock-names = "apb_pclk";
3160 replicator_out: endpoint {
3161 remote-endpoint = <&etr_in>;
3168 replicator_in: endpoint {
3169 remote-endpoint = <&etf_out>;
3176 compatible = "arm,coresight-tmc", "arm,primecell";
3177 reg = <0 0x06047000 0 0x1000>;
3179 clocks = <&aoss_qmp>;
3180 clock-names = "apb_pclk";
3192 #address-cells = <1>;
3199 <&merge_funnel_out>;
3206 compatible = "arm,coresight-tmc", "arm,primecell";
3207 reg = <0 0x06048000 0 0x1000>;
3209 clocks = <&aoss_qmp>;
3210 clock-names = "apb_pclk";
3224 compatible = "arm,coresight-etm4x", "arm,primecell";
3225 reg = <0 0x07040000 0 0x1000>;
3229 clocks = <&aoss_qmp>;
3230 clock-names = "apb_pclk";
3231 arm,coresight-loses-context-with-cpu;
3235 etm0_out: endpoint {
3244 compatible = "arm,coresight-etm4x", "arm,primecell";
3245 reg = <0 0x07140000 0 0x1000>;
3249 clocks = <&aoss_qmp>;
3250 clock-names = "apb_pclk";
3251 arm,coresight-loses-context-with-cpu;
3255 etm1_out: endpoint {
3264 compatible = "arm,coresight-etm4x", "arm,primecell";
3265 reg = <0 0x07240000 0 0x1000>;
3269 clocks = <&aoss_qmp>;
3270 clock-names = "apb_pclk";
3271 arm,coresight-loses-context-with-cpu;
3275 etm2_out: endpoint {
3284 compatible = "arm,coresight-etm4x", "arm,primecell";
3285 reg = <0 0x07340000 0 0x1000>;
3289 clocks = <&aoss_qmp>;
3290 clock-names = "apb_pclk";
3291 arm,coresight-loses-context-with-cpu;
3295 etm3_out: endpoint {
3304 compatible = "arm,coresight-etm4x", "arm,primecell";
3305 reg = <0 0x07440000 0 0x1000>;
3309 clocks = <&aoss_qmp>;
3310 clock-names = "apb_pclk";
3311 arm,coresight-loses-context-with-cpu;
3315 etm4_out: endpoint {
3324 compatible = "arm,coresight-etm4x", "arm,primecell";
3325 reg = <0 0x07540000 0 0x1000>;
3329 clocks = <&aoss_qmp>;
3330 clock-names = "apb_pclk";
3331 arm,coresight-loses-context-with-cpu;
3335 etm5_out: endpoint {
3344 compatible = "arm,coresight-etm4x", "arm,primecell";
3345 reg = <0 0x07640000 0 0x1000>;
3349 clocks = <&aoss_qmp>;
3350 clock-names = "apb_pclk";
3351 arm,coresight-loses-context-with-cpu;
3355 etm6_out: endpoint {
3364 compatible = "arm,coresight-etm4x", "arm,primecell";
3365 reg = <0 0x07740000 0 0x1000>;
3369 clocks = <&aoss_qmp>;
3370 clock-names = "apb_pclk";
3371 arm,coresight-loses-context-with-cpu;
3375 etm7_out: endpoint {
3383 funnel@7800000 { /* APSS Funnel */
3384 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3385 reg = <0 0x07800000 0 0x1000>;
3387 clocks = <&aoss_qmp>;
3388 clock-names = "apb_pclk";
3392 apss_funnel_out: endpoint {
3394 <&apss_merge_funnel_in>;
3400 #address-cells = <1>;
3405 apss_funnel_in0: endpoint {
3413 apss_funnel_in1: endpoint {
3421 apss_funnel_in2: endpoint {
3429 apss_funnel_in3: endpoint {
3437 apss_funnel_in4: endpoint {
3445 apss_funnel_in5: endpoint {
3453 apss_funnel_in6: endpoint {
3461 apss_funnel_in7: endpoint {
3470 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3471 reg = <0 0x07810000 0 0x1000>;
3473 clocks = <&aoss_qmp>;
3474 clock-names = "apb_pclk";
3478 apss_merge_funnel_out: endpoint {
3487 apss_merge_funnel_in: endpoint {
3495 sdhc_2: sdhci@8804000 {
3496 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3497 reg = <0 0x08804000 0 0x1000>;
3499 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3500 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3501 interrupt-names = "hc_irq", "pwr_irq";
3503 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3504 <&gcc GCC_SDCC2_APPS_CLK>,
3505 <&rpmhcc RPMH_CXO_CLK>;
3506 clock-names = "iface", "core", "xo";
3507 iommus = <&apps_smmu 0xa0 0xf>;
3508 power-domains = <&rpmhpd SDM845_CX>;
3509 operating-points-v2 = <&sdhc2_opp_table>;
3511 status = "disabled";
3513 sdhc2_opp_table: sdhc2-opp-table {
3514 compatible = "operating-points-v2";
3517 opp-hz = /bits/ 64 <9600000>;
3518 required-opps = <&rpmhpd_opp_min_svs>;
3522 opp-hz = /bits/ 64 <19200000>;
3523 required-opps = <&rpmhpd_opp_low_svs>;
3527 opp-hz = /bits/ 64 <100000000>;
3528 required-opps = <&rpmhpd_opp_svs>;
3532 opp-hz = /bits/ 64 <201500000>;
3533 required-opps = <&rpmhpd_opp_svs_l1>;
3538 qspi_opp_table: qspi-opp-table {
3539 compatible = "operating-points-v2";
3542 opp-hz = /bits/ 64 <19200000>;
3543 required-opps = <&rpmhpd_opp_min_svs>;
3547 opp-hz = /bits/ 64 <100000000>;
3548 required-opps = <&rpmhpd_opp_low_svs>;
3552 opp-hz = /bits/ 64 <150000000>;
3553 required-opps = <&rpmhpd_opp_svs>;
3557 opp-hz = /bits/ 64 <300000000>;
3558 required-opps = <&rpmhpd_opp_nom>;
3563 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3564 reg = <0 0x088df000 0 0x600>;
3565 #address-cells = <1>;
3567 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3568 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3569 <&gcc GCC_QSPI_CORE_CLK>;
3570 clock-names = "iface", "core";
3571 power-domains = <&rpmhpd SDM845_CX>;
3572 operating-points-v2 = <&qspi_opp_table>;
3573 status = "disabled";
3576 slim: slim@171c0000 {
3577 compatible = "qcom,slim-ngd-v2.1.0";
3578 reg = <0 0x171c0000 0 0x2c000>;
3579 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3581 qcom,apps-ch-pipes = <0x780000>;
3582 qcom,ea-pc = <0x270>;
3584 dmas = <&slimbam 3>, <&slimbam 4>,
3585 <&slimbam 5>, <&slimbam 6>;
3586 dma-names = "rx", "tx", "tx2", "rx2";
3588 iommus = <&apps_smmu 0x1806 0x0>;
3589 #address-cells = <1>;
3594 #address-cells = <2>;
3598 compatible = "slim217,250";
3603 compatible = "slim217,250";
3605 slim-ifc-dev = <&wcd9340_ifd>;
3607 #sound-dai-cells = <1>;
3609 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3610 interrupt-controller;
3611 #interrupt-cells = <1>;
3614 clock-frequency = <9600000>;
3615 clock-output-names = "mclk";
3616 qcom,micbias1-millivolt = <1800>;
3617 qcom,micbias2-millivolt = <1800>;
3618 qcom,micbias3-millivolt = <1800>;
3619 qcom,micbias4-millivolt = <1800>;
3621 #address-cells = <1>;
3624 wcdgpio: gpio-controller@42 {
3625 compatible = "qcom,wcd9340-gpio";
3632 compatible = "qcom,soundwire-v1.3.0";
3634 interrupts-extended = <&wcd9340 20>;
3636 qcom,dout-ports = <6>;
3637 qcom,din-ports = <2>;
3638 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3639 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3640 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3642 #sound-dai-cells = <1>;
3643 clocks = <&wcd9340>;
3644 clock-names = "iface";
3645 #address-cells = <2>;
3654 lmh_cluster1: lmh@17d70800 {
3655 compatible = "qcom,sdm845-lmh";
3656 reg = <0 0x17d70800 0 0x400>;
3657 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3659 qcom,lmh-temp-arm-millicelsius = <65000>;
3660 qcom,lmh-temp-low-millicelsius = <94500>;
3661 qcom,lmh-temp-high-millicelsius = <95000>;
3662 interrupt-controller;
3663 #interrupt-cells = <1>;
3666 lmh_cluster0: lmh@17d78800 {
3667 compatible = "qcom,sdm845-lmh";
3668 reg = <0 0x17d78800 0 0x400>;
3669 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3671 qcom,lmh-temp-arm-millicelsius = <65000>;
3672 qcom,lmh-temp-low-millicelsius = <94500>;
3673 qcom,lmh-temp-high-millicelsius = <95000>;
3674 interrupt-controller;
3675 #interrupt-cells = <1>;
3681 usb_1_hsphy: phy@88e2000 {
3682 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3683 reg = <0 0x088e2000 0 0x400>;
3684 status = "disabled";
3687 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3688 <&rpmhcc RPMH_CXO_CLK>;
3689 clock-names = "cfg_ahb", "ref";
3691 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3693 nvmem-cells = <&qusb2p_hstx_trim>;
3696 usb_2_hsphy: phy@88e3000 {
3697 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3698 reg = <0 0x088e3000 0 0x400>;
3699 status = "disabled";
3702 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3703 <&rpmhcc RPMH_CXO_CLK>;
3704 clock-names = "cfg_ahb", "ref";
3706 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3708 nvmem-cells = <&qusb2s_hstx_trim>;
3711 usb_1_qmpphy: phy@88e9000 {
3712 compatible = "qcom,sdm845-qmp-usb3-phy";
3713 reg = <0 0x088e9000 0 0x18c>,
3714 <0 0x088e8000 0 0x10>;
3715 status = "disabled";
3716 #address-cells = <2>;
3720 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3721 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3722 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3723 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3724 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3726 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3727 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3728 reset-names = "phy", "common";
3730 usb_1_ssphy: phy@88e9200 {
3731 reg = <0 0x088e9200 0 0x128>,
3732 <0 0x088e9400 0 0x200>,
3733 <0 0x088e9c00 0 0x218>,
3734 <0 0x088e9600 0 0x128>,
3735 <0 0x088e9800 0 0x200>,
3736 <0 0x088e9a00 0 0x100>;
3739 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3740 clock-names = "pipe0";
3741 clock-output-names = "usb3_phy_pipe_clk_src";
3745 usb_2_qmpphy: phy@88eb000 {
3746 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3747 reg = <0 0x088eb000 0 0x18c>;
3748 status = "disabled";
3749 #address-cells = <2>;
3753 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3754 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3755 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3756 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3757 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3759 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3760 <&gcc GCC_USB3_PHY_SEC_BCR>;
3761 reset-names = "phy", "common";
3763 usb_2_ssphy: phy@88eb200 {
3764 reg = <0 0x088eb200 0 0x128>,
3765 <0 0x088eb400 0 0x1fc>,
3766 <0 0x088eb800 0 0x218>,
3767 <0 0x088eb600 0 0x70>;
3770 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3771 clock-names = "pipe0";
3772 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3776 usb_1: usb@a6f8800 {
3777 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3778 reg = <0 0x0a6f8800 0 0x400>;
3779 status = "disabled";
3780 #address-cells = <2>;
3785 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3786 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3787 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3788 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3789 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3790 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3793 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3794 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3795 assigned-clock-rates = <19200000>, <150000000>;
3797 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3798 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3799 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3800 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3801 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3802 "dm_hs_phy_irq", "dp_hs_phy_irq";
3804 power-domains = <&gcc USB30_PRIM_GDSC>;
3806 resets = <&gcc GCC_USB30_PRIM_BCR>;
3808 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3809 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3810 interconnect-names = "usb-ddr", "apps-usb";
3812 usb_1_dwc3: dwc3@a600000 {
3813 compatible = "snps,dwc3";
3814 reg = <0 0x0a600000 0 0xcd00>;
3815 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3816 iommus = <&apps_smmu 0x740 0>;
3817 snps,dis_u2_susphy_quirk;
3818 snps,dis_enblslpm_quirk;
3819 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3820 phy-names = "usb2-phy", "usb3-phy";
3824 usb_2: usb@a8f8800 {
3825 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3826 reg = <0 0x0a8f8800 0 0x400>;
3827 status = "disabled";
3828 #address-cells = <2>;
3833 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3834 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3835 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3836 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3837 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3838 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3841 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3842 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3843 assigned-clock-rates = <19200000>, <150000000>;
3845 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3846 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3847 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3848 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3849 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3850 "dm_hs_phy_irq", "dp_hs_phy_irq";
3852 power-domains = <&gcc USB30_SEC_GDSC>;
3854 resets = <&gcc GCC_USB30_SEC_BCR>;
3856 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3857 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3858 interconnect-names = "usb-ddr", "apps-usb";
3860 usb_2_dwc3: dwc3@a800000 {
3861 compatible = "snps,dwc3";
3862 reg = <0 0x0a800000 0 0xcd00>;
3863 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3864 iommus = <&apps_smmu 0x760 0>;
3865 snps,dis_u2_susphy_quirk;
3866 snps,dis_enblslpm_quirk;
3867 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3868 phy-names = "usb2-phy", "usb3-phy";
3872 venus: video-codec@aa00000 {
3873 compatible = "qcom,sdm845-venus-v2";
3874 reg = <0 0x0aa00000 0 0xff000>;
3875 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3876 power-domains = <&videocc VENUS_GDSC>,
3877 <&videocc VCODEC0_GDSC>,
3878 <&videocc VCODEC1_GDSC>,
3879 <&rpmhpd SDM845_CX>;
3880 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3881 operating-points-v2 = <&venus_opp_table>;
3882 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3883 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3884 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3885 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3886 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3887 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3888 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3889 clock-names = "core", "iface", "bus",
3890 "vcodec0_core", "vcodec0_bus",
3891 "vcodec1_core", "vcodec1_bus";
3892 iommus = <&apps_smmu 0x10a0 0x8>,
3893 <&apps_smmu 0x10b0 0x0>;
3894 memory-region = <&venus_mem>;
3895 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3896 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3897 interconnect-names = "video-mem", "cpu-cfg";
3899 status = "disabled";
3902 compatible = "venus-decoder";
3906 compatible = "venus-encoder";
3909 venus_opp_table: venus-opp-table {
3910 compatible = "operating-points-v2";
3913 opp-hz = /bits/ 64 <100000000>;
3914 required-opps = <&rpmhpd_opp_min_svs>;
3918 opp-hz = /bits/ 64 <200000000>;
3919 required-opps = <&rpmhpd_opp_low_svs>;
3923 opp-hz = /bits/ 64 <320000000>;
3924 required-opps = <&rpmhpd_opp_svs>;
3928 opp-hz = /bits/ 64 <380000000>;
3929 required-opps = <&rpmhpd_opp_svs_l1>;
3933 opp-hz = /bits/ 64 <444000000>;
3934 required-opps = <&rpmhpd_opp_nom>;
3938 opp-hz = /bits/ 64 <533000097>;
3939 required-opps = <&rpmhpd_opp_turbo>;
3944 videocc: clock-controller@ab00000 {
3945 compatible = "qcom,sdm845-videocc";
3946 reg = <0 0x0ab00000 0 0x10000>;
3947 clocks = <&rpmhcc RPMH_CXO_CLK>;
3948 clock-names = "bi_tcxo";
3950 #power-domain-cells = <1>;
3954 camss: camss@a00000 {
3955 compatible = "qcom,sdm845-camss";
3957 reg = <0 0xacb3000 0 0x1000>,
3958 <0 0xacba000 0 0x1000>,
3959 <0 0xacc8000 0 0x1000>,
3960 <0 0xac65000 0 0x1000>,
3961 <0 0xac66000 0 0x1000>,
3962 <0 0xac67000 0 0x1000>,
3963 <0 0xac68000 0 0x1000>,
3964 <0 0xacaf000 0 0x4000>,
3965 <0 0xacb6000 0 0x4000>,
3966 <0 0xacc4000 0 0x4000>;
3967 reg-names = "csid0",
3978 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3979 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3980 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3981 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3982 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3983 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3984 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3985 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3986 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3987 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
3988 interrupt-names = "csid0",
3999 power-domains = <&clock_camcc IFE_0_GDSC>,
4000 <&clock_camcc IFE_1_GDSC>,
4001 <&clock_camcc TITAN_TOP_GDSC>;
4003 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4004 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4005 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4006 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4007 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4008 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4009 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4010 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4011 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4012 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4013 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4014 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4015 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4016 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4017 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4018 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4019 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4020 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4021 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4022 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4023 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4024 <&gcc GCC_CAMERA_AHB_CLK>,
4025 <&gcc GCC_CAMERA_AXI_CLK>,
4026 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4027 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4028 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4029 <&clock_camcc CAM_CC_IFE_0_CLK>,
4030 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4031 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4032 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4033 <&clock_camcc CAM_CC_IFE_1_CLK>,
4034 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4035 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4036 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4037 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4038 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4039 clock-names = "camnoc_axi",
4050 "csiphy0_timer_src",
4053 "csiphy1_timer_src",
4056 "csiphy2_timer_src",
4059 "csiphy3_timer_src",
4076 iommus = <&apps_smmu 0x0808 0x0>,
4077 <&apps_smmu 0x0810 0x8>,
4078 <&apps_smmu 0x0c08 0x0>,
4079 <&apps_smmu 0x0c10 0x8>;
4081 status = "disabled";
4084 #address-cells = <1>;
4090 compatible = "qcom,sdm845-cci";
4091 #address-cells = <1>;
4094 reg = <0 0x0ac4a000 0 0x4000>;
4095 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4096 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4098 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4099 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4100 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4101 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4102 <&clock_camcc CAM_CC_CCI_CLK>,
4103 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4104 clock-names = "camnoc_axi",
4111 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4112 <&clock_camcc CAM_CC_CCI_CLK>;
4113 assigned-clock-rates = <80000000>, <37500000>;
4115 pinctrl-names = "default", "sleep";
4116 pinctrl-0 = <&cci0_default &cci1_default>;
4117 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4119 status = "disabled";
4121 cci_i2c0: i2c-bus@0 {
4123 clock-frequency = <1000000>;
4124 #address-cells = <1>;
4128 cci_i2c1: i2c-bus@1 {
4130 clock-frequency = <1000000>;
4131 #address-cells = <1>;
4136 clock_camcc: clock-controller@ad00000 {
4137 compatible = "qcom,sdm845-camcc";
4138 reg = <0 0x0ad00000 0 0x10000>;
4141 #power-domain-cells = <1>;
4144 dsi_opp_table: dsi-opp-table {
4145 compatible = "operating-points-v2";
4148 opp-hz = /bits/ 64 <19200000>;
4149 required-opps = <&rpmhpd_opp_min_svs>;
4153 opp-hz = /bits/ 64 <180000000>;
4154 required-opps = <&rpmhpd_opp_low_svs>;
4158 opp-hz = /bits/ 64 <275000000>;
4159 required-opps = <&rpmhpd_opp_svs>;
4163 opp-hz = /bits/ 64 <328580000>;
4164 required-opps = <&rpmhpd_opp_svs_l1>;
4168 opp-hz = /bits/ 64 <358000000>;
4169 required-opps = <&rpmhpd_opp_nom>;
4173 mdss: mdss@ae00000 {
4174 compatible = "qcom,sdm845-mdss";
4175 reg = <0 0x0ae00000 0 0x1000>;
4178 power-domains = <&dispcc MDSS_GDSC>;
4180 clocks = <&gcc GCC_DISP_AHB_CLK>,
4181 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4182 clock-names = "iface", "core";
4184 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4185 assigned-clock-rates = <300000000>;
4187 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-controller;
4189 #interrupt-cells = <1>;
4191 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4192 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4193 interconnect-names = "mdp0-mem", "mdp1-mem";
4195 iommus = <&apps_smmu 0x880 0x8>,
4196 <&apps_smmu 0xc80 0x8>;
4198 status = "disabled";
4200 #address-cells = <2>;
4204 mdss_mdp: mdp@ae01000 {
4205 compatible = "qcom,sdm845-dpu";
4206 reg = <0 0x0ae01000 0 0x8f000>,
4207 <0 0x0aeb0000 0 0x2008>;
4208 reg-names = "mdp", "vbif";
4210 clocks = <&gcc GCC_DISP_AXI_CLK>,
4211 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4212 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4213 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4214 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4215 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4217 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4218 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4219 assigned-clock-rates = <300000000>,
4221 operating-points-v2 = <&mdp_opp_table>;
4222 power-domains = <&rpmhpd SDM845_CX>;
4224 interrupt-parent = <&mdss>;
4225 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4228 #address-cells = <1>;
4233 dpu_intf1_out: endpoint {
4234 remote-endpoint = <&dsi0_in>;
4240 dpu_intf2_out: endpoint {
4241 remote-endpoint = <&dsi1_in>;
4246 mdp_opp_table: mdp-opp-table {
4247 compatible = "operating-points-v2";
4250 opp-hz = /bits/ 64 <19200000>;
4251 required-opps = <&rpmhpd_opp_min_svs>;
4255 opp-hz = /bits/ 64 <171428571>;
4256 required-opps = <&rpmhpd_opp_low_svs>;
4260 opp-hz = /bits/ 64 <344000000>;
4261 required-opps = <&rpmhpd_opp_svs_l1>;
4265 opp-hz = /bits/ 64 <430000000>;
4266 required-opps = <&rpmhpd_opp_nom>;
4272 compatible = "qcom,mdss-dsi-ctrl";
4273 reg = <0 0x0ae94000 0 0x400>;
4274 reg-names = "dsi_ctrl";
4276 interrupt-parent = <&mdss>;
4277 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4279 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4280 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4281 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4282 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4283 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4284 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4285 clock-names = "byte",
4291 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4292 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4294 operating-points-v2 = <&dsi_opp_table>;
4295 power-domains = <&rpmhpd SDM845_CX>;
4300 status = "disabled";
4302 #address-cells = <1>;
4306 #address-cells = <1>;
4312 remote-endpoint = <&dpu_intf1_out>;
4318 dsi0_out: endpoint {
4324 dsi0_phy: dsi-phy@ae94400 {
4325 compatible = "qcom,dsi-phy-10nm";
4326 reg = <0 0x0ae94400 0 0x200>,
4327 <0 0x0ae94600 0 0x280>,
4328 <0 0x0ae94a00 0 0x1e0>;
4329 reg-names = "dsi_phy",
4336 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4337 <&rpmhcc RPMH_CXO_CLK>;
4338 clock-names = "iface", "ref";
4340 status = "disabled";
4344 compatible = "qcom,mdss-dsi-ctrl";
4345 reg = <0 0x0ae96000 0 0x400>;
4346 reg-names = "dsi_ctrl";
4348 interrupt-parent = <&mdss>;
4349 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4351 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4352 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4353 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4354 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4355 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4356 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4357 clock-names = "byte",
4363 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4364 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4366 operating-points-v2 = <&dsi_opp_table>;
4367 power-domains = <&rpmhpd SDM845_CX>;
4372 status = "disabled";
4374 #address-cells = <1>;
4378 #address-cells = <1>;
4384 remote-endpoint = <&dpu_intf2_out>;
4390 dsi1_out: endpoint {
4396 dsi1_phy: dsi-phy@ae96400 {
4397 compatible = "qcom,dsi-phy-10nm";
4398 reg = <0 0x0ae96400 0 0x200>,
4399 <0 0x0ae96600 0 0x280>,
4400 <0 0x0ae96a00 0 0x10e>;
4401 reg-names = "dsi_phy",
4408 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4409 <&rpmhcc RPMH_CXO_CLK>;
4410 clock-names = "iface", "ref";
4412 status = "disabled";
4417 compatible = "qcom,adreno-630.2", "qcom,adreno";
4419 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4420 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4423 * Look ma, no clocks! The GPU clocks and power are
4424 * controlled entirely by the GMU
4427 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4429 iommus = <&adreno_smmu 0>;
4431 operating-points-v2 = <&gpu_opp_table>;
4435 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4436 interconnect-names = "gfx-mem";
4438 status = "disabled";
4440 gpu_opp_table: opp-table {
4441 compatible = "operating-points-v2";
4444 opp-hz = /bits/ 64 <710000000>;
4445 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4446 opp-peak-kBps = <7216000>;
4450 opp-hz = /bits/ 64 <675000000>;
4451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4452 opp-peak-kBps = <7216000>;
4456 opp-hz = /bits/ 64 <596000000>;
4457 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4458 opp-peak-kBps = <6220000>;
4462 opp-hz = /bits/ 64 <520000000>;
4463 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4464 opp-peak-kBps = <6220000>;
4468 opp-hz = /bits/ 64 <414000000>;
4469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4470 opp-peak-kBps = <4068000>;
4474 opp-hz = /bits/ 64 <342000000>;
4475 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4476 opp-peak-kBps = <2724000>;
4480 opp-hz = /bits/ 64 <257000000>;
4481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4482 opp-peak-kBps = <1648000>;
4487 adreno_smmu: iommu@5040000 {
4488 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4489 reg = <0 0x5040000 0 0x10000>;
4491 #global-interrupts = <2>;
4492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4495 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4496 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4497 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4498 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4499 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4500 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4501 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4502 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4503 <&gcc GCC_GPU_CFG_AHB_CLK>;
4504 clock-names = "bus", "iface";
4506 power-domains = <&gpucc GPU_CX_GDSC>;
4510 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4512 reg = <0 0x506a000 0 0x30000>,
4513 <0 0xb280000 0 0x10000>,
4514 <0 0xb480000 0 0x10000>;
4515 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4517 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4518 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4519 interrupt-names = "hfi", "gmu";
4521 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4522 <&gpucc GPU_CC_CXO_CLK>,
4523 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4524 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4525 clock-names = "gmu", "cxo", "axi", "memnoc";
4527 power-domains = <&gpucc GPU_CX_GDSC>,
4528 <&gpucc GPU_GX_GDSC>;
4529 power-domain-names = "cx", "gx";
4531 iommus = <&adreno_smmu 5>;
4533 operating-points-v2 = <&gmu_opp_table>;
4535 status = "disabled";
4537 gmu_opp_table: opp-table {
4538 compatible = "operating-points-v2";
4541 opp-hz = /bits/ 64 <400000000>;
4542 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4546 opp-hz = /bits/ 64 <200000000>;
4547 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4552 dispcc: clock-controller@af00000 {
4553 compatible = "qcom,sdm845-dispcc";
4554 reg = <0 0x0af00000 0 0x10000>;
4555 clocks = <&rpmhcc RPMH_CXO_CLK>,
4556 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4557 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4564 clock-names = "bi_tcxo",
4565 "gcc_disp_gpll0_clk_src",
4566 "gcc_disp_gpll0_div_clk_src",
4567 "dsi0_phy_pll_out_byteclk",
4568 "dsi0_phy_pll_out_dsiclk",
4569 "dsi1_phy_pll_out_byteclk",
4570 "dsi1_phy_pll_out_dsiclk",
4571 "dp_link_clk_divsel_ten",
4572 "dp_vco_divided_clk_src_mux";
4575 #power-domain-cells = <1>;
4578 pdc_intc: interrupt-controller@b220000 {
4579 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4580 reg = <0 0x0b220000 0 0x30000>;
4581 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4582 #interrupt-cells = <2>;
4583 interrupt-parent = <&intc>;
4584 interrupt-controller;
4587 pdc_reset: reset-controller@b2e0000 {
4588 compatible = "qcom,sdm845-pdc-global";
4589 reg = <0 0x0b2e0000 0 0x20000>;
4593 tsens0: thermal-sensor@c263000 {
4594 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4595 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4596 <0 0x0c222000 0 0x1ff>; /* SROT */
4597 #qcom,sensors = <13>;
4598 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4599 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4600 interrupt-names = "uplow", "critical";
4601 #thermal-sensor-cells = <1>;
4604 tsens1: thermal-sensor@c265000 {
4605 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4606 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4607 <0 0x0c223000 0 0x1ff>; /* SROT */
4608 #qcom,sensors = <8>;
4609 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4610 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4611 interrupt-names = "uplow", "critical";
4612 #thermal-sensor-cells = <1>;
4615 aoss_reset: reset-controller@c2a0000 {
4616 compatible = "qcom,sdm845-aoss-cc";
4617 reg = <0 0x0c2a0000 0 0x31000>;
4621 aoss_qmp: power-controller@c300000 {
4622 compatible = "qcom,sdm845-aoss-qmp";
4623 reg = <0 0x0c300000 0 0x100000>;
4624 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4625 mboxes = <&apss_shared 0>;
4630 #cooling-cells = <2>;
4634 #cooling-cells = <2>;
4638 spmi_bus: spmi@c440000 {
4639 compatible = "qcom,spmi-pmic-arb";
4640 reg = <0 0x0c440000 0 0x1100>,
4641 <0 0x0c600000 0 0x2000000>,
4642 <0 0x0e600000 0 0x100000>,
4643 <0 0x0e700000 0 0xa0000>,
4644 <0 0x0c40a000 0 0x26000>;
4645 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4646 interrupt-names = "periph_irq";
4647 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4650 #address-cells = <2>;
4652 interrupt-controller;
4653 #interrupt-cells = <4>;
4658 compatible = "simple-mfd";
4659 reg = <0 0x146bf000 0 0x1000>;
4661 #address-cells = <1>;
4664 ranges = <0 0 0x146bf000 0x1000>;
4667 compatible = "qcom,pil-reloc-info";
4672 apps_smmu: iommu@15000000 {
4673 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4674 reg = <0 0x15000000 0 0x80000>;
4676 #global-interrupts = <1>;
4677 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4678 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4679 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4680 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4681 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4682 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4683 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4684 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4685 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4686 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4687 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4688 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4689 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4690 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4691 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4692 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4693 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4694 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4695 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4696 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4697 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4698 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4699 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4700 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4701 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4702 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4703 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4704 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4705 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4706 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4707 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4708 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4709 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4710 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4711 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4712 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4713 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4714 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4715 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4716 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4717 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4718 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4719 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4720 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4721 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4722 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4723 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4724 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4725 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4726 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4727 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4728 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4729 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4730 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4731 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4732 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4733 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4734 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4735 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4736 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4737 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4738 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4739 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4740 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4741 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4744 lpasscc: clock-controller@17014000 {
4745 compatible = "qcom,sdm845-lpasscc";
4746 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4747 reg-names = "cc", "qdsp6ss";
4749 status = "disabled";
4752 gladiator_noc: interconnect@17900000 {
4753 compatible = "qcom,sdm845-gladiator-noc";
4754 reg = <0 0x17900000 0 0xd080>;
4755 #interconnect-cells = <2>;
4756 qcom,bcm-voters = <&apps_bcm_voter>;
4760 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4761 reg = <0 0x17980000 0 0x1000>;
4762 clocks = <&sleep_clk>;
4763 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4766 apss_shared: mailbox@17990000 {
4767 compatible = "qcom,sdm845-apss-shared";
4768 reg = <0 0x17990000 0 0x1000>;
4772 apps_rsc: rsc@179c0000 {
4774 compatible = "qcom,rpmh-rsc";
4775 reg = <0 0x179c0000 0 0x10000>,
4776 <0 0x179d0000 0 0x10000>,
4777 <0 0x179e0000 0 0x10000>;
4778 reg-names = "drv-0", "drv-1", "drv-2";
4779 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4780 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4781 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4782 qcom,tcs-offset = <0xd00>;
4784 qcom,tcs-config = <ACTIVE_TCS 2>,
4789 apps_bcm_voter: bcm-voter {
4790 compatible = "qcom,bcm-voter";
4793 rpmhcc: clock-controller {
4794 compatible = "qcom,sdm845-rpmh-clk";
4797 clocks = <&xo_board>;
4800 rpmhpd: power-controller {
4801 compatible = "qcom,sdm845-rpmhpd";
4802 #power-domain-cells = <1>;
4803 operating-points-v2 = <&rpmhpd_opp_table>;
4805 rpmhpd_opp_table: opp-table {
4806 compatible = "operating-points-v2";
4808 rpmhpd_opp_ret: opp1 {
4809 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4812 rpmhpd_opp_min_svs: opp2 {
4813 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4816 rpmhpd_opp_low_svs: opp3 {
4817 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4820 rpmhpd_opp_svs: opp4 {
4821 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4824 rpmhpd_opp_svs_l1: opp5 {
4825 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4828 rpmhpd_opp_nom: opp6 {
4829 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4832 rpmhpd_opp_nom_l1: opp7 {
4833 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4836 rpmhpd_opp_nom_l2: opp8 {
4837 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4840 rpmhpd_opp_turbo: opp9 {
4841 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4844 rpmhpd_opp_turbo_l1: opp10 {
4845 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4851 intc: interrupt-controller@17a00000 {
4852 compatible = "arm,gic-v3";
4853 #address-cells = <2>;
4856 #interrupt-cells = <3>;
4857 interrupt-controller;
4858 reg = <0 0x17a00000 0 0x10000>, /* GICD */
4859 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
4860 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4862 msi-controller@17a40000 {
4863 compatible = "arm,gic-v3-its";
4866 reg = <0 0x17a40000 0 0x20000>;
4867 status = "disabled";
4871 slimbam: dma-controller@17184000 {
4872 compatible = "qcom,bam-v1.7.0";
4873 qcom,controlled-remotely;
4874 reg = <0 0x17184000 0 0x2a000>;
4875 num-channels = <31>;
4876 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4880 iommus = <&apps_smmu 0x1806 0x0>;
4884 #address-cells = <2>;
4887 compatible = "arm,armv7-timer-mem";
4888 reg = <0 0x17c90000 0 0x1000>;
4892 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4893 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4894 reg = <0 0x17ca0000 0 0x1000>,
4895 <0 0x17cb0000 0 0x1000>;
4900 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4901 reg = <0 0x17cc0000 0 0x1000>;
4902 status = "disabled";
4907 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4908 reg = <0 0x17cd0000 0 0x1000>;
4909 status = "disabled";
4914 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4915 reg = <0 0x17ce0000 0 0x1000>;
4916 status = "disabled";
4921 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4922 reg = <0 0x17cf0000 0 0x1000>;
4923 status = "disabled";
4928 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4929 reg = <0 0x17d00000 0 0x1000>;
4930 status = "disabled";
4935 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4936 reg = <0 0x17d10000 0 0x1000>;
4937 status = "disabled";
4941 osm_l3: interconnect@17d41000 {
4942 compatible = "qcom,sdm845-osm-l3";
4943 reg = <0 0x17d41000 0 0x1400>;
4945 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4946 clock-names = "xo", "alternate";
4948 #interconnect-cells = <1>;
4951 cpufreq_hw: cpufreq@17d43000 {
4952 compatible = "qcom,cpufreq-hw";
4953 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4954 reg-names = "freq-domain0", "freq-domain1";
4956 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
4958 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4959 clock-names = "xo", "alternate";
4961 #freq-domain-cells = <1>;
4964 wifi: wifi@18800000 {
4965 compatible = "qcom,wcn3990-wifi";
4966 status = "disabled";
4967 reg = <0 0x18800000 0 0x800000>;
4968 reg-names = "membase";
4969 memory-region = <&wlan_msa_mem>;
4970 clock-names = "cxo_ref_clk_pin";
4971 clocks = <&rpmhcc RPMH_RF_CLK2>;
4973 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4974 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4975 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4976 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4977 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4978 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4979 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4980 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4981 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4982 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4985 iommus = <&apps_smmu 0x0040 0x1>;
4991 polling-delay-passive = <250>;
4992 polling-delay = <1000>;
4994 thermal-sensors = <&tsens0 1>;
4997 cpu0_alert0: trip-point0 {
4998 temperature = <90000>;
4999 hysteresis = <2000>;
5003 cpu0_alert1: trip-point1 {
5004 temperature = <95000>;
5005 hysteresis = <2000>;
5009 cpu0_crit: cpu_crit {
5010 temperature = <110000>;
5011 hysteresis = <1000>;
5018 polling-delay-passive = <250>;
5019 polling-delay = <1000>;
5021 thermal-sensors = <&tsens0 2>;
5024 cpu1_alert0: trip-point0 {
5025 temperature = <90000>;
5026 hysteresis = <2000>;
5030 cpu1_alert1: trip-point1 {
5031 temperature = <95000>;
5032 hysteresis = <2000>;
5036 cpu1_crit: cpu_crit {
5037 temperature = <110000>;
5038 hysteresis = <1000>;
5045 polling-delay-passive = <250>;
5046 polling-delay = <1000>;
5048 thermal-sensors = <&tsens0 3>;
5051 cpu2_alert0: trip-point0 {
5052 temperature = <90000>;
5053 hysteresis = <2000>;
5057 cpu2_alert1: trip-point1 {
5058 temperature = <95000>;
5059 hysteresis = <2000>;
5063 cpu2_crit: cpu_crit {
5064 temperature = <110000>;
5065 hysteresis = <1000>;
5072 polling-delay-passive = <250>;
5073 polling-delay = <1000>;
5075 thermal-sensors = <&tsens0 4>;
5078 cpu3_alert0: trip-point0 {
5079 temperature = <90000>;
5080 hysteresis = <2000>;
5084 cpu3_alert1: trip-point1 {
5085 temperature = <95000>;
5086 hysteresis = <2000>;
5090 cpu3_crit: cpu_crit {
5091 temperature = <110000>;
5092 hysteresis = <1000>;
5099 polling-delay-passive = <250>;
5100 polling-delay = <1000>;
5102 thermal-sensors = <&tsens0 7>;
5105 cpu4_alert0: trip-point0 {
5106 temperature = <90000>;
5107 hysteresis = <2000>;
5111 cpu4_alert1: trip-point1 {
5112 temperature = <95000>;
5113 hysteresis = <2000>;
5117 cpu4_crit: cpu_crit {
5118 temperature = <110000>;
5119 hysteresis = <1000>;
5126 polling-delay-passive = <250>;
5127 polling-delay = <1000>;
5129 thermal-sensors = <&tsens0 8>;
5132 cpu5_alert0: trip-point0 {
5133 temperature = <90000>;
5134 hysteresis = <2000>;
5138 cpu5_alert1: trip-point1 {
5139 temperature = <95000>;
5140 hysteresis = <2000>;
5144 cpu5_crit: cpu_crit {
5145 temperature = <110000>;
5146 hysteresis = <1000>;
5153 polling-delay-passive = <250>;
5154 polling-delay = <1000>;
5156 thermal-sensors = <&tsens0 9>;
5159 cpu6_alert0: trip-point0 {
5160 temperature = <90000>;
5161 hysteresis = <2000>;
5165 cpu6_alert1: trip-point1 {
5166 temperature = <95000>;
5167 hysteresis = <2000>;
5171 cpu6_crit: cpu_crit {
5172 temperature = <110000>;
5173 hysteresis = <1000>;
5180 polling-delay-passive = <250>;
5181 polling-delay = <1000>;
5183 thermal-sensors = <&tsens0 10>;
5186 cpu7_alert0: trip-point0 {
5187 temperature = <90000>;
5188 hysteresis = <2000>;
5192 cpu7_alert1: trip-point1 {
5193 temperature = <95000>;
5194 hysteresis = <2000>;
5198 cpu7_crit: cpu_crit {
5199 temperature = <110000>;
5200 hysteresis = <1000>;
5207 polling-delay-passive = <250>;
5208 polling-delay = <1000>;
5210 thermal-sensors = <&tsens0 0>;
5213 aoss0_alert0: trip-point0 {
5214 temperature = <90000>;
5215 hysteresis = <2000>;
5222 polling-delay-passive = <250>;
5223 polling-delay = <1000>;
5225 thermal-sensors = <&tsens0 5>;
5228 cluster0_alert0: trip-point0 {
5229 temperature = <90000>;
5230 hysteresis = <2000>;
5233 cluster0_crit: cluster0_crit {
5234 temperature = <110000>;
5235 hysteresis = <2000>;
5242 polling-delay-passive = <250>;
5243 polling-delay = <1000>;
5245 thermal-sensors = <&tsens0 6>;
5248 cluster1_alert0: trip-point0 {
5249 temperature = <90000>;
5250 hysteresis = <2000>;
5253 cluster1_crit: cluster1_crit {
5254 temperature = <110000>;
5255 hysteresis = <2000>;
5262 polling-delay-passive = <250>;
5263 polling-delay = <1000>;
5265 thermal-sensors = <&tsens0 11>;
5268 gpu1_alert0: trip-point0 {
5269 temperature = <90000>;
5270 hysteresis = <2000>;
5276 gpu-thermal-bottom {
5277 polling-delay-passive = <250>;
5278 polling-delay = <1000>;
5280 thermal-sensors = <&tsens0 12>;
5283 gpu2_alert0: trip-point0 {
5284 temperature = <90000>;
5285 hysteresis = <2000>;
5292 polling-delay-passive = <250>;
5293 polling-delay = <1000>;
5295 thermal-sensors = <&tsens1 0>;
5298 aoss1_alert0: trip-point0 {
5299 temperature = <90000>;
5300 hysteresis = <2000>;
5307 polling-delay-passive = <250>;
5308 polling-delay = <1000>;
5310 thermal-sensors = <&tsens1 1>;
5313 q6_modem_alert0: trip-point0 {
5314 temperature = <90000>;
5315 hysteresis = <2000>;
5322 polling-delay-passive = <250>;
5323 polling-delay = <1000>;
5325 thermal-sensors = <&tsens1 2>;
5328 mem_alert0: trip-point0 {
5329 temperature = <90000>;
5330 hysteresis = <2000>;
5337 polling-delay-passive = <250>;
5338 polling-delay = <1000>;
5340 thermal-sensors = <&tsens1 3>;
5343 wlan_alert0: trip-point0 {
5344 temperature = <90000>;
5345 hysteresis = <2000>;
5352 polling-delay-passive = <250>;
5353 polling-delay = <1000>;
5355 thermal-sensors = <&tsens1 4>;
5358 q6_hvx_alert0: trip-point0 {
5359 temperature = <90000>;
5360 hysteresis = <2000>;
5367 polling-delay-passive = <250>;
5368 polling-delay = <1000>;
5370 thermal-sensors = <&tsens1 5>;
5373 camera_alert0: trip-point0 {
5374 temperature = <90000>;
5375 hysteresis = <2000>;
5382 polling-delay-passive = <250>;
5383 polling-delay = <1000>;
5385 thermal-sensors = <&tsens1 6>;
5388 video_alert0: trip-point0 {
5389 temperature = <90000>;
5390 hysteresis = <2000>;
5397 polling-delay-passive = <250>;
5398 polling-delay = <1000>;
5400 thermal-sensors = <&tsens1 7>;
5403 modem_alert0: trip-point0 {
5404 temperature = <90000>;
5405 hysteresis = <2000>;