arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sdm845.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,apr.h>
  23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         aliases {
  34                 i2c0 = &i2c0;
  35                 i2c1 = &i2c1;
  36                 i2c2 = &i2c2;
  37                 i2c3 = &i2c3;
  38                 i2c4 = &i2c4;
  39                 i2c5 = &i2c5;
  40                 i2c6 = &i2c6;
  41                 i2c7 = &i2c7;
  42                 i2c8 = &i2c8;
  43                 i2c9 = &i2c9;
  44                 i2c10 = &i2c10;
  45                 i2c11 = &i2c11;
  46                 i2c12 = &i2c12;
  47                 i2c13 = &i2c13;
  48                 i2c14 = &i2c14;
  49                 i2c15 = &i2c15;
  50                 spi0 = &spi0;
  51                 spi1 = &spi1;
  52                 spi2 = &spi2;
  53                 spi3 = &spi3;
  54                 spi4 = &spi4;
  55                 spi5 = &spi5;
  56                 spi6 = &spi6;
  57                 spi7 = &spi7;
  58                 spi8 = &spi8;
  59                 spi9 = &spi9;
  60                 spi10 = &spi10;
  61                 spi11 = &spi11;
  62                 spi12 = &spi12;
  63                 spi13 = &spi13;
  64                 spi14 = &spi14;
  65                 spi15 = &spi15;
  66         };
  67
  68         chosen { };
  69
  70         memory@80000000 {
  71                 device_type = "memory";
  72                 /* We expect the bootloader to fill in the size */
  73                 reg = <0 0x80000000 0 0>;
  74         };
  75
  76         reserved-memory {
  77                 #address-cells = <2>;
  78                 #size-cells = <2>;
  79                 ranges;
  80
  81                 hyp_mem: memory@85700000 {
  82                         reg = <0 0x85700000 0 0x600000>;
  83                         no-map;
  84                 };
  85
  86                 xbl_mem: memory@85e00000 {
  87                         reg = <0 0x85e00000 0 0x100000>;
  88                         no-map;
  89                 };
  90
  91                 aop_mem: memory@85fc0000 {
  92                         reg = <0 0x85fc0000 0 0x20000>;
  93                         no-map;
  94                 };
  95
  96                 aop_cmd_db_mem: memory@85fe0000 {
  97                         compatible = "qcom,cmd-db";
  98                         reg = <0x0 0x85fe0000 0 0x20000>;
  99                         no-map;
 100                 };
 101
 102                 smem_mem: memory@86000000 {
 103                         reg = <0x0 0x86000000 0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 tz_mem: memory@86200000 {
 108                         reg = <0 0x86200000 0 0x2d00000>;
 109                         no-map;
 110                 };
 111
 112                 rmtfs_mem: memory@88f00000 {
 113                         compatible = "qcom,rmtfs-mem";
 114                         reg = <0 0x88f00000 0 0x200000>;
 115                         no-map;
 116
 117                         qcom,client-id = <1>;
 118                         qcom,vmid = <15>;
 119                 };
 120
 121                 qseecom_mem: memory@8ab00000 {
 122                         reg = <0 0x8ab00000 0 0x1400000>;
 123                         no-map;
 124                 };
 125
 126                 camera_mem: memory@8bf00000 {
 127                         reg = <0 0x8bf00000 0 0x500000>;
 128                         no-map;
 129                 };
 130
 131                 ipa_fw_mem: memory@8c400000 {
 132                         reg = <0 0x8c400000 0 0x10000>;
 133                         no-map;
 134                 };
 135
 136                 ipa_gsi_mem: memory@8c410000 {
 137                         reg = <0 0x8c410000 0 0x5000>;
 138                         no-map;
 139                 };
 140
 141                 gpu_mem: memory@8c415000 {
 142                         reg = <0 0x8c415000 0 0x2000>;
 143                         no-map;
 144                 };
 145
 146                 adsp_mem: memory@8c500000 {
 147                         reg = <0 0x8c500000 0 0x1a00000>;
 148                         no-map;
 149                 };
 150
 151                 wlan_msa_mem: memory@8df00000 {
 152                         reg = <0 0x8df00000 0 0x100000>;
 153                         no-map;
 154                 };
 155
 156                 mpss_region: memory@8e000000 {
 157                         reg = <0 0x8e000000 0 0x7800000>;
 158                         no-map;
 159                 };
 160
 161                 venus_mem: memory@95800000 {
 162                         reg = <0 0x95800000 0 0x500000>;
 163                         no-map;
 164                 };
 165
 166                 cdsp_mem: memory@95d00000 {
 167                         reg = <0 0x95d00000 0 0x800000>;
 168                         no-map;
 169                 };
 170
 171                 mba_region: memory@96500000 {
 172                         reg = <0 0x96500000 0 0x200000>;
 173                         no-map;
 174                 };
 175
 176                 slpi_mem: memory@96700000 {
 177                         reg = <0 0x96700000 0 0x1400000>;
 178                         no-map;
 179                 };
 180
 181                 spss_mem: memory@97b00000 {
 182                         reg = <0 0x97b00000 0 0x100000>;
 183                         no-map;
 184                 };
 185         };
 186
 187         cpus {
 188                 #address-cells = <2>;
 189                 #size-cells = <0>;
 190
 191                 CPU0: cpu@0 {
 192                         device_type = "cpu";
 193                         compatible = "qcom,kryo385";
 194                         reg = <0x0 0x0>;
 195                         enable-method = "psci";
 196                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 197                                            &LITTLE_CPU_SLEEP_1
 198                                            &CLUSTER_SLEEP_0>;
 199                         capacity-dmips-mhz = <607>;
 200                         dynamic-power-coefficient = <100>;
 201                         qcom,freq-domain = <&cpufreq_hw 0>;
 202                         operating-points-v2 = <&cpu0_opp_table>;
 203                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 204                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 205                         #cooling-cells = <2>;
 206                         next-level-cache = <&L2_0>;
 207                         L2_0: l2-cache {
 208                                 compatible = "cache";
 209                                 next-level-cache = <&L3_0>;
 210                                 L3_0: l3-cache {
 211                                       compatible = "cache";
 212                                 };
 213                         };
 214                 };
 215
 216                 CPU1: cpu@100 {
 217                         device_type = "cpu";
 218                         compatible = "qcom,kryo385";
 219                         reg = <0x0 0x100>;
 220                         enable-method = "psci";
 221                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 222                                            &LITTLE_CPU_SLEEP_1
 223                                            &CLUSTER_SLEEP_0>;
 224                         capacity-dmips-mhz = <607>;
 225                         dynamic-power-coefficient = <100>;
 226                         qcom,freq-domain = <&cpufreq_hw 0>;
 227                         operating-points-v2 = <&cpu0_opp_table>;
 228                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 229                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 230                         #cooling-cells = <2>;
 231                         next-level-cache = <&L2_100>;
 232                         L2_100: l2-cache {
 233                                 compatible = "cache";
 234                                 next-level-cache = <&L3_0>;
 235                         };
 236                 };
 237
 238                 CPU2: cpu@200 {
 239                         device_type = "cpu";
 240                         compatible = "qcom,kryo385";
 241                         reg = <0x0 0x200>;
 242                         enable-method = "psci";
 243                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 244                                            &LITTLE_CPU_SLEEP_1
 245                                            &CLUSTER_SLEEP_0>;
 246                         capacity-dmips-mhz = <607>;
 247                         dynamic-power-coefficient = <100>;
 248                         qcom,freq-domain = <&cpufreq_hw 0>;
 249                         operating-points-v2 = <&cpu0_opp_table>;
 250                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 251                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 252                         #cooling-cells = <2>;
 253                         next-level-cache = <&L2_200>;
 254                         L2_200: l2-cache {
 255                                 compatible = "cache";
 256                                 next-level-cache = <&L3_0>;
 257                         };
 258                 };
 259
 260                 CPU3: cpu@300 {
 261                         device_type = "cpu";
 262                         compatible = "qcom,kryo385";
 263                         reg = <0x0 0x300>;
 264                         enable-method = "psci";
 265                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 266                                            &LITTLE_CPU_SLEEP_1
 267                                            &CLUSTER_SLEEP_0>;
 268                         capacity-dmips-mhz = <607>;
 269                         dynamic-power-coefficient = <100>;
 270                         qcom,freq-domain = <&cpufreq_hw 0>;
 271                         operating-points-v2 = <&cpu0_opp_table>;
 272                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 273                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 274                         #cooling-cells = <2>;
 275                         next-level-cache = <&L2_300>;
 276                         L2_300: l2-cache {
 277                                 compatible = "cache";
 278                                 next-level-cache = <&L3_0>;
 279                         };
 280                 };
 281
 282                 CPU4: cpu@400 {
 283                         device_type = "cpu";
 284                         compatible = "qcom,kryo385";
 285                         reg = <0x0 0x400>;
 286                         enable-method = "psci";
 287                         capacity-dmips-mhz = <1024>;
 288                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 289                                            &BIG_CPU_SLEEP_1
 290                                            &CLUSTER_SLEEP_0>;
 291                         dynamic-power-coefficient = <396>;
 292                         qcom,freq-domain = <&cpufreq_hw 1>;
 293                         operating-points-v2 = <&cpu4_opp_table>;
 294                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 295                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 296                         #cooling-cells = <2>;
 297                         next-level-cache = <&L2_400>;
 298                         L2_400: l2-cache {
 299                                 compatible = "cache";
 300                                 next-level-cache = <&L3_0>;
 301                         };
 302                 };
 303
 304                 CPU5: cpu@500 {
 305                         device_type = "cpu";
 306                         compatible = "qcom,kryo385";
 307                         reg = <0x0 0x500>;
 308                         enable-method = "psci";
 309                         capacity-dmips-mhz = <1024>;
 310                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 311                                            &BIG_CPU_SLEEP_1
 312                                            &CLUSTER_SLEEP_0>;
 313                         dynamic-power-coefficient = <396>;
 314                         qcom,freq-domain = <&cpufreq_hw 1>;
 315                         operating-points-v2 = <&cpu4_opp_table>;
 316                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 317                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 318                         #cooling-cells = <2>;
 319                         next-level-cache = <&L2_500>;
 320                         L2_500: l2-cache {
 321                                 compatible = "cache";
 322                                 next-level-cache = <&L3_0>;
 323                         };
 324                 };
 325
 326                 CPU6: cpu@600 {
 327                         device_type = "cpu";
 328                         compatible = "qcom,kryo385";
 329                         reg = <0x0 0x600>;
 330                         enable-method = "psci";
 331                         capacity-dmips-mhz = <1024>;
 332                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 333                                            &BIG_CPU_SLEEP_1
 334                                            &CLUSTER_SLEEP_0>;
 335                         dynamic-power-coefficient = <396>;
 336                         qcom,freq-domain = <&cpufreq_hw 1>;
 337                         operating-points-v2 = <&cpu4_opp_table>;
 338                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 339                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 340                         #cooling-cells = <2>;
 341                         next-level-cache = <&L2_600>;
 342                         L2_600: l2-cache {
 343                                 compatible = "cache";
 344                                 next-level-cache = <&L3_0>;
 345                         };
 346                 };
 347
 348                 CPU7: cpu@700 {
 349                         device_type = "cpu";
 350                         compatible = "qcom,kryo385";
 351                         reg = <0x0 0x700>;
 352                         enable-method = "psci";
 353                         capacity-dmips-mhz = <1024>;
 354                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 355                                            &BIG_CPU_SLEEP_1
 356                                            &CLUSTER_SLEEP_0>;
 357                         dynamic-power-coefficient = <396>;
 358                         qcom,freq-domain = <&cpufreq_hw 1>;
 359                         operating-points-v2 = <&cpu4_opp_table>;
 360                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 361                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 362                         #cooling-cells = <2>;
 363                         next-level-cache = <&L2_700>;
 364                         L2_700: l2-cache {
 365                                 compatible = "cache";
 366                                 next-level-cache = <&L3_0>;
 367                         };
 368                 };
 369
 370                 cpu-map {
 371                         cluster0 {
 372                                 core0 {
 373                                         cpu = <&CPU0>;
 374                                 };
 375
 376                                 core1 {
 377                                         cpu = <&CPU1>;
 378                                 };
 379
 380                                 core2 {
 381                                         cpu = <&CPU2>;
 382                                 };
 383
 384                                 core3 {
 385                                         cpu = <&CPU3>;
 386                                 };
 387
 388                                 core4 {
 389                                         cpu = <&CPU4>;
 390                                 };
 391
 392                                 core5 {
 393                                         cpu = <&CPU5>;
 394                                 };
 395
 396                                 core6 {
 397                                         cpu = <&CPU6>;
 398                                 };
 399
 400                                 core7 {
 401                                         cpu = <&CPU7>;
 402                                 };
 403                         };
 404                 };
 405
 406                 idle-states {
 407                         entry-method = "psci";
 408
 409                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 410                                 compatible = "arm,idle-state";
 411                                 idle-state-name = "little-power-down";
 412                                 arm,psci-suspend-param = <0x40000003>;
 413                                 entry-latency-us = <350>;
 414                                 exit-latency-us = <461>;
 415                                 min-residency-us = <1890>;
 416                                 local-timer-stop;
 417                         };
 418
 419                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 420                                 compatible = "arm,idle-state";
 421                                 idle-state-name = "little-rail-power-down";
 422                                 arm,psci-suspend-param = <0x40000004>;
 423                                 entry-latency-us = <360>;
 424                                 exit-latency-us = <531>;
 425                                 min-residency-us = <3934>;
 426                                 local-timer-stop;
 427                         };
 428
 429                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 430                                 compatible = "arm,idle-state";
 431                                 idle-state-name = "big-power-down";
 432                                 arm,psci-suspend-param = <0x40000003>;
 433                                 entry-latency-us = <264>;
 434                                 exit-latency-us = <621>;
 435                                 min-residency-us = <952>;
 436                                 local-timer-stop;
 437                         };
 438
 439                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 440                                 compatible = "arm,idle-state";
 441                                 idle-state-name = "big-rail-power-down";
 442                                 arm,psci-suspend-param = <0x40000004>;
 443                                 entry-latency-us = <702>;
 444                                 exit-latency-us = <1061>;
 445                                 min-residency-us = <4488>;
 446                                 local-timer-stop;
 447                         };
 448
 449                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 450                                 compatible = "arm,idle-state";
 451                                 idle-state-name = "cluster-power-down";
 452                                 arm,psci-suspend-param = <0x400000F4>;
 453                                 entry-latency-us = <3263>;
 454                                 exit-latency-us = <6562>;
 455                                 min-residency-us = <9987>;
 456                                 local-timer-stop;
 457                         };
 458                 };
 459         };
 460
 461         cpu0_opp_table: cpu0_opp_table {
 462                 compatible = "operating-points-v2";
 463                 opp-shared;
 464
 465                 cpu0_opp1: opp-300000000 {
 466                         opp-hz = /bits/ 64 <300000000>;
 467                         opp-peak-kBps = <800000 4800000>;
 468                 };
 469
 470                 cpu0_opp2: opp-403200000 {
 471                         opp-hz = /bits/ 64 <403200000>;
 472                         opp-peak-kBps = <800000 4800000>;
 473                 };
 474
 475                 cpu0_opp3: opp-480000000 {
 476                         opp-hz = /bits/ 64 <480000000>;
 477                         opp-peak-kBps = <800000 6451200>;
 478                 };
 479
 480                 cpu0_opp4: opp-576000000 {
 481                         opp-hz = /bits/ 64 <576000000>;
 482                         opp-peak-kBps = <800000 6451200>;
 483                 };
 484
 485                 cpu0_opp5: opp-652800000 {
 486                         opp-hz = /bits/ 64 <652800000>;
 487                         opp-peak-kBps = <800000 7680000>;
 488                 };
 489
 490                 cpu0_opp6: opp-748800000 {
 491                         opp-hz = /bits/ 64 <748800000>;
 492                         opp-peak-kBps = <1804000 9216000>;
 493                 };
 494
 495                 cpu0_opp7: opp-825600000 {
 496                         opp-hz = /bits/ 64 <825600000>;
 497                         opp-peak-kBps = <1804000 9216000>;
 498                 };
 499
 500                 cpu0_opp8: opp-902400000 {
 501                         opp-hz = /bits/ 64 <902400000>;
 502                         opp-peak-kBps = <1804000 10444800>;
 503                 };
 504
 505                 cpu0_opp9: opp-979200000 {
 506                         opp-hz = /bits/ 64 <979200000>;
 507                         opp-peak-kBps = <1804000 11980800>;
 508                 };
 509
 510                 cpu0_opp10: opp-1056000000 {
 511                         opp-hz = /bits/ 64 <1056000000>;
 512                         opp-peak-kBps = <1804000 11980800>;
 513                 };
 514
 515                 cpu0_opp11: opp-1132800000 {
 516                         opp-hz = /bits/ 64 <1132800000>;
 517                         opp-peak-kBps = <2188000 13516800>;
 518                 };
 519
 520                 cpu0_opp12: opp-1228800000 {
 521                         opp-hz = /bits/ 64 <1228800000>;
 522                         opp-peak-kBps = <2188000 15052800>;
 523                 };
 524
 525                 cpu0_opp13: opp-1324800000 {
 526                         opp-hz = /bits/ 64 <1324800000>;
 527                         opp-peak-kBps = <2188000 16588800>;
 528                 };
 529
 530                 cpu0_opp14: opp-1420800000 {
 531                         opp-hz = /bits/ 64 <1420800000>;
 532                         opp-peak-kBps = <3072000 18124800>;
 533                 };
 534
 535                 cpu0_opp15: opp-1516800000 {
 536                         opp-hz = /bits/ 64 <1516800000>;
 537                         opp-peak-kBps = <3072000 19353600>;
 538                 };
 539
 540                 cpu0_opp16: opp-1612800000 {
 541                         opp-hz = /bits/ 64 <1612800000>;
 542                         opp-peak-kBps = <4068000 19353600>;
 543                 };
 544
 545                 cpu0_opp17: opp-1689600000 {
 546                         opp-hz = /bits/ 64 <1689600000>;
 547                         opp-peak-kBps = <4068000 20889600>;
 548                 };
 549
 550                 cpu0_opp18: opp-1766400000 {
 551                         opp-hz = /bits/ 64 <1766400000>;
 552                         opp-peak-kBps = <4068000 22425600>;
 553                 };
 554         };
 555
 556         cpu4_opp_table: cpu4_opp_table {
 557                 compatible = "operating-points-v2";
 558                 opp-shared;
 559
 560                 cpu4_opp1: opp-300000000 {
 561                         opp-hz = /bits/ 64 <300000000>;
 562                         opp-peak-kBps = <800000 4800000>;
 563                 };
 564
 565                 cpu4_opp2: opp-403200000 {
 566                         opp-hz = /bits/ 64 <403200000>;
 567                         opp-peak-kBps = <800000 4800000>;
 568                 };
 569
 570                 cpu4_opp3: opp-480000000 {
 571                         opp-hz = /bits/ 64 <480000000>;
 572                         opp-peak-kBps = <1804000 4800000>;
 573                 };
 574
 575                 cpu4_opp4: opp-576000000 {
 576                         opp-hz = /bits/ 64 <576000000>;
 577                         opp-peak-kBps = <1804000 4800000>;
 578                 };
 579
 580                 cpu4_opp5: opp-652800000 {
 581                         opp-hz = /bits/ 64 <652800000>;
 582                         opp-peak-kBps = <1804000 4800000>;
 583                 };
 584
 585                 cpu4_opp6: opp-748800000 {
 586                         opp-hz = /bits/ 64 <748800000>;
 587                         opp-peak-kBps = <1804000 4800000>;
 588                 };
 589
 590                 cpu4_opp7: opp-825600000 {
 591                         opp-hz = /bits/ 64 <825600000>;
 592                         opp-peak-kBps = <2188000 9216000>;
 593                 };
 594
 595                 cpu4_opp8: opp-902400000 {
 596                         opp-hz = /bits/ 64 <902400000>;
 597                         opp-peak-kBps = <2188000 9216000>;
 598                 };
 599
 600                 cpu4_opp9: opp-979200000 {
 601                         opp-hz = /bits/ 64 <979200000>;
 602                         opp-peak-kBps = <2188000 9216000>;
 603                 };
 604
 605                 cpu4_opp10: opp-1056000000 {
 606                         opp-hz = /bits/ 64 <1056000000>;
 607                         opp-peak-kBps = <3072000 9216000>;
 608                 };
 609
 610                 cpu4_opp11: opp-1132800000 {
 611                         opp-hz = /bits/ 64 <1132800000>;
 612                         opp-peak-kBps = <3072000 11980800>;
 613                 };
 614
 615                 cpu4_opp12: opp-1209600000 {
 616                         opp-hz = /bits/ 64 <1209600000>;
 617                         opp-peak-kBps = <4068000 11980800>;
 618                 };
 619
 620                 cpu4_opp13: opp-1286400000 {
 621                         opp-hz = /bits/ 64 <1286400000>;
 622                         opp-peak-kBps = <4068000 11980800>;
 623                 };
 624
 625                 cpu4_opp14: opp-1363200000 {
 626                         opp-hz = /bits/ 64 <1363200000>;
 627                         opp-peak-kBps = <4068000 15052800>;
 628                 };
 629
 630                 cpu4_opp15: opp-1459200000 {
 631                         opp-hz = /bits/ 64 <1459200000>;
 632                         opp-peak-kBps = <4068000 15052800>;
 633                 };
 634
 635                 cpu4_opp16: opp-1536000000 {
 636                         opp-hz = /bits/ 64 <1536000000>;
 637                         opp-peak-kBps = <5412000 15052800>;
 638                 };
 639
 640                 cpu4_opp17: opp-1612800000 {
 641                         opp-hz = /bits/ 64 <1612800000>;
 642                         opp-peak-kBps = <5412000 15052800>;
 643                 };
 644
 645                 cpu4_opp18: opp-1689600000 {
 646                         opp-hz = /bits/ 64 <1689600000>;
 647                         opp-peak-kBps = <5412000 19353600>;
 648                 };
 649
 650                 cpu4_opp19: opp-1766400000 {
 651                         opp-hz = /bits/ 64 <1766400000>;
 652                         opp-peak-kBps = <6220000 19353600>;
 653                 };
 654
 655                 cpu4_opp20: opp-1843200000 {
 656                         opp-hz = /bits/ 64 <1843200000>;
 657                         opp-peak-kBps = <6220000 19353600>;
 658                 };
 659
 660                 cpu4_opp21: opp-1920000000 {
 661                         opp-hz = /bits/ 64 <1920000000>;
 662                         opp-peak-kBps = <7216000 19353600>;
 663                 };
 664
 665                 cpu4_opp22: opp-1996800000 {
 666                         opp-hz = /bits/ 64 <1996800000>;
 667                         opp-peak-kBps = <7216000 20889600>;
 668                 };
 669
 670                 cpu4_opp23: opp-2092800000 {
 671                         opp-hz = /bits/ 64 <2092800000>;
 672                         opp-peak-kBps = <7216000 20889600>;
 673                 };
 674
 675                 cpu4_opp24: opp-2169600000 {
 676                         opp-hz = /bits/ 64 <2169600000>;
 677                         opp-peak-kBps = <7216000 20889600>;
 678                 };
 679
 680                 cpu4_opp25: opp-2246400000 {
 681                         opp-hz = /bits/ 64 <2246400000>;
 682                         opp-peak-kBps = <7216000 20889600>;
 683                 };
 684
 685                 cpu4_opp26: opp-2323200000 {
 686                         opp-hz = /bits/ 64 <2323200000>;
 687                         opp-peak-kBps = <7216000 20889600>;
 688                 };
 689
 690                 cpu4_opp27: opp-2400000000 {
 691                         opp-hz = /bits/ 64 <2400000000>;
 692                         opp-peak-kBps = <7216000 22425600>;
 693                 };
 694
 695                 cpu4_opp28: opp-2476800000 {
 696                         opp-hz = /bits/ 64 <2476800000>;
 697                         opp-peak-kBps = <7216000 22425600>;
 698                 };
 699
 700                 cpu4_opp29: opp-2553600000 {
 701                         opp-hz = /bits/ 64 <2553600000>;
 702                         opp-peak-kBps = <7216000 22425600>;
 703                 };
 704
 705                 cpu4_opp30: opp-2649600000 {
 706                         opp-hz = /bits/ 64 <2649600000>;
 707                         opp-peak-kBps = <7216000 22425600>;
 708                 };
 709
 710                 cpu4_opp31: opp-2745600000 {
 711                         opp-hz = /bits/ 64 <2745600000>;
 712                         opp-peak-kBps = <7216000 25497600>;
 713                 };
 714
 715                 cpu4_opp32: opp-2803200000 {
 716                         opp-hz = /bits/ 64 <2803200000>;
 717                         opp-peak-kBps = <7216000 25497600>;
 718                 };
 719         };
 720
 721         pmu {
 722                 compatible = "arm,armv8-pmuv3";
 723                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 724         };
 725
 726         timer {
 727                 compatible = "arm,armv8-timer";
 728                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 729                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 730                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 731                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 732         };
 733
 734         clocks {
 735                 xo_board: xo-board {
 736                         compatible = "fixed-clock";
 737                         #clock-cells = <0>;
 738                         clock-frequency = <38400000>;
 739                         clock-output-names = "xo_board";
 740                 };
 741
 742                 sleep_clk: sleep-clk {
 743                         compatible = "fixed-clock";
 744                         #clock-cells = <0>;
 745                         clock-frequency = <32764>;
 746                 };
 747         };
 748
 749         firmware {
 750                 scm {
 751                         compatible = "qcom,scm-sdm845", "qcom,scm";
 752                 };
 753         };
 754
 755         adsp_pas: remoteproc-adsp {
 756                 compatible = "qcom,sdm845-adsp-pas";
 757
 758                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 759                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 760                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 761                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 762                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 763                 interrupt-names = "wdog", "fatal", "ready",
 764                                   "handover", "stop-ack";
 765
 766                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 767                 clock-names = "xo";
 768
 769                 memory-region = <&adsp_mem>;
 770
 771                 qcom,smem-states = <&adsp_smp2p_out 0>;
 772                 qcom,smem-state-names = "stop";
 773
 774                 status = "disabled";
 775
 776                 glink-edge {
 777                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 778                         label = "lpass";
 779                         qcom,remote-pid = <2>;
 780                         mboxes = <&apss_shared 8>;
 781
 782                         apr {
 783                                 compatible = "qcom,apr-v2";
 784                                 qcom,glink-channels = "apr_audio_svc";
 785                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
 786                                 #address-cells = <1>;
 787                                 #size-cells = <0>;
 788                                 qcom,intents = <512 20>;
 789
 790                                 apr-service@3 {
 791                                         reg = <APR_SVC_ADSP_CORE>;
 792                                         compatible = "qcom,q6core";
 793                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 794                                 };
 795
 796                                 q6afe: apr-service@4 {
 797                                         compatible = "qcom,q6afe";
 798                                         reg = <APR_SVC_AFE>;
 799                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 800                                         q6afedai: dais {
 801                                                 compatible = "qcom,q6afe-dais";
 802                                                 #address-cells = <1>;
 803                                                 #size-cells = <0>;
 804                                                 #sound-dai-cells = <1>;
 805                                         };
 806                                 };
 807
 808                                 q6asm: apr-service@7 {
 809                                         compatible = "qcom,q6asm";
 810                                         reg = <APR_SVC_ASM>;
 811                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 812                                         q6asmdai: dais {
 813                                                 compatible = "qcom,q6asm-dais";
 814                                                 #address-cells = <1>;
 815                                                 #size-cells = <0>;
 816                                                 #sound-dai-cells = <1>;
 817                                                 iommus = <&apps_smmu 0x1821 0x0>;
 818                                         };
 819                                 };
 820
 821                                 q6adm: apr-service@8 {
 822                                         compatible = "qcom,q6adm";
 823                                         reg = <APR_SVC_ADM>;
 824                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 825                                         q6routing: routing {
 826                                                 compatible = "qcom,q6adm-routing";
 827                                                 #sound-dai-cells = <0>;
 828                                         };
 829                                 };
 830                         };
 831
 832                         fastrpc {
 833                                 compatible = "qcom,fastrpc";
 834                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 835                                 label = "adsp";
 836                                 #address-cells = <1>;
 837                                 #size-cells = <0>;
 838
 839                                 compute-cb@3 {
 840                                         compatible = "qcom,fastrpc-compute-cb";
 841                                         reg = <3>;
 842                                         iommus = <&apps_smmu 0x1823 0x0>;
 843                                 };
 844
 845                                 compute-cb@4 {
 846                                         compatible = "qcom,fastrpc-compute-cb";
 847                                         reg = <4>;
 848                                         iommus = <&apps_smmu 0x1824 0x0>;
 849                                 };
 850                         };
 851                 };
 852         };
 853
 854         cdsp_pas: remoteproc-cdsp {
 855                 compatible = "qcom,sdm845-cdsp-pas";
 856
 857                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 858                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 859                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 860                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 861                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 862                 interrupt-names = "wdog", "fatal", "ready",
 863                                   "handover", "stop-ack";
 864
 865                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 866                 clock-names = "xo";
 867
 868                 memory-region = <&cdsp_mem>;
 869
 870                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 871                 qcom,smem-state-names = "stop";
 872
 873                 status = "disabled";
 874
 875                 glink-edge {
 876                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 877                         label = "turing";
 878                         qcom,remote-pid = <5>;
 879                         mboxes = <&apss_shared 4>;
 880                         fastrpc {
 881                                 compatible = "qcom,fastrpc";
 882                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 883                                 label = "cdsp";
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886
 887                                 compute-cb@1 {
 888                                         compatible = "qcom,fastrpc-compute-cb";
 889                                         reg = <1>;
 890                                         iommus = <&apps_smmu 0x1401 0x30>;
 891                                 };
 892
 893                                 compute-cb@2 {
 894                                         compatible = "qcom,fastrpc-compute-cb";
 895                                         reg = <2>;
 896                                         iommus = <&apps_smmu 0x1402 0x30>;
 897                                 };
 898
 899                                 compute-cb@3 {
 900                                         compatible = "qcom,fastrpc-compute-cb";
 901                                         reg = <3>;
 902                                         iommus = <&apps_smmu 0x1403 0x30>;
 903                                 };
 904
 905                                 compute-cb@4 {
 906                                         compatible = "qcom,fastrpc-compute-cb";
 907                                         reg = <4>;
 908                                         iommus = <&apps_smmu 0x1404 0x30>;
 909                                 };
 910
 911                                 compute-cb@5 {
 912                                         compatible = "qcom,fastrpc-compute-cb";
 913                                         reg = <5>;
 914                                         iommus = <&apps_smmu 0x1405 0x30>;
 915                                 };
 916
 917                                 compute-cb@6 {
 918                                         compatible = "qcom,fastrpc-compute-cb";
 919                                         reg = <6>;
 920                                         iommus = <&apps_smmu 0x1406 0x30>;
 921                                 };
 922
 923                                 compute-cb@7 {
 924                                         compatible = "qcom,fastrpc-compute-cb";
 925                                         reg = <7>;
 926                                         iommus = <&apps_smmu 0x1407 0x30>;
 927                                 };
 928
 929                                 compute-cb@8 {
 930                                         compatible = "qcom,fastrpc-compute-cb";
 931                                         reg = <8>;
 932                                         iommus = <&apps_smmu 0x1408 0x30>;
 933                                 };
 934                         };
 935                 };
 936         };
 937
 938         tcsr_mutex: hwlock {
 939                 compatible = "qcom,tcsr-mutex";
 940                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 941                 #hwlock-cells = <1>;
 942         };
 943
 944         smem {
 945                 compatible = "qcom,smem";
 946                 memory-region = <&smem_mem>;
 947                 hwlocks = <&tcsr_mutex 3>;
 948         };
 949
 950         smp2p-cdsp {
 951                 compatible = "qcom,smp2p";
 952                 qcom,smem = <94>, <432>;
 953
 954                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 955
 956                 mboxes = <&apss_shared 6>;
 957
 958                 qcom,local-pid = <0>;
 959                 qcom,remote-pid = <5>;
 960
 961                 cdsp_smp2p_out: master-kernel {
 962                         qcom,entry-name = "master-kernel";
 963                         #qcom,smem-state-cells = <1>;
 964                 };
 965
 966                 cdsp_smp2p_in: slave-kernel {
 967                         qcom,entry-name = "slave-kernel";
 968
 969                         interrupt-controller;
 970                         #interrupt-cells = <2>;
 971                 };
 972         };
 973
 974         smp2p-lpass {
 975                 compatible = "qcom,smp2p";
 976                 qcom,smem = <443>, <429>;
 977
 978                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 979
 980                 mboxes = <&apss_shared 10>;
 981
 982                 qcom,local-pid = <0>;
 983                 qcom,remote-pid = <2>;
 984
 985                 adsp_smp2p_out: master-kernel {
 986                         qcom,entry-name = "master-kernel";
 987                         #qcom,smem-state-cells = <1>;
 988                 };
 989
 990                 adsp_smp2p_in: slave-kernel {
 991                         qcom,entry-name = "slave-kernel";
 992
 993                         interrupt-controller;
 994                         #interrupt-cells = <2>;
 995                 };
 996         };
 997
 998         smp2p-mpss {
 999                 compatible = "qcom,smp2p";
1000                 qcom,smem = <435>, <428>;
1001                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1002                 mboxes = <&apss_shared 14>;
1003                 qcom,local-pid = <0>;
1004                 qcom,remote-pid = <1>;
1005
1006                 modem_smp2p_out: master-kernel {
1007                         qcom,entry-name = "master-kernel";
1008                         #qcom,smem-state-cells = <1>;
1009                 };
1010
1011                 modem_smp2p_in: slave-kernel {
1012                         qcom,entry-name = "slave-kernel";
1013                         interrupt-controller;
1014                         #interrupt-cells = <2>;
1015                 };
1016
1017                 ipa_smp2p_out: ipa-ap-to-modem {
1018                         qcom,entry-name = "ipa";
1019                         #qcom,smem-state-cells = <1>;
1020                 };
1021
1022                 ipa_smp2p_in: ipa-modem-to-ap {
1023                         qcom,entry-name = "ipa";
1024                         interrupt-controller;
1025                         #interrupt-cells = <2>;
1026                 };
1027         };
1028
1029         smp2p-slpi {
1030                 compatible = "qcom,smp2p";
1031                 qcom,smem = <481>, <430>;
1032                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1033                 mboxes = <&apss_shared 26>;
1034                 qcom,local-pid = <0>;
1035                 qcom,remote-pid = <3>;
1036
1037                 slpi_smp2p_out: master-kernel {
1038                         qcom,entry-name = "master-kernel";
1039                         #qcom,smem-state-cells = <1>;
1040                 };
1041
1042                 slpi_smp2p_in: slave-kernel {
1043                         qcom,entry-name = "slave-kernel";
1044                         interrupt-controller;
1045                         #interrupt-cells = <2>;
1046                 };
1047         };
1048
1049         psci {
1050                 compatible = "arm,psci-1.0";
1051                 method = "smc";
1052         };
1053
1054         soc: soc@0 {
1055                 #address-cells = <2>;
1056                 #size-cells = <2>;
1057                 ranges = <0 0 0 0 0x10 0>;
1058                 dma-ranges = <0 0 0 0 0x10 0>;
1059                 compatible = "simple-bus";
1060
1061                 gcc: clock-controller@100000 {
1062                         compatible = "qcom,gcc-sdm845";
1063                         reg = <0 0x00100000 0 0x1f0000>;
1064                         #clock-cells = <1>;
1065                         #reset-cells = <1>;
1066                         #power-domain-cells = <1>;
1067                 };
1068
1069                 qfprom@784000 {
1070                         compatible = "qcom,qfprom";
1071                         reg = <0 0x00784000 0 0x8ff>;
1072                         #address-cells = <1>;
1073                         #size-cells = <1>;
1074
1075                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1076                                 reg = <0x1eb 0x1>;
1077                                 bits = <1 4>;
1078                         };
1079
1080                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1081                                 reg = <0x1eb 0x2>;
1082                                 bits = <6 4>;
1083                         };
1084                 };
1085
1086                 rng: rng@793000 {
1087                         compatible = "qcom,prng-ee";
1088                         reg = <0 0x00793000 0 0x1000>;
1089                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1090                         clock-names = "core";
1091                 };
1092
1093                 qup_opp_table: qup-opp-table {
1094                         compatible = "operating-points-v2";
1095
1096                         opp-50000000 {
1097                                 opp-hz = /bits/ 64 <50000000>;
1098                                 required-opps = <&rpmhpd_opp_min_svs>;
1099                         };
1100
1101                         opp-75000000 {
1102                                 opp-hz = /bits/ 64 <75000000>;
1103                                 required-opps = <&rpmhpd_opp_low_svs>;
1104                         };
1105
1106                         opp-100000000 {
1107                                 opp-hz = /bits/ 64 <100000000>;
1108                                 required-opps = <&rpmhpd_opp_svs>;
1109                         };
1110
1111                         opp-128000000 {
1112                                 opp-hz = /bits/ 64 <128000000>;
1113                                 required-opps = <&rpmhpd_opp_nom>;
1114                         };
1115                 };
1116
1117                 qupv3_id_0: geniqup@8c0000 {
1118                         compatible = "qcom,geni-se-qup";
1119                         reg = <0 0x008c0000 0 0x6000>;
1120                         clock-names = "m-ahb", "s-ahb";
1121                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1122                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1123                         iommus = <&apps_smmu 0x3 0x0>;
1124                         #address-cells = <2>;
1125                         #size-cells = <2>;
1126                         ranges;
1127                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1128                         interconnect-names = "qup-core";
1129                         status = "disabled";
1130
1131                         i2c0: i2c@880000 {
1132                                 compatible = "qcom,geni-i2c";
1133                                 reg = <0 0x00880000 0 0x4000>;
1134                                 clock-names = "se";
1135                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1136                                 pinctrl-names = "default";
1137                                 pinctrl-0 = <&qup_i2c0_default>;
1138                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 power-domains = <&rpmhpd SDM845_CX>;
1142                                 operating-points-v2 = <&qup_opp_table>;
1143                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1144                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1145                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1146                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1147                                 status = "disabled";
1148                         };
1149
1150                         spi0: spi@880000 {
1151                                 compatible = "qcom,geni-spi";
1152                                 reg = <0 0x00880000 0 0x4000>;
1153                                 clock-names = "se";
1154                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1155                                 pinctrl-names = "default";
1156                                 pinctrl-0 = <&qup_spi0_default>;
1157                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1158                                 #address-cells = <1>;
1159                                 #size-cells = <0>;
1160                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1161                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1162                                 interconnect-names = "qup-core", "qup-config";
1163                                 status = "disabled";
1164                         };
1165
1166                         uart0: serial@880000 {
1167                                 compatible = "qcom,geni-uart";
1168                                 reg = <0 0x00880000 0 0x4000>;
1169                                 clock-names = "se";
1170                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1171                                 pinctrl-names = "default";
1172                                 pinctrl-0 = <&qup_uart0_default>;
1173                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1174                                 power-domains = <&rpmhpd SDM845_CX>;
1175                                 operating-points-v2 = <&qup_opp_table>;
1176                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1177                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1178                                 interconnect-names = "qup-core", "qup-config";
1179                                 status = "disabled";
1180                         };
1181
1182                         i2c1: i2c@884000 {
1183                                 compatible = "qcom,geni-i2c";
1184                                 reg = <0 0x00884000 0 0x4000>;
1185                                 clock-names = "se";
1186                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1187                                 pinctrl-names = "default";
1188                                 pinctrl-0 = <&qup_i2c1_default>;
1189                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1190                                 #address-cells = <1>;
1191                                 #size-cells = <0>;
1192                                 power-domains = <&rpmhpd SDM845_CX>;
1193                                 operating-points-v2 = <&qup_opp_table>;
1194                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1195                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1196                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1197                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198                                 status = "disabled";
1199                         };
1200
1201                         spi1: spi@884000 {
1202                                 compatible = "qcom,geni-spi";
1203                                 reg = <0 0x00884000 0 0x4000>;
1204                                 clock-names = "se";
1205                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1206                                 pinctrl-names = "default";
1207                                 pinctrl-0 = <&qup_spi1_default>;
1208                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1209                                 #address-cells = <1>;
1210                                 #size-cells = <0>;
1211                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1212                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1213                                 interconnect-names = "qup-core", "qup-config";
1214                                 status = "disabled";
1215                         };
1216
1217                         uart1: serial@884000 {
1218                                 compatible = "qcom,geni-uart";
1219                                 reg = <0 0x00884000 0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1222                                 pinctrl-names = "default";
1223                                 pinctrl-0 = <&qup_uart1_default>;
1224                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225                                 power-domains = <&rpmhpd SDM845_CX>;
1226                                 operating-points-v2 = <&qup_opp_table>;
1227                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1228                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1229                                 interconnect-names = "qup-core", "qup-config";
1230                                 status = "disabled";
1231                         };
1232
1233                         i2c2: i2c@888000 {
1234                                 compatible = "qcom,geni-i2c";
1235                                 reg = <0 0x00888000 0 0x4000>;
1236                                 clock-names = "se";
1237                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1238                                 pinctrl-names = "default";
1239                                 pinctrl-0 = <&qup_i2c2_default>;
1240                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1241                                 #address-cells = <1>;
1242                                 #size-cells = <0>;
1243                                 power-domains = <&rpmhpd SDM845_CX>;
1244                                 operating-points-v2 = <&qup_opp_table>;
1245                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1246                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1247                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1248                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249                                 status = "disabled";
1250                         };
1251
1252                         spi2: spi@888000 {
1253                                 compatible = "qcom,geni-spi";
1254                                 reg = <0 0x00888000 0 0x4000>;
1255                                 clock-names = "se";
1256                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1257                                 pinctrl-names = "default";
1258                                 pinctrl-0 = <&qup_spi2_default>;
1259                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1260                                 #address-cells = <1>;
1261                                 #size-cells = <0>;
1262                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1263                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1264                                 interconnect-names = "qup-core", "qup-config";
1265                                 status = "disabled";
1266                         };
1267
1268                         uart2: serial@888000 {
1269                                 compatible = "qcom,geni-uart";
1270                                 reg = <0 0x00888000 0 0x4000>;
1271                                 clock-names = "se";
1272                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1273                                 pinctrl-names = "default";
1274                                 pinctrl-0 = <&qup_uart2_default>;
1275                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1276                                 power-domains = <&rpmhpd SDM845_CX>;
1277                                 operating-points-v2 = <&qup_opp_table>;
1278                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1279                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1280                                 interconnect-names = "qup-core", "qup-config";
1281                                 status = "disabled";
1282                         };
1283
1284                         i2c3: i2c@88c000 {
1285                                 compatible = "qcom,geni-i2c";
1286                                 reg = <0 0x0088c000 0 0x4000>;
1287                                 clock-names = "se";
1288                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1289                                 pinctrl-names = "default";
1290                                 pinctrl-0 = <&qup_i2c3_default>;
1291                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1292                                 #address-cells = <1>;
1293                                 #size-cells = <0>;
1294                                 power-domains = <&rpmhpd SDM845_CX>;
1295                                 operating-points-v2 = <&qup_opp_table>;
1296                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1297                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1298                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1299                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1300                                 status = "disabled";
1301                         };
1302
1303                         spi3: spi@88c000 {
1304                                 compatible = "qcom,geni-spi";
1305                                 reg = <0 0x0088c000 0 0x4000>;
1306                                 clock-names = "se";
1307                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1308                                 pinctrl-names = "default";
1309                                 pinctrl-0 = <&qup_spi3_default>;
1310                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1311                                 #address-cells = <1>;
1312                                 #size-cells = <0>;
1313                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1314                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1315                                 interconnect-names = "qup-core", "qup-config";
1316                                 status = "disabled";
1317                         };
1318
1319                         uart3: serial@88c000 {
1320                                 compatible = "qcom,geni-uart";
1321                                 reg = <0 0x0088c000 0 0x4000>;
1322                                 clock-names = "se";
1323                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1324                                 pinctrl-names = "default";
1325                                 pinctrl-0 = <&qup_uart3_default>;
1326                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1327                                 power-domains = <&rpmhpd SDM845_CX>;
1328                                 operating-points-v2 = <&qup_opp_table>;
1329                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1330                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1331                                 interconnect-names = "qup-core", "qup-config";
1332                                 status = "disabled";
1333                         };
1334
1335                         i2c4: i2c@890000 {
1336                                 compatible = "qcom,geni-i2c";
1337                                 reg = <0 0x00890000 0 0x4000>;
1338                                 clock-names = "se";
1339                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1340                                 pinctrl-names = "default";
1341                                 pinctrl-0 = <&qup_i2c4_default>;
1342                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1343                                 #address-cells = <1>;
1344                                 #size-cells = <0>;
1345                                 power-domains = <&rpmhpd SDM845_CX>;
1346                                 operating-points-v2 = <&qup_opp_table>;
1347                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1348                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1349                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1350                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1351                                 status = "disabled";
1352                         };
1353
1354                         spi4: spi@890000 {
1355                                 compatible = "qcom,geni-spi";
1356                                 reg = <0 0x00890000 0 0x4000>;
1357                                 clock-names = "se";
1358                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1359                                 pinctrl-names = "default";
1360                                 pinctrl-0 = <&qup_spi4_default>;
1361                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1362                                 #address-cells = <1>;
1363                                 #size-cells = <0>;
1364                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1365                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1366                                 interconnect-names = "qup-core", "qup-config";
1367                                 status = "disabled";
1368                         };
1369
1370                         uart4: serial@890000 {
1371                                 compatible = "qcom,geni-uart";
1372                                 reg = <0 0x00890000 0 0x4000>;
1373                                 clock-names = "se";
1374                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1375                                 pinctrl-names = "default";
1376                                 pinctrl-0 = <&qup_uart4_default>;
1377                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1378                                 power-domains = <&rpmhpd SDM845_CX>;
1379                                 operating-points-v2 = <&qup_opp_table>;
1380                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1381                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1382                                 interconnect-names = "qup-core", "qup-config";
1383                                 status = "disabled";
1384                         };
1385
1386                         i2c5: i2c@894000 {
1387                                 compatible = "qcom,geni-i2c";
1388                                 reg = <0 0x00894000 0 0x4000>;
1389                                 clock-names = "se";
1390                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1391                                 pinctrl-names = "default";
1392                                 pinctrl-0 = <&qup_i2c5_default>;
1393                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1394                                 #address-cells = <1>;
1395                                 #size-cells = <0>;
1396                                 power-domains = <&rpmhpd SDM845_CX>;
1397                                 operating-points-v2 = <&qup_opp_table>;
1398                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1399                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1400                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1401                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1402                                 status = "disabled";
1403                         };
1404
1405                         spi5: spi@894000 {
1406                                 compatible = "qcom,geni-spi";
1407                                 reg = <0 0x00894000 0 0x4000>;
1408                                 clock-names = "se";
1409                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1410                                 pinctrl-names = "default";
1411                                 pinctrl-0 = <&qup_spi5_default>;
1412                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1413                                 #address-cells = <1>;
1414                                 #size-cells = <0>;
1415                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1416                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1417                                 interconnect-names = "qup-core", "qup-config";
1418                                 status = "disabled";
1419                         };
1420
1421                         uart5: serial@894000 {
1422                                 compatible = "qcom,geni-uart";
1423                                 reg = <0 0x00894000 0 0x4000>;
1424                                 clock-names = "se";
1425                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1426                                 pinctrl-names = "default";
1427                                 pinctrl-0 = <&qup_uart5_default>;
1428                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1429                                 power-domains = <&rpmhpd SDM845_CX>;
1430                                 operating-points-v2 = <&qup_opp_table>;
1431                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1432                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1433                                 interconnect-names = "qup-core", "qup-config";
1434                                 status = "disabled";
1435                         };
1436
1437                         i2c6: i2c@898000 {
1438                                 compatible = "qcom,geni-i2c";
1439                                 reg = <0 0x00898000 0 0x4000>;
1440                                 clock-names = "se";
1441                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1442                                 pinctrl-names = "default";
1443                                 pinctrl-0 = <&qup_i2c6_default>;
1444                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1445                                 #address-cells = <1>;
1446                                 #size-cells = <0>;
1447                                 power-domains = <&rpmhpd SDM845_CX>;
1448                                 operating-points-v2 = <&qup_opp_table>;
1449                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1450                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1451                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1452                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1453                                 status = "disabled";
1454                         };
1455
1456                         spi6: spi@898000 {
1457                                 compatible = "qcom,geni-spi";
1458                                 reg = <0 0x00898000 0 0x4000>;
1459                                 clock-names = "se";
1460                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1461                                 pinctrl-names = "default";
1462                                 pinctrl-0 = <&qup_spi6_default>;
1463                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1464                                 #address-cells = <1>;
1465                                 #size-cells = <0>;
1466                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1467                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1468                                 interconnect-names = "qup-core", "qup-config";
1469                                 status = "disabled";
1470                         };
1471
1472                         uart6: serial@898000 {
1473                                 compatible = "qcom,geni-uart";
1474                                 reg = <0 0x00898000 0 0x4000>;
1475                                 clock-names = "se";
1476                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_uart6_default>;
1479                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1480                                 power-domains = <&rpmhpd SDM845_CX>;
1481                                 operating-points-v2 = <&qup_opp_table>;
1482                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1483                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1484                                 interconnect-names = "qup-core", "qup-config";
1485                                 status = "disabled";
1486                         };
1487
1488                         i2c7: i2c@89c000 {
1489                                 compatible = "qcom,geni-i2c";
1490                                 reg = <0 0x0089c000 0 0x4000>;
1491                                 clock-names = "se";
1492                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1493                                 pinctrl-names = "default";
1494                                 pinctrl-0 = <&qup_i2c7_default>;
1495                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1496                                 #address-cells = <1>;
1497                                 #size-cells = <0>;
1498                                 power-domains = <&rpmhpd SDM845_CX>;
1499                                 operating-points-v2 = <&qup_opp_table>;
1500                                 status = "disabled";
1501                         };
1502
1503                         spi7: spi@89c000 {
1504                                 compatible = "qcom,geni-spi";
1505                                 reg = <0 0x0089c000 0 0x4000>;
1506                                 clock-names = "se";
1507                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1508                                 pinctrl-names = "default";
1509                                 pinctrl-0 = <&qup_spi7_default>;
1510                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1511                                 #address-cells = <1>;
1512                                 #size-cells = <0>;
1513                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1514                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1515                                 interconnect-names = "qup-core", "qup-config";
1516                                 status = "disabled";
1517                         };
1518
1519                         uart7: serial@89c000 {
1520                                 compatible = "qcom,geni-uart";
1521                                 reg = <0 0x0089c000 0 0x4000>;
1522                                 clock-names = "se";
1523                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1524                                 pinctrl-names = "default";
1525                                 pinctrl-0 = <&qup_uart7_default>;
1526                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1527                                 power-domains = <&rpmhpd SDM845_CX>;
1528                                 operating-points-v2 = <&qup_opp_table>;
1529                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1530                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1531                                 interconnect-names = "qup-core", "qup-config";
1532                                 status = "disabled";
1533                         };
1534                 };
1535
1536                 qupv3_id_1: geniqup@ac0000 {
1537                         compatible = "qcom,geni-se-qup";
1538                         reg = <0 0x00ac0000 0 0x6000>;
1539                         clock-names = "m-ahb", "s-ahb";
1540                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1541                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1542                         iommus = <&apps_smmu 0x6c3 0x0>;
1543                         #address-cells = <2>;
1544                         #size-cells = <2>;
1545                         ranges;
1546                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1547                         interconnect-names = "qup-core";
1548                         status = "disabled";
1549
1550                         i2c8: i2c@a80000 {
1551                                 compatible = "qcom,geni-i2c";
1552                                 reg = <0 0x00a80000 0 0x4000>;
1553                                 clock-names = "se";
1554                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1555                                 pinctrl-names = "default";
1556                                 pinctrl-0 = <&qup_i2c8_default>;
1557                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1558                                 #address-cells = <1>;
1559                                 #size-cells = <0>;
1560                                 power-domains = <&rpmhpd SDM845_CX>;
1561                                 operating-points-v2 = <&qup_opp_table>;
1562                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1563                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1564                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1565                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1566                                 status = "disabled";
1567                         };
1568
1569                         spi8: spi@a80000 {
1570                                 compatible = "qcom,geni-spi";
1571                                 reg = <0 0x00a80000 0 0x4000>;
1572                                 clock-names = "se";
1573                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1574                                 pinctrl-names = "default";
1575                                 pinctrl-0 = <&qup_spi8_default>;
1576                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1577                                 #address-cells = <1>;
1578                                 #size-cells = <0>;
1579                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1580                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1581                                 interconnect-names = "qup-core", "qup-config";
1582                                 status = "disabled";
1583                         };
1584
1585                         uart8: serial@a80000 {
1586                                 compatible = "qcom,geni-uart";
1587                                 reg = <0 0x00a80000 0 0x4000>;
1588                                 clock-names = "se";
1589                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1590                                 pinctrl-names = "default";
1591                                 pinctrl-0 = <&qup_uart8_default>;
1592                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1593                                 power-domains = <&rpmhpd SDM845_CX>;
1594                                 operating-points-v2 = <&qup_opp_table>;
1595                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1596                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1597                                 interconnect-names = "qup-core", "qup-config";
1598                                 status = "disabled";
1599                         };
1600
1601                         i2c9: i2c@a84000 {
1602                                 compatible = "qcom,geni-i2c";
1603                                 reg = <0 0x00a84000 0 0x4000>;
1604                                 clock-names = "se";
1605                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1606                                 pinctrl-names = "default";
1607                                 pinctrl-0 = <&qup_i2c9_default>;
1608                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1609                                 #address-cells = <1>;
1610                                 #size-cells = <0>;
1611                                 power-domains = <&rpmhpd SDM845_CX>;
1612                                 operating-points-v2 = <&qup_opp_table>;
1613                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1614                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1615                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1616                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1617                                 status = "disabled";
1618                         };
1619
1620                         spi9: spi@a84000 {
1621                                 compatible = "qcom,geni-spi";
1622                                 reg = <0 0x00a84000 0 0x4000>;
1623                                 clock-names = "se";
1624                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1625                                 pinctrl-names = "default";
1626                                 pinctrl-0 = <&qup_spi9_default>;
1627                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1631                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1632                                 interconnect-names = "qup-core", "qup-config";
1633                                 status = "disabled";
1634                         };
1635
1636                         uart9: serial@a84000 {
1637                                 compatible = "qcom,geni-debug-uart";
1638                                 reg = <0 0x00a84000 0 0x4000>;
1639                                 clock-names = "se";
1640                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1641                                 pinctrl-names = "default";
1642                                 pinctrl-0 = <&qup_uart9_default>;
1643                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1644                                 power-domains = <&rpmhpd SDM845_CX>;
1645                                 operating-points-v2 = <&qup_opp_table>;
1646                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1647                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1648                                 interconnect-names = "qup-core", "qup-config";
1649                                 status = "disabled";
1650                         };
1651
1652                         i2c10: i2c@a88000 {
1653                                 compatible = "qcom,geni-i2c";
1654                                 reg = <0 0x00a88000 0 0x4000>;
1655                                 clock-names = "se";
1656                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1657                                 pinctrl-names = "default";
1658                                 pinctrl-0 = <&qup_i2c10_default>;
1659                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1660                                 #address-cells = <1>;
1661                                 #size-cells = <0>;
1662                                 power-domains = <&rpmhpd SDM845_CX>;
1663                                 operating-points-v2 = <&qup_opp_table>;
1664                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1665                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1666                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1667                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1668                                 status = "disabled";
1669                         };
1670
1671                         spi10: spi@a88000 {
1672                                 compatible = "qcom,geni-spi";
1673                                 reg = <0 0x00a88000 0 0x4000>;
1674                                 clock-names = "se";
1675                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1676                                 pinctrl-names = "default";
1677                                 pinctrl-0 = <&qup_spi10_default>;
1678                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1679                                 #address-cells = <1>;
1680                                 #size-cells = <0>;
1681                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1682                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1683                                 interconnect-names = "qup-core", "qup-config";
1684                                 status = "disabled";
1685                         };
1686
1687                         uart10: serial@a88000 {
1688                                 compatible = "qcom,geni-uart";
1689                                 reg = <0 0x00a88000 0 0x4000>;
1690                                 clock-names = "se";
1691                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1692                                 pinctrl-names = "default";
1693                                 pinctrl-0 = <&qup_uart10_default>;
1694                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1695                                 power-domains = <&rpmhpd SDM845_CX>;
1696                                 operating-points-v2 = <&qup_opp_table>;
1697                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1698                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1699                                 interconnect-names = "qup-core", "qup-config";
1700                                 status = "disabled";
1701                         };
1702
1703                         i2c11: i2c@a8c000 {
1704                                 compatible = "qcom,geni-i2c";
1705                                 reg = <0 0x00a8c000 0 0x4000>;
1706                                 clock-names = "se";
1707                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1708                                 pinctrl-names = "default";
1709                                 pinctrl-0 = <&qup_i2c11_default>;
1710                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1711                                 #address-cells = <1>;
1712                                 #size-cells = <0>;
1713                                 power-domains = <&rpmhpd SDM845_CX>;
1714                                 operating-points-v2 = <&qup_opp_table>;
1715                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1716                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1717                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1718                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1719                                 status = "disabled";
1720                         };
1721
1722                         spi11: spi@a8c000 {
1723                                 compatible = "qcom,geni-spi";
1724                                 reg = <0 0x00a8c000 0 0x4000>;
1725                                 clock-names = "se";
1726                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1727                                 pinctrl-names = "default";
1728                                 pinctrl-0 = <&qup_spi11_default>;
1729                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1730                                 #address-cells = <1>;
1731                                 #size-cells = <0>;
1732                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1733                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1734                                 interconnect-names = "qup-core", "qup-config";
1735                                 status = "disabled";
1736                         };
1737
1738                         uart11: serial@a8c000 {
1739                                 compatible = "qcom,geni-uart";
1740                                 reg = <0 0x00a8c000 0 0x4000>;
1741                                 clock-names = "se";
1742                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1743                                 pinctrl-names = "default";
1744                                 pinctrl-0 = <&qup_uart11_default>;
1745                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1746                                 power-domains = <&rpmhpd SDM845_CX>;
1747                                 operating-points-v2 = <&qup_opp_table>;
1748                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1749                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1750                                 interconnect-names = "qup-core", "qup-config";
1751                                 status = "disabled";
1752                         };
1753
1754                         i2c12: i2c@a90000 {
1755                                 compatible = "qcom,geni-i2c";
1756                                 reg = <0 0x00a90000 0 0x4000>;
1757                                 clock-names = "se";
1758                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1759                                 pinctrl-names = "default";
1760                                 pinctrl-0 = <&qup_i2c12_default>;
1761                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1762                                 #address-cells = <1>;
1763                                 #size-cells = <0>;
1764                                 power-domains = <&rpmhpd SDM845_CX>;
1765                                 operating-points-v2 = <&qup_opp_table>;
1766                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1767                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1768                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1769                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1770                                 status = "disabled";
1771                         };
1772
1773                         spi12: spi@a90000 {
1774                                 compatible = "qcom,geni-spi";
1775                                 reg = <0 0x00a90000 0 0x4000>;
1776                                 clock-names = "se";
1777                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1778                                 pinctrl-names = "default";
1779                                 pinctrl-0 = <&qup_spi12_default>;
1780                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1781                                 #address-cells = <1>;
1782                                 #size-cells = <0>;
1783                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1784                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1785                                 interconnect-names = "qup-core", "qup-config";
1786                                 status = "disabled";
1787                         };
1788
1789                         uart12: serial@a90000 {
1790                                 compatible = "qcom,geni-uart";
1791                                 reg = <0 0x00a90000 0 0x4000>;
1792                                 clock-names = "se";
1793                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1794                                 pinctrl-names = "default";
1795                                 pinctrl-0 = <&qup_uart12_default>;
1796                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1797                                 power-domains = <&rpmhpd SDM845_CX>;
1798                                 operating-points-v2 = <&qup_opp_table>;
1799                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1800                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1801                                 interconnect-names = "qup-core", "qup-config";
1802                                 status = "disabled";
1803                         };
1804
1805                         i2c13: i2c@a94000 {
1806                                 compatible = "qcom,geni-i2c";
1807                                 reg = <0 0x00a94000 0 0x4000>;
1808                                 clock-names = "se";
1809                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1810                                 pinctrl-names = "default";
1811                                 pinctrl-0 = <&qup_i2c13_default>;
1812                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1813                                 #address-cells = <1>;
1814                                 #size-cells = <0>;
1815                                 power-domains = <&rpmhpd SDM845_CX>;
1816                                 operating-points-v2 = <&qup_opp_table>;
1817                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1818                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1819                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1820                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1821                                 status = "disabled";
1822                         };
1823
1824                         spi13: spi@a94000 {
1825                                 compatible = "qcom,geni-spi";
1826                                 reg = <0 0x00a94000 0 0x4000>;
1827                                 clock-names = "se";
1828                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1829                                 pinctrl-names = "default";
1830                                 pinctrl-0 = <&qup_spi13_default>;
1831                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1832                                 #address-cells = <1>;
1833                                 #size-cells = <0>;
1834                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1835                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1836                                 interconnect-names = "qup-core", "qup-config";
1837                                 status = "disabled";
1838                         };
1839
1840                         uart13: serial@a94000 {
1841                                 compatible = "qcom,geni-uart";
1842                                 reg = <0 0x00a94000 0 0x4000>;
1843                                 clock-names = "se";
1844                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1845                                 pinctrl-names = "default";
1846                                 pinctrl-0 = <&qup_uart13_default>;
1847                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1848                                 power-domains = <&rpmhpd SDM845_CX>;
1849                                 operating-points-v2 = <&qup_opp_table>;
1850                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1851                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1852                                 interconnect-names = "qup-core", "qup-config";
1853                                 status = "disabled";
1854                         };
1855
1856                         i2c14: i2c@a98000 {
1857                                 compatible = "qcom,geni-i2c";
1858                                 reg = <0 0x00a98000 0 0x4000>;
1859                                 clock-names = "se";
1860                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1861                                 pinctrl-names = "default";
1862                                 pinctrl-0 = <&qup_i2c14_default>;
1863                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1864                                 #address-cells = <1>;
1865                                 #size-cells = <0>;
1866                                 power-domains = <&rpmhpd SDM845_CX>;
1867                                 operating-points-v2 = <&qup_opp_table>;
1868                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1869                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1870                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1871                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1872                                 status = "disabled";
1873                         };
1874
1875                         spi14: spi@a98000 {
1876                                 compatible = "qcom,geni-spi";
1877                                 reg = <0 0x00a98000 0 0x4000>;
1878                                 clock-names = "se";
1879                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1880                                 pinctrl-names = "default";
1881                                 pinctrl-0 = <&qup_spi14_default>;
1882                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1883                                 #address-cells = <1>;
1884                                 #size-cells = <0>;
1885                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1886                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1887                                 interconnect-names = "qup-core", "qup-config";
1888                                 status = "disabled";
1889                         };
1890
1891                         uart14: serial@a98000 {
1892                                 compatible = "qcom,geni-uart";
1893                                 reg = <0 0x00a98000 0 0x4000>;
1894                                 clock-names = "se";
1895                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1896                                 pinctrl-names = "default";
1897                                 pinctrl-0 = <&qup_uart14_default>;
1898                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1899                                 power-domains = <&rpmhpd SDM845_CX>;
1900                                 operating-points-v2 = <&qup_opp_table>;
1901                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1902                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1903                                 interconnect-names = "qup-core", "qup-config";
1904                                 status = "disabled";
1905                         };
1906
1907                         i2c15: i2c@a9c000 {
1908                                 compatible = "qcom,geni-i2c";
1909                                 reg = <0 0x00a9c000 0 0x4000>;
1910                                 clock-names = "se";
1911                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912                                 pinctrl-names = "default";
1913                                 pinctrl-0 = <&qup_i2c15_default>;
1914                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1915                                 #address-cells = <1>;
1916                                 #size-cells = <0>;
1917                                 power-domains = <&rpmhpd SDM845_CX>;
1918                                 operating-points-v2 = <&qup_opp_table>;
1919                                 status = "disabled";
1920                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1921                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1922                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1923                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1924                         };
1925
1926                         spi15: spi@a9c000 {
1927                                 compatible = "qcom,geni-spi";
1928                                 reg = <0 0x00a9c000 0 0x4000>;
1929                                 clock-names = "se";
1930                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1931                                 pinctrl-names = "default";
1932                                 pinctrl-0 = <&qup_spi15_default>;
1933                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1934                                 #address-cells = <1>;
1935                                 #size-cells = <0>;
1936                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1937                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1938                                 interconnect-names = "qup-core", "qup-config";
1939                                 status = "disabled";
1940                         };
1941
1942                         uart15: serial@a9c000 {
1943                                 compatible = "qcom,geni-uart";
1944                                 reg = <0 0x00a9c000 0 0x4000>;
1945                                 clock-names = "se";
1946                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1947                                 pinctrl-names = "default";
1948                                 pinctrl-0 = <&qup_uart15_default>;
1949                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1950                                 power-domains = <&rpmhpd SDM845_CX>;
1951                                 operating-points-v2 = <&qup_opp_table>;
1952                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1953                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1954                                 interconnect-names = "qup-core", "qup-config";
1955                                 status = "disabled";
1956                         };
1957                 };
1958
1959                 system-cache-controller@1100000 {
1960                         compatible = "qcom,sdm845-llcc";
1961                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1962                         reg-names = "llcc_base", "llcc_broadcast_base";
1963                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1964                 };
1965
1966                 pcie0: pci@1c00000 {
1967                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1968                         reg = <0 0x01c00000 0 0x2000>,
1969                               <0 0x60000000 0 0xf1d>,
1970                               <0 0x60000f20 0 0xa8>,
1971                               <0 0x60100000 0 0x100000>;
1972                         reg-names = "parf", "dbi", "elbi", "config";
1973                         device_type = "pci";
1974                         linux,pci-domain = <0>;
1975                         bus-range = <0x00 0xff>;
1976                         num-lanes = <1>;
1977
1978                         #address-cells = <3>;
1979                         #size-cells = <2>;
1980
1981                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1982                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1983
1984                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1985                         interrupt-names = "msi";
1986                         #interrupt-cells = <1>;
1987                         interrupt-map-mask = <0 0 0 0x7>;
1988                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1989                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1990                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1991                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1992
1993                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1994                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1995                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1996                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1997                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1998                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1999                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2000                         clock-names = "pipe",
2001                                       "aux",
2002                                       "cfg",
2003                                       "bus_master",
2004                                       "bus_slave",
2005                                       "slave_q2a",
2006                                       "tbu";
2007
2008                         iommus = <&apps_smmu 0x1c10 0xf>;
2009                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
2010                                     <0x100 &apps_smmu 0x1c11 0x1>,
2011                                     <0x200 &apps_smmu 0x1c12 0x1>,
2012                                     <0x300 &apps_smmu 0x1c13 0x1>,
2013                                     <0x400 &apps_smmu 0x1c14 0x1>,
2014                                     <0x500 &apps_smmu 0x1c15 0x1>,
2015                                     <0x600 &apps_smmu 0x1c16 0x1>,
2016                                     <0x700 &apps_smmu 0x1c17 0x1>,
2017                                     <0x800 &apps_smmu 0x1c18 0x1>,
2018                                     <0x900 &apps_smmu 0x1c19 0x1>,
2019                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
2020                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
2021                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
2022                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
2023                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
2024                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
2025
2026                         resets = <&gcc GCC_PCIE_0_BCR>;
2027                         reset-names = "pci";
2028
2029                         power-domains = <&gcc PCIE_0_GDSC>;
2030
2031                         phys = <&pcie0_lane>;
2032                         phy-names = "pciephy";
2033
2034                         status = "disabled";
2035                 };
2036
2037                 pcie0_phy: phy@1c06000 {
2038                         compatible = "qcom,sdm845-qmp-pcie-phy";
2039                         reg = <0 0x01c06000 0 0x18c>;
2040                         #address-cells = <2>;
2041                         #size-cells = <2>;
2042                         ranges;
2043                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2044                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2045                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
2046                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2047                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2048
2049                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2050                         reset-names = "phy";
2051
2052                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2053                         assigned-clock-rates = <100000000>;
2054
2055                         status = "disabled";
2056
2057                         pcie0_lane: lanes@1c06200 {
2058                                 reg = <0 0x01c06200 0 0x128>,
2059                                       <0 0x01c06400 0 0x1fc>,
2060                                       <0 0x01c06800 0 0x218>,
2061                                       <0 0x01c06600 0 0x70>;
2062                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2063                                 clock-names = "pipe0";
2064
2065                                 #phy-cells = <0>;
2066                                 clock-output-names = "pcie_0_pipe_clk";
2067                         };
2068                 };
2069
2070                 pcie1: pci@1c08000 {
2071                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2072                         reg = <0 0x01c08000 0 0x2000>,
2073                               <0 0x40000000 0 0xf1d>,
2074                               <0 0x40000f20 0 0xa8>,
2075                               <0 0x40100000 0 0x100000>;
2076                         reg-names = "parf", "dbi", "elbi", "config";
2077                         device_type = "pci";
2078                         linux,pci-domain = <1>;
2079                         bus-range = <0x00 0xff>;
2080                         num-lanes = <1>;
2081
2082                         #address-cells = <3>;
2083                         #size-cells = <2>;
2084
2085                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2086                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2087
2088                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2089                         interrupt-names = "msi";
2090                         #interrupt-cells = <1>;
2091                         interrupt-map-mask = <0 0 0 0x7>;
2092                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2093                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2094                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2095                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2096
2097                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2098                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2099                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2100                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2101                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2102                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2103                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2104                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2105                         clock-names = "pipe",
2106                                       "aux",
2107                                       "cfg",
2108                                       "bus_master",
2109                                       "bus_slave",
2110                                       "slave_q2a",
2111                                       "ref",
2112                                       "tbu";
2113
2114                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2115                         assigned-clock-rates = <19200000>;
2116
2117                         iommus = <&apps_smmu 0x1c00 0xf>;
2118                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2119                                     <0x100 &apps_smmu 0x1c01 0x1>,
2120                                     <0x200 &apps_smmu 0x1c02 0x1>,
2121                                     <0x300 &apps_smmu 0x1c03 0x1>,
2122                                     <0x400 &apps_smmu 0x1c04 0x1>,
2123                                     <0x500 &apps_smmu 0x1c05 0x1>,
2124                                     <0x600 &apps_smmu 0x1c06 0x1>,
2125                                     <0x700 &apps_smmu 0x1c07 0x1>,
2126                                     <0x800 &apps_smmu 0x1c08 0x1>,
2127                                     <0x900 &apps_smmu 0x1c09 0x1>,
2128                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
2129                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
2130                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
2131                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
2132                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
2133                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
2134
2135                         resets = <&gcc GCC_PCIE_1_BCR>;
2136                         reset-names = "pci";
2137
2138                         power-domains = <&gcc PCIE_1_GDSC>;
2139
2140                         phys = <&pcie1_lane>;
2141                         phy-names = "pciephy";
2142
2143                         status = "disabled";
2144                 };
2145
2146                 pcie1_phy: phy@1c0a000 {
2147                         compatible = "qcom,sdm845-qhp-pcie-phy";
2148                         reg = <0 0x01c0a000 0 0x800>;
2149                         #address-cells = <2>;
2150                         #size-cells = <2>;
2151                         ranges;
2152                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2153                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2154                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2155                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2156                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2157
2158                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2159                         reset-names = "phy";
2160
2161                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2162                         assigned-clock-rates = <100000000>;
2163
2164                         status = "disabled";
2165
2166                         pcie1_lane: lanes@1c06200 {
2167                                 reg = <0 0x01c0a800 0 0x800>,
2168                                       <0 0x01c0a800 0 0x800>,
2169                                       <0 0x01c0b800 0 0x400>;
2170                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2171                                 clock-names = "pipe0";
2172
2173                                 #phy-cells = <0>;
2174                                 clock-output-names = "pcie_1_pipe_clk";
2175                         };
2176                 };
2177
2178                 mem_noc: interconnect@1380000 {
2179                         compatible = "qcom,sdm845-mem-noc";
2180                         reg = <0 0x01380000 0 0x27200>;
2181                         #interconnect-cells = <2>;
2182                         qcom,bcm-voters = <&apps_bcm_voter>;
2183                 };
2184
2185                 dc_noc: interconnect@14e0000 {
2186                         compatible = "qcom,sdm845-dc-noc";
2187                         reg = <0 0x014e0000 0 0x400>;
2188                         #interconnect-cells = <2>;
2189                         qcom,bcm-voters = <&apps_bcm_voter>;
2190                 };
2191
2192                 config_noc: interconnect@1500000 {
2193                         compatible = "qcom,sdm845-config-noc";
2194                         reg = <0 0x01500000 0 0x5080>;
2195                         #interconnect-cells = <2>;
2196                         qcom,bcm-voters = <&apps_bcm_voter>;
2197                 };
2198
2199                 system_noc: interconnect@1620000 {
2200                         compatible = "qcom,sdm845-system-noc";
2201                         reg = <0 0x01620000 0 0x18080>;
2202                         #interconnect-cells = <2>;
2203                         qcom,bcm-voters = <&apps_bcm_voter>;
2204                 };
2205
2206                 aggre1_noc: interconnect@16e0000 {
2207                         compatible = "qcom,sdm845-aggre1-noc";
2208                         reg = <0 0x016e0000 0 0x15080>;
2209                         #interconnect-cells = <2>;
2210                         qcom,bcm-voters = <&apps_bcm_voter>;
2211                 };
2212
2213                 aggre2_noc: interconnect@1700000 {
2214                         compatible = "qcom,sdm845-aggre2-noc";
2215                         reg = <0 0x01700000 0 0x1f300>;
2216                         #interconnect-cells = <2>;
2217                         qcom,bcm-voters = <&apps_bcm_voter>;
2218                 };
2219
2220                 mmss_noc: interconnect@1740000 {
2221                         compatible = "qcom,sdm845-mmss-noc";
2222                         reg = <0 0x01740000 0 0x1c100>;
2223                         #interconnect-cells = <2>;
2224                         qcom,bcm-voters = <&apps_bcm_voter>;
2225                 };
2226
2227                 ufs_mem_hc: ufshc@1d84000 {
2228                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2229                                      "jedec,ufs-2.0";
2230                         reg = <0 0x01d84000 0 0x2500>,
2231                               <0 0x01d90000 0 0x8000>;
2232                         reg-names = "std", "ice";
2233                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2234                         phys = <&ufs_mem_phy_lanes>;
2235                         phy-names = "ufsphy";
2236                         lanes-per-direction = <2>;
2237                         power-domains = <&gcc UFS_PHY_GDSC>;
2238                         #reset-cells = <1>;
2239                         resets = <&gcc GCC_UFS_PHY_BCR>;
2240                         reset-names = "rst";
2241
2242                         iommus = <&apps_smmu 0x100 0xf>;
2243
2244                         clock-names =
2245                                 "core_clk",
2246                                 "bus_aggr_clk",
2247                                 "iface_clk",
2248                                 "core_clk_unipro",
2249                                 "ref_clk",
2250                                 "tx_lane0_sync_clk",
2251                                 "rx_lane0_sync_clk",
2252                                 "rx_lane1_sync_clk",
2253                                 "ice_core_clk";
2254                         clocks =
2255                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2256                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2257                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2258                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2259                                 <&rpmhcc RPMH_CXO_CLK>,
2260                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2261                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2262                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2263                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2264                         freq-table-hz =
2265                                 <50000000 200000000>,
2266                                 <0 0>,
2267                                 <0 0>,
2268                                 <37500000 150000000>,
2269                                 <0 0>,
2270                                 <0 0>,
2271                                 <0 0>,
2272                                 <0 0>,
2273                                 <0 300000000>;
2274
2275                         status = "disabled";
2276                 };
2277
2278                 ufs_mem_phy: phy@1d87000 {
2279                         compatible = "qcom,sdm845-qmp-ufs-phy";
2280                         reg = <0 0x01d87000 0 0x18c>;
2281                         #address-cells = <2>;
2282                         #size-cells = <2>;
2283                         ranges;
2284                         clock-names = "ref",
2285                                       "ref_aux";
2286                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2287                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2288
2289                         resets = <&ufs_mem_hc 0>;
2290                         reset-names = "ufsphy";
2291                         status = "disabled";
2292
2293                         ufs_mem_phy_lanes: lanes@1d87400 {
2294                                 reg = <0 0x01d87400 0 0x108>,
2295                                       <0 0x01d87600 0 0x1e0>,
2296                                       <0 0x01d87c00 0 0x1dc>,
2297                                       <0 0x01d87800 0 0x108>,
2298                                       <0 0x01d87a00 0 0x1e0>;
2299                                 #phy-cells = <0>;
2300                         };
2301                 };
2302
2303                 cryptobam: dma@1dc4000 {
2304                         compatible = "qcom,bam-v1.7.0";
2305                         reg = <0 0x01dc4000 0 0x24000>;
2306                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2307                         clocks = <&rpmhcc 15>;
2308                         clock-names = "bam_clk";
2309                         #dma-cells = <1>;
2310                         qcom,ee = <0>;
2311                         qcom,controlled-remotely = <1>;
2312                         iommus = <&apps_smmu 0x704 0x1>,
2313                                  <&apps_smmu 0x706 0x1>,
2314                                  <&apps_smmu 0x714 0x1>,
2315                                  <&apps_smmu 0x716 0x1>;
2316                 };
2317
2318                 crypto: crypto@1dfa000 {
2319                         compatible = "qcom,crypto-v5.4";
2320                         reg = <0 0x01dfa000 0 0x6000>;
2321                         clocks = <&gcc GCC_CE1_AHB_CLK>,
2322                                  <&gcc GCC_CE1_AHB_CLK>,
2323                                  <&rpmhcc 15>;
2324                         clock-names = "iface", "bus", "core";
2325                         dmas = <&cryptobam 6>, <&cryptobam 7>;
2326                         dma-names = "rx", "tx";
2327                         iommus = <&apps_smmu 0x704 0x1>,
2328                                  <&apps_smmu 0x706 0x1>,
2329                                  <&apps_smmu 0x714 0x1>,
2330                                  <&apps_smmu 0x716 0x1>;
2331                 };
2332
2333                 ipa: ipa@1e40000 {
2334                         compatible = "qcom,sdm845-ipa";
2335
2336                         iommus = <&apps_smmu 0x720 0x0>,
2337                                  <&apps_smmu 0x722 0x0>;
2338                         reg = <0 0x1e40000 0 0x7000>,
2339                               <0 0x1e47000 0 0x2000>,
2340                               <0 0x1e04000 0 0x2c000>;
2341                         reg-names = "ipa-reg",
2342                                     "ipa-shared",
2343                                     "gsi";
2344
2345                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2346                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2347                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2348                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2349                         interrupt-names = "ipa",
2350                                           "gsi",
2351                                           "ipa-clock-query",
2352                                           "ipa-setup-ready";
2353
2354                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2355                         clock-names = "core";
2356
2357                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2358                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2359                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2360                         interconnect-names = "memory",
2361                                              "imem",
2362                                              "config";
2363
2364                         qcom,smem-states = <&ipa_smp2p_out 0>,
2365                                            <&ipa_smp2p_out 1>;
2366                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2367                                                 "ipa-clock-enabled";
2368
2369                         status = "disabled";
2370                 };
2371
2372                 tcsr_mutex_regs: syscon@1f40000 {
2373                         compatible = "syscon";
2374                         reg = <0 0x01f40000 0 0x40000>;
2375                 };
2376
2377                 tlmm: pinctrl@3400000 {
2378                         compatible = "qcom,sdm845-pinctrl";
2379                         reg = <0 0x03400000 0 0xc00000>;
2380                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2381                         gpio-controller;
2382                         #gpio-cells = <2>;
2383                         interrupt-controller;
2384                         #interrupt-cells = <2>;
2385                         gpio-ranges = <&tlmm 0 0 150>;
2386                         wakeup-parent = <&pdc_intc>;
2387
2388                         cci0_default: cci0-default {
2389                                 /* SDA, SCL */
2390                                 pins = "gpio17", "gpio18";
2391                                 function = "cci_i2c";
2392
2393                                 bias-pull-up;
2394                                 drive-strength = <2>; /* 2 mA */
2395                         };
2396
2397                         cci0_sleep: cci0-sleep {
2398                                 /* SDA, SCL */
2399                                 pins = "gpio17", "gpio18";
2400                                 function = "cci_i2c";
2401
2402                                 drive-strength = <2>; /* 2 mA */
2403                                 bias-pull-down;
2404                         };
2405
2406                         cci1_default: cci1-default {
2407                                 /* SDA, SCL */
2408                                 pins = "gpio19", "gpio20";
2409                                 function = "cci_i2c";
2410
2411                                 bias-pull-up;
2412                                 drive-strength = <2>; /* 2 mA */
2413                         };
2414
2415                         cci1_sleep: cci1-sleep {
2416                                 /* SDA, SCL */
2417                                 pins = "gpio19", "gpio20";
2418                                 function = "cci_i2c";
2419
2420                                 drive-strength = <2>; /* 2 mA */
2421                                 bias-pull-down;
2422                         };
2423
2424                         qspi_clk: qspi-clk {
2425                                 pinmux {
2426                                         pins = "gpio95";
2427                                         function = "qspi_clk";
2428                                 };
2429                         };
2430
2431                         qspi_cs0: qspi-cs0 {
2432                                 pinmux {
2433                                         pins = "gpio90";
2434                                         function = "qspi_cs";
2435                                 };
2436                         };
2437
2438                         qspi_cs1: qspi-cs1 {
2439                                 pinmux {
2440                                         pins = "gpio89";
2441                                         function = "qspi_cs";
2442                                 };
2443                         };
2444
2445                         qspi_data01: qspi-data01 {
2446                                 pinmux-data {
2447                                         pins = "gpio91", "gpio92";
2448                                         function = "qspi_data";
2449                                 };
2450                         };
2451
2452                         qspi_data12: qspi-data12 {
2453                                 pinmux-data {
2454                                         pins = "gpio93", "gpio94";
2455                                         function = "qspi_data";
2456                                 };
2457                         };
2458
2459                         qup_i2c0_default: qup-i2c0-default {
2460                                 pinmux {
2461                                         pins = "gpio0", "gpio1";
2462                                         function = "qup0";
2463                                 };
2464                         };
2465
2466                         qup_i2c1_default: qup-i2c1-default {
2467                                 pinmux {
2468                                         pins = "gpio17", "gpio18";
2469                                         function = "qup1";
2470                                 };
2471                         };
2472
2473                         qup_i2c2_default: qup-i2c2-default {
2474                                 pinmux {
2475                                         pins = "gpio27", "gpio28";
2476                                         function = "qup2";
2477                                 };
2478                         };
2479
2480                         qup_i2c3_default: qup-i2c3-default {
2481                                 pinmux {
2482                                         pins = "gpio41", "gpio42";
2483                                         function = "qup3";
2484                                 };
2485                         };
2486
2487                         qup_i2c4_default: qup-i2c4-default {
2488                                 pinmux {
2489                                         pins = "gpio89", "gpio90";
2490                                         function = "qup4";
2491                                 };
2492                         };
2493
2494                         qup_i2c5_default: qup-i2c5-default {
2495                                 pinmux {
2496                                         pins = "gpio85", "gpio86";
2497                                         function = "qup5";
2498                                 };
2499                         };
2500
2501                         qup_i2c6_default: qup-i2c6-default {
2502                                 pinmux {
2503                                         pins = "gpio45", "gpio46";
2504                                         function = "qup6";
2505                                 };
2506                         };
2507
2508                         qup_i2c7_default: qup-i2c7-default {
2509                                 pinmux {
2510                                         pins = "gpio93", "gpio94";
2511                                         function = "qup7";
2512                                 };
2513                         };
2514
2515                         qup_i2c8_default: qup-i2c8-default {
2516                                 pinmux {
2517                                         pins = "gpio65", "gpio66";
2518                                         function = "qup8";
2519                                 };
2520                         };
2521
2522                         qup_i2c9_default: qup-i2c9-default {
2523                                 pinmux {
2524                                         pins = "gpio6", "gpio7";
2525                                         function = "qup9";
2526                                 };
2527                         };
2528
2529                         qup_i2c10_default: qup-i2c10-default {
2530                                 pinmux {
2531                                         pins = "gpio55", "gpio56";
2532                                         function = "qup10";
2533                                 };
2534                         };
2535
2536                         qup_i2c11_default: qup-i2c11-default {
2537                                 pinmux {
2538                                         pins = "gpio31", "gpio32";
2539                                         function = "qup11";
2540                                 };
2541                         };
2542
2543                         qup_i2c12_default: qup-i2c12-default {
2544                                 pinmux {
2545                                         pins = "gpio49", "gpio50";
2546                                         function = "qup12";
2547                                 };
2548                         };
2549
2550                         qup_i2c13_default: qup-i2c13-default {
2551                                 pinmux {
2552                                         pins = "gpio105", "gpio106";
2553                                         function = "qup13";
2554                                 };
2555                         };
2556
2557                         qup_i2c14_default: qup-i2c14-default {
2558                                 pinmux {
2559                                         pins = "gpio33", "gpio34";
2560                                         function = "qup14";
2561                                 };
2562                         };
2563
2564                         qup_i2c15_default: qup-i2c15-default {
2565                                 pinmux {
2566                                         pins = "gpio81", "gpio82";
2567                                         function = "qup15";
2568                                 };
2569                         };
2570
2571                         qup_spi0_default: qup-spi0-default {
2572                                 pinmux {
2573                                         pins = "gpio0", "gpio1",
2574                                                "gpio2", "gpio3";
2575                                         function = "qup0";
2576                                 };
2577                         };
2578
2579                         qup_spi1_default: qup-spi1-default {
2580                                 pinmux {
2581                                         pins = "gpio17", "gpio18",
2582                                                "gpio19", "gpio20";
2583                                         function = "qup1";
2584                                 };
2585                         };
2586
2587                         qup_spi2_default: qup-spi2-default {
2588                                 pinmux {
2589                                         pins = "gpio27", "gpio28",
2590                                                "gpio29", "gpio30";
2591                                         function = "qup2";
2592                                 };
2593                         };
2594
2595                         qup_spi3_default: qup-spi3-default {
2596                                 pinmux {
2597                                         pins = "gpio41", "gpio42",
2598                                                "gpio43", "gpio44";
2599                                         function = "qup3";
2600                                 };
2601                         };
2602
2603                         qup_spi4_default: qup-spi4-default {
2604                                 pinmux {
2605                                         pins = "gpio89", "gpio90",
2606                                                "gpio91", "gpio92";
2607                                         function = "qup4";
2608                                 };
2609                         };
2610
2611                         qup_spi5_default: qup-spi5-default {
2612                                 pinmux {
2613                                         pins = "gpio85", "gpio86",
2614                                                "gpio87", "gpio88";
2615                                         function = "qup5";
2616                                 };
2617                         };
2618
2619                         qup_spi6_default: qup-spi6-default {
2620                                 pinmux {
2621                                         pins = "gpio45", "gpio46",
2622                                                "gpio47", "gpio48";
2623                                         function = "qup6";
2624                                 };
2625                         };
2626
2627                         qup_spi7_default: qup-spi7-default {
2628                                 pinmux {
2629                                         pins = "gpio93", "gpio94",
2630                                                "gpio95", "gpio96";
2631                                         function = "qup7";
2632                                 };
2633                         };
2634
2635                         qup_spi8_default: qup-spi8-default {
2636                                 pinmux {
2637                                         pins = "gpio65", "gpio66",
2638                                                "gpio67", "gpio68";
2639                                         function = "qup8";
2640                                 };
2641                         };
2642
2643                         qup_spi9_default: qup-spi9-default {
2644                                 pinmux {
2645                                         pins = "gpio6", "gpio7",
2646                                                "gpio4", "gpio5";
2647                                         function = "qup9";
2648                                 };
2649                         };
2650
2651                         qup_spi10_default: qup-spi10-default {
2652                                 pinmux {
2653                                         pins = "gpio55", "gpio56",
2654                                                "gpio53", "gpio54";
2655                                         function = "qup10";
2656                                 };
2657                         };
2658
2659                         qup_spi11_default: qup-spi11-default {
2660                                 pinmux {
2661                                         pins = "gpio31", "gpio32",
2662                                                "gpio33", "gpio34";
2663                                         function = "qup11";
2664                                 };
2665                         };
2666
2667                         qup_spi12_default: qup-spi12-default {
2668                                 pinmux {
2669                                         pins = "gpio49", "gpio50",
2670                                                "gpio51", "gpio52";
2671                                         function = "qup12";
2672                                 };
2673                         };
2674
2675                         qup_spi13_default: qup-spi13-default {
2676                                 pinmux {
2677                                         pins = "gpio105", "gpio106",
2678                                                "gpio107", "gpio108";
2679                                         function = "qup13";
2680                                 };
2681                         };
2682
2683                         qup_spi14_default: qup-spi14-default {
2684                                 pinmux {
2685                                         pins = "gpio33", "gpio34",
2686                                                "gpio31", "gpio32";
2687                                         function = "qup14";
2688                                 };
2689                         };
2690
2691                         qup_spi15_default: qup-spi15-default {
2692                                 pinmux {
2693                                         pins = "gpio81", "gpio82",
2694                                                "gpio83", "gpio84";
2695                                         function = "qup15";
2696                                 };
2697                         };
2698
2699                         qup_uart0_default: qup-uart0-default {
2700                                 pinmux {
2701                                         pins = "gpio2", "gpio3";
2702                                         function = "qup0";
2703                                 };
2704                         };
2705
2706                         qup_uart1_default: qup-uart1-default {
2707                                 pinmux {
2708                                         pins = "gpio19", "gpio20";
2709                                         function = "qup1";
2710                                 };
2711                         };
2712
2713                         qup_uart2_default: qup-uart2-default {
2714                                 pinmux {
2715                                         pins = "gpio29", "gpio30";
2716                                         function = "qup2";
2717                                 };
2718                         };
2719
2720                         qup_uart3_default: qup-uart3-default {
2721                                 pinmux {
2722                                         pins = "gpio43", "gpio44";
2723                                         function = "qup3";
2724                                 };
2725                         };
2726
2727                         qup_uart4_default: qup-uart4-default {
2728                                 pinmux {
2729                                         pins = "gpio91", "gpio92";
2730                                         function = "qup4";
2731                                 };
2732                         };
2733
2734                         qup_uart5_default: qup-uart5-default {
2735                                 pinmux {
2736                                         pins = "gpio87", "gpio88";
2737                                         function = "qup5";
2738                                 };
2739                         };
2740
2741                         qup_uart6_default: qup-uart6-default {
2742                                 pinmux {
2743                                         pins = "gpio47", "gpio48";
2744                                         function = "qup6";
2745                                 };
2746                         };
2747
2748                         qup_uart7_default: qup-uart7-default {
2749                                 pinmux {
2750                                         pins = "gpio95", "gpio96";
2751                                         function = "qup7";
2752                                 };
2753                         };
2754
2755                         qup_uart8_default: qup-uart8-default {
2756                                 pinmux {
2757                                         pins = "gpio67", "gpio68";
2758                                         function = "qup8";
2759                                 };
2760                         };
2761
2762                         qup_uart9_default: qup-uart9-default {
2763                                 pinmux {
2764                                         pins = "gpio4", "gpio5";
2765                                         function = "qup9";
2766                                 };
2767                         };
2768
2769                         qup_uart10_default: qup-uart10-default {
2770                                 pinmux {
2771                                         pins = "gpio53", "gpio54";
2772                                         function = "qup10";
2773                                 };
2774                         };
2775
2776                         qup_uart11_default: qup-uart11-default {
2777                                 pinmux {
2778                                         pins = "gpio33", "gpio34";
2779                                         function = "qup11";
2780                                 };
2781                         };
2782
2783                         qup_uart12_default: qup-uart12-default {
2784                                 pinmux {
2785                                         pins = "gpio51", "gpio52";
2786                                         function = "qup12";
2787                                 };
2788                         };
2789
2790                         qup_uart13_default: qup-uart13-default {
2791                                 pinmux {
2792                                         pins = "gpio107", "gpio108";
2793                                         function = "qup13";
2794                                 };
2795                         };
2796
2797                         qup_uart14_default: qup-uart14-default {
2798                                 pinmux {
2799                                         pins = "gpio31", "gpio32";
2800                                         function = "qup14";
2801                                 };
2802                         };
2803
2804                         qup_uart15_default: qup-uart15-default {
2805                                 pinmux {
2806                                         pins = "gpio83", "gpio84";
2807                                         function = "qup15";
2808                                 };
2809                         };
2810
2811                         quat_mi2s_sleep: quat_mi2s_sleep {
2812                                 mux {
2813                                         pins = "gpio58", "gpio59";
2814                                         function = "gpio";
2815                                 };
2816
2817                                 config {
2818                                         pins = "gpio58", "gpio59";
2819                                         drive-strength = <2>;
2820                                         bias-pull-down;
2821                                         input-enable;
2822                                 };
2823                         };
2824
2825                         quat_mi2s_active: quat_mi2s_active {
2826                                 mux {
2827                                         pins = "gpio58", "gpio59";
2828                                         function = "qua_mi2s";
2829                                 };
2830
2831                                 config {
2832                                         pins = "gpio58", "gpio59";
2833                                         drive-strength = <8>;
2834                                         bias-disable;
2835                                         output-high;
2836                                 };
2837                         };
2838
2839                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2840                                 mux {
2841                                         pins = "gpio60";
2842                                         function = "gpio";
2843                                 };
2844
2845                                 config {
2846                                         pins = "gpio60";
2847                                         drive-strength = <2>;
2848                                         bias-pull-down;
2849                                         input-enable;
2850                                 };
2851                         };
2852
2853                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2854                                 mux {
2855                                         pins = "gpio60";
2856                                         function = "qua_mi2s";
2857                                 };
2858
2859                                 config {
2860                                         pins = "gpio60";
2861                                         drive-strength = <8>;
2862                                         bias-disable;
2863                                 };
2864                         };
2865
2866                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2867                                 mux {
2868                                         pins = "gpio61";
2869                                         function = "gpio";
2870                                 };
2871
2872                                 config {
2873                                         pins = "gpio61";
2874                                         drive-strength = <2>;
2875                                         bias-pull-down;
2876                                         input-enable;
2877                                 };
2878                         };
2879
2880                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2881                                 mux {
2882                                         pins = "gpio61";
2883                                         function = "qua_mi2s";
2884                                 };
2885
2886                                 config {
2887                                         pins = "gpio61";
2888                                         drive-strength = <8>;
2889                                         bias-disable;
2890                                 };
2891                         };
2892
2893                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2894                                 mux {
2895                                         pins = "gpio62";
2896                                         function = "gpio";
2897                                 };
2898
2899                                 config {
2900                                         pins = "gpio62";
2901                                         drive-strength = <2>;
2902                                         bias-pull-down;
2903                                         input-enable;
2904                                 };
2905                         };
2906
2907                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2908                                 mux {
2909                                         pins = "gpio62";
2910                                         function = "qua_mi2s";
2911                                 };
2912
2913                                 config {
2914                                         pins = "gpio62";
2915                                         drive-strength = <8>;
2916                                         bias-disable;
2917                                 };
2918                         };
2919
2920                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2921                                 mux {
2922                                         pins = "gpio63";
2923                                         function = "gpio";
2924                                 };
2925
2926                                 config {
2927                                         pins = "gpio63";
2928                                         drive-strength = <2>;
2929                                         bias-pull-down;
2930                                         input-enable;
2931                                 };
2932                         };
2933
2934                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2935                                 mux {
2936                                         pins = "gpio63";
2937                                         function = "qua_mi2s";
2938                                 };
2939
2940                                 config {
2941                                         pins = "gpio63";
2942                                         drive-strength = <8>;
2943                                         bias-disable;
2944                                 };
2945                         };
2946                 };
2947
2948                 mss_pil: remoteproc@4080000 {
2949                         compatible = "qcom,sdm845-mss-pil";
2950                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2951                         reg-names = "qdsp6", "rmb";
2952
2953                         interrupts-extended =
2954                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2955                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2956                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2957                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2958                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2959                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2960                         interrupt-names = "wdog", "fatal", "ready",
2961                                           "handover", "stop-ack",
2962                                           "shutdown-ack";
2963
2964                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2965                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2966                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2967                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2968                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2969                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2970                                  <&gcc GCC_PRNG_AHB_CLK>,
2971                                  <&rpmhcc RPMH_CXO_CLK>;
2972                         clock-names = "iface", "bus", "mem", "gpll0_mss",
2973                                       "snoc_axi", "mnoc_axi", "prng", "xo";
2974
2975                         qcom,smem-states = <&modem_smp2p_out 0>;
2976                         qcom,smem-state-names = "stop";
2977
2978                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2979                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2980                         reset-names = "mss_restart", "pdc_reset";
2981
2982                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2983
2984                         power-domains = <&aoss_qmp 2>,
2985                                         <&rpmhpd SDM845_CX>,
2986                                         <&rpmhpd SDM845_MX>,
2987                                         <&rpmhpd SDM845_MSS>;
2988                         power-domain-names = "load_state", "cx", "mx", "mss";
2989
2990                         mba {
2991                                 memory-region = <&mba_region>;
2992                         };
2993
2994                         mpss {
2995                                 memory-region = <&mpss_region>;
2996                         };
2997
2998                         glink-edge {
2999                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3000                                 label = "modem";
3001                                 qcom,remote-pid = <1>;
3002                                 mboxes = <&apss_shared 12>;
3003                         };
3004                 };
3005
3006                 gpucc: clock-controller@5090000 {
3007                         compatible = "qcom,sdm845-gpucc";
3008                         reg = <0 0x05090000 0 0x9000>;
3009                         #clock-cells = <1>;
3010                         #reset-cells = <1>;
3011                         #power-domain-cells = <1>;
3012                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3013                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3014                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3015                         clock-names = "bi_tcxo",
3016                                       "gcc_gpu_gpll0_clk_src",
3017                                       "gcc_gpu_gpll0_div_clk_src";
3018                 };
3019
3020                 stm@6002000 {
3021                         compatible = "arm,coresight-stm", "arm,primecell";
3022                         reg = <0 0x06002000 0 0x1000>,
3023                               <0 0x16280000 0 0x180000>;
3024                         reg-names = "stm-base", "stm-stimulus-base";
3025
3026                         clocks = <&aoss_qmp>;
3027                         clock-names = "apb_pclk";
3028
3029                         out-ports {
3030                                 port {
3031                                         stm_out: endpoint {
3032                                                 remote-endpoint =
3033                                                   <&funnel0_in7>;
3034                                         };
3035                                 };
3036                         };
3037                 };
3038
3039                 funnel@6041000 {
3040                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3041                         reg = <0 0x06041000 0 0x1000>;
3042
3043                         clocks = <&aoss_qmp>;
3044                         clock-names = "apb_pclk";
3045
3046                         out-ports {
3047                                 port {
3048                                         funnel0_out: endpoint {
3049                                                 remote-endpoint =
3050                                                   <&merge_funnel_in0>;
3051                                         };
3052                                 };
3053                         };
3054
3055                         in-ports {
3056                                 #address-cells = <1>;
3057                                 #size-cells = <0>;
3058
3059                                 port@7 {
3060                                         reg = <7>;
3061                                         funnel0_in7: endpoint {
3062                                                 remote-endpoint = <&stm_out>;
3063                                         };
3064                                 };
3065                         };
3066                 };
3067
3068                 funnel@6043000 {
3069                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3070                         reg = <0 0x06043000 0 0x1000>;
3071
3072                         clocks = <&aoss_qmp>;
3073                         clock-names = "apb_pclk";
3074
3075                         out-ports {
3076                                 port {
3077                                         funnel2_out: endpoint {
3078                                                 remote-endpoint =
3079                                                   <&merge_funnel_in2>;
3080                                         };
3081                                 };
3082                         };
3083
3084                         in-ports {
3085                                 #address-cells = <1>;
3086                                 #size-cells = <0>;
3087
3088                                 port@5 {
3089                                         reg = <5>;
3090                                         funnel2_in5: endpoint {
3091                                                 remote-endpoint =
3092                                                   <&apss_merge_funnel_out>;
3093                                         };
3094                                 };
3095                         };
3096                 };
3097
3098                 funnel@6045000 {
3099                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3100                         reg = <0 0x06045000 0 0x1000>;
3101
3102                         clocks = <&aoss_qmp>;
3103                         clock-names = "apb_pclk";
3104
3105                         out-ports {
3106                                 port {
3107                                         merge_funnel_out: endpoint {
3108                                                 remote-endpoint = <&etf_in>;
3109                                         };
3110                                 };
3111                         };
3112
3113                         in-ports {
3114                                 #address-cells = <1>;
3115                                 #size-cells = <0>;
3116
3117                                 port@0 {
3118                                         reg = <0>;
3119                                         merge_funnel_in0: endpoint {
3120                                                 remote-endpoint =
3121                                                   <&funnel0_out>;
3122                                         };
3123                                 };
3124
3125                                 port@2 {
3126                                         reg = <2>;
3127                                         merge_funnel_in2: endpoint {
3128                                                 remote-endpoint =
3129                                                   <&funnel2_out>;
3130                                         };
3131                                 };
3132                         };
3133                 };
3134
3135                 replicator@6046000 {
3136                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3137                         reg = <0 0x06046000 0 0x1000>;
3138
3139                         clocks = <&aoss_qmp>;
3140                         clock-names = "apb_pclk";
3141
3142                         out-ports {
3143                                 port {
3144                                         replicator_out: endpoint {
3145                                                 remote-endpoint = <&etr_in>;
3146                                         };
3147                                 };
3148                         };
3149
3150                         in-ports {
3151                                 port {
3152                                         replicator_in: endpoint {
3153                                                 remote-endpoint = <&etf_out>;
3154                                         };
3155                                 };
3156                         };
3157                 };
3158
3159                 etf@6047000 {
3160                         compatible = "arm,coresight-tmc", "arm,primecell";
3161                         reg = <0 0x06047000 0 0x1000>;
3162
3163                         clocks = <&aoss_qmp>;
3164                         clock-names = "apb_pclk";
3165
3166                         out-ports {
3167                                 port {
3168                                         etf_out: endpoint {
3169                                                 remote-endpoint =
3170                                                   <&replicator_in>;
3171                                         };
3172                                 };
3173                         };
3174
3175                         in-ports {
3176                                 #address-cells = <1>;
3177                                 #size-cells = <0>;
3178
3179                                 port@1 {
3180                                         reg = <1>;
3181                                         etf_in: endpoint {
3182                                                 remote-endpoint =
3183                                                   <&merge_funnel_out>;
3184                                         };
3185                                 };
3186                         };
3187                 };
3188
3189                 etr@6048000 {
3190                         compatible = "arm,coresight-tmc", "arm,primecell";
3191                         reg = <0 0x06048000 0 0x1000>;
3192
3193                         clocks = <&aoss_qmp>;
3194                         clock-names = "apb_pclk";
3195                         arm,scatter-gather;
3196
3197                         in-ports {
3198                                 port {
3199                                         etr_in: endpoint {
3200                                                 remote-endpoint =
3201                                                   <&replicator_out>;
3202                                         };
3203                                 };
3204                         };
3205                 };
3206
3207                 etm@7040000 {
3208                         compatible = "arm,coresight-etm4x", "arm,primecell";
3209                         reg = <0 0x07040000 0 0x1000>;
3210
3211                         cpu = <&CPU0>;
3212
3213                         clocks = <&aoss_qmp>;
3214                         clock-names = "apb_pclk";
3215                         arm,coresight-loses-context-with-cpu;
3216
3217                         out-ports {
3218                                 port {
3219                                         etm0_out: endpoint {
3220                                                 remote-endpoint =
3221                                                   <&apss_funnel_in0>;
3222                                         };
3223                                 };
3224                         };
3225                 };
3226
3227                 etm@7140000 {
3228                         compatible = "arm,coresight-etm4x", "arm,primecell";
3229                         reg = <0 0x07140000 0 0x1000>;
3230
3231                         cpu = <&CPU1>;
3232
3233                         clocks = <&aoss_qmp>;
3234                         clock-names = "apb_pclk";
3235                         arm,coresight-loses-context-with-cpu;
3236
3237                         out-ports {
3238                                 port {
3239                                         etm1_out: endpoint {
3240                                                 remote-endpoint =
3241                                                   <&apss_funnel_in1>;
3242                                         };
3243                                 };
3244                         };
3245                 };
3246
3247                 etm@7240000 {
3248                         compatible = "arm,coresight-etm4x", "arm,primecell";
3249                         reg = <0 0x07240000 0 0x1000>;
3250
3251                         cpu = <&CPU2>;
3252
3253                         clocks = <&aoss_qmp>;
3254                         clock-names = "apb_pclk";
3255                         arm,coresight-loses-context-with-cpu;
3256
3257                         out-ports {
3258                                 port {
3259                                         etm2_out: endpoint {
3260                                                 remote-endpoint =
3261                                                   <&apss_funnel_in2>;
3262                                         };
3263                                 };
3264                         };
3265                 };
3266
3267                 etm@7340000 {
3268                         compatible = "arm,coresight-etm4x", "arm,primecell";
3269                         reg = <0 0x07340000 0 0x1000>;
3270
3271                         cpu = <&CPU3>;
3272
3273                         clocks = <&aoss_qmp>;
3274                         clock-names = "apb_pclk";
3275                         arm,coresight-loses-context-with-cpu;
3276
3277                         out-ports {
3278                                 port {
3279                                         etm3_out: endpoint {
3280                                                 remote-endpoint =
3281                                                   <&apss_funnel_in3>;
3282                                         };
3283                                 };
3284                         };
3285                 };
3286
3287                 etm@7440000 {
3288                         compatible = "arm,coresight-etm4x", "arm,primecell";
3289                         reg = <0 0x07440000 0 0x1000>;
3290
3291                         cpu = <&CPU4>;
3292
3293                         clocks = <&aoss_qmp>;
3294                         clock-names = "apb_pclk";
3295                         arm,coresight-loses-context-with-cpu;
3296
3297                         out-ports {
3298                                 port {
3299                                         etm4_out: endpoint {
3300                                                 remote-endpoint =
3301                                                   <&apss_funnel_in4>;
3302                                         };
3303                                 };
3304                         };
3305                 };
3306
3307                 etm@7540000 {
3308                         compatible = "arm,coresight-etm4x", "arm,primecell";
3309                         reg = <0 0x07540000 0 0x1000>;
3310
3311                         cpu = <&CPU5>;
3312
3313                         clocks = <&aoss_qmp>;
3314                         clock-names = "apb_pclk";
3315                         arm,coresight-loses-context-with-cpu;
3316
3317                         out-ports {
3318                                 port {
3319                                         etm5_out: endpoint {
3320                                                 remote-endpoint =
3321                                                   <&apss_funnel_in5>;
3322                                         };
3323                                 };
3324                         };
3325                 };
3326
3327                 etm@7640000 {
3328                         compatible = "arm,coresight-etm4x", "arm,primecell";
3329                         reg = <0 0x07640000 0 0x1000>;
3330
3331                         cpu = <&CPU6>;
3332
3333                         clocks = <&aoss_qmp>;
3334                         clock-names = "apb_pclk";
3335                         arm,coresight-loses-context-with-cpu;
3336
3337                         out-ports {
3338                                 port {
3339                                         etm6_out: endpoint {
3340                                                 remote-endpoint =
3341                                                   <&apss_funnel_in6>;
3342                                         };
3343                                 };
3344                         };
3345                 };
3346
3347                 etm@7740000 {
3348                         compatible = "arm,coresight-etm4x", "arm,primecell";
3349                         reg = <0 0x07740000 0 0x1000>;
3350
3351                         cpu = <&CPU7>;
3352
3353                         clocks = <&aoss_qmp>;
3354                         clock-names = "apb_pclk";
3355                         arm,coresight-loses-context-with-cpu;
3356
3357                         out-ports {
3358                                 port {
3359                                         etm7_out: endpoint {
3360                                                 remote-endpoint =
3361                                                   <&apss_funnel_in7>;
3362                                         };
3363                                 };
3364                         };
3365                 };
3366
3367                 funnel@7800000 { /* APSS Funnel */
3368                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3369                         reg = <0 0x07800000 0 0x1000>;
3370
3371                         clocks = <&aoss_qmp>;
3372                         clock-names = "apb_pclk";
3373
3374                         out-ports {
3375                                 port {
3376                                         apss_funnel_out: endpoint {
3377                                                 remote-endpoint =
3378                                                   <&apss_merge_funnel_in>;
3379                                         };
3380                                 };
3381                         };
3382
3383                         in-ports {
3384                                 #address-cells = <1>;
3385                                 #size-cells = <0>;
3386
3387                                 port@0 {
3388                                         reg = <0>;
3389                                         apss_funnel_in0: endpoint {
3390                                                 remote-endpoint =
3391                                                   <&etm0_out>;
3392                                         };
3393                                 };
3394
3395                                 port@1 {
3396                                         reg = <1>;
3397                                         apss_funnel_in1: endpoint {
3398                                                 remote-endpoint =
3399                                                   <&etm1_out>;
3400                                         };
3401                                 };
3402
3403                                 port@2 {
3404                                         reg = <2>;
3405                                         apss_funnel_in2: endpoint {
3406                                                 remote-endpoint =
3407                                                   <&etm2_out>;
3408                                         };
3409                                 };
3410
3411                                 port@3 {
3412                                         reg = <3>;
3413                                         apss_funnel_in3: endpoint {
3414                                                 remote-endpoint =
3415                                                   <&etm3_out>;
3416                                         };
3417                                 };
3418
3419                                 port@4 {
3420                                         reg = <4>;
3421                                         apss_funnel_in4: endpoint {
3422                                                 remote-endpoint =
3423                                                   <&etm4_out>;
3424                                         };
3425                                 };
3426
3427                                 port@5 {
3428                                         reg = <5>;
3429                                         apss_funnel_in5: endpoint {
3430                                                 remote-endpoint =
3431                                                   <&etm5_out>;
3432                                         };
3433                                 };
3434
3435                                 port@6 {
3436                                         reg = <6>;
3437                                         apss_funnel_in6: endpoint {
3438                                                 remote-endpoint =
3439                                                   <&etm6_out>;
3440                                         };
3441                                 };
3442
3443                                 port@7 {
3444                                         reg = <7>;
3445                                         apss_funnel_in7: endpoint {
3446                                                 remote-endpoint =
3447                                                   <&etm7_out>;
3448                                         };
3449                                 };
3450                         };
3451                 };
3452
3453                 funnel@7810000 {
3454                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3455                         reg = <0 0x07810000 0 0x1000>;
3456
3457                         clocks = <&aoss_qmp>;
3458                         clock-names = "apb_pclk";
3459
3460                         out-ports {
3461                                 port {
3462                                         apss_merge_funnel_out: endpoint {
3463                                                 remote-endpoint =
3464                                                   <&funnel2_in5>;
3465                                         };
3466                                 };
3467                         };
3468
3469                         in-ports {
3470                                 port {
3471                                         apss_merge_funnel_in: endpoint {
3472                                                 remote-endpoint =
3473                                                   <&apss_funnel_out>;
3474                                         };
3475                                 };
3476                         };
3477                 };
3478
3479                 sdhc_2: sdhci@8804000 {
3480                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3481                         reg = <0 0x08804000 0 0x1000>;
3482
3483                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3484                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3485                         interrupt-names = "hc_irq", "pwr_irq";
3486
3487                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3488                                  <&gcc GCC_SDCC2_APPS_CLK>;
3489                         clock-names = "iface", "core";
3490                         iommus = <&apps_smmu 0xa0 0xf>;
3491                         power-domains = <&rpmhpd SDM845_CX>;
3492                         operating-points-v2 = <&sdhc2_opp_table>;
3493
3494                         status = "disabled";
3495
3496                         sdhc2_opp_table: sdhc2-opp-table {
3497                                 compatible = "operating-points-v2";
3498
3499                                 opp-9600000 {
3500                                         opp-hz = /bits/ 64 <9600000>;
3501                                         required-opps = <&rpmhpd_opp_min_svs>;
3502                                 };
3503
3504                                 opp-19200000 {
3505                                         opp-hz = /bits/ 64 <19200000>;
3506                                         required-opps = <&rpmhpd_opp_low_svs>;
3507                                 };
3508
3509                                 opp-100000000 {
3510                                         opp-hz = /bits/ 64 <100000000>;
3511                                         required-opps = <&rpmhpd_opp_svs>;
3512                                 };
3513
3514                                 opp-201500000 {
3515                                         opp-hz = /bits/ 64 <201500000>;
3516                                         required-opps = <&rpmhpd_opp_svs_l1>;
3517                                 };
3518                         };
3519                 };
3520
3521                 qspi_opp_table: qspi-opp-table {
3522                         compatible = "operating-points-v2";
3523
3524                         opp-19200000 {
3525                                 opp-hz = /bits/ 64 <19200000>;
3526                                 required-opps = <&rpmhpd_opp_min_svs>;
3527                         };
3528
3529                         opp-100000000 {
3530                                 opp-hz = /bits/ 64 <100000000>;
3531                                 required-opps = <&rpmhpd_opp_low_svs>;
3532                         };
3533
3534                         opp-150000000 {
3535                                 opp-hz = /bits/ 64 <150000000>;
3536                                 required-opps = <&rpmhpd_opp_svs>;
3537                         };
3538
3539                         opp-300000000 {
3540                                 opp-hz = /bits/ 64 <300000000>;
3541                                 required-opps = <&rpmhpd_opp_nom>;
3542                         };
3543                 };
3544
3545                 qspi: spi@88df000 {
3546                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3547                         reg = <0 0x088df000 0 0x600>;
3548                         #address-cells = <1>;
3549                         #size-cells = <0>;
3550                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3551                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3552                                  <&gcc GCC_QSPI_CORE_CLK>;
3553                         clock-names = "iface", "core";
3554                         power-domains = <&rpmhpd SDM845_CX>;
3555                         operating-points-v2 = <&qspi_opp_table>;
3556                         status = "disabled";
3557                 };
3558
3559                 slim: slim@171c0000 {
3560                         compatible = "qcom,slim-ngd-v2.1.0";
3561                         reg = <0 0x171c0000 0 0x2c000>;
3562                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3563
3564                         qcom,apps-ch-pipes = <0x780000>;
3565                         qcom,ea-pc = <0x270>;
3566                         status = "okay";
3567                         dmas =  <&slimbam 3>, <&slimbam 4>,
3568                                 <&slimbam 5>, <&slimbam 6>;
3569                         dma-names = "rx", "tx", "tx2", "rx2";
3570
3571                         iommus = <&apps_smmu 0x1806 0x0>;
3572                         #address-cells = <1>;
3573                         #size-cells = <0>;
3574
3575                         ngd@1 {
3576                                 reg = <1>;
3577                                 #address-cells = <2>;
3578                                 #size-cells = <0>;
3579
3580                                 wcd9340_ifd: ifd@0{
3581                                         compatible = "slim217,250";
3582                                         reg  = <0 0>;
3583                                 };
3584
3585                                 wcd9340: codec@1{
3586                                         compatible = "slim217,250";
3587                                         reg  = <1 0>;
3588                                         slim-ifc-dev  = <&wcd9340_ifd>;
3589
3590                                         #sound-dai-cells = <1>;
3591
3592                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3593                                         interrupt-controller;
3594                                         #interrupt-cells = <1>;
3595
3596                                         #clock-cells = <0>;
3597                                         clock-frequency = <9600000>;
3598                                         clock-output-names = "mclk";
3599                                         qcom,micbias1-millivolt = <1800>;
3600                                         qcom,micbias2-millivolt = <1800>;
3601                                         qcom,micbias3-millivolt = <1800>;
3602                                         qcom,micbias4-millivolt = <1800>;
3603
3604                                         #address-cells = <1>;
3605                                         #size-cells = <1>;
3606
3607                                         wcdgpio: gpio-controller@42 {
3608                                                 compatible = "qcom,wcd9340-gpio";
3609                                                 gpio-controller;
3610                                                 #gpio-cells = <2>;
3611                                                 reg = <0x42 0x2>;
3612                                         };
3613
3614                                         swm: swm@c85 {
3615                                                 compatible = "qcom,soundwire-v1.3.0";
3616                                                 reg = <0xc85 0x40>;
3617                                                 interrupts-extended = <&wcd9340 20>;
3618
3619                                                 qcom,dout-ports = <6>;
3620                                                 qcom,din-ports  = <2>;
3621                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3622                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3623                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3624
3625                                                 #sound-dai-cells = <1>;
3626                                                 clocks = <&wcd9340>;
3627                                                 clock-names = "iface";
3628                                                 #address-cells = <2>;
3629                                                 #size-cells = <0>;
3630
3631
3632                                         };
3633                                 };
3634                         };
3635                 };
3636
3637                 sound: sound {
3638                 };
3639
3640                 usb_1_hsphy: phy@88e2000 {
3641                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3642                         reg = <0 0x088e2000 0 0x400>;
3643                         status = "disabled";
3644                         #phy-cells = <0>;
3645
3646                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3647                                  <&rpmhcc RPMH_CXO_CLK>;
3648                         clock-names = "cfg_ahb", "ref";
3649
3650                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3651
3652                         nvmem-cells = <&qusb2p_hstx_trim>;
3653                 };
3654
3655                 usb_2_hsphy: phy@88e3000 {
3656                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3657                         reg = <0 0x088e3000 0 0x400>;
3658                         status = "disabled";
3659                         #phy-cells = <0>;
3660
3661                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3662                                  <&rpmhcc RPMH_CXO_CLK>;
3663                         clock-names = "cfg_ahb", "ref";
3664
3665                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3666
3667                         nvmem-cells = <&qusb2s_hstx_trim>;
3668                 };
3669
3670                 usb_1_qmpphy: phy@88e9000 {
3671                         compatible = "qcom,sdm845-qmp-usb3-phy";
3672                         reg = <0 0x088e9000 0 0x18c>,
3673                               <0 0x088e8000 0 0x10>;
3674                         reg-names = "reg-base", "dp_com";
3675                         status = "disabled";
3676                         #clock-cells = <1>;
3677                         #address-cells = <2>;
3678                         #size-cells = <2>;
3679                         ranges;
3680
3681                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3682                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3683                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3684                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3685                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3686
3687                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3688                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3689                         reset-names = "phy", "common";
3690
3691                         usb_1_ssphy: lanes@88e9200 {
3692                                 reg = <0 0x088e9200 0 0x128>,
3693                                       <0 0x088e9400 0 0x200>,
3694                                       <0 0x088e9c00 0 0x218>,
3695                                       <0 0x088e9600 0 0x128>,
3696                                       <0 0x088e9800 0 0x200>,
3697                                       <0 0x088e9a00 0 0x100>;
3698                                 #phy-cells = <0>;
3699                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3700                                 clock-names = "pipe0";
3701                                 clock-output-names = "usb3_phy_pipe_clk_src";
3702                         };
3703                 };
3704
3705                 usb_2_qmpphy: phy@88eb000 {
3706                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3707                         reg = <0 0x088eb000 0 0x18c>;
3708                         status = "disabled";
3709                         #clock-cells = <1>;
3710                         #address-cells = <2>;
3711                         #size-cells = <2>;
3712                         ranges;
3713
3714                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3715                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3716                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3717                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3718                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3719
3720                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3721                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3722                         reset-names = "phy", "common";
3723
3724                         usb_2_ssphy: lane@88eb200 {
3725                                 reg = <0 0x088eb200 0 0x128>,
3726                                       <0 0x088eb400 0 0x1fc>,
3727                                       <0 0x088eb800 0 0x218>,
3728                                       <0 0x088eb600 0 0x70>;
3729                                 #phy-cells = <0>;
3730                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3731                                 clock-names = "pipe0";
3732                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3733                         };
3734                 };
3735
3736                 usb_1: usb@a6f8800 {
3737                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3738                         reg = <0 0x0a6f8800 0 0x400>;
3739                         status = "disabled";
3740                         #address-cells = <2>;
3741                         #size-cells = <2>;
3742                         ranges;
3743                         dma-ranges;
3744
3745                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3746                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3747                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3748                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3749                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3750                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3751                                       "sleep";
3752
3753                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3754                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3755                         assigned-clock-rates = <19200000>, <150000000>;
3756
3757                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3758                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3759                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3760                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3761                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3762                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3763
3764                         power-domains = <&gcc USB30_PRIM_GDSC>;
3765
3766                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3767
3768                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3769                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3770                         interconnect-names = "usb-ddr", "apps-usb";
3771
3772                         usb_1_dwc3: dwc3@a600000 {
3773                                 compatible = "snps,dwc3";
3774                                 reg = <0 0x0a600000 0 0xcd00>;
3775                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3776                                 iommus = <&apps_smmu 0x740 0>;
3777                                 snps,dis_u2_susphy_quirk;
3778                                 snps,dis_enblslpm_quirk;
3779                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3780                                 phy-names = "usb2-phy", "usb3-phy";
3781                         };
3782                 };
3783
3784                 usb_2: usb@a8f8800 {
3785                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3786                         reg = <0 0x0a8f8800 0 0x400>;
3787                         status = "disabled";
3788                         #address-cells = <2>;
3789                         #size-cells = <2>;
3790                         ranges;
3791                         dma-ranges;
3792
3793                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3794                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3795                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3796                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3797                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3798                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3799                                       "sleep";
3800
3801                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3802                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3803                         assigned-clock-rates = <19200000>, <150000000>;
3804
3805                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3806                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3807                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3808                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3809                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3810                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3811
3812                         power-domains = <&gcc USB30_SEC_GDSC>;
3813
3814                         resets = <&gcc GCC_USB30_SEC_BCR>;
3815
3816                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3817                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3818                         interconnect-names = "usb-ddr", "apps-usb";
3819
3820                         usb_2_dwc3: dwc3@a800000 {
3821                                 compatible = "snps,dwc3";
3822                                 reg = <0 0x0a800000 0 0xcd00>;
3823                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3824                                 iommus = <&apps_smmu 0x760 0>;
3825                                 snps,dis_u2_susphy_quirk;
3826                                 snps,dis_enblslpm_quirk;
3827                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3828                                 phy-names = "usb2-phy", "usb3-phy";
3829                         };
3830                 };
3831
3832                 venus: video-codec@aa00000 {
3833                         compatible = "qcom,sdm845-venus-v2";
3834                         reg = <0 0x0aa00000 0 0xff000>;
3835                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3836                         power-domains = <&videocc VENUS_GDSC>,
3837                                         <&videocc VCODEC0_GDSC>,
3838                                         <&videocc VCODEC1_GDSC>,
3839                                         <&rpmhpd SDM845_CX>;
3840                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3841                         operating-points-v2 = <&venus_opp_table>;
3842                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3843                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3844                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3845                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3846                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3847                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3848                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3849                         clock-names = "core", "iface", "bus",
3850                                       "vcodec0_core", "vcodec0_bus",
3851                                       "vcodec1_core", "vcodec1_bus";
3852                         iommus = <&apps_smmu 0x10a0 0x8>,
3853                                  <&apps_smmu 0x10b0 0x0>;
3854                         memory-region = <&venus_mem>;
3855                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3856                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3857                         interconnect-names = "video-mem", "cpu-cfg";
3858
3859                         video-core0 {
3860                                 compatible = "venus-decoder";
3861                         };
3862
3863                         video-core1 {
3864                                 compatible = "venus-encoder";
3865                         };
3866
3867                         venus_opp_table: venus-opp-table {
3868                                 compatible = "operating-points-v2";
3869
3870                                 opp-100000000 {
3871                                         opp-hz = /bits/ 64 <100000000>;
3872                                         required-opps = <&rpmhpd_opp_min_svs>;
3873                                 };
3874
3875                                 opp-200000000 {
3876                                         opp-hz = /bits/ 64 <200000000>;
3877                                         required-opps = <&rpmhpd_opp_low_svs>;
3878                                 };
3879
3880                                 opp-320000000 {
3881                                         opp-hz = /bits/ 64 <320000000>;
3882                                         required-opps = <&rpmhpd_opp_svs>;
3883                                 };
3884
3885                                 opp-380000000 {
3886                                         opp-hz = /bits/ 64 <380000000>;
3887                                         required-opps = <&rpmhpd_opp_svs_l1>;
3888                                 };
3889
3890                                 opp-444000000 {
3891                                         opp-hz = /bits/ 64 <444000000>;
3892                                         required-opps = <&rpmhpd_opp_nom>;
3893                                 };
3894
3895                                 opp-533000097 {
3896                                         opp-hz = /bits/ 64 <533000097>;
3897                                         required-opps = <&rpmhpd_opp_turbo>;
3898                                 };
3899                         };
3900                 };
3901
3902                 videocc: clock-controller@ab00000 {
3903                         compatible = "qcom,sdm845-videocc";
3904                         reg = <0 0x0ab00000 0 0x10000>;
3905                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3906                         clock-names = "bi_tcxo";
3907                         #clock-cells = <1>;
3908                         #power-domain-cells = <1>;
3909                         #reset-cells = <1>;
3910                 };
3911
3912                 cci: cci@ac4a000 {
3913                         compatible = "qcom,sdm845-cci";
3914                         #address-cells = <1>;
3915                         #size-cells = <0>;
3916
3917                         reg = <0 0x0ac4a000 0 0x4000>;
3918                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3919                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
3920
3921                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3922                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
3923                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3924                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
3925                                 <&clock_camcc CAM_CC_CCI_CLK>,
3926                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
3927                         clock-names = "camnoc_axi",
3928                                 "soc_ahb",
3929                                 "slow_ahb_src",
3930                                 "cpas_ahb",
3931                                 "cci",
3932                                 "cci_src";
3933
3934                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3935                                 <&clock_camcc CAM_CC_CCI_CLK>;
3936                         assigned-clock-rates = <80000000>, <37500000>;
3937
3938                         pinctrl-names = "default", "sleep";
3939                         pinctrl-0 = <&cci0_default &cci1_default>;
3940                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3941
3942                         status = "disabled";
3943
3944                         cci_i2c0: i2c-bus@0 {
3945                                 reg = <0>;
3946                                 clock-frequency = <1000000>;
3947                                 #address-cells = <1>;
3948                                 #size-cells = <0>;
3949                         };
3950
3951                         cci_i2c1: i2c-bus@1 {
3952                                 reg = <1>;
3953                                 clock-frequency = <1000000>;
3954                                 #address-cells = <1>;
3955                                 #size-cells = <0>;
3956                         };
3957                 };
3958
3959                 clock_camcc: clock-controller@ad00000 {
3960                         compatible = "qcom,sdm845-camcc";
3961                         reg = <0 0x0ad00000 0 0x10000>;
3962                         #clock-cells = <1>;
3963                         #reset-cells = <1>;
3964                         #power-domain-cells = <1>;
3965                 };
3966
3967                 dsi_opp_table: dsi-opp-table {
3968                         compatible = "operating-points-v2";
3969
3970                         opp-19200000 {
3971                                 opp-hz = /bits/ 64 <19200000>;
3972                                 required-opps = <&rpmhpd_opp_min_svs>;
3973                         };
3974
3975                         opp-180000000 {
3976                                 opp-hz = /bits/ 64 <180000000>;
3977                                 required-opps = <&rpmhpd_opp_low_svs>;
3978                         };
3979
3980                         opp-275000000 {
3981                                 opp-hz = /bits/ 64 <275000000>;
3982                                 required-opps = <&rpmhpd_opp_svs>;
3983                         };
3984
3985                         opp-328580000 {
3986                                 opp-hz = /bits/ 64 <328580000>;
3987                                 required-opps = <&rpmhpd_opp_svs_l1>;
3988                         };
3989
3990                         opp-358000000 {
3991                                 opp-hz = /bits/ 64 <358000000>;
3992                                 required-opps = <&rpmhpd_opp_nom>;
3993                         };
3994                 };
3995
3996                 mdss: mdss@ae00000 {
3997                         compatible = "qcom,sdm845-mdss";
3998                         reg = <0 0x0ae00000 0 0x1000>;
3999                         reg-names = "mdss";
4000
4001                         power-domains = <&dispcc MDSS_GDSC>;
4002
4003                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4004                                  <&gcc GCC_DISP_AXI_CLK>,
4005                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4006                         clock-names = "iface", "bus", "core";
4007
4008                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4009                         assigned-clock-rates = <300000000>;
4010
4011                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4012                         interrupt-controller;
4013                         #interrupt-cells = <1>;
4014
4015                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4016                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4017                         interconnect-names = "mdp0-mem", "mdp1-mem";
4018
4019                         iommus = <&apps_smmu 0x880 0x8>,
4020                                  <&apps_smmu 0xc80 0x8>;
4021
4022                         status = "disabled";
4023
4024                         #address-cells = <2>;
4025                         #size-cells = <2>;
4026                         ranges;
4027
4028                         mdss_mdp: mdp@ae01000 {
4029                                 compatible = "qcom,sdm845-dpu";
4030                                 reg = <0 0x0ae01000 0 0x8f000>,
4031                                       <0 0x0aeb0000 0 0x2008>;
4032                                 reg-names = "mdp", "vbif";
4033
4034                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4035                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
4036                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4037                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4038                                 clock-names = "iface", "bus", "core", "vsync";
4039
4040                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4041                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4042                                 assigned-clock-rates = <300000000>,
4043                                                        <19200000>;
4044                                 operating-points-v2 = <&mdp_opp_table>;
4045                                 power-domains = <&rpmhpd SDM845_CX>;
4046
4047                                 interrupt-parent = <&mdss>;
4048                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4049
4050                                 status = "disabled";
4051
4052                                 ports {
4053                                         #address-cells = <1>;
4054                                         #size-cells = <0>;
4055
4056                                         port@0 {
4057                                                 reg = <0>;
4058                                                 dpu_intf1_out: endpoint {
4059                                                         remote-endpoint = <&dsi0_in>;
4060                                                 };
4061                                         };
4062
4063                                         port@1 {
4064                                                 reg = <1>;
4065                                                 dpu_intf2_out: endpoint {
4066                                                         remote-endpoint = <&dsi1_in>;
4067                                                 };
4068                                         };
4069                                 };
4070
4071                                 mdp_opp_table: mdp-opp-table {
4072                                         compatible = "operating-points-v2";
4073
4074                                         opp-19200000 {
4075                                                 opp-hz = /bits/ 64 <19200000>;
4076                                                 required-opps = <&rpmhpd_opp_min_svs>;
4077                                         };
4078
4079                                         opp-171428571 {
4080                                                 opp-hz = /bits/ 64 <171428571>;
4081                                                 required-opps = <&rpmhpd_opp_low_svs>;
4082                                         };
4083
4084                                         opp-344000000 {
4085                                                 opp-hz = /bits/ 64 <344000000>;
4086                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4087                                         };
4088
4089                                         opp-430000000 {
4090                                                 opp-hz = /bits/ 64 <430000000>;
4091                                                 required-opps = <&rpmhpd_opp_nom>;
4092                                         };
4093                                 };
4094                         };
4095
4096                         dsi0: dsi@ae94000 {
4097                                 compatible = "qcom,mdss-dsi-ctrl";
4098                                 reg = <0 0x0ae94000 0 0x400>;
4099                                 reg-names = "dsi_ctrl";
4100
4101                                 interrupt-parent = <&mdss>;
4102                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4103
4104                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4105                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4106                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4107                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4108                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4109                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4110                                 clock-names = "byte",
4111                                               "byte_intf",
4112                                               "pixel",
4113                                               "core",
4114                                               "iface",
4115                                               "bus";
4116                                 operating-points-v2 = <&dsi_opp_table>;
4117                                 power-domains = <&rpmhpd SDM845_CX>;
4118
4119                                 phys = <&dsi0_phy>;
4120                                 phy-names = "dsi";
4121
4122                                 status = "disabled";
4123
4124                                 ports {
4125                                         #address-cells = <1>;
4126                                         #size-cells = <0>;
4127
4128                                         port@0 {
4129                                                 reg = <0>;
4130                                                 dsi0_in: endpoint {
4131                                                         remote-endpoint = <&dpu_intf1_out>;
4132                                                 };
4133                                         };
4134
4135                                         port@1 {
4136                                                 reg = <1>;
4137                                                 dsi0_out: endpoint {
4138                                                 };
4139                                         };
4140                                 };
4141                         };
4142
4143                         dsi0_phy: dsi-phy@ae94400 {
4144                                 compatible = "qcom,dsi-phy-10nm";
4145                                 reg = <0 0x0ae94400 0 0x200>,
4146                                       <0 0x0ae94600 0 0x280>,
4147                                       <0 0x0ae94a00 0 0x1e0>;
4148                                 reg-names = "dsi_phy",
4149                                             "dsi_phy_lane",
4150                                             "dsi_pll";
4151
4152                                 #clock-cells = <1>;
4153                                 #phy-cells = <0>;
4154
4155                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4156                                          <&rpmhcc RPMH_CXO_CLK>;
4157                                 clock-names = "iface", "ref";
4158
4159                                 status = "disabled";
4160                         };
4161
4162                         dsi1: dsi@ae96000 {
4163                                 compatible = "qcom,mdss-dsi-ctrl";
4164                                 reg = <0 0x0ae96000 0 0x400>;
4165                                 reg-names = "dsi_ctrl";
4166
4167                                 interrupt-parent = <&mdss>;
4168                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4169
4170                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4171                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4172                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4173                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4174                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4175                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4176                                 clock-names = "byte",
4177                                               "byte_intf",
4178                                               "pixel",
4179                                               "core",
4180                                               "iface",
4181                                               "bus";
4182                                 operating-points-v2 = <&dsi_opp_table>;
4183                                 power-domains = <&rpmhpd SDM845_CX>;
4184
4185                                 phys = <&dsi1_phy>;
4186                                 phy-names = "dsi";
4187
4188                                 status = "disabled";
4189
4190                                 ports {
4191                                         #address-cells = <1>;
4192                                         #size-cells = <0>;
4193
4194                                         port@0 {
4195                                                 reg = <0>;
4196                                                 dsi1_in: endpoint {
4197                                                         remote-endpoint = <&dpu_intf2_out>;
4198                                                 };
4199                                         };
4200
4201                                         port@1 {
4202                                                 reg = <1>;
4203                                                 dsi1_out: endpoint {
4204                                                 };
4205                                         };
4206                                 };
4207                         };
4208
4209                         dsi1_phy: dsi-phy@ae96400 {
4210                                 compatible = "qcom,dsi-phy-10nm";
4211                                 reg = <0 0x0ae96400 0 0x200>,
4212                                       <0 0x0ae96600 0 0x280>,
4213                                       <0 0x0ae96a00 0 0x10e>;
4214                                 reg-names = "dsi_phy",
4215                                             "dsi_phy_lane",
4216                                             "dsi_pll";
4217
4218                                 #clock-cells = <1>;
4219                                 #phy-cells = <0>;
4220
4221                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4222                                          <&rpmhcc RPMH_CXO_CLK>;
4223                                 clock-names = "iface", "ref";
4224
4225                                 status = "disabled";
4226                         };
4227                 };
4228
4229                 gpu: gpu@5000000 {
4230                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4231                         #stream-id-cells = <16>;
4232
4233                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4234                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4235
4236                         /*
4237                          * Look ma, no clocks! The GPU clocks and power are
4238                          * controlled entirely by the GMU
4239                          */
4240
4241                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4242
4243                         iommus = <&adreno_smmu 0>;
4244
4245                         operating-points-v2 = <&gpu_opp_table>;
4246
4247                         qcom,gmu = <&gmu>;
4248
4249                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4250                         interconnect-names = "gfx-mem";
4251
4252                         gpu_opp_table: opp-table {
4253                                 compatible = "operating-points-v2";
4254
4255                                 opp-710000000 {
4256                                         opp-hz = /bits/ 64 <710000000>;
4257                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4258                                         opp-peak-kBps = <7216000>;
4259                                 };
4260
4261                                 opp-675000000 {
4262                                         opp-hz = /bits/ 64 <675000000>;
4263                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4264                                         opp-peak-kBps = <7216000>;
4265                                 };
4266
4267                                 opp-596000000 {
4268                                         opp-hz = /bits/ 64 <596000000>;
4269                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4270                                         opp-peak-kBps = <6220000>;
4271                                 };
4272
4273                                 opp-520000000 {
4274                                         opp-hz = /bits/ 64 <520000000>;
4275                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4276                                         opp-peak-kBps = <6220000>;
4277                                 };
4278
4279                                 opp-414000000 {
4280                                         opp-hz = /bits/ 64 <414000000>;
4281                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4282                                         opp-peak-kBps = <4068000>;
4283                                 };
4284
4285                                 opp-342000000 {
4286                                         opp-hz = /bits/ 64 <342000000>;
4287                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4288                                         opp-peak-kBps = <2724000>;
4289                                 };
4290
4291                                 opp-257000000 {
4292                                         opp-hz = /bits/ 64 <257000000>;
4293                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4294                                         opp-peak-kBps = <1648000>;
4295                                 };
4296                         };
4297                 };
4298
4299                 adreno_smmu: iommu@5040000 {
4300                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4301                         reg = <0 0x5040000 0 0x10000>;
4302                         #iommu-cells = <1>;
4303                         #global-interrupts = <2>;
4304                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4305                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4306                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4307                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4308                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4309                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4310                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4311                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4312                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4313                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4314                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4315                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4316                         clock-names = "bus", "iface";
4317
4318                         power-domains = <&gpucc GPU_CX_GDSC>;
4319                 };
4320
4321                 gmu: gmu@506a000 {
4322                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4323
4324                         reg = <0 0x506a000 0 0x30000>,
4325                               <0 0xb280000 0 0x10000>,
4326                               <0 0xb480000 0 0x10000>;
4327                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4328
4329                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4330                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4331                         interrupt-names = "hfi", "gmu";
4332
4333                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4334                                  <&gpucc GPU_CC_CXO_CLK>,
4335                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4336                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4337                         clock-names = "gmu", "cxo", "axi", "memnoc";
4338
4339                         power-domains = <&gpucc GPU_CX_GDSC>,
4340                                         <&gpucc GPU_GX_GDSC>;
4341                         power-domain-names = "cx", "gx";
4342
4343                         iommus = <&adreno_smmu 5>;
4344
4345                         operating-points-v2 = <&gmu_opp_table>;
4346
4347                         gmu_opp_table: opp-table {
4348                                 compatible = "operating-points-v2";
4349
4350                                 opp-400000000 {
4351                                         opp-hz = /bits/ 64 <400000000>;
4352                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4353                                 };
4354
4355                                 opp-200000000 {
4356                                         opp-hz = /bits/ 64 <200000000>;
4357                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4358                                 };
4359                         };
4360                 };
4361
4362                 dispcc: clock-controller@af00000 {
4363                         compatible = "qcom,sdm845-dispcc";
4364                         reg = <0 0x0af00000 0 0x10000>;
4365                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4366                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4367                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4368                                  <&dsi0_phy 0>,
4369                                  <&dsi0_phy 1>,
4370                                  <&dsi1_phy 0>,
4371                                  <&dsi1_phy 1>,
4372                                  <0>,
4373                                  <0>;
4374                         clock-names = "bi_tcxo",
4375                                       "gcc_disp_gpll0_clk_src",
4376                                       "gcc_disp_gpll0_div_clk_src",
4377                                       "dsi0_phy_pll_out_byteclk",
4378                                       "dsi0_phy_pll_out_dsiclk",
4379                                       "dsi1_phy_pll_out_byteclk",
4380                                       "dsi1_phy_pll_out_dsiclk",
4381                                       "dp_link_clk_divsel_ten",
4382                                       "dp_vco_divided_clk_src_mux";
4383                         #clock-cells = <1>;
4384                         #reset-cells = <1>;
4385                         #power-domain-cells = <1>;
4386                 };
4387
4388                 pdc_intc: interrupt-controller@b220000 {
4389                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4390                         reg = <0 0x0b220000 0 0x30000>;
4391                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4392                         #interrupt-cells = <2>;
4393                         interrupt-parent = <&intc>;
4394                         interrupt-controller;
4395                 };
4396
4397                 pdc_reset: reset-controller@b2e0000 {
4398                         compatible = "qcom,sdm845-pdc-global";
4399                         reg = <0 0x0b2e0000 0 0x20000>;
4400                         #reset-cells = <1>;
4401                 };
4402
4403                 tsens0: thermal-sensor@c263000 {
4404                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4405                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4406                               <0 0x0c222000 0 0x1ff>; /* SROT */
4407                         #qcom,sensors = <13>;
4408                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4409                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4410                         interrupt-names = "uplow", "critical";
4411                         #thermal-sensor-cells = <1>;
4412                 };
4413
4414                 tsens1: thermal-sensor@c265000 {
4415                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4416                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4417                               <0 0x0c223000 0 0x1ff>; /* SROT */
4418                         #qcom,sensors = <8>;
4419                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4420                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4421                         interrupt-names = "uplow", "critical";
4422                         #thermal-sensor-cells = <1>;
4423                 };
4424
4425                 aoss_reset: reset-controller@c2a0000 {
4426                         compatible = "qcom,sdm845-aoss-cc";
4427                         reg = <0 0x0c2a0000 0 0x31000>;
4428                         #reset-cells = <1>;
4429                 };
4430
4431                 aoss_qmp: qmp@c300000 {
4432                         compatible = "qcom,sdm845-aoss-qmp";
4433                         reg = <0 0x0c300000 0 0x100000>;
4434                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4435                         mboxes = <&apss_shared 0>;
4436
4437                         #clock-cells = <0>;
4438                         #power-domain-cells = <1>;
4439
4440                         cx_cdev: cx {
4441                                 #cooling-cells = <2>;
4442                         };
4443
4444                         ebi_cdev: ebi {
4445                                 #cooling-cells = <2>;
4446                         };
4447                 };
4448
4449                 spmi_bus: spmi@c440000 {
4450                         compatible = "qcom,spmi-pmic-arb";
4451                         reg = <0 0x0c440000 0 0x1100>,
4452                               <0 0x0c600000 0 0x2000000>,
4453                               <0 0x0e600000 0 0x100000>,
4454                               <0 0x0e700000 0 0xa0000>,
4455                               <0 0x0c40a000 0 0x26000>;
4456                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4457                         interrupt-names = "periph_irq";
4458                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4459                         qcom,ee = <0>;
4460                         qcom,channel = <0>;
4461                         #address-cells = <2>;
4462                         #size-cells = <0>;
4463                         interrupt-controller;
4464                         #interrupt-cells = <4>;
4465                         cell-index = <0>;
4466                 };
4467
4468                 imem@146bf000 {
4469                         compatible = "simple-mfd";
4470                         reg = <0 0x146bf000 0 0x1000>;
4471
4472                         #address-cells = <1>;
4473                         #size-cells = <1>;
4474
4475                         ranges = <0 0 0x146bf000 0x1000>;
4476
4477                         pil-reloc@94c {
4478                                 compatible = "qcom,pil-reloc-info";
4479                                 reg = <0x94c 0xc8>;
4480                         };
4481                 };
4482
4483                 apps_smmu: iommu@15000000 {
4484                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4485                         reg = <0 0x15000000 0 0x80000>;
4486                         #iommu-cells = <2>;
4487                         #global-interrupts = <1>;
4488                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4489                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4490                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4491                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4492                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4493                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4494                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4495                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4496                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4497                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4498                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4499                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4500                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4501                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4502                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4503                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4504                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4505                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4506                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4507                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4508                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4509                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4510                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4511                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4512                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4513                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4514                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4515                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4516                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4517                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4518                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4519                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4520                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4521                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4522                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4523                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4524                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4525                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4526                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4527                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4528                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4529                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4530                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4531                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4532                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4533                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4534                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4535                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4536                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4537                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4538                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4539                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4540                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4541                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4542                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4543                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4544                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4545                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4546                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4547                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4548                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4549                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4550                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4551                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4552                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4553                 };
4554
4555                 lpasscc: clock-controller@17014000 {
4556                         compatible = "qcom,sdm845-lpasscc";
4557                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4558                         reg-names = "cc", "qdsp6ss";
4559                         #clock-cells = <1>;
4560                         status = "disabled";
4561                 };
4562
4563                 gladiator_noc: interconnect@17900000 {
4564                         compatible = "qcom,sdm845-gladiator-noc";
4565                         reg = <0 0x17900000 0 0xd080>;
4566                         #interconnect-cells = <2>;
4567                         qcom,bcm-voters = <&apps_bcm_voter>;
4568                 };
4569
4570                 watchdog@17980000 {
4571                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4572                         reg = <0 0x17980000 0 0x1000>;
4573                         clocks = <&sleep_clk>;
4574                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4575                 };
4576
4577                 apss_shared: mailbox@17990000 {
4578                         compatible = "qcom,sdm845-apss-shared";
4579                         reg = <0 0x17990000 0 0x1000>;
4580                         #mbox-cells = <1>;
4581                 };
4582
4583                 apps_rsc: rsc@179c0000 {
4584                         label = "apps_rsc";
4585                         compatible = "qcom,rpmh-rsc";
4586                         reg = <0 0x179c0000 0 0x10000>,
4587                               <0 0x179d0000 0 0x10000>,
4588                               <0 0x179e0000 0 0x10000>;
4589                         reg-names = "drv-0", "drv-1", "drv-2";
4590                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4591                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4592                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4593                         qcom,tcs-offset = <0xd00>;
4594                         qcom,drv-id = <2>;
4595                         qcom,tcs-config = <ACTIVE_TCS  2>,
4596                                           <SLEEP_TCS   3>,
4597                                           <WAKE_TCS    3>,
4598                                           <CONTROL_TCS 1>;
4599
4600                         apps_bcm_voter: bcm-voter {
4601                                 compatible = "qcom,bcm-voter";
4602                         };
4603
4604                         rpmhcc: clock-controller {
4605                                 compatible = "qcom,sdm845-rpmh-clk";
4606                                 #clock-cells = <1>;
4607                                 clock-names = "xo";
4608                                 clocks = <&xo_board>;
4609                         };
4610
4611                         rpmhpd: power-controller {
4612                                 compatible = "qcom,sdm845-rpmhpd";
4613                                 #power-domain-cells = <1>;
4614                                 operating-points-v2 = <&rpmhpd_opp_table>;
4615
4616                                 rpmhpd_opp_table: opp-table {
4617                                         compatible = "operating-points-v2";
4618
4619                                         rpmhpd_opp_ret: opp1 {
4620                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4621                                         };
4622
4623                                         rpmhpd_opp_min_svs: opp2 {
4624                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4625                                         };
4626
4627                                         rpmhpd_opp_low_svs: opp3 {
4628                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4629                                         };
4630
4631                                         rpmhpd_opp_svs: opp4 {
4632                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4633                                         };
4634
4635                                         rpmhpd_opp_svs_l1: opp5 {
4636                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4637                                         };
4638
4639                                         rpmhpd_opp_nom: opp6 {
4640                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4641                                         };
4642
4643                                         rpmhpd_opp_nom_l1: opp7 {
4644                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4645                                         };
4646
4647                                         rpmhpd_opp_nom_l2: opp8 {
4648                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4649                                         };
4650
4651                                         rpmhpd_opp_turbo: opp9 {
4652                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4653                                         };
4654
4655                                         rpmhpd_opp_turbo_l1: opp10 {
4656                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4657                                         };
4658                                 };
4659                         };
4660                 };
4661
4662                 intc: interrupt-controller@17a00000 {
4663                         compatible = "arm,gic-v3";
4664                         #address-cells = <2>;
4665                         #size-cells = <2>;
4666                         ranges;
4667                         #interrupt-cells = <3>;
4668                         interrupt-controller;
4669                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
4670                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
4671                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4672
4673                         msi-controller@17a40000 {
4674                                 compatible = "arm,gic-v3-its";
4675                                 msi-controller;
4676                                 #msi-cells = <1>;
4677                                 reg = <0 0x17a40000 0 0x20000>;
4678                                 status = "disabled";
4679                         };
4680                 };
4681
4682                 slimbam: dma-controller@17184000 {
4683                         compatible = "qcom,bam-v1.7.0";
4684                         qcom,controlled-remotely;
4685                         reg = <0 0x17184000 0 0x2a000>;
4686                         num-channels  = <31>;
4687                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4688                         #dma-cells = <1>;
4689                         qcom,ee = <1>;
4690                         qcom,num-ees = <2>;
4691                         iommus = <&apps_smmu 0x1806 0x0>;
4692                 };
4693
4694                 timer@17c90000 {
4695                         #address-cells = <2>;
4696                         #size-cells = <2>;
4697                         ranges;
4698                         compatible = "arm,armv7-timer-mem";
4699                         reg = <0 0x17c90000 0 0x1000>;
4700
4701                         frame@17ca0000 {
4702                                 frame-number = <0>;
4703                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4704                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4705                                 reg = <0 0x17ca0000 0 0x1000>,
4706                                       <0 0x17cb0000 0 0x1000>;
4707                         };
4708
4709                         frame@17cc0000 {
4710                                 frame-number = <1>;
4711                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4712                                 reg = <0 0x17cc0000 0 0x1000>;
4713                                 status = "disabled";
4714                         };
4715
4716                         frame@17cd0000 {
4717                                 frame-number = <2>;
4718                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4719                                 reg = <0 0x17cd0000 0 0x1000>;
4720                                 status = "disabled";
4721                         };
4722
4723                         frame@17ce0000 {
4724                                 frame-number = <3>;
4725                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4726                                 reg = <0 0x17ce0000 0 0x1000>;
4727                                 status = "disabled";
4728                         };
4729
4730                         frame@17cf0000 {
4731                                 frame-number = <4>;
4732                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4733                                 reg = <0 0x17cf0000 0 0x1000>;
4734                                 status = "disabled";
4735                         };
4736
4737                         frame@17d00000 {
4738                                 frame-number = <5>;
4739                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4740                                 reg = <0 0x17d00000 0 0x1000>;
4741                                 status = "disabled";
4742                         };
4743
4744                         frame@17d10000 {
4745                                 frame-number = <6>;
4746                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4747                                 reg = <0 0x17d10000 0 0x1000>;
4748                                 status = "disabled";
4749                         };
4750                 };
4751
4752                 osm_l3: interconnect@17d41000 {
4753                         compatible = "qcom,sdm845-osm-l3";
4754                         reg = <0 0x17d41000 0 0x1400>;
4755
4756                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4757                         clock-names = "xo", "alternate";
4758
4759                         #interconnect-cells = <1>;
4760                 };
4761
4762                 cpufreq_hw: cpufreq@17d43000 {
4763                         compatible = "qcom,cpufreq-hw";
4764                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4765                         reg-names = "freq-domain0", "freq-domain1";
4766
4767                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4768                         clock-names = "xo", "alternate";
4769
4770                         #freq-domain-cells = <1>;
4771                 };
4772
4773                 wifi: wifi@18800000 {
4774                         compatible = "qcom,wcn3990-wifi";
4775                         status = "disabled";
4776                         reg = <0 0x18800000 0 0x800000>;
4777                         reg-names = "membase";
4778                         memory-region = <&wlan_msa_mem>;
4779                         clock-names = "cxo_ref_clk_pin";
4780                         clocks = <&rpmhcc RPMH_RF_CLK2>;
4781                         interrupts =
4782                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4783                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4784                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4785                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4786                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4787                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4788                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4789                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4790                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4791                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4792                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4793                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4794                         iommus = <&apps_smmu 0x0040 0x1>;
4795                 };
4796         };
4797
4798         thermal-zones {
4799                 cpu0-thermal {
4800                         polling-delay-passive = <250>;
4801                         polling-delay = <1000>;
4802
4803                         thermal-sensors = <&tsens0 1>;
4804
4805                         trips {
4806                                 cpu0_alert0: trip-point0 {
4807                                         temperature = <90000>;
4808                                         hysteresis = <2000>;
4809                                         type = "passive";
4810                                 };
4811
4812                                 cpu0_alert1: trip-point1 {
4813                                         temperature = <95000>;
4814                                         hysteresis = <2000>;
4815                                         type = "passive";
4816                                 };
4817
4818                                 cpu0_crit: cpu_crit {
4819                                         temperature = <110000>;
4820                                         hysteresis = <1000>;
4821                                         type = "critical";
4822                                 };
4823                         };
4824
4825                         cooling-maps {
4826                                 map0 {
4827                                         trip = <&cpu0_alert0>;
4828                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4829                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4830                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4831                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4832                                 };
4833                                 map1 {
4834                                         trip = <&cpu0_alert1>;
4835                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4836                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4837                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4838                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4839                                 };
4840                         };
4841                 };
4842
4843                 cpu1-thermal {
4844                         polling-delay-passive = <250>;
4845                         polling-delay = <1000>;
4846
4847                         thermal-sensors = <&tsens0 2>;
4848
4849                         trips {
4850                                 cpu1_alert0: trip-point0 {
4851                                         temperature = <90000>;
4852                                         hysteresis = <2000>;
4853                                         type = "passive";
4854                                 };
4855
4856                                 cpu1_alert1: trip-point1 {
4857                                         temperature = <95000>;
4858                                         hysteresis = <2000>;
4859                                         type = "passive";
4860                                 };
4861
4862                                 cpu1_crit: cpu_crit {
4863                                         temperature = <110000>;
4864                                         hysteresis = <1000>;
4865                                         type = "critical";
4866                                 };
4867                         };
4868
4869                         cooling-maps {
4870                                 map0 {
4871                                         trip = <&cpu1_alert0>;
4872                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4873                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4874                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4875                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4876                                 };
4877                                 map1 {
4878                                         trip = <&cpu1_alert1>;
4879                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4880                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4881                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4882                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4883                                 };
4884                         };
4885                 };
4886
4887                 cpu2-thermal {
4888                         polling-delay-passive = <250>;
4889                         polling-delay = <1000>;
4890
4891                         thermal-sensors = <&tsens0 3>;
4892
4893                         trips {
4894                                 cpu2_alert0: trip-point0 {
4895                                         temperature = <90000>;
4896                                         hysteresis = <2000>;
4897                                         type = "passive";
4898                                 };
4899
4900                                 cpu2_alert1: trip-point1 {
4901                                         temperature = <95000>;
4902                                         hysteresis = <2000>;
4903                                         type = "passive";
4904                                 };
4905
4906                                 cpu2_crit: cpu_crit {
4907                                         temperature = <110000>;
4908                                         hysteresis = <1000>;
4909                                         type = "critical";
4910                                 };
4911                         };
4912
4913                         cooling-maps {
4914                                 map0 {
4915                                         trip = <&cpu2_alert0>;
4916                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4917                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4918                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4919                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4920                                 };
4921                                 map1 {
4922                                         trip = <&cpu2_alert1>;
4923                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4924                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4925                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4926                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4927                                 };
4928                         };
4929                 };
4930
4931                 cpu3-thermal {
4932                         polling-delay-passive = <250>;
4933                         polling-delay = <1000>;
4934
4935                         thermal-sensors = <&tsens0 4>;
4936
4937                         trips {
4938                                 cpu3_alert0: trip-point0 {
4939                                         temperature = <90000>;
4940                                         hysteresis = <2000>;
4941                                         type = "passive";
4942                                 };
4943
4944                                 cpu3_alert1: trip-point1 {
4945                                         temperature = <95000>;
4946                                         hysteresis = <2000>;
4947                                         type = "passive";
4948                                 };
4949
4950                                 cpu3_crit: cpu_crit {
4951                                         temperature = <110000>;
4952                                         hysteresis = <1000>;
4953                                         type = "critical";
4954                                 };
4955                         };
4956
4957                         cooling-maps {
4958                                 map0 {
4959                                         trip = <&cpu3_alert0>;
4960                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4961                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4962                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4963                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4964                                 };
4965                                 map1 {
4966                                         trip = <&cpu3_alert1>;
4967                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4968                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4969                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4970                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4971                                 };
4972                         };
4973                 };
4974
4975                 cpu4-thermal {
4976                         polling-delay-passive = <250>;
4977                         polling-delay = <1000>;
4978
4979                         thermal-sensors = <&tsens0 7>;
4980
4981                         trips {
4982                                 cpu4_alert0: trip-point0 {
4983                                         temperature = <90000>;
4984                                         hysteresis = <2000>;
4985                                         type = "passive";
4986                                 };
4987
4988                                 cpu4_alert1: trip-point1 {
4989                                         temperature = <95000>;
4990                                         hysteresis = <2000>;
4991                                         type = "passive";
4992                                 };
4993
4994                                 cpu4_crit: cpu_crit {
4995                                         temperature = <110000>;
4996                                         hysteresis = <1000>;
4997                                         type = "critical";
4998                                 };
4999                         };
5000
5001                         cooling-maps {
5002                                 map0 {
5003                                         trip = <&cpu4_alert0>;
5004                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5005                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5006                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5007                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5008                                 };
5009                                 map1 {
5010                                         trip = <&cpu4_alert1>;
5011                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5012                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5013                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5014                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5015                                 };
5016                         };
5017                 };
5018
5019                 cpu5-thermal {
5020                         polling-delay-passive = <250>;
5021                         polling-delay = <1000>;
5022
5023                         thermal-sensors = <&tsens0 8>;
5024
5025                         trips {
5026                                 cpu5_alert0: trip-point0 {
5027                                         temperature = <90000>;
5028                                         hysteresis = <2000>;
5029                                         type = "passive";
5030                                 };
5031
5032                                 cpu5_alert1: trip-point1 {
5033                                         temperature = <95000>;
5034                                         hysteresis = <2000>;
5035                                         type = "passive";
5036                                 };
5037
5038                                 cpu5_crit: cpu_crit {
5039                                         temperature = <110000>;
5040                                         hysteresis = <1000>;
5041                                         type = "critical";
5042                                 };
5043                         };
5044
5045                         cooling-maps {
5046                                 map0 {
5047                                         trip = <&cpu5_alert0>;
5048                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5049                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5050                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5051                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5052                                 };
5053                                 map1 {
5054                                         trip = <&cpu5_alert1>;
5055                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5056                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5057                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5058                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5059                                 };
5060                         };
5061                 };
5062
5063                 cpu6-thermal {
5064                         polling-delay-passive = <250>;
5065                         polling-delay = <1000>;
5066
5067                         thermal-sensors = <&tsens0 9>;
5068
5069                         trips {
5070                                 cpu6_alert0: trip-point0 {
5071                                         temperature = <90000>;
5072                                         hysteresis = <2000>;
5073                                         type = "passive";
5074                                 };
5075
5076                                 cpu6_alert1: trip-point1 {
5077                                         temperature = <95000>;
5078                                         hysteresis = <2000>;
5079                                         type = "passive";
5080                                 };
5081
5082                                 cpu6_crit: cpu_crit {
5083                                         temperature = <110000>;
5084                                         hysteresis = <1000>;
5085                                         type = "critical";
5086                                 };
5087                         };
5088
5089                         cooling-maps {
5090                                 map0 {
5091                                         trip = <&cpu6_alert0>;
5092                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5093                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5094                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5095                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5096                                 };
5097                                 map1 {
5098                                         trip = <&cpu6_alert1>;
5099                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5100                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5101                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5102                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5103                                 };
5104                         };
5105                 };
5106
5107                 cpu7-thermal {
5108                         polling-delay-passive = <250>;
5109                         polling-delay = <1000>;
5110
5111                         thermal-sensors = <&tsens0 10>;
5112
5113                         trips {
5114                                 cpu7_alert0: trip-point0 {
5115                                         temperature = <90000>;
5116                                         hysteresis = <2000>;
5117                                         type = "passive";
5118                                 };
5119
5120                                 cpu7_alert1: trip-point1 {
5121                                         temperature = <95000>;
5122                                         hysteresis = <2000>;
5123                                         type = "passive";
5124                                 };
5125
5126                                 cpu7_crit: cpu_crit {
5127                                         temperature = <110000>;
5128                                         hysteresis = <1000>;
5129                                         type = "critical";
5130                                 };
5131                         };
5132
5133                         cooling-maps {
5134                                 map0 {
5135                                         trip = <&cpu7_alert0>;
5136                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5137                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5138                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5139                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5140                                 };
5141                                 map1 {
5142                                         trip = <&cpu7_alert1>;
5143                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5144                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5145                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5146                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5147                                 };
5148                         };
5149                 };
5150
5151                 aoss0-thermal {
5152                         polling-delay-passive = <250>;
5153                         polling-delay = <1000>;
5154
5155                         thermal-sensors = <&tsens0 0>;
5156
5157                         trips {
5158                                 aoss0_alert0: trip-point0 {
5159                                         temperature = <90000>;
5160                                         hysteresis = <2000>;
5161                                         type = "hot";
5162                                 };
5163                         };
5164                 };
5165
5166                 cluster0-thermal {
5167                         polling-delay-passive = <250>;
5168                         polling-delay = <1000>;
5169
5170                         thermal-sensors = <&tsens0 5>;
5171
5172                         trips {
5173                                 cluster0_alert0: trip-point0 {
5174                                         temperature = <90000>;
5175                                         hysteresis = <2000>;
5176                                         type = "hot";
5177                                 };
5178                                 cluster0_crit: cluster0_crit {
5179                                         temperature = <110000>;
5180                                         hysteresis = <2000>;
5181                                         type = "critical";
5182                                 };
5183                         };
5184                 };
5185
5186                 cluster1-thermal {
5187                         polling-delay-passive = <250>;
5188                         polling-delay = <1000>;
5189
5190                         thermal-sensors = <&tsens0 6>;
5191
5192                         trips {
5193                                 cluster1_alert0: trip-point0 {
5194                                         temperature = <90000>;
5195                                         hysteresis = <2000>;
5196                                         type = "hot";
5197                                 };
5198                                 cluster1_crit: cluster1_crit {
5199                                         temperature = <110000>;
5200                                         hysteresis = <2000>;
5201                                         type = "critical";
5202                                 };
5203                         };
5204                 };
5205
5206                 gpu-thermal-top {
5207                         polling-delay-passive = <250>;
5208                         polling-delay = <1000>;
5209
5210                         thermal-sensors = <&tsens0 11>;
5211
5212                         trips {
5213                                 gpu1_alert0: trip-point0 {
5214                                         temperature = <90000>;
5215                                         hysteresis = <2000>;
5216                                         type = "hot";
5217                                 };
5218                         };
5219                 };
5220
5221                 gpu-thermal-bottom {
5222                         polling-delay-passive = <250>;
5223                         polling-delay = <1000>;
5224
5225                         thermal-sensors = <&tsens0 12>;
5226
5227                         trips {
5228                                 gpu2_alert0: trip-point0 {
5229                                         temperature = <90000>;
5230                                         hysteresis = <2000>;
5231                                         type = "hot";
5232                                 };
5233                         };
5234                 };
5235
5236                 aoss1-thermal {
5237                         polling-delay-passive = <250>;
5238                         polling-delay = <1000>;
5239
5240                         thermal-sensors = <&tsens1 0>;
5241
5242                         trips {
5243                                 aoss1_alert0: trip-point0 {
5244                                         temperature = <90000>;
5245                                         hysteresis = <2000>;
5246                                         type = "hot";
5247                                 };
5248                         };
5249                 };
5250
5251                 q6-modem-thermal {
5252                         polling-delay-passive = <250>;
5253                         polling-delay = <1000>;
5254
5255                         thermal-sensors = <&tsens1 1>;
5256
5257                         trips {
5258                                 q6_modem_alert0: trip-point0 {
5259                                         temperature = <90000>;
5260                                         hysteresis = <2000>;
5261                                         type = "hot";
5262                                 };
5263                         };
5264                 };
5265
5266                 mem-thermal {
5267                         polling-delay-passive = <250>;
5268                         polling-delay = <1000>;
5269
5270                         thermal-sensors = <&tsens1 2>;
5271
5272                         trips {
5273                                 mem_alert0: trip-point0 {
5274                                         temperature = <90000>;
5275                                         hysteresis = <2000>;
5276                                         type = "hot";
5277                                 };
5278                         };
5279                 };
5280
5281                 wlan-thermal {
5282                         polling-delay-passive = <250>;
5283                         polling-delay = <1000>;
5284
5285                         thermal-sensors = <&tsens1 3>;
5286
5287                         trips {
5288                                 wlan_alert0: trip-point0 {
5289                                         temperature = <90000>;
5290                                         hysteresis = <2000>;
5291                                         type = "hot";
5292                                 };
5293                         };
5294                 };
5295
5296                 q6-hvx-thermal {
5297                         polling-delay-passive = <250>;
5298                         polling-delay = <1000>;
5299
5300                         thermal-sensors = <&tsens1 4>;
5301
5302                         trips {
5303                                 q6_hvx_alert0: trip-point0 {
5304                                         temperature = <90000>;
5305                                         hysteresis = <2000>;
5306                                         type = "hot";
5307                                 };
5308                         };
5309                 };
5310
5311                 camera-thermal {
5312                         polling-delay-passive = <250>;
5313                         polling-delay = <1000>;
5314
5315                         thermal-sensors = <&tsens1 5>;
5316
5317                         trips {
5318                                 camera_alert0: trip-point0 {
5319                                         temperature = <90000>;
5320                                         hysteresis = <2000>;
5321                                         type = "hot";
5322                                 };
5323                         };
5324                 };
5325
5326                 video-thermal {
5327                         polling-delay-passive = <250>;
5328                         polling-delay = <1000>;
5329
5330                         thermal-sensors = <&tsens1 6>;
5331
5332                         trips {
5333                                 video_alert0: trip-point0 {
5334                                         temperature = <90000>;
5335                                         hysteresis = <2000>;
5336                                         type = "hot";
5337                                 };
5338                         };
5339                 };
5340
5341                 modem-thermal {
5342                         polling-delay-passive = <250>;
5343                         polling-delay = <1000>;
5344
5345                         thermal-sensors = <&tsens1 7>;
5346
5347                         trips {
5348                                 modem_alert0: trip-point0 {
5349                                         temperature = <90000>;
5350                                         hysteresis = <2000>;
5351                                         type = "hot";
5352                                 };
5353                         };
5354                 };
5355         };
5356 };