arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sdm845.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,apr.h>
  23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         aliases {
  34                 i2c0 = &i2c0;
  35                 i2c1 = &i2c1;
  36                 i2c2 = &i2c2;
  37                 i2c3 = &i2c3;
  38                 i2c4 = &i2c4;
  39                 i2c5 = &i2c5;
  40                 i2c6 = &i2c6;
  41                 i2c7 = &i2c7;
  42                 i2c8 = &i2c8;
  43                 i2c9 = &i2c9;
  44                 i2c10 = &i2c10;
  45                 i2c11 = &i2c11;
  46                 i2c12 = &i2c12;
  47                 i2c13 = &i2c13;
  48                 i2c14 = &i2c14;
  49                 i2c15 = &i2c15;
  50                 spi0 = &spi0;
  51                 spi1 = &spi1;
  52                 spi2 = &spi2;
  53                 spi3 = &spi3;
  54                 spi4 = &spi4;
  55                 spi5 = &spi5;
  56                 spi6 = &spi6;
  57                 spi7 = &spi7;
  58                 spi8 = &spi8;
  59                 spi9 = &spi9;
  60                 spi10 = &spi10;
  61                 spi11 = &spi11;
  62                 spi12 = &spi12;
  63                 spi13 = &spi13;
  64                 spi14 = &spi14;
  65                 spi15 = &spi15;
  66         };
  67
  68         chosen { };
  69
  70         memory@80000000 {
  71                 device_type = "memory";
  72                 /* We expect the bootloader to fill in the size */
  73                 reg = <0 0x80000000 0 0>;
  74         };
  75
  76         reserved-memory {
  77                 #address-cells = <2>;
  78                 #size-cells = <2>;
  79                 ranges;
  80
  81                 hyp_mem: memory@85700000 {
  82                         reg = <0 0x85700000 0 0x600000>;
  83                         no-map;
  84                 };
  85
  86                 xbl_mem: memory@85e00000 {
  87                         reg = <0 0x85e00000 0 0x100000>;
  88                         no-map;
  89                 };
  90
  91                 aop_mem: memory@85fc0000 {
  92                         reg = <0 0x85fc0000 0 0x20000>;
  93                         no-map;
  94                 };
  95
  96                 aop_cmd_db_mem: memory@85fe0000 {
  97                         compatible = "qcom,cmd-db";
  98                         reg = <0x0 0x85fe0000 0 0x20000>;
  99                         no-map;
 100                 };
 101
 102                 smem_mem: memory@86000000 {
 103                         reg = <0x0 0x86000000 0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 tz_mem: memory@86200000 {
 108                         reg = <0 0x86200000 0 0x2d00000>;
 109                         no-map;
 110                 };
 111
 112                 rmtfs_mem: memory@88f00000 {
 113                         compatible = "qcom,rmtfs-mem";
 114                         reg = <0 0x88f00000 0 0x200000>;
 115                         no-map;
 116
 117                         qcom,client-id = <1>;
 118                         qcom,vmid = <15>;
 119                 };
 120
 121                 qseecom_mem: memory@8ab00000 {
 122                         reg = <0 0x8ab00000 0 0x1400000>;
 123                         no-map;
 124                 };
 125
 126                 camera_mem: memory@8bf00000 {
 127                         reg = <0 0x8bf00000 0 0x500000>;
 128                         no-map;
 129                 };
 130
 131                 ipa_fw_mem: memory@8c400000 {
 132                         reg = <0 0x8c400000 0 0x10000>;
 133                         no-map;
 134                 };
 135
 136                 ipa_gsi_mem: memory@8c410000 {
 137                         reg = <0 0x8c410000 0 0x5000>;
 138                         no-map;
 139                 };
 140
 141                 gpu_mem: memory@8c415000 {
 142                         reg = <0 0x8c415000 0 0x2000>;
 143                         no-map;
 144                 };
 145
 146                 adsp_mem: memory@8c500000 {
 147                         reg = <0 0x8c500000 0 0x1a00000>;
 148                         no-map;
 149                 };
 150
 151                 wlan_msa_mem: memory@8df00000 {
 152                         reg = <0 0x8df00000 0 0x100000>;
 153                         no-map;
 154                 };
 155
 156                 mpss_region: memory@8e000000 {
 157                         reg = <0 0x8e000000 0 0x7800000>;
 158                         no-map;
 159                 };
 160
 161                 venus_mem: memory@95800000 {
 162                         reg = <0 0x95800000 0 0x500000>;
 163                         no-map;
 164                 };
 165
 166                 cdsp_mem: memory@95d00000 {
 167                         reg = <0 0x95d00000 0 0x800000>;
 168                         no-map;
 169                 };
 170
 171                 mba_region: memory@96500000 {
 172                         reg = <0 0x96500000 0 0x200000>;
 173                         no-map;
 174                 };
 175
 176                 slpi_mem: memory@96700000 {
 177                         reg = <0 0x96700000 0 0x1400000>;
 178                         no-map;
 179                 };
 180
 181                 spss_mem: memory@97b00000 {
 182                         reg = <0 0x97b00000 0 0x100000>;
 183                         no-map;
 184                 };
 185         };
 186
 187         cpus {
 188                 #address-cells = <2>;
 189                 #size-cells = <0>;
 190
 191                 CPU0: cpu@0 {
 192                         device_type = "cpu";
 193                         compatible = "qcom,kryo385";
 194                         reg = <0x0 0x0>;
 195                         enable-method = "psci";
 196                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 197                                            &LITTLE_CPU_SLEEP_1
 198                                            &CLUSTER_SLEEP_0>;
 199                         capacity-dmips-mhz = <607>;
 200                         dynamic-power-coefficient = <100>;
 201                         qcom,freq-domain = <&cpufreq_hw 0>;
 202                         operating-points-v2 = <&cpu0_opp_table>;
 203                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 204                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 205                         #cooling-cells = <2>;
 206                         next-level-cache = <&L2_0>;
 207                         L2_0: l2-cache {
 208                                 compatible = "cache";
 209                                 next-level-cache = <&L3_0>;
 210                                 L3_0: l3-cache {
 211                                       compatible = "cache";
 212                                 };
 213                         };
 214                 };
 215
 216                 CPU1: cpu@100 {
 217                         device_type = "cpu";
 218                         compatible = "qcom,kryo385";
 219                         reg = <0x0 0x100>;
 220                         enable-method = "psci";
 221                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 222                                            &LITTLE_CPU_SLEEP_1
 223                                            &CLUSTER_SLEEP_0>;
 224                         capacity-dmips-mhz = <607>;
 225                         dynamic-power-coefficient = <100>;
 226                         qcom,freq-domain = <&cpufreq_hw 0>;
 227                         operating-points-v2 = <&cpu0_opp_table>;
 228                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 229                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 230                         #cooling-cells = <2>;
 231                         next-level-cache = <&L2_100>;
 232                         L2_100: l2-cache {
 233                                 compatible = "cache";
 234                                 next-level-cache = <&L3_0>;
 235                         };
 236                 };
 237
 238                 CPU2: cpu@200 {
 239                         device_type = "cpu";
 240                         compatible = "qcom,kryo385";
 241                         reg = <0x0 0x200>;
 242                         enable-method = "psci";
 243                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 244                                            &LITTLE_CPU_SLEEP_1
 245                                            &CLUSTER_SLEEP_0>;
 246                         capacity-dmips-mhz = <607>;
 247                         dynamic-power-coefficient = <100>;
 248                         qcom,freq-domain = <&cpufreq_hw 0>;
 249                         operating-points-v2 = <&cpu0_opp_table>;
 250                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 251                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 252                         #cooling-cells = <2>;
 253                         next-level-cache = <&L2_200>;
 254                         L2_200: l2-cache {
 255                                 compatible = "cache";
 256                                 next-level-cache = <&L3_0>;
 257                         };
 258                 };
 259
 260                 CPU3: cpu@300 {
 261                         device_type = "cpu";
 262                         compatible = "qcom,kryo385";
 263                         reg = <0x0 0x300>;
 264                         enable-method = "psci";
 265                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 266                                            &LITTLE_CPU_SLEEP_1
 267                                            &CLUSTER_SLEEP_0>;
 268                         capacity-dmips-mhz = <607>;
 269                         dynamic-power-coefficient = <100>;
 270                         qcom,freq-domain = <&cpufreq_hw 0>;
 271                         operating-points-v2 = <&cpu0_opp_table>;
 272                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 273                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 274                         #cooling-cells = <2>;
 275                         next-level-cache = <&L2_300>;
 276                         L2_300: l2-cache {
 277                                 compatible = "cache";
 278                                 next-level-cache = <&L3_0>;
 279                         };
 280                 };
 281
 282                 CPU4: cpu@400 {
 283                         device_type = "cpu";
 284                         compatible = "qcom,kryo385";
 285                         reg = <0x0 0x400>;
 286                         enable-method = "psci";
 287                         capacity-dmips-mhz = <1024>;
 288                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 289                                            &BIG_CPU_SLEEP_1
 290                                            &CLUSTER_SLEEP_0>;
 291                         dynamic-power-coefficient = <396>;
 292                         qcom,freq-domain = <&cpufreq_hw 1>;
 293                         operating-points-v2 = <&cpu4_opp_table>;
 294                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 295                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 296                         #cooling-cells = <2>;
 297                         next-level-cache = <&L2_400>;
 298                         L2_400: l2-cache {
 299                                 compatible = "cache";
 300                                 next-level-cache = <&L3_0>;
 301                         };
 302                 };
 303
 304                 CPU5: cpu@500 {
 305                         device_type = "cpu";
 306                         compatible = "qcom,kryo385";
 307                         reg = <0x0 0x500>;
 308                         enable-method = "psci";
 309                         capacity-dmips-mhz = <1024>;
 310                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 311                                            &BIG_CPU_SLEEP_1
 312                                            &CLUSTER_SLEEP_0>;
 313                         dynamic-power-coefficient = <396>;
 314                         qcom,freq-domain = <&cpufreq_hw 1>;
 315                         operating-points-v2 = <&cpu4_opp_table>;
 316                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 317                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 318                         #cooling-cells = <2>;
 319                         next-level-cache = <&L2_500>;
 320                         L2_500: l2-cache {
 321                                 compatible = "cache";
 322                                 next-level-cache = <&L3_0>;
 323                         };
 324                 };
 325
 326                 CPU6: cpu@600 {
 327                         device_type = "cpu";
 328                         compatible = "qcom,kryo385";
 329                         reg = <0x0 0x600>;
 330                         enable-method = "psci";
 331                         capacity-dmips-mhz = <1024>;
 332                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 333                                            &BIG_CPU_SLEEP_1
 334                                            &CLUSTER_SLEEP_0>;
 335                         dynamic-power-coefficient = <396>;
 336                         qcom,freq-domain = <&cpufreq_hw 1>;
 337                         operating-points-v2 = <&cpu4_opp_table>;
 338                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 339                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 340                         #cooling-cells = <2>;
 341                         next-level-cache = <&L2_600>;
 342                         L2_600: l2-cache {
 343                                 compatible = "cache";
 344                                 next-level-cache = <&L3_0>;
 345                         };
 346                 };
 347
 348                 CPU7: cpu@700 {
 349                         device_type = "cpu";
 350                         compatible = "qcom,kryo385";
 351                         reg = <0x0 0x700>;
 352                         enable-method = "psci";
 353                         capacity-dmips-mhz = <1024>;
 354                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 355                                            &BIG_CPU_SLEEP_1
 356                                            &CLUSTER_SLEEP_0>;
 357                         dynamic-power-coefficient = <396>;
 358                         qcom,freq-domain = <&cpufreq_hw 1>;
 359                         operating-points-v2 = <&cpu4_opp_table>;
 360                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 361                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 362                         #cooling-cells = <2>;
 363                         next-level-cache = <&L2_700>;
 364                         L2_700: l2-cache {
 365                                 compatible = "cache";
 366                                 next-level-cache = <&L3_0>;
 367                         };
 368                 };
 369
 370                 cpu-map {
 371                         cluster0 {
 372                                 core0 {
 373                                         cpu = <&CPU0>;
 374                                 };
 375
 376                                 core1 {
 377                                         cpu = <&CPU1>;
 378                                 };
 379
 380                                 core2 {
 381                                         cpu = <&CPU2>;
 382                                 };
 383
 384                                 core3 {
 385                                         cpu = <&CPU3>;
 386                                 };
 387
 388                                 core4 {
 389                                         cpu = <&CPU4>;
 390                                 };
 391
 392                                 core5 {
 393                                         cpu = <&CPU5>;
 394                                 };
 395
 396                                 core6 {
 397                                         cpu = <&CPU6>;
 398                                 };
 399
 400                                 core7 {
 401                                         cpu = <&CPU7>;
 402                                 };
 403                         };
 404                 };
 405
 406                 idle-states {
 407                         entry-method = "psci";
 408
 409                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 410                                 compatible = "arm,idle-state";
 411                                 idle-state-name = "little-power-down";
 412                                 arm,psci-suspend-param = <0x40000003>;
 413                                 entry-latency-us = <350>;
 414                                 exit-latency-us = <461>;
 415                                 min-residency-us = <1890>;
 416                                 local-timer-stop;
 417                         };
 418
 419                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 420                                 compatible = "arm,idle-state";
 421                                 idle-state-name = "little-rail-power-down";
 422                                 arm,psci-suspend-param = <0x40000004>;
 423                                 entry-latency-us = <360>;
 424                                 exit-latency-us = <531>;
 425                                 min-residency-us = <3934>;
 426                                 local-timer-stop;
 427                         };
 428
 429                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 430                                 compatible = "arm,idle-state";
 431                                 idle-state-name = "big-power-down";
 432                                 arm,psci-suspend-param = <0x40000003>;
 433                                 entry-latency-us = <264>;
 434                                 exit-latency-us = <621>;
 435                                 min-residency-us = <952>;
 436                                 local-timer-stop;
 437                         };
 438
 439                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 440                                 compatible = "arm,idle-state";
 441                                 idle-state-name = "big-rail-power-down";
 442                                 arm,psci-suspend-param = <0x40000004>;
 443                                 entry-latency-us = <702>;
 444                                 exit-latency-us = <1061>;
 445                                 min-residency-us = <4488>;
 446                                 local-timer-stop;
 447                         };
 448
 449                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 450                                 compatible = "arm,idle-state";
 451                                 idle-state-name = "cluster-power-down";
 452                                 arm,psci-suspend-param = <0x400000F4>;
 453                                 entry-latency-us = <3263>;
 454                                 exit-latency-us = <6562>;
 455                                 min-residency-us = <9987>;
 456                                 local-timer-stop;
 457                         };
 458                 };
 459         };
 460
 461         cpu0_opp_table: cpu0_opp_table {
 462                 compatible = "operating-points-v2";
 463                 opp-shared;
 464
 465                 cpu0_opp1: opp-300000000 {
 466                         opp-hz = /bits/ 64 <300000000>;
 467                         opp-peak-kBps = <800000 4800000>;
 468                 };
 469
 470                 cpu0_opp2: opp-403200000 {
 471                         opp-hz = /bits/ 64 <403200000>;
 472                         opp-peak-kBps = <800000 4800000>;
 473                 };
 474
 475                 cpu0_opp3: opp-480000000 {
 476                         opp-hz = /bits/ 64 <480000000>;
 477                         opp-peak-kBps = <800000 6451200>;
 478                 };
 479
 480                 cpu0_opp4: opp-576000000 {
 481                         opp-hz = /bits/ 64 <576000000>;
 482                         opp-peak-kBps = <800000 6451200>;
 483                 };
 484
 485                 cpu0_opp5: opp-652800000 {
 486                         opp-hz = /bits/ 64 <652800000>;
 487                         opp-peak-kBps = <800000 7680000>;
 488                 };
 489
 490                 cpu0_opp6: opp-748800000 {
 491                         opp-hz = /bits/ 64 <748800000>;
 492                         opp-peak-kBps = <1804000 9216000>;
 493                 };
 494
 495                 cpu0_opp7: opp-825600000 {
 496                         opp-hz = /bits/ 64 <825600000>;
 497                         opp-peak-kBps = <1804000 9216000>;
 498                 };
 499
 500                 cpu0_opp8: opp-902400000 {
 501                         opp-hz = /bits/ 64 <902400000>;
 502                         opp-peak-kBps = <1804000 10444800>;
 503                 };
 504
 505                 cpu0_opp9: opp-979200000 {
 506                         opp-hz = /bits/ 64 <979200000>;
 507                         opp-peak-kBps = <1804000 11980800>;
 508                 };
 509
 510                 cpu0_opp10: opp-1056000000 {
 511                         opp-hz = /bits/ 64 <1056000000>;
 512                         opp-peak-kBps = <1804000 11980800>;
 513                 };
 514
 515                 cpu0_opp11: opp-1132800000 {
 516                         opp-hz = /bits/ 64 <1132800000>;
 517                         opp-peak-kBps = <2188000 13516800>;
 518                 };
 519
 520                 cpu0_opp12: opp-1228800000 {
 521                         opp-hz = /bits/ 64 <1228800000>;
 522                         opp-peak-kBps = <2188000 15052800>;
 523                 };
 524
 525                 cpu0_opp13: opp-1324800000 {
 526                         opp-hz = /bits/ 64 <1324800000>;
 527                         opp-peak-kBps = <2188000 16588800>;
 528                 };
 529
 530                 cpu0_opp14: opp-1420800000 {
 531                         opp-hz = /bits/ 64 <1420800000>;
 532                         opp-peak-kBps = <3072000 18124800>;
 533                 };
 534
 535                 cpu0_opp15: opp-1516800000 {
 536                         opp-hz = /bits/ 64 <1516800000>;
 537                         opp-peak-kBps = <3072000 19353600>;
 538                 };
 539
 540                 cpu0_opp16: opp-1612800000 {
 541                         opp-hz = /bits/ 64 <1612800000>;
 542                         opp-peak-kBps = <4068000 19353600>;
 543                 };
 544
 545                 cpu0_opp17: opp-1689600000 {
 546                         opp-hz = /bits/ 64 <1689600000>;
 547                         opp-peak-kBps = <4068000 20889600>;
 548                 };
 549
 550                 cpu0_opp18: opp-1766400000 {
 551                         opp-hz = /bits/ 64 <1766400000>;
 552                         opp-peak-kBps = <4068000 22425600>;
 553                 };
 554         };
 555
 556         cpu4_opp_table: cpu4_opp_table {
 557                 compatible = "operating-points-v2";
 558                 opp-shared;
 559
 560                 cpu4_opp1: opp-300000000 {
 561                         opp-hz = /bits/ 64 <300000000>;
 562                         opp-peak-kBps = <800000 4800000>;
 563                 };
 564
 565                 cpu4_opp2: opp-403200000 {
 566                         opp-hz = /bits/ 64 <403200000>;
 567                         opp-peak-kBps = <800000 4800000>;
 568                 };
 569
 570                 cpu4_opp3: opp-480000000 {
 571                         opp-hz = /bits/ 64 <480000000>;
 572                         opp-peak-kBps = <1804000 4800000>;
 573                 };
 574
 575                 cpu4_opp4: opp-576000000 {
 576                         opp-hz = /bits/ 64 <576000000>;
 577                         opp-peak-kBps = <1804000 4800000>;
 578                 };
 579
 580                 cpu4_opp5: opp-652800000 {
 581                         opp-hz = /bits/ 64 <652800000>;
 582                         opp-peak-kBps = <1804000 4800000>;
 583                 };
 584
 585                 cpu4_opp6: opp-748800000 {
 586                         opp-hz = /bits/ 64 <748800000>;
 587                         opp-peak-kBps = <1804000 4800000>;
 588                 };
 589
 590                 cpu4_opp7: opp-825600000 {
 591                         opp-hz = /bits/ 64 <825600000>;
 592                         opp-peak-kBps = <2188000 9216000>;
 593                 };
 594
 595                 cpu4_opp8: opp-902400000 {
 596                         opp-hz = /bits/ 64 <902400000>;
 597                         opp-peak-kBps = <2188000 9216000>;
 598                 };
 599
 600                 cpu4_opp9: opp-979200000 {
 601                         opp-hz = /bits/ 64 <979200000>;
 602                         opp-peak-kBps = <2188000 9216000>;
 603                 };
 604
 605                 cpu4_opp10: opp-1056000000 {
 606                         opp-hz = /bits/ 64 <1056000000>;
 607                         opp-peak-kBps = <3072000 9216000>;
 608                 };
 609
 610                 cpu4_opp11: opp-1132800000 {
 611                         opp-hz = /bits/ 64 <1132800000>;
 612                         opp-peak-kBps = <3072000 11980800>;
 613                 };
 614
 615                 cpu4_opp12: opp-1209600000 {
 616                         opp-hz = /bits/ 64 <1209600000>;
 617                         opp-peak-kBps = <4068000 11980800>;
 618                 };
 619
 620                 cpu4_opp13: opp-1286400000 {
 621                         opp-hz = /bits/ 64 <1286400000>;
 622                         opp-peak-kBps = <4068000 11980800>;
 623                 };
 624
 625                 cpu4_opp14: opp-1363200000 {
 626                         opp-hz = /bits/ 64 <1363200000>;
 627                         opp-peak-kBps = <4068000 15052800>;
 628                 };
 629
 630                 cpu4_opp15: opp-1459200000 {
 631                         opp-hz = /bits/ 64 <1459200000>;
 632                         opp-peak-kBps = <4068000 15052800>;
 633                 };
 634
 635                 cpu4_opp16: opp-1536000000 {
 636                         opp-hz = /bits/ 64 <1536000000>;
 637                         opp-peak-kBps = <5412000 15052800>;
 638                 };
 639
 640                 cpu4_opp17: opp-1612800000 {
 641                         opp-hz = /bits/ 64 <1612800000>;
 642                         opp-peak-kBps = <5412000 15052800>;
 643                 };
 644
 645                 cpu4_opp18: opp-1689600000 {
 646                         opp-hz = /bits/ 64 <1689600000>;
 647                         opp-peak-kBps = <5412000 19353600>;
 648                 };
 649
 650                 cpu4_opp19: opp-1766400000 {
 651                         opp-hz = /bits/ 64 <1766400000>;
 652                         opp-peak-kBps = <6220000 19353600>;
 653                 };
 654
 655                 cpu4_opp20: opp-1843200000 {
 656                         opp-hz = /bits/ 64 <1843200000>;
 657                         opp-peak-kBps = <6220000 19353600>;
 658                 };
 659
 660                 cpu4_opp21: opp-1920000000 {
 661                         opp-hz = /bits/ 64 <1920000000>;
 662                         opp-peak-kBps = <7216000 19353600>;
 663                 };
 664
 665                 cpu4_opp22: opp-1996800000 {
 666                         opp-hz = /bits/ 64 <1996800000>;
 667                         opp-peak-kBps = <7216000 20889600>;
 668                 };
 669
 670                 cpu4_opp23: opp-2092800000 {
 671                         opp-hz = /bits/ 64 <2092800000>;
 672                         opp-peak-kBps = <7216000 20889600>;
 673                 };
 674
 675                 cpu4_opp24: opp-2169600000 {
 676                         opp-hz = /bits/ 64 <2169600000>;
 677                         opp-peak-kBps = <7216000 20889600>;
 678                 };
 679
 680                 cpu4_opp25: opp-2246400000 {
 681                         opp-hz = /bits/ 64 <2246400000>;
 682                         opp-peak-kBps = <7216000 20889600>;
 683                 };
 684
 685                 cpu4_opp26: opp-2323200000 {
 686                         opp-hz = /bits/ 64 <2323200000>;
 687                         opp-peak-kBps = <7216000 20889600>;
 688                 };
 689
 690                 cpu4_opp27: opp-2400000000 {
 691                         opp-hz = /bits/ 64 <2400000000>;
 692                         opp-peak-kBps = <7216000 22425600>;
 693                 };
 694
 695                 cpu4_opp28: opp-2476800000 {
 696                         opp-hz = /bits/ 64 <2476800000>;
 697                         opp-peak-kBps = <7216000 22425600>;
 698                 };
 699
 700                 cpu4_opp29: opp-2553600000 {
 701                         opp-hz = /bits/ 64 <2553600000>;
 702                         opp-peak-kBps = <7216000 22425600>;
 703                 };
 704
 705                 cpu4_opp30: opp-2649600000 {
 706                         opp-hz = /bits/ 64 <2649600000>;
 707                         opp-peak-kBps = <7216000 22425600>;
 708                 };
 709
 710                 cpu4_opp31: opp-2745600000 {
 711                         opp-hz = /bits/ 64 <2745600000>;
 712                         opp-peak-kBps = <7216000 25497600>;
 713                 };
 714
 715                 cpu4_opp32: opp-2803200000 {
 716                         opp-hz = /bits/ 64 <2803200000>;
 717                         opp-peak-kBps = <7216000 25497600>;
 718                 };
 719         };
 720
 721         pmu {
 722                 compatible = "arm,armv8-pmuv3";
 723                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 724         };
 725
 726         timer {
 727                 compatible = "arm,armv8-timer";
 728                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 729                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 730                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 731                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 732         };
 733
 734         clocks {
 735                 xo_board: xo-board {
 736                         compatible = "fixed-clock";
 737                         #clock-cells = <0>;
 738                         clock-frequency = <38400000>;
 739                         clock-output-names = "xo_board";
 740                 };
 741
 742                 sleep_clk: sleep-clk {
 743                         compatible = "fixed-clock";
 744                         #clock-cells = <0>;
 745                         clock-frequency = <32764>;
 746                 };
 747         };
 748
 749         firmware {
 750                 scm {
 751                         compatible = "qcom,scm-sdm845", "qcom,scm";
 752                 };
 753         };
 754
 755         adsp_pas: remoteproc-adsp {
 756                 compatible = "qcom,sdm845-adsp-pas";
 757
 758                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 759                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 760                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 761                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 762                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 763                 interrupt-names = "wdog", "fatal", "ready",
 764                                   "handover", "stop-ack";
 765
 766                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 767                 clock-names = "xo";
 768
 769                 memory-region = <&adsp_mem>;
 770
 771                 qcom,smem-states = <&adsp_smp2p_out 0>;
 772                 qcom,smem-state-names = "stop";
 773
 774                 status = "disabled";
 775
 776                 glink-edge {
 777                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 778                         label = "lpass";
 779                         qcom,remote-pid = <2>;
 780                         mboxes = <&apss_shared 8>;
 781
 782                         apr {
 783                                 compatible = "qcom,apr-v2";
 784                                 qcom,glink-channels = "apr_audio_svc";
 785                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
 786                                 #address-cells = <1>;
 787                                 #size-cells = <0>;
 788                                 qcom,intents = <512 20>;
 789
 790                                 apr-service@3 {
 791                                         reg = <APR_SVC_ADSP_CORE>;
 792                                         compatible = "qcom,q6core";
 793                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 794                                 };
 795
 796                                 q6afe: apr-service@4 {
 797                                         compatible = "qcom,q6afe";
 798                                         reg = <APR_SVC_AFE>;
 799                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 800                                         q6afedai: dais {
 801                                                 compatible = "qcom,q6afe-dais";
 802                                                 #address-cells = <1>;
 803                                                 #size-cells = <0>;
 804                                                 #sound-dai-cells = <1>;
 805                                         };
 806                                 };
 807
 808                                 q6asm: apr-service@7 {
 809                                         compatible = "qcom,q6asm";
 810                                         reg = <APR_SVC_ASM>;
 811                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 812                                         q6asmdai: dais {
 813                                                 compatible = "qcom,q6asm-dais";
 814                                                 #address-cells = <1>;
 815                                                 #size-cells = <0>;
 816                                                 #sound-dai-cells = <1>;
 817                                                 iommus = <&apps_smmu 0x1821 0x0>;
 818                                         };
 819                                 };
 820
 821                                 q6adm: apr-service@8 {
 822                                         compatible = "qcom,q6adm";
 823                                         reg = <APR_SVC_ADM>;
 824                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 825                                         q6routing: routing {
 826                                                 compatible = "qcom,q6adm-routing";
 827                                                 #sound-dai-cells = <0>;
 828                                         };
 829                                 };
 830                         };
 831
 832                         fastrpc {
 833                                 compatible = "qcom,fastrpc";
 834                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 835                                 label = "adsp";
 836                                 #address-cells = <1>;
 837                                 #size-cells = <0>;
 838
 839                                 compute-cb@3 {
 840                                         compatible = "qcom,fastrpc-compute-cb";
 841                                         reg = <3>;
 842                                         iommus = <&apps_smmu 0x1823 0x0>;
 843                                 };
 844
 845                                 compute-cb@4 {
 846                                         compatible = "qcom,fastrpc-compute-cb";
 847                                         reg = <4>;
 848                                         iommus = <&apps_smmu 0x1824 0x0>;
 849                                 };
 850                         };
 851                 };
 852         };
 853
 854         cdsp_pas: remoteproc-cdsp {
 855                 compatible = "qcom,sdm845-cdsp-pas";
 856
 857                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 858                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 859                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 860                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 861                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 862                 interrupt-names = "wdog", "fatal", "ready",
 863                                   "handover", "stop-ack";
 864
 865                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 866                 clock-names = "xo";
 867
 868                 memory-region = <&cdsp_mem>;
 869
 870                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 871                 qcom,smem-state-names = "stop";
 872
 873                 status = "disabled";
 874
 875                 glink-edge {
 876                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 877                         label = "turing";
 878                         qcom,remote-pid = <5>;
 879                         mboxes = <&apss_shared 4>;
 880                         fastrpc {
 881                                 compatible = "qcom,fastrpc";
 882                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 883                                 label = "cdsp";
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886
 887                                 compute-cb@1 {
 888                                         compatible = "qcom,fastrpc-compute-cb";
 889                                         reg = <1>;
 890                                         iommus = <&apps_smmu 0x1401 0x30>;
 891                                 };
 892
 893                                 compute-cb@2 {
 894                                         compatible = "qcom,fastrpc-compute-cb";
 895                                         reg = <2>;
 896                                         iommus = <&apps_smmu 0x1402 0x30>;
 897                                 };
 898
 899                                 compute-cb@3 {
 900                                         compatible = "qcom,fastrpc-compute-cb";
 901                                         reg = <3>;
 902                                         iommus = <&apps_smmu 0x1403 0x30>;
 903                                 };
 904
 905                                 compute-cb@4 {
 906                                         compatible = "qcom,fastrpc-compute-cb";
 907                                         reg = <4>;
 908                                         iommus = <&apps_smmu 0x1404 0x30>;
 909                                 };
 910
 911                                 compute-cb@5 {
 912                                         compatible = "qcom,fastrpc-compute-cb";
 913                                         reg = <5>;
 914                                         iommus = <&apps_smmu 0x1405 0x30>;
 915                                 };
 916
 917                                 compute-cb@6 {
 918                                         compatible = "qcom,fastrpc-compute-cb";
 919                                         reg = <6>;
 920                                         iommus = <&apps_smmu 0x1406 0x30>;
 921                                 };
 922
 923                                 compute-cb@7 {
 924                                         compatible = "qcom,fastrpc-compute-cb";
 925                                         reg = <7>;
 926                                         iommus = <&apps_smmu 0x1407 0x30>;
 927                                 };
 928
 929                                 compute-cb@8 {
 930                                         compatible = "qcom,fastrpc-compute-cb";
 931                                         reg = <8>;
 932                                         iommus = <&apps_smmu 0x1408 0x30>;
 933                                 };
 934                         };
 935                 };
 936         };
 937
 938         tcsr_mutex: hwlock {
 939                 compatible = "qcom,tcsr-mutex";
 940                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 941                 #hwlock-cells = <1>;
 942         };
 943
 944         smem {
 945                 compatible = "qcom,smem";
 946                 memory-region = <&smem_mem>;
 947                 hwlocks = <&tcsr_mutex 3>;
 948         };
 949
 950         smp2p-cdsp {
 951                 compatible = "qcom,smp2p";
 952                 qcom,smem = <94>, <432>;
 953
 954                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 955
 956                 mboxes = <&apss_shared 6>;
 957
 958                 qcom,local-pid = <0>;
 959                 qcom,remote-pid = <5>;
 960
 961                 cdsp_smp2p_out: master-kernel {
 962                         qcom,entry-name = "master-kernel";
 963                         #qcom,smem-state-cells = <1>;
 964                 };
 965
 966                 cdsp_smp2p_in: slave-kernel {
 967                         qcom,entry-name = "slave-kernel";
 968
 969                         interrupt-controller;
 970                         #interrupt-cells = <2>;
 971                 };
 972         };
 973
 974         smp2p-lpass {
 975                 compatible = "qcom,smp2p";
 976                 qcom,smem = <443>, <429>;
 977
 978                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 979
 980                 mboxes = <&apss_shared 10>;
 981
 982                 qcom,local-pid = <0>;
 983                 qcom,remote-pid = <2>;
 984
 985                 adsp_smp2p_out: master-kernel {
 986                         qcom,entry-name = "master-kernel";
 987                         #qcom,smem-state-cells = <1>;
 988                 };
 989
 990                 adsp_smp2p_in: slave-kernel {
 991                         qcom,entry-name = "slave-kernel";
 992
 993                         interrupt-controller;
 994                         #interrupt-cells = <2>;
 995                 };
 996         };
 997
 998         smp2p-mpss {
 999                 compatible = "qcom,smp2p";
1000                 qcom,smem = <435>, <428>;
1001                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1002                 mboxes = <&apss_shared 14>;
1003                 qcom,local-pid = <0>;
1004                 qcom,remote-pid = <1>;
1005
1006                 modem_smp2p_out: master-kernel {
1007                         qcom,entry-name = "master-kernel";
1008                         #qcom,smem-state-cells = <1>;
1009                 };
1010
1011                 modem_smp2p_in: slave-kernel {
1012                         qcom,entry-name = "slave-kernel";
1013                         interrupt-controller;
1014                         #interrupt-cells = <2>;
1015                 };
1016
1017                 ipa_smp2p_out: ipa-ap-to-modem {
1018                         qcom,entry-name = "ipa";
1019                         #qcom,smem-state-cells = <1>;
1020                 };
1021
1022                 ipa_smp2p_in: ipa-modem-to-ap {
1023                         qcom,entry-name = "ipa";
1024                         interrupt-controller;
1025                         #interrupt-cells = <2>;
1026                 };
1027         };
1028
1029         smp2p-slpi {
1030                 compatible = "qcom,smp2p";
1031                 qcom,smem = <481>, <430>;
1032                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1033                 mboxes = <&apss_shared 26>;
1034                 qcom,local-pid = <0>;
1035                 qcom,remote-pid = <3>;
1036
1037                 slpi_smp2p_out: master-kernel {
1038                         qcom,entry-name = "master-kernel";
1039                         #qcom,smem-state-cells = <1>;
1040                 };
1041
1042                 slpi_smp2p_in: slave-kernel {
1043                         qcom,entry-name = "slave-kernel";
1044                         interrupt-controller;
1045                         #interrupt-cells = <2>;
1046                 };
1047         };
1048
1049         psci {
1050                 compatible = "arm,psci-1.0";
1051                 method = "smc";
1052         };
1053
1054         soc: soc@0 {
1055                 #address-cells = <2>;
1056                 #size-cells = <2>;
1057                 ranges = <0 0 0 0 0x10 0>;
1058                 dma-ranges = <0 0 0 0 0x10 0>;
1059                 compatible = "simple-bus";
1060
1061                 gcc: clock-controller@100000 {
1062                         compatible = "qcom,gcc-sdm845";
1063                         reg = <0 0x00100000 0 0x1f0000>;
1064                         #clock-cells = <1>;
1065                         #reset-cells = <1>;
1066                         #power-domain-cells = <1>;
1067                 };
1068
1069                 qfprom@784000 {
1070                         compatible = "qcom,qfprom";
1071                         reg = <0 0x00784000 0 0x8ff>;
1072                         #address-cells = <1>;
1073                         #size-cells = <1>;
1074
1075                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1076                                 reg = <0x1eb 0x1>;
1077                                 bits = <1 4>;
1078                         };
1079
1080                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1081                                 reg = <0x1eb 0x2>;
1082                                 bits = <6 4>;
1083                         };
1084                 };
1085
1086                 rng: rng@793000 {
1087                         compatible = "qcom,prng-ee";
1088                         reg = <0 0x00793000 0 0x1000>;
1089                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1090                         clock-names = "core";
1091                 };
1092
1093                 qup_opp_table: qup-opp-table {
1094                         compatible = "operating-points-v2";
1095
1096                         opp-50000000 {
1097                                 opp-hz = /bits/ 64 <50000000>;
1098                                 required-opps = <&rpmhpd_opp_min_svs>;
1099                         };
1100
1101                         opp-75000000 {
1102                                 opp-hz = /bits/ 64 <75000000>;
1103                                 required-opps = <&rpmhpd_opp_low_svs>;
1104                         };
1105
1106                         opp-100000000 {
1107                                 opp-hz = /bits/ 64 <100000000>;
1108                                 required-opps = <&rpmhpd_opp_svs>;
1109                         };
1110
1111                         opp-128000000 {
1112                                 opp-hz = /bits/ 64 <128000000>;
1113                                 required-opps = <&rpmhpd_opp_nom>;
1114                         };
1115                 };
1116
1117                 qupv3_id_0: geniqup@8c0000 {
1118                         compatible = "qcom,geni-se-qup";
1119                         reg = <0 0x008c0000 0 0x6000>;
1120                         clock-names = "m-ahb", "s-ahb";
1121                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1122                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1123                         iommus = <&apps_smmu 0x3 0x0>;
1124                         #address-cells = <2>;
1125                         #size-cells = <2>;
1126                         ranges;
1127                         status = "disabled";
1128
1129                         i2c0: i2c@880000 {
1130                                 compatible = "qcom,geni-i2c";
1131                                 reg = <0 0x00880000 0 0x4000>;
1132                                 clock-names = "se";
1133                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1134                                 pinctrl-names = "default";
1135                                 pinctrl-0 = <&qup_i2c0_default>;
1136                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1137                                 #address-cells = <1>;
1138                                 #size-cells = <0>;
1139                                 power-domains = <&rpmhpd SDM845_CX>;
1140                                 operating-points-v2 = <&qup_opp_table>;
1141                                 status = "disabled";
1142                         };
1143
1144                         spi0: spi@880000 {
1145                                 compatible = "qcom,geni-spi";
1146                                 reg = <0 0x00880000 0 0x4000>;
1147                                 clock-names = "se";
1148                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1149                                 pinctrl-names = "default";
1150                                 pinctrl-0 = <&qup_spi0_default>;
1151                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1152                                 #address-cells = <1>;
1153                                 #size-cells = <0>;
1154                                 status = "disabled";
1155                         };
1156
1157                         uart0: serial@880000 {
1158                                 compatible = "qcom,geni-uart";
1159                                 reg = <0 0x00880000 0 0x4000>;
1160                                 clock-names = "se";
1161                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1162                                 pinctrl-names = "default";
1163                                 pinctrl-0 = <&qup_uart0_default>;
1164                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1165                                 power-domains = <&rpmhpd SDM845_CX>;
1166                                 operating-points-v2 = <&qup_opp_table>;
1167                                 status = "disabled";
1168                         };
1169
1170                         i2c1: i2c@884000 {
1171                                 compatible = "qcom,geni-i2c";
1172                                 reg = <0 0x00884000 0 0x4000>;
1173                                 clock-names = "se";
1174                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1175                                 pinctrl-names = "default";
1176                                 pinctrl-0 = <&qup_i2c1_default>;
1177                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1178                                 #address-cells = <1>;
1179                                 #size-cells = <0>;
1180                                 power-domains = <&rpmhpd SDM845_CX>;
1181                                 operating-points-v2 = <&qup_opp_table>;
1182                                 status = "disabled";
1183                         };
1184
1185                         spi1: spi@884000 {
1186                                 compatible = "qcom,geni-spi";
1187                                 reg = <0 0x00884000 0 0x4000>;
1188                                 clock-names = "se";
1189                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1190                                 pinctrl-names = "default";
1191                                 pinctrl-0 = <&qup_spi1_default>;
1192                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1193                                 #address-cells = <1>;
1194                                 #size-cells = <0>;
1195                                 status = "disabled";
1196                         };
1197
1198                         uart1: serial@884000 {
1199                                 compatible = "qcom,geni-uart";
1200                                 reg = <0 0x00884000 0 0x4000>;
1201                                 clock-names = "se";
1202                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1203                                 pinctrl-names = "default";
1204                                 pinctrl-0 = <&qup_uart1_default>;
1205                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1206                                 power-domains = <&rpmhpd SDM845_CX>;
1207                                 operating-points-v2 = <&qup_opp_table>;
1208                                 status = "disabled";
1209                         };
1210
1211                         i2c2: i2c@888000 {
1212                                 compatible = "qcom,geni-i2c";
1213                                 reg = <0 0x00888000 0 0x4000>;
1214                                 clock-names = "se";
1215                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1216                                 pinctrl-names = "default";
1217                                 pinctrl-0 = <&qup_i2c2_default>;
1218                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1219                                 #address-cells = <1>;
1220                                 #size-cells = <0>;
1221                                 power-domains = <&rpmhpd SDM845_CX>;
1222                                 operating-points-v2 = <&qup_opp_table>;
1223                                 status = "disabled";
1224                         };
1225
1226                         spi2: spi@888000 {
1227                                 compatible = "qcom,geni-spi";
1228                                 reg = <0 0x00888000 0 0x4000>;
1229                                 clock-names = "se";
1230                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1231                                 pinctrl-names = "default";
1232                                 pinctrl-0 = <&qup_spi2_default>;
1233                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1234                                 #address-cells = <1>;
1235                                 #size-cells = <0>;
1236                                 status = "disabled";
1237                         };
1238
1239                         uart2: serial@888000 {
1240                                 compatible = "qcom,geni-uart";
1241                                 reg = <0 0x00888000 0 0x4000>;
1242                                 clock-names = "se";
1243                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1244                                 pinctrl-names = "default";
1245                                 pinctrl-0 = <&qup_uart2_default>;
1246                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1247                                 power-domains = <&rpmhpd SDM845_CX>;
1248                                 operating-points-v2 = <&qup_opp_table>;
1249                                 status = "disabled";
1250                         };
1251
1252                         i2c3: i2c@88c000 {
1253                                 compatible = "qcom,geni-i2c";
1254                                 reg = <0 0x0088c000 0 0x4000>;
1255                                 clock-names = "se";
1256                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1257                                 pinctrl-names = "default";
1258                                 pinctrl-0 = <&qup_i2c3_default>;
1259                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1260                                 #address-cells = <1>;
1261                                 #size-cells = <0>;
1262                                 power-domains = <&rpmhpd SDM845_CX>;
1263                                 operating-points-v2 = <&qup_opp_table>;
1264                                 status = "disabled";
1265                         };
1266
1267                         spi3: spi@88c000 {
1268                                 compatible = "qcom,geni-spi";
1269                                 reg = <0 0x0088c000 0 0x4000>;
1270                                 clock-names = "se";
1271                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1272                                 pinctrl-names = "default";
1273                                 pinctrl-0 = <&qup_spi3_default>;
1274                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1275                                 #address-cells = <1>;
1276                                 #size-cells = <0>;
1277                                 status = "disabled";
1278                         };
1279
1280                         uart3: serial@88c000 {
1281                                 compatible = "qcom,geni-uart";
1282                                 reg = <0 0x0088c000 0 0x4000>;
1283                                 clock-names = "se";
1284                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1285                                 pinctrl-names = "default";
1286                                 pinctrl-0 = <&qup_uart3_default>;
1287                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1288                                 power-domains = <&rpmhpd SDM845_CX>;
1289                                 operating-points-v2 = <&qup_opp_table>;
1290                                 status = "disabled";
1291                         };
1292
1293                         i2c4: i2c@890000 {
1294                                 compatible = "qcom,geni-i2c";
1295                                 reg = <0 0x00890000 0 0x4000>;
1296                                 clock-names = "se";
1297                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1298                                 pinctrl-names = "default";
1299                                 pinctrl-0 = <&qup_i2c4_default>;
1300                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1301                                 #address-cells = <1>;
1302                                 #size-cells = <0>;
1303                                 power-domains = <&rpmhpd SDM845_CX>;
1304                                 operating-points-v2 = <&qup_opp_table>;
1305                                 status = "disabled";
1306                         };
1307
1308                         spi4: spi@890000 {
1309                                 compatible = "qcom,geni-spi";
1310                                 reg = <0 0x00890000 0 0x4000>;
1311                                 clock-names = "se";
1312                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1313                                 pinctrl-names = "default";
1314                                 pinctrl-0 = <&qup_spi4_default>;
1315                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1316                                 #address-cells = <1>;
1317                                 #size-cells = <0>;
1318                                 status = "disabled";
1319                         };
1320
1321                         uart4: serial@890000 {
1322                                 compatible = "qcom,geni-uart";
1323                                 reg = <0 0x00890000 0 0x4000>;
1324                                 clock-names = "se";
1325                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1326                                 pinctrl-names = "default";
1327                                 pinctrl-0 = <&qup_uart4_default>;
1328                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1329                                 power-domains = <&rpmhpd SDM845_CX>;
1330                                 operating-points-v2 = <&qup_opp_table>;
1331                                 status = "disabled";
1332                         };
1333
1334                         i2c5: i2c@894000 {
1335                                 compatible = "qcom,geni-i2c";
1336                                 reg = <0 0x00894000 0 0x4000>;
1337                                 clock-names = "se";
1338                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1339                                 pinctrl-names = "default";
1340                                 pinctrl-0 = <&qup_i2c5_default>;
1341                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1342                                 #address-cells = <1>;
1343                                 #size-cells = <0>;
1344                                 power-domains = <&rpmhpd SDM845_CX>;
1345                                 operating-points-v2 = <&qup_opp_table>;
1346                                 status = "disabled";
1347                         };
1348
1349                         spi5: spi@894000 {
1350                                 compatible = "qcom,geni-spi";
1351                                 reg = <0 0x00894000 0 0x4000>;
1352                                 clock-names = "se";
1353                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1354                                 pinctrl-names = "default";
1355                                 pinctrl-0 = <&qup_spi5_default>;
1356                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1357                                 #address-cells = <1>;
1358                                 #size-cells = <0>;
1359                                 status = "disabled";
1360                         };
1361
1362                         uart5: serial@894000 {
1363                                 compatible = "qcom,geni-uart";
1364                                 reg = <0 0x00894000 0 0x4000>;
1365                                 clock-names = "se";
1366                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1367                                 pinctrl-names = "default";
1368                                 pinctrl-0 = <&qup_uart5_default>;
1369                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1370                                 power-domains = <&rpmhpd SDM845_CX>;
1371                                 operating-points-v2 = <&qup_opp_table>;
1372                                 status = "disabled";
1373                         };
1374
1375                         i2c6: i2c@898000 {
1376                                 compatible = "qcom,geni-i2c";
1377                                 reg = <0 0x00898000 0 0x4000>;
1378                                 clock-names = "se";
1379                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1380                                 pinctrl-names = "default";
1381                                 pinctrl-0 = <&qup_i2c6_default>;
1382                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1383                                 #address-cells = <1>;
1384                                 #size-cells = <0>;
1385                                 power-domains = <&rpmhpd SDM845_CX>;
1386                                 operating-points-v2 = <&qup_opp_table>;
1387                                 status = "disabled";
1388                         };
1389
1390                         spi6: spi@898000 {
1391                                 compatible = "qcom,geni-spi";
1392                                 reg = <0 0x00898000 0 0x4000>;
1393                                 clock-names = "se";
1394                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1395                                 pinctrl-names = "default";
1396                                 pinctrl-0 = <&qup_spi6_default>;
1397                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1398                                 #address-cells = <1>;
1399                                 #size-cells = <0>;
1400                                 status = "disabled";
1401                         };
1402
1403                         uart6: serial@898000 {
1404                                 compatible = "qcom,geni-uart";
1405                                 reg = <0 0x00898000 0 0x4000>;
1406                                 clock-names = "se";
1407                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1408                                 pinctrl-names = "default";
1409                                 pinctrl-0 = <&qup_uart6_default>;
1410                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1411                                 power-domains = <&rpmhpd SDM845_CX>;
1412                                 operating-points-v2 = <&qup_opp_table>;
1413                                 status = "disabled";
1414                         };
1415
1416                         i2c7: i2c@89c000 {
1417                                 compatible = "qcom,geni-i2c";
1418                                 reg = <0 0x0089c000 0 0x4000>;
1419                                 clock-names = "se";
1420                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1421                                 pinctrl-names = "default";
1422                                 pinctrl-0 = <&qup_i2c7_default>;
1423                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1424                                 #address-cells = <1>;
1425                                 #size-cells = <0>;
1426                                 power-domains = <&rpmhpd SDM845_CX>;
1427                                 operating-points-v2 = <&qup_opp_table>;
1428                                 status = "disabled";
1429                         };
1430
1431                         spi7: spi@89c000 {
1432                                 compatible = "qcom,geni-spi";
1433                                 reg = <0 0x0089c000 0 0x4000>;
1434                                 clock-names = "se";
1435                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1436                                 pinctrl-names = "default";
1437                                 pinctrl-0 = <&qup_spi7_default>;
1438                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1439                                 #address-cells = <1>;
1440                                 #size-cells = <0>;
1441                                 status = "disabled";
1442                         };
1443
1444                         uart7: serial@89c000 {
1445                                 compatible = "qcom,geni-uart";
1446                                 reg = <0 0x0089c000 0 0x4000>;
1447                                 clock-names = "se";
1448                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1449                                 pinctrl-names = "default";
1450                                 pinctrl-0 = <&qup_uart7_default>;
1451                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1452                                 power-domains = <&rpmhpd SDM845_CX>;
1453                                 operating-points-v2 = <&qup_opp_table>;
1454                                 status = "disabled";
1455                         };
1456                 };
1457
1458                 qupv3_id_1: geniqup@ac0000 {
1459                         compatible = "qcom,geni-se-qup";
1460                         reg = <0 0x00ac0000 0 0x6000>;
1461                         clock-names = "m-ahb", "s-ahb";
1462                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1463                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1464                         iommus = <&apps_smmu 0x6c3 0x0>;
1465                         #address-cells = <2>;
1466                         #size-cells = <2>;
1467                         ranges;
1468                         status = "disabled";
1469
1470                         i2c8: i2c@a80000 {
1471                                 compatible = "qcom,geni-i2c";
1472                                 reg = <0 0x00a80000 0 0x4000>;
1473                                 clock-names = "se";
1474                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1475                                 pinctrl-names = "default";
1476                                 pinctrl-0 = <&qup_i2c8_default>;
1477                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1478                                 #address-cells = <1>;
1479                                 #size-cells = <0>;
1480                                 power-domains = <&rpmhpd SDM845_CX>;
1481                                 operating-points-v2 = <&qup_opp_table>;
1482                                 status = "disabled";
1483                         };
1484
1485                         spi8: spi@a80000 {
1486                                 compatible = "qcom,geni-spi";
1487                                 reg = <0 0x00a80000 0 0x4000>;
1488                                 clock-names = "se";
1489                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1490                                 pinctrl-names = "default";
1491                                 pinctrl-0 = <&qup_spi8_default>;
1492                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1493                                 #address-cells = <1>;
1494                                 #size-cells = <0>;
1495                                 status = "disabled";
1496                         };
1497
1498                         uart8: serial@a80000 {
1499                                 compatible = "qcom,geni-uart";
1500                                 reg = <0 0x00a80000 0 0x4000>;
1501                                 clock-names = "se";
1502                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1503                                 pinctrl-names = "default";
1504                                 pinctrl-0 = <&qup_uart8_default>;
1505                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1506                                 power-domains = <&rpmhpd SDM845_CX>;
1507                                 operating-points-v2 = <&qup_opp_table>;
1508                                 status = "disabled";
1509                         };
1510
1511                         i2c9: i2c@a84000 {
1512                                 compatible = "qcom,geni-i2c";
1513                                 reg = <0 0x00a84000 0 0x4000>;
1514                                 clock-names = "se";
1515                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1516                                 pinctrl-names = "default";
1517                                 pinctrl-0 = <&qup_i2c9_default>;
1518                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1519                                 #address-cells = <1>;
1520                                 #size-cells = <0>;
1521                                 power-domains = <&rpmhpd SDM845_CX>;
1522                                 operating-points-v2 = <&qup_opp_table>;
1523                                 status = "disabled";
1524                         };
1525
1526                         spi9: spi@a84000 {
1527                                 compatible = "qcom,geni-spi";
1528                                 reg = <0 0x00a84000 0 0x4000>;
1529                                 clock-names = "se";
1530                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1531                                 pinctrl-names = "default";
1532                                 pinctrl-0 = <&qup_spi9_default>;
1533                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1534                                 #address-cells = <1>;
1535                                 #size-cells = <0>;
1536                                 status = "disabled";
1537                         };
1538
1539                         uart9: serial@a84000 {
1540                                 compatible = "qcom,geni-debug-uart";
1541                                 reg = <0 0x00a84000 0 0x4000>;
1542                                 clock-names = "se";
1543                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1544                                 pinctrl-names = "default";
1545                                 pinctrl-0 = <&qup_uart9_default>;
1546                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1547                                 power-domains = <&rpmhpd SDM845_CX>;
1548                                 operating-points-v2 = <&qup_opp_table>;
1549                                 status = "disabled";
1550                         };
1551
1552                         i2c10: i2c@a88000 {
1553                                 compatible = "qcom,geni-i2c";
1554                                 reg = <0 0x00a88000 0 0x4000>;
1555                                 clock-names = "se";
1556                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1557                                 pinctrl-names = "default";
1558                                 pinctrl-0 = <&qup_i2c10_default>;
1559                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1560                                 #address-cells = <1>;
1561                                 #size-cells = <0>;
1562                                 power-domains = <&rpmhpd SDM845_CX>;
1563                                 operating-points-v2 = <&qup_opp_table>;
1564                                 status = "disabled";
1565                         };
1566
1567                         spi10: spi@a88000 {
1568                                 compatible = "qcom,geni-spi";
1569                                 reg = <0 0x00a88000 0 0x4000>;
1570                                 clock-names = "se";
1571                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1572                                 pinctrl-names = "default";
1573                                 pinctrl-0 = <&qup_spi10_default>;
1574                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1575                                 #address-cells = <1>;
1576                                 #size-cells = <0>;
1577                                 status = "disabled";
1578                         };
1579
1580                         uart10: serial@a88000 {
1581                                 compatible = "qcom,geni-uart";
1582                                 reg = <0 0x00a88000 0 0x4000>;
1583                                 clock-names = "se";
1584                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1585                                 pinctrl-names = "default";
1586                                 pinctrl-0 = <&qup_uart10_default>;
1587                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1588                                 power-domains = <&rpmhpd SDM845_CX>;
1589                                 operating-points-v2 = <&qup_opp_table>;
1590                                 status = "disabled";
1591                         };
1592
1593                         i2c11: i2c@a8c000 {
1594                                 compatible = "qcom,geni-i2c";
1595                                 reg = <0 0x00a8c000 0 0x4000>;
1596                                 clock-names = "se";
1597                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1598                                 pinctrl-names = "default";
1599                                 pinctrl-0 = <&qup_i2c11_default>;
1600                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1601                                 #address-cells = <1>;
1602                                 #size-cells = <0>;
1603                                 power-domains = <&rpmhpd SDM845_CX>;
1604                                 operating-points-v2 = <&qup_opp_table>;
1605                                 status = "disabled";
1606                         };
1607
1608                         spi11: spi@a8c000 {
1609                                 compatible = "qcom,geni-spi";
1610                                 reg = <0 0x00a8c000 0 0x4000>;
1611                                 clock-names = "se";
1612                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1613                                 pinctrl-names = "default";
1614                                 pinctrl-0 = <&qup_spi11_default>;
1615                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1616                                 #address-cells = <1>;
1617                                 #size-cells = <0>;
1618                                 status = "disabled";
1619                         };
1620
1621                         uart11: serial@a8c000 {
1622                                 compatible = "qcom,geni-uart";
1623                                 reg = <0 0x00a8c000 0 0x4000>;
1624                                 clock-names = "se";
1625                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1626                                 pinctrl-names = "default";
1627                                 pinctrl-0 = <&qup_uart11_default>;
1628                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1629                                 power-domains = <&rpmhpd SDM845_CX>;
1630                                 operating-points-v2 = <&qup_opp_table>;
1631                                 status = "disabled";
1632                         };
1633
1634                         i2c12: i2c@a90000 {
1635                                 compatible = "qcom,geni-i2c";
1636                                 reg = <0 0x00a90000 0 0x4000>;
1637                                 clock-names = "se";
1638                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1639                                 pinctrl-names = "default";
1640                                 pinctrl-0 = <&qup_i2c12_default>;
1641                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1642                                 #address-cells = <1>;
1643                                 #size-cells = <0>;
1644                                 power-domains = <&rpmhpd SDM845_CX>;
1645                                 operating-points-v2 = <&qup_opp_table>;
1646                                 status = "disabled";
1647                         };
1648
1649                         spi12: spi@a90000 {
1650                                 compatible = "qcom,geni-spi";
1651                                 reg = <0 0x00a90000 0 0x4000>;
1652                                 clock-names = "se";
1653                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1654                                 pinctrl-names = "default";
1655                                 pinctrl-0 = <&qup_spi12_default>;
1656                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1657                                 #address-cells = <1>;
1658                                 #size-cells = <0>;
1659                                 status = "disabled";
1660                         };
1661
1662                         uart12: serial@a90000 {
1663                                 compatible = "qcom,geni-uart";
1664                                 reg = <0 0x00a90000 0 0x4000>;
1665                                 clock-names = "se";
1666                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1667                                 pinctrl-names = "default";
1668                                 pinctrl-0 = <&qup_uart12_default>;
1669                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1670                                 power-domains = <&rpmhpd SDM845_CX>;
1671                                 operating-points-v2 = <&qup_opp_table>;
1672                                 status = "disabled";
1673                         };
1674
1675                         i2c13: i2c@a94000 {
1676                                 compatible = "qcom,geni-i2c";
1677                                 reg = <0 0x00a94000 0 0x4000>;
1678                                 clock-names = "se";
1679                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680                                 pinctrl-names = "default";
1681                                 pinctrl-0 = <&qup_i2c13_default>;
1682                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683                                 #address-cells = <1>;
1684                                 #size-cells = <0>;
1685                                 power-domains = <&rpmhpd SDM845_CX>;
1686                                 operating-points-v2 = <&qup_opp_table>;
1687                                 status = "disabled";
1688                         };
1689
1690                         spi13: spi@a94000 {
1691                                 compatible = "qcom,geni-spi";
1692                                 reg = <0 0x00a94000 0 0x4000>;
1693                                 clock-names = "se";
1694                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1695                                 pinctrl-names = "default";
1696                                 pinctrl-0 = <&qup_spi13_default>;
1697                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1698                                 #address-cells = <1>;
1699                                 #size-cells = <0>;
1700                                 status = "disabled";
1701                         };
1702
1703                         uart13: serial@a94000 {
1704                                 compatible = "qcom,geni-uart";
1705                                 reg = <0 0x00a94000 0 0x4000>;
1706                                 clock-names = "se";
1707                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1708                                 pinctrl-names = "default";
1709                                 pinctrl-0 = <&qup_uart13_default>;
1710                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1711                                 power-domains = <&rpmhpd SDM845_CX>;
1712                                 operating-points-v2 = <&qup_opp_table>;
1713                                 status = "disabled";
1714                         };
1715
1716                         i2c14: i2c@a98000 {
1717                                 compatible = "qcom,geni-i2c";
1718                                 reg = <0 0x00a98000 0 0x4000>;
1719                                 clock-names = "se";
1720                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1721                                 pinctrl-names = "default";
1722                                 pinctrl-0 = <&qup_i2c14_default>;
1723                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1724                                 #address-cells = <1>;
1725                                 #size-cells = <0>;
1726                                 power-domains = <&rpmhpd SDM845_CX>;
1727                                 operating-points-v2 = <&qup_opp_table>;
1728                                 status = "disabled";
1729                         };
1730
1731                         spi14: spi@a98000 {
1732                                 compatible = "qcom,geni-spi";
1733                                 reg = <0 0x00a98000 0 0x4000>;
1734                                 clock-names = "se";
1735                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1736                                 pinctrl-names = "default";
1737                                 pinctrl-0 = <&qup_spi14_default>;
1738                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1739                                 #address-cells = <1>;
1740                                 #size-cells = <0>;
1741                                 status = "disabled";
1742                         };
1743
1744                         uart14: serial@a98000 {
1745                                 compatible = "qcom,geni-uart";
1746                                 reg = <0 0x00a98000 0 0x4000>;
1747                                 clock-names = "se";
1748                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1749                                 pinctrl-names = "default";
1750                                 pinctrl-0 = <&qup_uart14_default>;
1751                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1752                                 power-domains = <&rpmhpd SDM845_CX>;
1753                                 operating-points-v2 = <&qup_opp_table>;
1754                                 status = "disabled";
1755                         };
1756
1757                         i2c15: i2c@a9c000 {
1758                                 compatible = "qcom,geni-i2c";
1759                                 reg = <0 0x00a9c000 0 0x4000>;
1760                                 clock-names = "se";
1761                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1762                                 pinctrl-names = "default";
1763                                 pinctrl-0 = <&qup_i2c15_default>;
1764                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1765                                 #address-cells = <1>;
1766                                 #size-cells = <0>;
1767                                 power-domains = <&rpmhpd SDM845_CX>;
1768                                 operating-points-v2 = <&qup_opp_table>;
1769                                 status = "disabled";
1770                         };
1771
1772                         spi15: spi@a9c000 {
1773                                 compatible = "qcom,geni-spi";
1774                                 reg = <0 0x00a9c000 0 0x4000>;
1775                                 clock-names = "se";
1776                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1777                                 pinctrl-names = "default";
1778                                 pinctrl-0 = <&qup_spi15_default>;
1779                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1780                                 #address-cells = <1>;
1781                                 #size-cells = <0>;
1782                                 status = "disabled";
1783                         };
1784
1785                         uart15: serial@a9c000 {
1786                                 compatible = "qcom,geni-uart";
1787                                 reg = <0 0x00a9c000 0 0x4000>;
1788                                 clock-names = "se";
1789                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1790                                 pinctrl-names = "default";
1791                                 pinctrl-0 = <&qup_uart15_default>;
1792                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1793                                 power-domains = <&rpmhpd SDM845_CX>;
1794                                 operating-points-v2 = <&qup_opp_table>;
1795                                 status = "disabled";
1796                         };
1797                 };
1798
1799                 system-cache-controller@1100000 {
1800                         compatible = "qcom,sdm845-llcc";
1801                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1802                         reg-names = "llcc_base", "llcc_broadcast_base";
1803                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1804                 };
1805
1806                 pcie0: pci@1c00000 {
1807                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1808                         reg = <0 0x01c00000 0 0x2000>,
1809                               <0 0x60000000 0 0xf1d>,
1810                               <0 0x60000f20 0 0xa8>,
1811                               <0 0x60100000 0 0x100000>;
1812                         reg-names = "parf", "dbi", "elbi", "config";
1813                         device_type = "pci";
1814                         linux,pci-domain = <0>;
1815                         bus-range = <0x00 0xff>;
1816                         num-lanes = <1>;
1817
1818                         #address-cells = <3>;
1819                         #size-cells = <2>;
1820
1821                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1822                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1823
1824                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1825                         interrupt-names = "msi";
1826                         #interrupt-cells = <1>;
1827                         interrupt-map-mask = <0 0 0 0x7>;
1828                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1829                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1830                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1831                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1832
1833                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1834                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1835                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1836                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1837                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1838                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1839                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1840                         clock-names = "pipe",
1841                                       "aux",
1842                                       "cfg",
1843                                       "bus_master",
1844                                       "bus_slave",
1845                                       "slave_q2a",
1846                                       "tbu";
1847
1848                         iommus = <&apps_smmu 0x1c10 0xf>;
1849                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
1850                                     <0x100 &apps_smmu 0x1c11 0x1>,
1851                                     <0x200 &apps_smmu 0x1c12 0x1>,
1852                                     <0x300 &apps_smmu 0x1c13 0x1>,
1853                                     <0x400 &apps_smmu 0x1c14 0x1>,
1854                                     <0x500 &apps_smmu 0x1c15 0x1>,
1855                                     <0x600 &apps_smmu 0x1c16 0x1>,
1856                                     <0x700 &apps_smmu 0x1c17 0x1>,
1857                                     <0x800 &apps_smmu 0x1c18 0x1>,
1858                                     <0x900 &apps_smmu 0x1c19 0x1>,
1859                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
1860                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
1861                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
1862                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
1863                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
1864                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
1865
1866                         resets = <&gcc GCC_PCIE_0_BCR>;
1867                         reset-names = "pci";
1868
1869                         power-domains = <&gcc PCIE_0_GDSC>;
1870
1871                         phys = <&pcie0_lane>;
1872                         phy-names = "pciephy";
1873
1874                         status = "disabled";
1875                 };
1876
1877                 pcie0_phy: phy@1c06000 {
1878                         compatible = "qcom,sdm845-qmp-pcie-phy";
1879                         reg = <0 0x01c06000 0 0x18c>;
1880                         #address-cells = <2>;
1881                         #size-cells = <2>;
1882                         ranges;
1883                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1884                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1885                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1886                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1887                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1888
1889                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1890                         reset-names = "phy";
1891
1892                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1893                         assigned-clock-rates = <100000000>;
1894
1895                         status = "disabled";
1896
1897                         pcie0_lane: lanes@1c06200 {
1898                                 reg = <0 0x01c06200 0 0x128>,
1899                                       <0 0x01c06400 0 0x1fc>,
1900                                       <0 0x01c06800 0 0x218>,
1901                                       <0 0x01c06600 0 0x70>;
1902                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1903                                 clock-names = "pipe0";
1904
1905                                 #phy-cells = <0>;
1906                                 clock-output-names = "pcie_0_pipe_clk";
1907                         };
1908                 };
1909
1910                 pcie1: pci@1c08000 {
1911                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1912                         reg = <0 0x01c08000 0 0x2000>,
1913                               <0 0x40000000 0 0xf1d>,
1914                               <0 0x40000f20 0 0xa8>,
1915                               <0 0x40100000 0 0x100000>;
1916                         reg-names = "parf", "dbi", "elbi", "config";
1917                         device_type = "pci";
1918                         linux,pci-domain = <1>;
1919                         bus-range = <0x00 0xff>;
1920                         num-lanes = <1>;
1921
1922                         #address-cells = <3>;
1923                         #size-cells = <2>;
1924
1925                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1926                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1927
1928                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1929                         interrupt-names = "msi";
1930                         #interrupt-cells = <1>;
1931                         interrupt-map-mask = <0 0 0 0x7>;
1932                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1933                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1934                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1935                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1936
1937                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1938                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1939                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1940                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1941                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1942                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1943                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1944                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1945                         clock-names = "pipe",
1946                                       "aux",
1947                                       "cfg",
1948                                       "bus_master",
1949                                       "bus_slave",
1950                                       "slave_q2a",
1951                                       "ref",
1952                                       "tbu";
1953
1954                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1955                         assigned-clock-rates = <19200000>;
1956
1957                         iommus = <&apps_smmu 0x1c00 0xf>;
1958                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1959                                     <0x100 &apps_smmu 0x1c01 0x1>,
1960                                     <0x200 &apps_smmu 0x1c02 0x1>,
1961                                     <0x300 &apps_smmu 0x1c03 0x1>,
1962                                     <0x400 &apps_smmu 0x1c04 0x1>,
1963                                     <0x500 &apps_smmu 0x1c05 0x1>,
1964                                     <0x600 &apps_smmu 0x1c06 0x1>,
1965                                     <0x700 &apps_smmu 0x1c07 0x1>,
1966                                     <0x800 &apps_smmu 0x1c08 0x1>,
1967                                     <0x900 &apps_smmu 0x1c09 0x1>,
1968                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
1969                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
1970                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
1971                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
1972                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
1973                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
1974
1975                         resets = <&gcc GCC_PCIE_1_BCR>;
1976                         reset-names = "pci";
1977
1978                         power-domains = <&gcc PCIE_1_GDSC>;
1979
1980                         phys = <&pcie1_lane>;
1981                         phy-names = "pciephy";
1982
1983                         status = "disabled";
1984                 };
1985
1986                 pcie1_phy: phy@1c0a000 {
1987                         compatible = "qcom,sdm845-qhp-pcie-phy";
1988                         reg = <0 0x01c0a000 0 0x800>;
1989                         #address-cells = <2>;
1990                         #size-cells = <2>;
1991                         ranges;
1992                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1993                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1994                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1995                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1996                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1997
1998                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1999                         reset-names = "phy";
2000
2001                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2002                         assigned-clock-rates = <100000000>;
2003
2004                         status = "disabled";
2005
2006                         pcie1_lane: lanes@1c06200 {
2007                                 reg = <0 0x01c0a800 0 0x800>,
2008                                       <0 0x01c0a800 0 0x800>,
2009                                       <0 0x01c0b800 0 0x400>;
2010                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2011                                 clock-names = "pipe0";
2012
2013                                 #phy-cells = <0>;
2014                                 clock-output-names = "pcie_1_pipe_clk";
2015                         };
2016                 };
2017
2018                 mem_noc: interconnect@1380000 {
2019                         compatible = "qcom,sdm845-mem-noc";
2020                         reg = <0 0x01380000 0 0x27200>;
2021                         #interconnect-cells = <2>;
2022                         qcom,bcm-voters = <&apps_bcm_voter>;
2023                 };
2024
2025                 dc_noc: interconnect@14e0000 {
2026                         compatible = "qcom,sdm845-dc-noc";
2027                         reg = <0 0x014e0000 0 0x400>;
2028                         #interconnect-cells = <2>;
2029                         qcom,bcm-voters = <&apps_bcm_voter>;
2030                 };
2031
2032                 config_noc: interconnect@1500000 {
2033                         compatible = "qcom,sdm845-config-noc";
2034                         reg = <0 0x01500000 0 0x5080>;
2035                         #interconnect-cells = <2>;
2036                         qcom,bcm-voters = <&apps_bcm_voter>;
2037                 };
2038
2039                 system_noc: interconnect@1620000 {
2040                         compatible = "qcom,sdm845-system-noc";
2041                         reg = <0 0x01620000 0 0x18080>;
2042                         #interconnect-cells = <2>;
2043                         qcom,bcm-voters = <&apps_bcm_voter>;
2044                 };
2045
2046                 aggre1_noc: interconnect@16e0000 {
2047                         compatible = "qcom,sdm845-aggre1-noc";
2048                         reg = <0 0x016e0000 0 0x15080>;
2049                         #interconnect-cells = <2>;
2050                         qcom,bcm-voters = <&apps_bcm_voter>;
2051                 };
2052
2053                 aggre2_noc: interconnect@1700000 {
2054                         compatible = "qcom,sdm845-aggre2-noc";
2055                         reg = <0 0x01700000 0 0x1f300>;
2056                         #interconnect-cells = <2>;
2057                         qcom,bcm-voters = <&apps_bcm_voter>;
2058                 };
2059
2060                 mmss_noc: interconnect@1740000 {
2061                         compatible = "qcom,sdm845-mmss-noc";
2062                         reg = <0 0x01740000 0 0x1c100>;
2063                         #interconnect-cells = <2>;
2064                         qcom,bcm-voters = <&apps_bcm_voter>;
2065                 };
2066
2067                 ufs_mem_hc: ufshc@1d84000 {
2068                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2069                                      "jedec,ufs-2.0";
2070                         reg = <0 0x01d84000 0 0x2500>,
2071                               <0 0x01d90000 0 0x8000>;
2072                         reg-names = "std", "ice";
2073                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2074                         phys = <&ufs_mem_phy_lanes>;
2075                         phy-names = "ufsphy";
2076                         lanes-per-direction = <2>;
2077                         power-domains = <&gcc UFS_PHY_GDSC>;
2078                         #reset-cells = <1>;
2079                         resets = <&gcc GCC_UFS_PHY_BCR>;
2080                         reset-names = "rst";
2081
2082                         iommus = <&apps_smmu 0x100 0xf>;
2083
2084                         clock-names =
2085                                 "core_clk",
2086                                 "bus_aggr_clk",
2087                                 "iface_clk",
2088                                 "core_clk_unipro",
2089                                 "ref_clk",
2090                                 "tx_lane0_sync_clk",
2091                                 "rx_lane0_sync_clk",
2092                                 "rx_lane1_sync_clk",
2093                                 "ice_core_clk";
2094                         clocks =
2095                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2096                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2097                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2098                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2099                                 <&rpmhcc RPMH_CXO_CLK>,
2100                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2101                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2102                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2103                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2104                         freq-table-hz =
2105                                 <50000000 200000000>,
2106                                 <0 0>,
2107                                 <0 0>,
2108                                 <37500000 150000000>,
2109                                 <0 0>,
2110                                 <0 0>,
2111                                 <0 0>,
2112                                 <0 0>,
2113                                 <0 300000000>;
2114
2115                         status = "disabled";
2116                 };
2117
2118                 ufs_mem_phy: phy@1d87000 {
2119                         compatible = "qcom,sdm845-qmp-ufs-phy";
2120                         reg = <0 0x01d87000 0 0x18c>;
2121                         #address-cells = <2>;
2122                         #size-cells = <2>;
2123                         ranges;
2124                         clock-names = "ref",
2125                                       "ref_aux";
2126                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2127                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2128
2129                         resets = <&ufs_mem_hc 0>;
2130                         reset-names = "ufsphy";
2131                         status = "disabled";
2132
2133                         ufs_mem_phy_lanes: lanes@1d87400 {
2134                                 reg = <0 0x01d87400 0 0x108>,
2135                                       <0 0x01d87600 0 0x1e0>,
2136                                       <0 0x01d87c00 0 0x1dc>,
2137                                       <0 0x01d87800 0 0x108>,
2138                                       <0 0x01d87a00 0 0x1e0>;
2139                                 #phy-cells = <0>;
2140                         };
2141                 };
2142
2143                 ipa: ipa@1e40000 {
2144                         compatible = "qcom,sdm845-ipa";
2145
2146                         iommus = <&apps_smmu 0x720 0x0>,
2147                                  <&apps_smmu 0x722 0x0>;
2148                         reg = <0 0x1e40000 0 0x7000>,
2149                               <0 0x1e47000 0 0x2000>,
2150                               <0 0x1e04000 0 0x2c000>;
2151                         reg-names = "ipa-reg",
2152                                     "ipa-shared",
2153                                     "gsi";
2154
2155                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2156                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2157                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2158                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2159                         interrupt-names = "ipa",
2160                                           "gsi",
2161                                           "ipa-clock-query",
2162                                           "ipa-setup-ready";
2163
2164                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2165                         clock-names = "core";
2166
2167                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2168                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2169                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2170                         interconnect-names = "memory",
2171                                              "imem",
2172                                              "config";
2173
2174                         qcom,smem-states = <&ipa_smp2p_out 0>,
2175                                            <&ipa_smp2p_out 1>;
2176                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2177                                                 "ipa-clock-enabled";
2178
2179                         modem-remoteproc = <&mss_pil>;
2180
2181                         status = "disabled";
2182                 };
2183
2184                 tcsr_mutex_regs: syscon@1f40000 {
2185                         compatible = "syscon";
2186                         reg = <0 0x01f40000 0 0x40000>;
2187                 };
2188
2189                 tlmm: pinctrl@3400000 {
2190                         compatible = "qcom,sdm845-pinctrl";
2191                         reg = <0 0x03400000 0 0xc00000>;
2192                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2193                         gpio-controller;
2194                         #gpio-cells = <2>;
2195                         interrupt-controller;
2196                         #interrupt-cells = <2>;
2197                         gpio-ranges = <&tlmm 0 0 150>;
2198                         wakeup-parent = <&pdc_intc>;
2199
2200                         cci0_default: cci0-default {
2201                                 /* SDA, SCL */
2202                                 pins = "gpio17", "gpio18";
2203                                 function = "cci_i2c";
2204
2205                                 bias-pull-up;
2206                                 drive-strength = <2>; /* 2 mA */
2207                         };
2208
2209                         cci0_sleep: cci0-sleep {
2210                                 /* SDA, SCL */
2211                                 pins = "gpio17", "gpio18";
2212                                 function = "cci_i2c";
2213
2214                                 drive-strength = <2>; /* 2 mA */
2215                                 bias-pull-down;
2216                         };
2217
2218                         cci1_default: cci1-default {
2219                                 /* SDA, SCL */
2220                                 pins = "gpio19", "gpio20";
2221                                 function = "cci_i2c";
2222
2223                                 bias-pull-up;
2224                                 drive-strength = <2>; /* 2 mA */
2225                         };
2226
2227                         cci1_sleep: cci1-sleep {
2228                                 /* SDA, SCL */
2229                                 pins = "gpio19", "gpio20";
2230                                 function = "cci_i2c";
2231
2232                                 drive-strength = <2>; /* 2 mA */
2233                                 bias-pull-down;
2234                         };
2235
2236                         qspi_clk: qspi-clk {
2237                                 pinmux {
2238                                         pins = "gpio95";
2239                                         function = "qspi_clk";
2240                                 };
2241                         };
2242
2243                         qspi_cs0: qspi-cs0 {
2244                                 pinmux {
2245                                         pins = "gpio90";
2246                                         function = "qspi_cs";
2247                                 };
2248                         };
2249
2250                         qspi_cs1: qspi-cs1 {
2251                                 pinmux {
2252                                         pins = "gpio89";
2253                                         function = "qspi_cs";
2254                                 };
2255                         };
2256
2257                         qspi_data01: qspi-data01 {
2258                                 pinmux-data {
2259                                         pins = "gpio91", "gpio92";
2260                                         function = "qspi_data";
2261                                 };
2262                         };
2263
2264                         qspi_data12: qspi-data12 {
2265                                 pinmux-data {
2266                                         pins = "gpio93", "gpio94";
2267                                         function = "qspi_data";
2268                                 };
2269                         };
2270
2271                         qup_i2c0_default: qup-i2c0-default {
2272                                 pinmux {
2273                                         pins = "gpio0", "gpio1";
2274                                         function = "qup0";
2275                                 };
2276                         };
2277
2278                         qup_i2c1_default: qup-i2c1-default {
2279                                 pinmux {
2280                                         pins = "gpio17", "gpio18";
2281                                         function = "qup1";
2282                                 };
2283                         };
2284
2285                         qup_i2c2_default: qup-i2c2-default {
2286                                 pinmux {
2287                                         pins = "gpio27", "gpio28";
2288                                         function = "qup2";
2289                                 };
2290                         };
2291
2292                         qup_i2c3_default: qup-i2c3-default {
2293                                 pinmux {
2294                                         pins = "gpio41", "gpio42";
2295                                         function = "qup3";
2296                                 };
2297                         };
2298
2299                         qup_i2c4_default: qup-i2c4-default {
2300                                 pinmux {
2301                                         pins = "gpio89", "gpio90";
2302                                         function = "qup4";
2303                                 };
2304                         };
2305
2306                         qup_i2c5_default: qup-i2c5-default {
2307                                 pinmux {
2308                                         pins = "gpio85", "gpio86";
2309                                         function = "qup5";
2310                                 };
2311                         };
2312
2313                         qup_i2c6_default: qup-i2c6-default {
2314                                 pinmux {
2315                                         pins = "gpio45", "gpio46";
2316                                         function = "qup6";
2317                                 };
2318                         };
2319
2320                         qup_i2c7_default: qup-i2c7-default {
2321                                 pinmux {
2322                                         pins = "gpio93", "gpio94";
2323                                         function = "qup7";
2324                                 };
2325                         };
2326
2327                         qup_i2c8_default: qup-i2c8-default {
2328                                 pinmux {
2329                                         pins = "gpio65", "gpio66";
2330                                         function = "qup8";
2331                                 };
2332                         };
2333
2334                         qup_i2c9_default: qup-i2c9-default {
2335                                 pinmux {
2336                                         pins = "gpio6", "gpio7";
2337                                         function = "qup9";
2338                                 };
2339                         };
2340
2341                         qup_i2c10_default: qup-i2c10-default {
2342                                 pinmux {
2343                                         pins = "gpio55", "gpio56";
2344                                         function = "qup10";
2345                                 };
2346                         };
2347
2348                         qup_i2c11_default: qup-i2c11-default {
2349                                 pinmux {
2350                                         pins = "gpio31", "gpio32";
2351                                         function = "qup11";
2352                                 };
2353                         };
2354
2355                         qup_i2c12_default: qup-i2c12-default {
2356                                 pinmux {
2357                                         pins = "gpio49", "gpio50";
2358                                         function = "qup12";
2359                                 };
2360                         };
2361
2362                         qup_i2c13_default: qup-i2c13-default {
2363                                 pinmux {
2364                                         pins = "gpio105", "gpio106";
2365                                         function = "qup13";
2366                                 };
2367                         };
2368
2369                         qup_i2c14_default: qup-i2c14-default {
2370                                 pinmux {
2371                                         pins = "gpio33", "gpio34";
2372                                         function = "qup14";
2373                                 };
2374                         };
2375
2376                         qup_i2c15_default: qup-i2c15-default {
2377                                 pinmux {
2378                                         pins = "gpio81", "gpio82";
2379                                         function = "qup15";
2380                                 };
2381                         };
2382
2383                         qup_spi0_default: qup-spi0-default {
2384                                 pinmux {
2385                                         pins = "gpio0", "gpio1",
2386                                                "gpio2", "gpio3";
2387                                         function = "qup0";
2388                                 };
2389                         };
2390
2391                         qup_spi1_default: qup-spi1-default {
2392                                 pinmux {
2393                                         pins = "gpio17", "gpio18",
2394                                                "gpio19", "gpio20";
2395                                         function = "qup1";
2396                                 };
2397                         };
2398
2399                         qup_spi2_default: qup-spi2-default {
2400                                 pinmux {
2401                                         pins = "gpio27", "gpio28",
2402                                                "gpio29", "gpio30";
2403                                         function = "qup2";
2404                                 };
2405                         };
2406
2407                         qup_spi3_default: qup-spi3-default {
2408                                 pinmux {
2409                                         pins = "gpio41", "gpio42",
2410                                                "gpio43", "gpio44";
2411                                         function = "qup3";
2412                                 };
2413                         };
2414
2415                         qup_spi4_default: qup-spi4-default {
2416                                 pinmux {
2417                                         pins = "gpio89", "gpio90",
2418                                                "gpio91", "gpio92";
2419                                         function = "qup4";
2420                                 };
2421                         };
2422
2423                         qup_spi5_default: qup-spi5-default {
2424                                 pinmux {
2425                                         pins = "gpio85", "gpio86",
2426                                                "gpio87", "gpio88";
2427                                         function = "qup5";
2428                                 };
2429                         };
2430
2431                         qup_spi6_default: qup-spi6-default {
2432                                 pinmux {
2433                                         pins = "gpio45", "gpio46",
2434                                                "gpio47", "gpio48";
2435                                         function = "qup6";
2436                                 };
2437                         };
2438
2439                         qup_spi7_default: qup-spi7-default {
2440                                 pinmux {
2441                                         pins = "gpio93", "gpio94",
2442                                                "gpio95", "gpio96";
2443                                         function = "qup7";
2444                                 };
2445                         };
2446
2447                         qup_spi8_default: qup-spi8-default {
2448                                 pinmux {
2449                                         pins = "gpio65", "gpio66",
2450                                                "gpio67", "gpio68";
2451                                         function = "qup8";
2452                                 };
2453                         };
2454
2455                         qup_spi9_default: qup-spi9-default {
2456                                 pinmux {
2457                                         pins = "gpio6", "gpio7",
2458                                                "gpio4", "gpio5";
2459                                         function = "qup9";
2460                                 };
2461                         };
2462
2463                         qup_spi10_default: qup-spi10-default {
2464                                 pinmux {
2465                                         pins = "gpio55", "gpio56",
2466                                                "gpio53", "gpio54";
2467                                         function = "qup10";
2468                                 };
2469                         };
2470
2471                         qup_spi11_default: qup-spi11-default {
2472                                 pinmux {
2473                                         pins = "gpio31", "gpio32",
2474                                                "gpio33", "gpio34";
2475                                         function = "qup11";
2476                                 };
2477                         };
2478
2479                         qup_spi12_default: qup-spi12-default {
2480                                 pinmux {
2481                                         pins = "gpio49", "gpio50",
2482                                                "gpio51", "gpio52";
2483                                         function = "qup12";
2484                                 };
2485                         };
2486
2487                         qup_spi13_default: qup-spi13-default {
2488                                 pinmux {
2489                                         pins = "gpio105", "gpio106",
2490                                                "gpio107", "gpio108";
2491                                         function = "qup13";
2492                                 };
2493                         };
2494
2495                         qup_spi14_default: qup-spi14-default {
2496                                 pinmux {
2497                                         pins = "gpio33", "gpio34",
2498                                                "gpio31", "gpio32";
2499                                         function = "qup14";
2500                                 };
2501                         };
2502
2503                         qup_spi15_default: qup-spi15-default {
2504                                 pinmux {
2505                                         pins = "gpio81", "gpio82",
2506                                                "gpio83", "gpio84";
2507                                         function = "qup15";
2508                                 };
2509                         };
2510
2511                         qup_uart0_default: qup-uart0-default {
2512                                 pinmux {
2513                                         pins = "gpio2", "gpio3";
2514                                         function = "qup0";
2515                                 };
2516                         };
2517
2518                         qup_uart1_default: qup-uart1-default {
2519                                 pinmux {
2520                                         pins = "gpio19", "gpio20";
2521                                         function = "qup1";
2522                                 };
2523                         };
2524
2525                         qup_uart2_default: qup-uart2-default {
2526                                 pinmux {
2527                                         pins = "gpio29", "gpio30";
2528                                         function = "qup2";
2529                                 };
2530                         };
2531
2532                         qup_uart3_default: qup-uart3-default {
2533                                 pinmux {
2534                                         pins = "gpio43", "gpio44";
2535                                         function = "qup3";
2536                                 };
2537                         };
2538
2539                         qup_uart4_default: qup-uart4-default {
2540                                 pinmux {
2541                                         pins = "gpio91", "gpio92";
2542                                         function = "qup4";
2543                                 };
2544                         };
2545
2546                         qup_uart5_default: qup-uart5-default {
2547                                 pinmux {
2548                                         pins = "gpio87", "gpio88";
2549                                         function = "qup5";
2550                                 };
2551                         };
2552
2553                         qup_uart6_default: qup-uart6-default {
2554                                 pinmux {
2555                                         pins = "gpio47", "gpio48";
2556                                         function = "qup6";
2557                                 };
2558                         };
2559
2560                         qup_uart7_default: qup-uart7-default {
2561                                 pinmux {
2562                                         pins = "gpio95", "gpio96";
2563                                         function = "qup7";
2564                                 };
2565                         };
2566
2567                         qup_uart8_default: qup-uart8-default {
2568                                 pinmux {
2569                                         pins = "gpio67", "gpio68";
2570                                         function = "qup8";
2571                                 };
2572                         };
2573
2574                         qup_uart9_default: qup-uart9-default {
2575                                 pinmux {
2576                                         pins = "gpio4", "gpio5";
2577                                         function = "qup9";
2578                                 };
2579                         };
2580
2581                         qup_uart10_default: qup-uart10-default {
2582                                 pinmux {
2583                                         pins = "gpio53", "gpio54";
2584                                         function = "qup10";
2585                                 };
2586                         };
2587
2588                         qup_uart11_default: qup-uart11-default {
2589                                 pinmux {
2590                                         pins = "gpio33", "gpio34";
2591                                         function = "qup11";
2592                                 };
2593                         };
2594
2595                         qup_uart12_default: qup-uart12-default {
2596                                 pinmux {
2597                                         pins = "gpio51", "gpio52";
2598                                         function = "qup12";
2599                                 };
2600                         };
2601
2602                         qup_uart13_default: qup-uart13-default {
2603                                 pinmux {
2604                                         pins = "gpio107", "gpio108";
2605                                         function = "qup13";
2606                                 };
2607                         };
2608
2609                         qup_uart14_default: qup-uart14-default {
2610                                 pinmux {
2611                                         pins = "gpio31", "gpio32";
2612                                         function = "qup14";
2613                                 };
2614                         };
2615
2616                         qup_uart15_default: qup-uart15-default {
2617                                 pinmux {
2618                                         pins = "gpio83", "gpio84";
2619                                         function = "qup15";
2620                                 };
2621                         };
2622
2623                         quat_mi2s_sleep: quat_mi2s_sleep {
2624                                 mux {
2625                                         pins = "gpio58", "gpio59";
2626                                         function = "gpio";
2627                                 };
2628
2629                                 config {
2630                                         pins = "gpio58", "gpio59";
2631                                         drive-strength = <2>;
2632                                         bias-pull-down;
2633                                         input-enable;
2634                                 };
2635                         };
2636
2637                         quat_mi2s_active: quat_mi2s_active {
2638                                 mux {
2639                                         pins = "gpio58", "gpio59";
2640                                         function = "qua_mi2s";
2641                                 };
2642
2643                                 config {
2644                                         pins = "gpio58", "gpio59";
2645                                         drive-strength = <8>;
2646                                         bias-disable;
2647                                         output-high;
2648                                 };
2649                         };
2650
2651                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2652                                 mux {
2653                                         pins = "gpio60";
2654                                         function = "gpio";
2655                                 };
2656
2657                                 config {
2658                                         pins = "gpio60";
2659                                         drive-strength = <2>;
2660                                         bias-pull-down;
2661                                         input-enable;
2662                                 };
2663                         };
2664
2665                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2666                                 mux {
2667                                         pins = "gpio60";
2668                                         function = "qua_mi2s";
2669                                 };
2670
2671                                 config {
2672                                         pins = "gpio60";
2673                                         drive-strength = <8>;
2674                                         bias-disable;
2675                                 };
2676                         };
2677
2678                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2679                                 mux {
2680                                         pins = "gpio61";
2681                                         function = "gpio";
2682                                 };
2683
2684                                 config {
2685                                         pins = "gpio61";
2686                                         drive-strength = <2>;
2687                                         bias-pull-down;
2688                                         input-enable;
2689                                 };
2690                         };
2691
2692                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2693                                 mux {
2694                                         pins = "gpio61";
2695                                         function = "qua_mi2s";
2696                                 };
2697
2698                                 config {
2699                                         pins = "gpio61";
2700                                         drive-strength = <8>;
2701                                         bias-disable;
2702                                 };
2703                         };
2704
2705                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2706                                 mux {
2707                                         pins = "gpio62";
2708                                         function = "gpio";
2709                                 };
2710
2711                                 config {
2712                                         pins = "gpio62";
2713                                         drive-strength = <2>;
2714                                         bias-pull-down;
2715                                         input-enable;
2716                                 };
2717                         };
2718
2719                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2720                                 mux {
2721                                         pins = "gpio62";
2722                                         function = "qua_mi2s";
2723                                 };
2724
2725                                 config {
2726                                         pins = "gpio62";
2727                                         drive-strength = <8>;
2728                                         bias-disable;
2729                                 };
2730                         };
2731
2732                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2733                                 mux {
2734                                         pins = "gpio63";
2735                                         function = "gpio";
2736                                 };
2737
2738                                 config {
2739                                         pins = "gpio63";
2740                                         drive-strength = <2>;
2741                                         bias-pull-down;
2742                                         input-enable;
2743                                 };
2744                         };
2745
2746                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2747                                 mux {
2748                                         pins = "gpio63";
2749                                         function = "qua_mi2s";
2750                                 };
2751
2752                                 config {
2753                                         pins = "gpio63";
2754                                         drive-strength = <8>;
2755                                         bias-disable;
2756                                 };
2757                         };
2758                 };
2759
2760                 mss_pil: remoteproc@4080000 {
2761                         compatible = "qcom,sdm845-mss-pil";
2762                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2763                         reg-names = "qdsp6", "rmb";
2764
2765                         interrupts-extended =
2766                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2767                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2768                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2769                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2770                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2771                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2772                         interrupt-names = "wdog", "fatal", "ready",
2773                                           "handover", "stop-ack",
2774                                           "shutdown-ack";
2775
2776                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2777                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2778                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2779                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2780                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2781                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2782                                  <&gcc GCC_PRNG_AHB_CLK>,
2783                                  <&rpmhcc RPMH_CXO_CLK>;
2784                         clock-names = "iface", "bus", "mem", "gpll0_mss",
2785                                       "snoc_axi", "mnoc_axi", "prng", "xo";
2786
2787                         qcom,smem-states = <&modem_smp2p_out 0>;
2788                         qcom,smem-state-names = "stop";
2789
2790                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2791                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2792                         reset-names = "mss_restart", "pdc_reset";
2793
2794                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2795
2796                         power-domains = <&aoss_qmp 2>,
2797                                         <&rpmhpd SDM845_CX>,
2798                                         <&rpmhpd SDM845_MX>,
2799                                         <&rpmhpd SDM845_MSS>;
2800                         power-domain-names = "load_state", "cx", "mx", "mss";
2801
2802                         mba {
2803                                 memory-region = <&mba_region>;
2804                         };
2805
2806                         mpss {
2807                                 memory-region = <&mpss_region>;
2808                         };
2809
2810                         glink-edge {
2811                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2812                                 label = "modem";
2813                                 qcom,remote-pid = <1>;
2814                                 mboxes = <&apss_shared 12>;
2815                         };
2816                 };
2817
2818                 gpucc: clock-controller@5090000 {
2819                         compatible = "qcom,sdm845-gpucc";
2820                         reg = <0 0x05090000 0 0x9000>;
2821                         #clock-cells = <1>;
2822                         #reset-cells = <1>;
2823                         #power-domain-cells = <1>;
2824                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2825                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2826                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2827                         clock-names = "bi_tcxo",
2828                                       "gcc_gpu_gpll0_clk_src",
2829                                       "gcc_gpu_gpll0_div_clk_src";
2830                 };
2831
2832                 stm@6002000 {
2833                         compatible = "arm,coresight-stm", "arm,primecell";
2834                         reg = <0 0x06002000 0 0x1000>,
2835                               <0 0x16280000 0 0x180000>;
2836                         reg-names = "stm-base", "stm-stimulus-base";
2837
2838                         clocks = <&aoss_qmp>;
2839                         clock-names = "apb_pclk";
2840
2841                         out-ports {
2842                                 port {
2843                                         stm_out: endpoint {
2844                                                 remote-endpoint =
2845                                                   <&funnel0_in7>;
2846                                         };
2847                                 };
2848                         };
2849                 };
2850
2851                 funnel@6041000 {
2852                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2853                         reg = <0 0x06041000 0 0x1000>;
2854
2855                         clocks = <&aoss_qmp>;
2856                         clock-names = "apb_pclk";
2857
2858                         out-ports {
2859                                 port {
2860                                         funnel0_out: endpoint {
2861                                                 remote-endpoint =
2862                                                   <&merge_funnel_in0>;
2863                                         };
2864                                 };
2865                         };
2866
2867                         in-ports {
2868                                 #address-cells = <1>;
2869                                 #size-cells = <0>;
2870
2871                                 port@7 {
2872                                         reg = <7>;
2873                                         funnel0_in7: endpoint {
2874                                                 remote-endpoint = <&stm_out>;
2875                                         };
2876                                 };
2877                         };
2878                 };
2879
2880                 funnel@6043000 {
2881                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2882                         reg = <0 0x06043000 0 0x1000>;
2883
2884                         clocks = <&aoss_qmp>;
2885                         clock-names = "apb_pclk";
2886
2887                         out-ports {
2888                                 port {
2889                                         funnel2_out: endpoint {
2890                                                 remote-endpoint =
2891                                                   <&merge_funnel_in2>;
2892                                         };
2893                                 };
2894                         };
2895
2896                         in-ports {
2897                                 #address-cells = <1>;
2898                                 #size-cells = <0>;
2899
2900                                 port@5 {
2901                                         reg = <5>;
2902                                         funnel2_in5: endpoint {
2903                                                 remote-endpoint =
2904                                                   <&apss_merge_funnel_out>;
2905                                         };
2906                                 };
2907                         };
2908                 };
2909
2910                 funnel@6045000 {
2911                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2912                         reg = <0 0x06045000 0 0x1000>;
2913
2914                         clocks = <&aoss_qmp>;
2915                         clock-names = "apb_pclk";
2916
2917                         out-ports {
2918                                 port {
2919                                         merge_funnel_out: endpoint {
2920                                                 remote-endpoint = <&etf_in>;
2921                                         };
2922                                 };
2923                         };
2924
2925                         in-ports {
2926                                 #address-cells = <1>;
2927                                 #size-cells = <0>;
2928
2929                                 port@0 {
2930                                         reg = <0>;
2931                                         merge_funnel_in0: endpoint {
2932                                                 remote-endpoint =
2933                                                   <&funnel0_out>;
2934                                         };
2935                                 };
2936
2937                                 port@2 {
2938                                         reg = <2>;
2939                                         merge_funnel_in2: endpoint {
2940                                                 remote-endpoint =
2941                                                   <&funnel2_out>;
2942                                         };
2943                                 };
2944                         };
2945                 };
2946
2947                 replicator@6046000 {
2948                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2949                         reg = <0 0x06046000 0 0x1000>;
2950
2951                         clocks = <&aoss_qmp>;
2952                         clock-names = "apb_pclk";
2953
2954                         out-ports {
2955                                 port {
2956                                         replicator_out: endpoint {
2957                                                 remote-endpoint = <&etr_in>;
2958                                         };
2959                                 };
2960                         };
2961
2962                         in-ports {
2963                                 port {
2964                                         replicator_in: endpoint {
2965                                                 remote-endpoint = <&etf_out>;
2966                                         };
2967                                 };
2968                         };
2969                 };
2970
2971                 etf@6047000 {
2972                         compatible = "arm,coresight-tmc", "arm,primecell";
2973                         reg = <0 0x06047000 0 0x1000>;
2974
2975                         clocks = <&aoss_qmp>;
2976                         clock-names = "apb_pclk";
2977
2978                         out-ports {
2979                                 port {
2980                                         etf_out: endpoint {
2981                                                 remote-endpoint =
2982                                                   <&replicator_in>;
2983                                         };
2984                                 };
2985                         };
2986
2987                         in-ports {
2988                                 #address-cells = <1>;
2989                                 #size-cells = <0>;
2990
2991                                 port@1 {
2992                                         reg = <1>;
2993                                         etf_in: endpoint {
2994                                                 remote-endpoint =
2995                                                   <&merge_funnel_out>;
2996                                         };
2997                                 };
2998                         };
2999                 };
3000
3001                 etr@6048000 {
3002                         compatible = "arm,coresight-tmc", "arm,primecell";
3003                         reg = <0 0x06048000 0 0x1000>;
3004
3005                         clocks = <&aoss_qmp>;
3006                         clock-names = "apb_pclk";
3007                         arm,scatter-gather;
3008
3009                         in-ports {
3010                                 port {
3011                                         etr_in: endpoint {
3012                                                 remote-endpoint =
3013                                                   <&replicator_out>;
3014                                         };
3015                                 };
3016                         };
3017                 };
3018
3019                 etm@7040000 {
3020                         compatible = "arm,coresight-etm4x", "arm,primecell";
3021                         reg = <0 0x07040000 0 0x1000>;
3022
3023                         cpu = <&CPU0>;
3024
3025                         clocks = <&aoss_qmp>;
3026                         clock-names = "apb_pclk";
3027                         arm,coresight-loses-context-with-cpu;
3028
3029                         out-ports {
3030                                 port {
3031                                         etm0_out: endpoint {
3032                                                 remote-endpoint =
3033                                                   <&apss_funnel_in0>;
3034                                         };
3035                                 };
3036                         };
3037                 };
3038
3039                 etm@7140000 {
3040                         compatible = "arm,coresight-etm4x", "arm,primecell";
3041                         reg = <0 0x07140000 0 0x1000>;
3042
3043                         cpu = <&CPU1>;
3044
3045                         clocks = <&aoss_qmp>;
3046                         clock-names = "apb_pclk";
3047                         arm,coresight-loses-context-with-cpu;
3048
3049                         out-ports {
3050                                 port {
3051                                         etm1_out: endpoint {
3052                                                 remote-endpoint =
3053                                                   <&apss_funnel_in1>;
3054                                         };
3055                                 };
3056                         };
3057                 };
3058
3059                 etm@7240000 {
3060                         compatible = "arm,coresight-etm4x", "arm,primecell";
3061                         reg = <0 0x07240000 0 0x1000>;
3062
3063                         cpu = <&CPU2>;
3064
3065                         clocks = <&aoss_qmp>;
3066                         clock-names = "apb_pclk";
3067                         arm,coresight-loses-context-with-cpu;
3068
3069                         out-ports {
3070                                 port {
3071                                         etm2_out: endpoint {
3072                                                 remote-endpoint =
3073                                                   <&apss_funnel_in2>;
3074                                         };
3075                                 };
3076                         };
3077                 };
3078
3079                 etm@7340000 {
3080                         compatible = "arm,coresight-etm4x", "arm,primecell";
3081                         reg = <0 0x07340000 0 0x1000>;
3082
3083                         cpu = <&CPU3>;
3084
3085                         clocks = <&aoss_qmp>;
3086                         clock-names = "apb_pclk";
3087                         arm,coresight-loses-context-with-cpu;
3088
3089                         out-ports {
3090                                 port {
3091                                         etm3_out: endpoint {
3092                                                 remote-endpoint =
3093                                                   <&apss_funnel_in3>;
3094                                         };
3095                                 };
3096                         };
3097                 };
3098
3099                 etm@7440000 {
3100                         compatible = "arm,coresight-etm4x", "arm,primecell";
3101                         reg = <0 0x07440000 0 0x1000>;
3102
3103                         cpu = <&CPU4>;
3104
3105                         clocks = <&aoss_qmp>;
3106                         clock-names = "apb_pclk";
3107                         arm,coresight-loses-context-with-cpu;
3108
3109                         out-ports {
3110                                 port {
3111                                         etm4_out: endpoint {
3112                                                 remote-endpoint =
3113                                                   <&apss_funnel_in4>;
3114                                         };
3115                                 };
3116                         };
3117                 };
3118
3119                 etm@7540000 {
3120                         compatible = "arm,coresight-etm4x", "arm,primecell";
3121                         reg = <0 0x07540000 0 0x1000>;
3122
3123                         cpu = <&CPU5>;
3124
3125                         clocks = <&aoss_qmp>;
3126                         clock-names = "apb_pclk";
3127                         arm,coresight-loses-context-with-cpu;
3128
3129                         out-ports {
3130                                 port {
3131                                         etm5_out: endpoint {
3132                                                 remote-endpoint =
3133                                                   <&apss_funnel_in5>;
3134                                         };
3135                                 };
3136                         };
3137                 };
3138
3139                 etm@7640000 {
3140                         compatible = "arm,coresight-etm4x", "arm,primecell";
3141                         reg = <0 0x07640000 0 0x1000>;
3142
3143                         cpu = <&CPU6>;
3144
3145                         clocks = <&aoss_qmp>;
3146                         clock-names = "apb_pclk";
3147                         arm,coresight-loses-context-with-cpu;
3148
3149                         out-ports {
3150                                 port {
3151                                         etm6_out: endpoint {
3152                                                 remote-endpoint =
3153                                                   <&apss_funnel_in6>;
3154                                         };
3155                                 };
3156                         };
3157                 };
3158
3159                 etm@7740000 {
3160                         compatible = "arm,coresight-etm4x", "arm,primecell";
3161                         reg = <0 0x07740000 0 0x1000>;
3162
3163                         cpu = <&CPU7>;
3164
3165                         clocks = <&aoss_qmp>;
3166                         clock-names = "apb_pclk";
3167                         arm,coresight-loses-context-with-cpu;
3168
3169                         out-ports {
3170                                 port {
3171                                         etm7_out: endpoint {
3172                                                 remote-endpoint =
3173                                                   <&apss_funnel_in7>;
3174                                         };
3175                                 };
3176                         };
3177                 };
3178
3179                 funnel@7800000 { /* APSS Funnel */
3180                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3181                         reg = <0 0x07800000 0 0x1000>;
3182
3183                         clocks = <&aoss_qmp>;
3184                         clock-names = "apb_pclk";
3185
3186                         out-ports {
3187                                 port {
3188                                         apss_funnel_out: endpoint {
3189                                                 remote-endpoint =
3190                                                   <&apss_merge_funnel_in>;
3191                                         };
3192                                 };
3193                         };
3194
3195                         in-ports {
3196                                 #address-cells = <1>;
3197                                 #size-cells = <0>;
3198
3199                                 port@0 {
3200                                         reg = <0>;
3201                                         apss_funnel_in0: endpoint {
3202                                                 remote-endpoint =
3203                                                   <&etm0_out>;
3204                                         };
3205                                 };
3206
3207                                 port@1 {
3208                                         reg = <1>;
3209                                         apss_funnel_in1: endpoint {
3210                                                 remote-endpoint =
3211                                                   <&etm1_out>;
3212                                         };
3213                                 };
3214
3215                                 port@2 {
3216                                         reg = <2>;
3217                                         apss_funnel_in2: endpoint {
3218                                                 remote-endpoint =
3219                                                   <&etm2_out>;
3220                                         };
3221                                 };
3222
3223                                 port@3 {
3224                                         reg = <3>;
3225                                         apss_funnel_in3: endpoint {
3226                                                 remote-endpoint =
3227                                                   <&etm3_out>;
3228                                         };
3229                                 };
3230
3231                                 port@4 {
3232                                         reg = <4>;
3233                                         apss_funnel_in4: endpoint {
3234                                                 remote-endpoint =
3235                                                   <&etm4_out>;
3236                                         };
3237                                 };
3238
3239                                 port@5 {
3240                                         reg = <5>;
3241                                         apss_funnel_in5: endpoint {
3242                                                 remote-endpoint =
3243                                                   <&etm5_out>;
3244                                         };
3245                                 };
3246
3247                                 port@6 {
3248                                         reg = <6>;
3249                                         apss_funnel_in6: endpoint {
3250                                                 remote-endpoint =
3251                                                   <&etm6_out>;
3252                                         };
3253                                 };
3254
3255                                 port@7 {
3256                                         reg = <7>;
3257                                         apss_funnel_in7: endpoint {
3258                                                 remote-endpoint =
3259                                                   <&etm7_out>;
3260                                         };
3261                                 };
3262                         };
3263                 };
3264
3265                 funnel@7810000 {
3266                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3267                         reg = <0 0x07810000 0 0x1000>;
3268
3269                         clocks = <&aoss_qmp>;
3270                         clock-names = "apb_pclk";
3271
3272                         out-ports {
3273                                 port {
3274                                         apss_merge_funnel_out: endpoint {
3275                                                 remote-endpoint =
3276                                                   <&funnel2_in5>;
3277                                         };
3278                                 };
3279                         };
3280
3281                         in-ports {
3282                                 port {
3283                                         apss_merge_funnel_in: endpoint {
3284                                                 remote-endpoint =
3285                                                   <&apss_funnel_out>;
3286                                         };
3287                                 };
3288                         };
3289                 };
3290
3291                 sdhc_2: sdhci@8804000 {
3292                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3293                         reg = <0 0x08804000 0 0x1000>;
3294
3295                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3297                         interrupt-names = "hc_irq", "pwr_irq";
3298
3299                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3300                                  <&gcc GCC_SDCC2_APPS_CLK>;
3301                         clock-names = "iface", "core";
3302                         iommus = <&apps_smmu 0xa0 0xf>;
3303                         power-domains = <&rpmhpd SDM845_CX>;
3304                         operating-points-v2 = <&sdhc2_opp_table>;
3305
3306                         status = "disabled";
3307
3308                         sdhc2_opp_table: sdhc2-opp-table {
3309                                 compatible = "operating-points-v2";
3310
3311                                 opp-9600000 {
3312                                         opp-hz = /bits/ 64 <9600000>;
3313                                         required-opps = <&rpmhpd_opp_min_svs>;
3314                                 };
3315
3316                                 opp-19200000 {
3317                                         opp-hz = /bits/ 64 <19200000>;
3318                                         required-opps = <&rpmhpd_opp_low_svs>;
3319                                 };
3320
3321                                 opp-100000000 {
3322                                         opp-hz = /bits/ 64 <100000000>;
3323                                         required-opps = <&rpmhpd_opp_svs>;
3324                                 };
3325
3326                                 opp-201500000 {
3327                                         opp-hz = /bits/ 64 <201500000>;
3328                                         required-opps = <&rpmhpd_opp_svs_l1>;
3329                                 };
3330                         };
3331                 };
3332
3333                 qspi_opp_table: qspi-opp-table {
3334                         compatible = "operating-points-v2";
3335
3336                         opp-19200000 {
3337                                 opp-hz = /bits/ 64 <19200000>;
3338                                 required-opps = <&rpmhpd_opp_min_svs>;
3339                         };
3340
3341                         opp-100000000 {
3342                                 opp-hz = /bits/ 64 <100000000>;
3343                                 required-opps = <&rpmhpd_opp_low_svs>;
3344                         };
3345
3346                         opp-150000000 {
3347                                 opp-hz = /bits/ 64 <150000000>;
3348                                 required-opps = <&rpmhpd_opp_svs>;
3349                         };
3350
3351                         opp-300000000 {
3352                                 opp-hz = /bits/ 64 <300000000>;
3353                                 required-opps = <&rpmhpd_opp_nom>;
3354                         };
3355                 };
3356
3357                 qspi: spi@88df000 {
3358                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3359                         reg = <0 0x088df000 0 0x600>;
3360                         #address-cells = <1>;
3361                         #size-cells = <0>;
3362                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3363                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3364                                  <&gcc GCC_QSPI_CORE_CLK>;
3365                         clock-names = "iface", "core";
3366                         power-domains = <&rpmhpd SDM845_CX>;
3367                         operating-points-v2 = <&qspi_opp_table>;
3368                         status = "disabled";
3369                 };
3370
3371                 slim: slim@171c0000 {
3372                         compatible = "qcom,slim-ngd-v2.1.0";
3373                         reg = <0 0x171c0000 0 0x2c000>;
3374                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3375
3376                         qcom,apps-ch-pipes = <0x780000>;
3377                         qcom,ea-pc = <0x270>;
3378                         status = "okay";
3379                         dmas =  <&slimbam 3>, <&slimbam 4>,
3380                                 <&slimbam 5>, <&slimbam 6>;
3381                         dma-names = "rx", "tx", "tx2", "rx2";
3382
3383                         iommus = <&apps_smmu 0x1806 0x0>;
3384                         #address-cells = <1>;
3385                         #size-cells = <0>;
3386
3387                         ngd@1 {
3388                                 reg = <1>;
3389                                 #address-cells = <2>;
3390                                 #size-cells = <0>;
3391
3392                                 wcd9340_ifd: ifd@0{
3393                                         compatible = "slim217,250";
3394                                         reg  = <0 0>;
3395                                 };
3396
3397                                 wcd9340: codec@1{
3398                                         compatible = "slim217,250";
3399                                         reg  = <1 0>;
3400                                         slim-ifc-dev  = <&wcd9340_ifd>;
3401
3402                                         #sound-dai-cells = <1>;
3403
3404                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3405                                         interrupt-controller;
3406                                         #interrupt-cells = <1>;
3407
3408                                         #clock-cells = <0>;
3409                                         clock-frequency = <9600000>;
3410                                         clock-output-names = "mclk";
3411                                         qcom,micbias1-millivolt = <1800>;
3412                                         qcom,micbias2-millivolt = <1800>;
3413                                         qcom,micbias3-millivolt = <1800>;
3414                                         qcom,micbias4-millivolt = <1800>;
3415
3416                                         #address-cells = <1>;
3417                                         #size-cells = <1>;
3418
3419                                         wcdgpio: gpio-controller@42 {
3420                                                 compatible = "qcom,wcd9340-gpio";
3421                                                 gpio-controller;
3422                                                 #gpio-cells = <2>;
3423                                                 reg = <0x42 0x2>;
3424                                         };
3425
3426                                         swm: swm@c85 {
3427                                                 compatible = "qcom,soundwire-v1.3.0";
3428                                                 reg = <0xc85 0x40>;
3429                                                 interrupts-extended = <&wcd9340 20>;
3430
3431                                                 qcom,dout-ports = <6>;
3432                                                 qcom,din-ports  = <2>;
3433                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3434                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3435                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3436
3437                                                 #sound-dai-cells = <1>;
3438                                                 clocks = <&wcd9340>;
3439                                                 clock-names = "iface";
3440                                                 #address-cells = <2>;
3441                                                 #size-cells = <0>;
3442
3443
3444                                         };
3445                                 };
3446                         };
3447                 };
3448
3449                 sound: sound {
3450                 };
3451
3452                 usb_1_hsphy: phy@88e2000 {
3453                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3454                         reg = <0 0x088e2000 0 0x400>;
3455                         status = "disabled";
3456                         #phy-cells = <0>;
3457
3458                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3459                                  <&rpmhcc RPMH_CXO_CLK>;
3460                         clock-names = "cfg_ahb", "ref";
3461
3462                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3463
3464                         nvmem-cells = <&qusb2p_hstx_trim>;
3465                 };
3466
3467                 usb_2_hsphy: phy@88e3000 {
3468                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3469                         reg = <0 0x088e3000 0 0x400>;
3470                         status = "disabled";
3471                         #phy-cells = <0>;
3472
3473                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3474                                  <&rpmhcc RPMH_CXO_CLK>;
3475                         clock-names = "cfg_ahb", "ref";
3476
3477                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3478
3479                         nvmem-cells = <&qusb2s_hstx_trim>;
3480                 };
3481
3482                 usb_1_qmpphy: phy@88e9000 {
3483                         compatible = "qcom,sdm845-qmp-usb3-phy";
3484                         reg = <0 0x088e9000 0 0x18c>,
3485                               <0 0x088e8000 0 0x10>;
3486                         reg-names = "reg-base", "dp_com";
3487                         status = "disabled";
3488                         #clock-cells = <1>;
3489                         #address-cells = <2>;
3490                         #size-cells = <2>;
3491                         ranges;
3492
3493                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3494                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3495                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3496                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3497                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3498
3499                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3500                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3501                         reset-names = "phy", "common";
3502
3503                         usb_1_ssphy: lanes@88e9200 {
3504                                 reg = <0 0x088e9200 0 0x128>,
3505                                       <0 0x088e9400 0 0x200>,
3506                                       <0 0x088e9c00 0 0x218>,
3507                                       <0 0x088e9600 0 0x128>,
3508                                       <0 0x088e9800 0 0x200>,
3509                                       <0 0x088e9a00 0 0x100>;
3510                                 #phy-cells = <0>;
3511                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3512                                 clock-names = "pipe0";
3513                                 clock-output-names = "usb3_phy_pipe_clk_src";
3514                         };
3515                 };
3516
3517                 usb_2_qmpphy: phy@88eb000 {
3518                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3519                         reg = <0 0x088eb000 0 0x18c>;
3520                         status = "disabled";
3521                         #clock-cells = <1>;
3522                         #address-cells = <2>;
3523                         #size-cells = <2>;
3524                         ranges;
3525
3526                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3527                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3528                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3529                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3530                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3531
3532                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3533                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3534                         reset-names = "phy", "common";
3535
3536                         usb_2_ssphy: lane@88eb200 {
3537                                 reg = <0 0x088eb200 0 0x128>,
3538                                       <0 0x088eb400 0 0x1fc>,
3539                                       <0 0x088eb800 0 0x218>,
3540                                       <0 0x088eb600 0 0x70>;
3541                                 #phy-cells = <0>;
3542                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3543                                 clock-names = "pipe0";
3544                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3545                         };
3546                 };
3547
3548                 usb_1: usb@a6f8800 {
3549                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3550                         reg = <0 0x0a6f8800 0 0x400>;
3551                         status = "disabled";
3552                         #address-cells = <2>;
3553                         #size-cells = <2>;
3554                         ranges;
3555                         dma-ranges;
3556
3557                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3558                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3559                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3560                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3561                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3562                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3563                                       "sleep";
3564
3565                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3566                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3567                         assigned-clock-rates = <19200000>, <150000000>;
3568
3569                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3570                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3571                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3572                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3573                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3574                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3575
3576                         power-domains = <&gcc USB30_PRIM_GDSC>;
3577
3578                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3579
3580                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3581                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3582                         interconnect-names = "usb-ddr", "apps-usb";
3583
3584                         usb_1_dwc3: dwc3@a600000 {
3585                                 compatible = "snps,dwc3";
3586                                 reg = <0 0x0a600000 0 0xcd00>;
3587                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3588                                 iommus = <&apps_smmu 0x740 0>;
3589                                 snps,dis_u2_susphy_quirk;
3590                                 snps,dis_enblslpm_quirk;
3591                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3592                                 phy-names = "usb2-phy", "usb3-phy";
3593                         };
3594                 };
3595
3596                 usb_2: usb@a8f8800 {
3597                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3598                         reg = <0 0x0a8f8800 0 0x400>;
3599                         status = "disabled";
3600                         #address-cells = <2>;
3601                         #size-cells = <2>;
3602                         ranges;
3603                         dma-ranges;
3604
3605                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3606                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3607                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3608                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3609                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3610                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3611                                       "sleep";
3612
3613                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3614                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3615                         assigned-clock-rates = <19200000>, <150000000>;
3616
3617                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3618                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3619                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3620                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3621                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3622                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3623
3624                         power-domains = <&gcc USB30_SEC_GDSC>;
3625
3626                         resets = <&gcc GCC_USB30_SEC_BCR>;
3627
3628                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3629                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3630                         interconnect-names = "usb-ddr", "apps-usb";
3631
3632                         usb_2_dwc3: dwc3@a800000 {
3633                                 compatible = "snps,dwc3";
3634                                 reg = <0 0x0a800000 0 0xcd00>;
3635                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3636                                 iommus = <&apps_smmu 0x760 0>;
3637                                 snps,dis_u2_susphy_quirk;
3638                                 snps,dis_enblslpm_quirk;
3639                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3640                                 phy-names = "usb2-phy", "usb3-phy";
3641                         };
3642                 };
3643
3644                 venus: video-codec@aa00000 {
3645                         compatible = "qcom,sdm845-venus-v2";
3646                         reg = <0 0x0aa00000 0 0xff000>;
3647                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3648                         power-domains = <&videocc VENUS_GDSC>,
3649                                         <&videocc VCODEC0_GDSC>,
3650                                         <&videocc VCODEC1_GDSC>,
3651                                         <&rpmhpd SDM845_CX>;
3652                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3653                         operating-points-v2 = <&venus_opp_table>;
3654                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3655                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3656                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3657                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3658                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3659                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3660                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3661                         clock-names = "core", "iface", "bus",
3662                                       "vcodec0_core", "vcodec0_bus",
3663                                       "vcodec1_core", "vcodec1_bus";
3664                         iommus = <&apps_smmu 0x10a0 0x8>,
3665                                  <&apps_smmu 0x10b0 0x0>;
3666                         memory-region = <&venus_mem>;
3667                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3668                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3669                         interconnect-names = "video-mem", "cpu-cfg";
3670
3671                         video-core0 {
3672                                 compatible = "venus-decoder";
3673                         };
3674
3675                         video-core1 {
3676                                 compatible = "venus-encoder";
3677                         };
3678
3679                         venus_opp_table: venus-opp-table {
3680                                 compatible = "operating-points-v2";
3681
3682                                 opp-100000000 {
3683                                         opp-hz = /bits/ 64 <100000000>;
3684                                         required-opps = <&rpmhpd_opp_min_svs>;
3685                                 };
3686
3687                                 opp-200000000 {
3688                                         opp-hz = /bits/ 64 <200000000>;
3689                                         required-opps = <&rpmhpd_opp_low_svs>;
3690                                 };
3691
3692                                 opp-320000000 {
3693                                         opp-hz = /bits/ 64 <320000000>;
3694                                         required-opps = <&rpmhpd_opp_svs>;
3695                                 };
3696
3697                                 opp-380000000 {
3698                                         opp-hz = /bits/ 64 <380000000>;
3699                                         required-opps = <&rpmhpd_opp_svs_l1>;
3700                                 };
3701
3702                                 opp-444000000 {
3703                                         opp-hz = /bits/ 64 <444000000>;
3704                                         required-opps = <&rpmhpd_opp_nom>;
3705                                 };
3706
3707                                 opp-533000097 {
3708                                         opp-hz = /bits/ 64 <533000097>;
3709                                         required-opps = <&rpmhpd_opp_turbo>;
3710                                 };
3711                         };
3712                 };
3713
3714                 videocc: clock-controller@ab00000 {
3715                         compatible = "qcom,sdm845-videocc";
3716                         reg = <0 0x0ab00000 0 0x10000>;
3717                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3718                         clock-names = "bi_tcxo";
3719                         #clock-cells = <1>;
3720                         #power-domain-cells = <1>;
3721                         #reset-cells = <1>;
3722                 };
3723
3724                 cci: cci@ac4a000 {
3725                         compatible = "qcom,sdm845-cci";
3726                         #address-cells = <1>;
3727                         #size-cells = <0>;
3728
3729                         reg = <0 0x0ac4a000 0 0x4000>;
3730                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3731                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
3732
3733                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3734                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
3735                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3736                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
3737                                 <&clock_camcc CAM_CC_CCI_CLK>,
3738                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
3739                         clock-names = "camnoc_axi",
3740                                 "soc_ahb",
3741                                 "slow_ahb_src",
3742                                 "cpas_ahb",
3743                                 "cci",
3744                                 "cci_src";
3745
3746                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3747                                 <&clock_camcc CAM_CC_CCI_CLK>;
3748                         assigned-clock-rates = <80000000>, <37500000>;
3749
3750                         pinctrl-names = "default", "sleep";
3751                         pinctrl-0 = <&cci0_default &cci1_default>;
3752                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3753
3754                         status = "disabled";
3755
3756                         cci_i2c0: i2c-bus@0 {
3757                                 reg = <0>;
3758                                 clock-frequency = <1000000>;
3759                                 #address-cells = <1>;
3760                                 #size-cells = <0>;
3761                         };
3762
3763                         cci_i2c1: i2c-bus@1 {
3764                                 reg = <1>;
3765                                 clock-frequency = <1000000>;
3766                                 #address-cells = <1>;
3767                                 #size-cells = <0>;
3768                         };
3769                 };
3770
3771                 clock_camcc: clock-controller@ad00000 {
3772                         compatible = "qcom,sdm845-camcc";
3773                         reg = <0 0x0ad00000 0 0x10000>;
3774                         #clock-cells = <1>;
3775                         #reset-cells = <1>;
3776                         #power-domain-cells = <1>;
3777                 };
3778
3779                 dsi_opp_table: dsi-opp-table {
3780                         compatible = "operating-points-v2";
3781
3782                         opp-19200000 {
3783                                 opp-hz = /bits/ 64 <19200000>;
3784                                 required-opps = <&rpmhpd_opp_min_svs>;
3785                         };
3786
3787                         opp-180000000 {
3788                                 opp-hz = /bits/ 64 <180000000>;
3789                                 required-opps = <&rpmhpd_opp_low_svs>;
3790                         };
3791
3792                         opp-275000000 {
3793                                 opp-hz = /bits/ 64 <275000000>;
3794                                 required-opps = <&rpmhpd_opp_svs>;
3795                         };
3796
3797                         opp-328580000 {
3798                                 opp-hz = /bits/ 64 <328580000>;
3799                                 required-opps = <&rpmhpd_opp_svs_l1>;
3800                         };
3801
3802                         opp-358000000 {
3803                                 opp-hz = /bits/ 64 <358000000>;
3804                                 required-opps = <&rpmhpd_opp_nom>;
3805                         };
3806                 };
3807
3808                 mdss: mdss@ae00000 {
3809                         compatible = "qcom,sdm845-mdss";
3810                         reg = <0 0x0ae00000 0 0x1000>;
3811                         reg-names = "mdss";
3812
3813                         power-domains = <&dispcc MDSS_GDSC>;
3814
3815                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3816                                  <&gcc GCC_DISP_AXI_CLK>,
3817                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3818                         clock-names = "iface", "bus", "core";
3819
3820                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
3821                         assigned-clock-rates = <300000000>;
3822
3823                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3824                         interrupt-controller;
3825                         #interrupt-cells = <1>;
3826
3827                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
3828                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
3829                         interconnect-names = "mdp0-mem", "mdp1-mem";
3830
3831                         iommus = <&apps_smmu 0x880 0x8>,
3832                                  <&apps_smmu 0xc80 0x8>;
3833
3834                         status = "disabled";
3835
3836                         #address-cells = <2>;
3837                         #size-cells = <2>;
3838                         ranges;
3839
3840                         mdss_mdp: mdp@ae01000 {
3841                                 compatible = "qcom,sdm845-dpu";
3842                                 reg = <0 0x0ae01000 0 0x8f000>,
3843                                       <0 0x0aeb0000 0 0x2008>;
3844                                 reg-names = "mdp", "vbif";
3845
3846                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3847                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
3848                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3849                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3850                                 clock-names = "iface", "bus", "core", "vsync";
3851
3852                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3853                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3854                                 assigned-clock-rates = <300000000>,
3855                                                        <19200000>;
3856                                 operating-points-v2 = <&mdp_opp_table>;
3857                                 power-domains = <&rpmhpd SDM845_CX>;
3858
3859                                 interrupt-parent = <&mdss>;
3860                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3861
3862                                 status = "disabled";
3863
3864                                 ports {
3865                                         #address-cells = <1>;
3866                                         #size-cells = <0>;
3867
3868                                         port@0 {
3869                                                 reg = <0>;
3870                                                 dpu_intf1_out: endpoint {
3871                                                         remote-endpoint = <&dsi0_in>;
3872                                                 };
3873                                         };
3874
3875                                         port@1 {
3876                                                 reg = <1>;
3877                                                 dpu_intf2_out: endpoint {
3878                                                         remote-endpoint = <&dsi1_in>;
3879                                                 };
3880                                         };
3881                                 };
3882
3883                                 mdp_opp_table: mdp-opp-table {
3884                                         compatible = "operating-points-v2";
3885
3886                                         opp-19200000 {
3887                                                 opp-hz = /bits/ 64 <19200000>;
3888                                                 required-opps = <&rpmhpd_opp_min_svs>;
3889                                         };
3890
3891                                         opp-171428571 {
3892                                                 opp-hz = /bits/ 64 <171428571>;
3893                                                 required-opps = <&rpmhpd_opp_low_svs>;
3894                                         };
3895
3896                                         opp-344000000 {
3897                                                 opp-hz = /bits/ 64 <344000000>;
3898                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3899                                         };
3900
3901                                         opp-430000000 {
3902                                                 opp-hz = /bits/ 64 <430000000>;
3903                                                 required-opps = <&rpmhpd_opp_nom>;
3904                                         };
3905                                 };
3906                         };
3907
3908                         dsi0: dsi@ae94000 {
3909                                 compatible = "qcom,mdss-dsi-ctrl";
3910                                 reg = <0 0x0ae94000 0 0x400>;
3911                                 reg-names = "dsi_ctrl";
3912
3913                                 interrupt-parent = <&mdss>;
3914                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
3915
3916                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3917                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3918                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3919                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3920                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3921                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
3922                                 clock-names = "byte",
3923                                               "byte_intf",
3924                                               "pixel",
3925                                               "core",
3926                                               "iface",
3927                                               "bus";
3928                                 operating-points-v2 = <&dsi_opp_table>;
3929                                 power-domains = <&rpmhpd SDM845_CX>;
3930
3931                                 phys = <&dsi0_phy>;
3932                                 phy-names = "dsi";
3933
3934                                 status = "disabled";
3935
3936                                 ports {
3937                                         #address-cells = <1>;
3938                                         #size-cells = <0>;
3939
3940                                         port@0 {
3941                                                 reg = <0>;
3942                                                 dsi0_in: endpoint {
3943                                                         remote-endpoint = <&dpu_intf1_out>;
3944                                                 };
3945                                         };
3946
3947                                         port@1 {
3948                                                 reg = <1>;
3949                                                 dsi0_out: endpoint {
3950                                                 };
3951                                         };
3952                                 };
3953                         };
3954
3955                         dsi0_phy: dsi-phy@ae94400 {
3956                                 compatible = "qcom,dsi-phy-10nm";
3957                                 reg = <0 0x0ae94400 0 0x200>,
3958                                       <0 0x0ae94600 0 0x280>,
3959                                       <0 0x0ae94a00 0 0x1e0>;
3960                                 reg-names = "dsi_phy",
3961                                             "dsi_phy_lane",
3962                                             "dsi_pll";
3963
3964                                 #clock-cells = <1>;
3965                                 #phy-cells = <0>;
3966
3967                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3968                                          <&rpmhcc RPMH_CXO_CLK>;
3969                                 clock-names = "iface", "ref";
3970
3971                                 status = "disabled";
3972                         };
3973
3974                         dsi1: dsi@ae96000 {
3975                                 compatible = "qcom,mdss-dsi-ctrl";
3976                                 reg = <0 0x0ae96000 0 0x400>;
3977                                 reg-names = "dsi_ctrl";
3978
3979                                 interrupt-parent = <&mdss>;
3980                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
3981
3982                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3983                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3984                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3985                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3986                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3987                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
3988                                 clock-names = "byte",
3989                                               "byte_intf",
3990                                               "pixel",
3991                                               "core",
3992                                               "iface",
3993                                               "bus";
3994                                 operating-points-v2 = <&dsi_opp_table>;
3995                                 power-domains = <&rpmhpd SDM845_CX>;
3996
3997                                 phys = <&dsi1_phy>;
3998                                 phy-names = "dsi";
3999
4000                                 status = "disabled";
4001
4002                                 ports {
4003                                         #address-cells = <1>;
4004                                         #size-cells = <0>;
4005
4006                                         port@0 {
4007                                                 reg = <0>;
4008                                                 dsi1_in: endpoint {
4009                                                         remote-endpoint = <&dpu_intf2_out>;
4010                                                 };
4011                                         };
4012
4013                                         port@1 {
4014                                                 reg = <1>;
4015                                                 dsi1_out: endpoint {
4016                                                 };
4017                                         };
4018                                 };
4019                         };
4020
4021                         dsi1_phy: dsi-phy@ae96400 {
4022                                 compatible = "qcom,dsi-phy-10nm";
4023                                 reg = <0 0x0ae96400 0 0x200>,
4024                                       <0 0x0ae96600 0 0x280>,
4025                                       <0 0x0ae96a00 0 0x10e>;
4026                                 reg-names = "dsi_phy",
4027                                             "dsi_phy_lane",
4028                                             "dsi_pll";
4029
4030                                 #clock-cells = <1>;
4031                                 #phy-cells = <0>;
4032
4033                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4034                                          <&rpmhcc RPMH_CXO_CLK>;
4035                                 clock-names = "iface", "ref";
4036
4037                                 status = "disabled";
4038                         };
4039                 };
4040
4041                 gpu: gpu@5000000 {
4042                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4043                         #stream-id-cells = <16>;
4044
4045                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4046                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4047
4048                         /*
4049                          * Look ma, no clocks! The GPU clocks and power are
4050                          * controlled entirely by the GMU
4051                          */
4052
4053                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4054
4055                         iommus = <&adreno_smmu 0>;
4056
4057                         operating-points-v2 = <&gpu_opp_table>;
4058
4059                         qcom,gmu = <&gmu>;
4060
4061                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4062                         interconnect-names = "gfx-mem";
4063
4064                         gpu_opp_table: opp-table {
4065                                 compatible = "operating-points-v2";
4066
4067                                 opp-710000000 {
4068                                         opp-hz = /bits/ 64 <710000000>;
4069                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4070                                         opp-peak-kBps = <7216000>;
4071                                 };
4072
4073                                 opp-675000000 {
4074                                         opp-hz = /bits/ 64 <675000000>;
4075                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4076                                         opp-peak-kBps = <7216000>;
4077                                 };
4078
4079                                 opp-596000000 {
4080                                         opp-hz = /bits/ 64 <596000000>;
4081                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4082                                         opp-peak-kBps = <6220000>;
4083                                 };
4084
4085                                 opp-520000000 {
4086                                         opp-hz = /bits/ 64 <520000000>;
4087                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4088                                         opp-peak-kBps = <6220000>;
4089                                 };
4090
4091                                 opp-414000000 {
4092                                         opp-hz = /bits/ 64 <414000000>;
4093                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4094                                         opp-peak-kBps = <4068000>;
4095                                 };
4096
4097                                 opp-342000000 {
4098                                         opp-hz = /bits/ 64 <342000000>;
4099                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4100                                         opp-peak-kBps = <2724000>;
4101                                 };
4102
4103                                 opp-257000000 {
4104                                         opp-hz = /bits/ 64 <257000000>;
4105                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4106                                         opp-peak-kBps = <1648000>;
4107                                 };
4108                         };
4109                 };
4110
4111                 adreno_smmu: iommu@5040000 {
4112                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4113                         reg = <0 0x5040000 0 0x10000>;
4114                         #iommu-cells = <1>;
4115                         #global-interrupts = <2>;
4116                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4117                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4118                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4119                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4120                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4121                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4122                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4123                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4124                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4125                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4126                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4127                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4128                         clock-names = "bus", "iface";
4129
4130                         power-domains = <&gpucc GPU_CX_GDSC>;
4131                 };
4132
4133                 gmu: gmu@506a000 {
4134                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4135
4136                         reg = <0 0x506a000 0 0x30000>,
4137                               <0 0xb280000 0 0x10000>,
4138                               <0 0xb480000 0 0x10000>;
4139                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4140
4141                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4142                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4143                         interrupt-names = "hfi", "gmu";
4144
4145                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4146                                  <&gpucc GPU_CC_CXO_CLK>,
4147                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4148                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4149                         clock-names = "gmu", "cxo", "axi", "memnoc";
4150
4151                         power-domains = <&gpucc GPU_CX_GDSC>,
4152                                         <&gpucc GPU_GX_GDSC>;
4153                         power-domain-names = "cx", "gx";
4154
4155                         iommus = <&adreno_smmu 5>;
4156
4157                         operating-points-v2 = <&gmu_opp_table>;
4158
4159                         gmu_opp_table: opp-table {
4160                                 compatible = "operating-points-v2";
4161
4162                                 opp-400000000 {
4163                                         opp-hz = /bits/ 64 <400000000>;
4164                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4165                                 };
4166
4167                                 opp-200000000 {
4168                                         opp-hz = /bits/ 64 <200000000>;
4169                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4170                                 };
4171                         };
4172                 };
4173
4174                 dispcc: clock-controller@af00000 {
4175                         compatible = "qcom,sdm845-dispcc";
4176                         reg = <0 0x0af00000 0 0x10000>;
4177                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4178                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4179                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4180                                  <&dsi0_phy 0>,
4181                                  <&dsi0_phy 1>,
4182                                  <&dsi1_phy 0>,
4183                                  <&dsi1_phy 1>,
4184                                  <0>,
4185                                  <0>;
4186                         clock-names = "bi_tcxo",
4187                                       "gcc_disp_gpll0_clk_src",
4188                                       "gcc_disp_gpll0_div_clk_src",
4189                                       "dsi0_phy_pll_out_byteclk",
4190                                       "dsi0_phy_pll_out_dsiclk",
4191                                       "dsi1_phy_pll_out_byteclk",
4192                                       "dsi1_phy_pll_out_dsiclk",
4193                                       "dp_link_clk_divsel_ten",
4194                                       "dp_vco_divided_clk_src_mux";
4195                         #clock-cells = <1>;
4196                         #reset-cells = <1>;
4197                         #power-domain-cells = <1>;
4198                 };
4199
4200                 pdc_intc: interrupt-controller@b220000 {
4201                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4202                         reg = <0 0x0b220000 0 0x30000>;
4203                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4204                         #interrupt-cells = <2>;
4205                         interrupt-parent = <&intc>;
4206                         interrupt-controller;
4207                 };
4208
4209                 pdc_reset: reset-controller@b2e0000 {
4210                         compatible = "qcom,sdm845-pdc-global";
4211                         reg = <0 0x0b2e0000 0 0x20000>;
4212                         #reset-cells = <1>;
4213                 };
4214
4215                 tsens0: thermal-sensor@c263000 {
4216                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4217                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4218                               <0 0x0c222000 0 0x1ff>; /* SROT */
4219                         #qcom,sensors = <13>;
4220                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4221                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4222                         interrupt-names = "uplow", "critical";
4223                         #thermal-sensor-cells = <1>;
4224                 };
4225
4226                 tsens1: thermal-sensor@c265000 {
4227                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4228                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4229                               <0 0x0c223000 0 0x1ff>; /* SROT */
4230                         #qcom,sensors = <8>;
4231                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4232                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4233                         interrupt-names = "uplow", "critical";
4234                         #thermal-sensor-cells = <1>;
4235                 };
4236
4237                 aoss_reset: reset-controller@c2a0000 {
4238                         compatible = "qcom,sdm845-aoss-cc";
4239                         reg = <0 0x0c2a0000 0 0x31000>;
4240                         #reset-cells = <1>;
4241                 };
4242
4243                 aoss_qmp: qmp@c300000 {
4244                         compatible = "qcom,sdm845-aoss-qmp";
4245                         reg = <0 0x0c300000 0 0x100000>;
4246                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4247                         mboxes = <&apss_shared 0>;
4248
4249                         #clock-cells = <0>;
4250                         #power-domain-cells = <1>;
4251
4252                         cx_cdev: cx {
4253                                 #cooling-cells = <2>;
4254                         };
4255
4256                         ebi_cdev: ebi {
4257                                 #cooling-cells = <2>;
4258                         };
4259                 };
4260
4261                 spmi_bus: spmi@c440000 {
4262                         compatible = "qcom,spmi-pmic-arb";
4263                         reg = <0 0x0c440000 0 0x1100>,
4264                               <0 0x0c600000 0 0x2000000>,
4265                               <0 0x0e600000 0 0x100000>,
4266                               <0 0x0e700000 0 0xa0000>,
4267                               <0 0x0c40a000 0 0x26000>;
4268                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4269                         interrupt-names = "periph_irq";
4270                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4271                         qcom,ee = <0>;
4272                         qcom,channel = <0>;
4273                         #address-cells = <2>;
4274                         #size-cells = <0>;
4275                         interrupt-controller;
4276                         #interrupt-cells = <4>;
4277                         cell-index = <0>;
4278                 };
4279
4280                 imem@146bf000 {
4281                         compatible = "simple-mfd";
4282                         reg = <0 0x146bf000 0 0x1000>;
4283
4284                         #address-cells = <1>;
4285                         #size-cells = <1>;
4286
4287                         ranges = <0 0 0x146bf000 0x1000>;
4288
4289                         pil-reloc@94c {
4290                                 compatible = "qcom,pil-reloc-info";
4291                                 reg = <0x94c 0xc8>;
4292                         };
4293                 };
4294
4295                 apps_smmu: iommu@15000000 {
4296                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4297                         reg = <0 0x15000000 0 0x80000>;
4298                         #iommu-cells = <2>;
4299                         #global-interrupts = <1>;
4300                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4301                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4302                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4303                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4304                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4305                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4306                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4307                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4308                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4309                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4310                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4311                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4312                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4313                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4314                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4315                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4316                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4317                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4318                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4319                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4320                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4321                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4322                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4323                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4324                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4325                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4326                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4327                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4328                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4329                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4330                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4331                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4332                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4333                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4334                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4335                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4336                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4337                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4338                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4339                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4340                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4341                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4342                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4343                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4344                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4345                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4346                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4347                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4348                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4349                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4350                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4351                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4352                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4353                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4354                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4355                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4356                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4357                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4358                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4359                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4360                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4361                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4362                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4363                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4364                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4365                 };
4366
4367                 lpasscc: clock-controller@17014000 {
4368                         compatible = "qcom,sdm845-lpasscc";
4369                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4370                         reg-names = "cc", "qdsp6ss";
4371                         #clock-cells = <1>;
4372                         status = "disabled";
4373                 };
4374
4375                 gladiator_noc: interconnect@17900000 {
4376                         compatible = "qcom,sdm845-gladiator-noc";
4377                         reg = <0 0x17900000 0 0xd080>;
4378                         #interconnect-cells = <2>;
4379                         qcom,bcm-voters = <&apps_bcm_voter>;
4380                 };
4381
4382                 watchdog@17980000 {
4383                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4384                         reg = <0 0x17980000 0 0x1000>;
4385                         clocks = <&sleep_clk>;
4386                 };
4387
4388                 apss_shared: mailbox@17990000 {
4389                         compatible = "qcom,sdm845-apss-shared";
4390                         reg = <0 0x17990000 0 0x1000>;
4391                         #mbox-cells = <1>;
4392                 };
4393
4394                 apps_rsc: rsc@179c0000 {
4395                         label = "apps_rsc";
4396                         compatible = "qcom,rpmh-rsc";
4397                         reg = <0 0x179c0000 0 0x10000>,
4398                               <0 0x179d0000 0 0x10000>,
4399                               <0 0x179e0000 0 0x10000>;
4400                         reg-names = "drv-0", "drv-1", "drv-2";
4401                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4402                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4403                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4404                         qcom,tcs-offset = <0xd00>;
4405                         qcom,drv-id = <2>;
4406                         qcom,tcs-config = <ACTIVE_TCS  2>,
4407                                           <SLEEP_TCS   3>,
4408                                           <WAKE_TCS    3>,
4409                                           <CONTROL_TCS 1>;
4410
4411                         apps_bcm_voter: bcm-voter {
4412                                 compatible = "qcom,bcm-voter";
4413                         };
4414
4415                         rpmhcc: clock-controller {
4416                                 compatible = "qcom,sdm845-rpmh-clk";
4417                                 #clock-cells = <1>;
4418                                 clock-names = "xo";
4419                                 clocks = <&xo_board>;
4420                         };
4421
4422                         rpmhpd: power-controller {
4423                                 compatible = "qcom,sdm845-rpmhpd";
4424                                 #power-domain-cells = <1>;
4425                                 operating-points-v2 = <&rpmhpd_opp_table>;
4426
4427                                 rpmhpd_opp_table: opp-table {
4428                                         compatible = "operating-points-v2";
4429
4430                                         rpmhpd_opp_ret: opp1 {
4431                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4432                                         };
4433
4434                                         rpmhpd_opp_min_svs: opp2 {
4435                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4436                                         };
4437
4438                                         rpmhpd_opp_low_svs: opp3 {
4439                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4440                                         };
4441
4442                                         rpmhpd_opp_svs: opp4 {
4443                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4444                                         };
4445
4446                                         rpmhpd_opp_svs_l1: opp5 {
4447                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4448                                         };
4449
4450                                         rpmhpd_opp_nom: opp6 {
4451                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4452                                         };
4453
4454                                         rpmhpd_opp_nom_l1: opp7 {
4455                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4456                                         };
4457
4458                                         rpmhpd_opp_nom_l2: opp8 {
4459                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4460                                         };
4461
4462                                         rpmhpd_opp_turbo: opp9 {
4463                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4464                                         };
4465
4466                                         rpmhpd_opp_turbo_l1: opp10 {
4467                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4468                                         };
4469                                 };
4470                         };
4471                 };
4472
4473                 intc: interrupt-controller@17a00000 {
4474                         compatible = "arm,gic-v3";
4475                         #address-cells = <2>;
4476                         #size-cells = <2>;
4477                         ranges;
4478                         #interrupt-cells = <3>;
4479                         interrupt-controller;
4480                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
4481                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
4482                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4483
4484                         msi-controller@17a40000 {
4485                                 compatible = "arm,gic-v3-its";
4486                                 msi-controller;
4487                                 #msi-cells = <1>;
4488                                 reg = <0 0x17a40000 0 0x20000>;
4489                                 status = "disabled";
4490                         };
4491                 };
4492
4493                 slimbam: dma-controller@17184000 {
4494                         compatible = "qcom,bam-v1.7.0";
4495                         qcom,controlled-remotely;
4496                         reg = <0 0x17184000 0 0x2a000>;
4497                         num-channels  = <31>;
4498                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4499                         #dma-cells = <1>;
4500                         qcom,ee = <1>;
4501                         qcom,num-ees = <2>;
4502                         iommus = <&apps_smmu 0x1806 0x0>;
4503                 };
4504
4505                 timer@17c90000 {
4506                         #address-cells = <2>;
4507                         #size-cells = <2>;
4508                         ranges;
4509                         compatible = "arm,armv7-timer-mem";
4510                         reg = <0 0x17c90000 0 0x1000>;
4511
4512                         frame@17ca0000 {
4513                                 frame-number = <0>;
4514                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4515                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4516                                 reg = <0 0x17ca0000 0 0x1000>,
4517                                       <0 0x17cb0000 0 0x1000>;
4518                         };
4519
4520                         frame@17cc0000 {
4521                                 frame-number = <1>;
4522                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4523                                 reg = <0 0x17cc0000 0 0x1000>;
4524                                 status = "disabled";
4525                         };
4526
4527                         frame@17cd0000 {
4528                                 frame-number = <2>;
4529                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4530                                 reg = <0 0x17cd0000 0 0x1000>;
4531                                 status = "disabled";
4532                         };
4533
4534                         frame@17ce0000 {
4535                                 frame-number = <3>;
4536                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4537                                 reg = <0 0x17ce0000 0 0x1000>;
4538                                 status = "disabled";
4539                         };
4540
4541                         frame@17cf0000 {
4542                                 frame-number = <4>;
4543                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4544                                 reg = <0 0x17cf0000 0 0x1000>;
4545                                 status = "disabled";
4546                         };
4547
4548                         frame@17d00000 {
4549                                 frame-number = <5>;
4550                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4551                                 reg = <0 0x17d00000 0 0x1000>;
4552                                 status = "disabled";
4553                         };
4554
4555                         frame@17d10000 {
4556                                 frame-number = <6>;
4557                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4558                                 reg = <0 0x17d10000 0 0x1000>;
4559                                 status = "disabled";
4560                         };
4561                 };
4562
4563                 osm_l3: interconnect@17d41000 {
4564                         compatible = "qcom,sdm845-osm-l3";
4565                         reg = <0 0x17d41000 0 0x1400>;
4566
4567                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4568                         clock-names = "xo", "alternate";
4569
4570                         #interconnect-cells = <1>;
4571                 };
4572
4573                 cpufreq_hw: cpufreq@17d43000 {
4574                         compatible = "qcom,cpufreq-hw";
4575                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4576                         reg-names = "freq-domain0", "freq-domain1";
4577
4578                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4579                         clock-names = "xo", "alternate";
4580
4581                         #freq-domain-cells = <1>;
4582                 };
4583
4584                 wifi: wifi@18800000 {
4585                         compatible = "qcom,wcn3990-wifi";
4586                         status = "disabled";
4587                         reg = <0 0x18800000 0 0x800000>;
4588                         reg-names = "membase";
4589                         memory-region = <&wlan_msa_mem>;
4590                         clock-names = "cxo_ref_clk_pin";
4591                         clocks = <&rpmhcc RPMH_RF_CLK2>;
4592                         interrupts =
4593                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4594                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4595                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4596                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4597                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4598                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4599                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4600                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4601                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4602                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4603                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4604                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4605                         iommus = <&apps_smmu 0x0040 0x1>;
4606                 };
4607         };
4608
4609         thermal-zones {
4610                 cpu0-thermal {
4611                         polling-delay-passive = <250>;
4612                         polling-delay = <1000>;
4613
4614                         thermal-sensors = <&tsens0 1>;
4615
4616                         trips {
4617                                 cpu0_alert0: trip-point0 {
4618                                         temperature = <90000>;
4619                                         hysteresis = <2000>;
4620                                         type = "passive";
4621                                 };
4622
4623                                 cpu0_alert1: trip-point1 {
4624                                         temperature = <95000>;
4625                                         hysteresis = <2000>;
4626                                         type = "passive";
4627                                 };
4628
4629                                 cpu0_crit: cpu_crit {
4630                                         temperature = <110000>;
4631                                         hysteresis = <1000>;
4632                                         type = "critical";
4633                                 };
4634                         };
4635
4636                         cooling-maps {
4637                                 map0 {
4638                                         trip = <&cpu0_alert0>;
4639                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4641                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4642                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4643                                 };
4644                                 map1 {
4645                                         trip = <&cpu0_alert1>;
4646                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4648                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4649                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4650                                 };
4651                         };
4652                 };
4653
4654                 cpu1-thermal {
4655                         polling-delay-passive = <250>;
4656                         polling-delay = <1000>;
4657
4658                         thermal-sensors = <&tsens0 2>;
4659
4660                         trips {
4661                                 cpu1_alert0: trip-point0 {
4662                                         temperature = <90000>;
4663                                         hysteresis = <2000>;
4664                                         type = "passive";
4665                                 };
4666
4667                                 cpu1_alert1: trip-point1 {
4668                                         temperature = <95000>;
4669                                         hysteresis = <2000>;
4670                                         type = "passive";
4671                                 };
4672
4673                                 cpu1_crit: cpu_crit {
4674                                         temperature = <110000>;
4675                                         hysteresis = <1000>;
4676                                         type = "critical";
4677                                 };
4678                         };
4679
4680                         cooling-maps {
4681                                 map0 {
4682                                         trip = <&cpu1_alert0>;
4683                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4684                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4685                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4686                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4687                                 };
4688                                 map1 {
4689                                         trip = <&cpu1_alert1>;
4690                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4691                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4692                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4693                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4694                                 };
4695                         };
4696                 };
4697
4698                 cpu2-thermal {
4699                         polling-delay-passive = <250>;
4700                         polling-delay = <1000>;
4701
4702                         thermal-sensors = <&tsens0 3>;
4703
4704                         trips {
4705                                 cpu2_alert0: trip-point0 {
4706                                         temperature = <90000>;
4707                                         hysteresis = <2000>;
4708                                         type = "passive";
4709                                 };
4710
4711                                 cpu2_alert1: trip-point1 {
4712                                         temperature = <95000>;
4713                                         hysteresis = <2000>;
4714                                         type = "passive";
4715                                 };
4716
4717                                 cpu2_crit: cpu_crit {
4718                                         temperature = <110000>;
4719                                         hysteresis = <1000>;
4720                                         type = "critical";
4721                                 };
4722                         };
4723
4724                         cooling-maps {
4725                                 map0 {
4726                                         trip = <&cpu2_alert0>;
4727                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4728                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4729                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4730                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4731                                 };
4732                                 map1 {
4733                                         trip = <&cpu2_alert1>;
4734                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4735                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4736                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4737                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4738                                 };
4739                         };
4740                 };
4741
4742                 cpu3-thermal {
4743                         polling-delay-passive = <250>;
4744                         polling-delay = <1000>;
4745
4746                         thermal-sensors = <&tsens0 4>;
4747
4748                         trips {
4749                                 cpu3_alert0: trip-point0 {
4750                                         temperature = <90000>;
4751                                         hysteresis = <2000>;
4752                                         type = "passive";
4753                                 };
4754
4755                                 cpu3_alert1: trip-point1 {
4756                                         temperature = <95000>;
4757                                         hysteresis = <2000>;
4758                                         type = "passive";
4759                                 };
4760
4761                                 cpu3_crit: cpu_crit {
4762                                         temperature = <110000>;
4763                                         hysteresis = <1000>;
4764                                         type = "critical";
4765                                 };
4766                         };
4767
4768                         cooling-maps {
4769                                 map0 {
4770                                         trip = <&cpu3_alert0>;
4771                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4772                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4773                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4775                                 };
4776                                 map1 {
4777                                         trip = <&cpu3_alert1>;
4778                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4779                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4780                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4781                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4782                                 };
4783                         };
4784                 };
4785
4786                 cpu4-thermal {
4787                         polling-delay-passive = <250>;
4788                         polling-delay = <1000>;
4789
4790                         thermal-sensors = <&tsens0 7>;
4791
4792                         trips {
4793                                 cpu4_alert0: trip-point0 {
4794                                         temperature = <90000>;
4795                                         hysteresis = <2000>;
4796                                         type = "passive";
4797                                 };
4798
4799                                 cpu4_alert1: trip-point1 {
4800                                         temperature = <95000>;
4801                                         hysteresis = <2000>;
4802                                         type = "passive";
4803                                 };
4804
4805                                 cpu4_crit: cpu_crit {
4806                                         temperature = <110000>;
4807                                         hysteresis = <1000>;
4808                                         type = "critical";
4809                                 };
4810                         };
4811
4812                         cooling-maps {
4813                                 map0 {
4814                                         trip = <&cpu4_alert0>;
4815                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4816                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4819                                 };
4820                                 map1 {
4821                                         trip = <&cpu4_alert1>;
4822                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4823                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4824                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4825                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4826                                 };
4827                         };
4828                 };
4829
4830                 cpu5-thermal {
4831                         polling-delay-passive = <250>;
4832                         polling-delay = <1000>;
4833
4834                         thermal-sensors = <&tsens0 8>;
4835
4836                         trips {
4837                                 cpu5_alert0: trip-point0 {
4838                                         temperature = <90000>;
4839                                         hysteresis = <2000>;
4840                                         type = "passive";
4841                                 };
4842
4843                                 cpu5_alert1: trip-point1 {
4844                                         temperature = <95000>;
4845                                         hysteresis = <2000>;
4846                                         type = "passive";
4847                                 };
4848
4849                                 cpu5_crit: cpu_crit {
4850                                         temperature = <110000>;
4851                                         hysteresis = <1000>;
4852                                         type = "critical";
4853                                 };
4854                         };
4855
4856                         cooling-maps {
4857                                 map0 {
4858                                         trip = <&cpu5_alert0>;
4859                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863                                 };
4864                                 map1 {
4865                                         trip = <&cpu5_alert1>;
4866                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4867                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4868                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4869                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4870                                 };
4871                         };
4872                 };
4873
4874                 cpu6-thermal {
4875                         polling-delay-passive = <250>;
4876                         polling-delay = <1000>;
4877
4878                         thermal-sensors = <&tsens0 9>;
4879
4880                         trips {
4881                                 cpu6_alert0: trip-point0 {
4882                                         temperature = <90000>;
4883                                         hysteresis = <2000>;
4884                                         type = "passive";
4885                                 };
4886
4887                                 cpu6_alert1: trip-point1 {
4888                                         temperature = <95000>;
4889                                         hysteresis = <2000>;
4890                                         type = "passive";
4891                                 };
4892
4893                                 cpu6_crit: cpu_crit {
4894                                         temperature = <110000>;
4895                                         hysteresis = <1000>;
4896                                         type = "critical";
4897                                 };
4898                         };
4899
4900                         cooling-maps {
4901                                 map0 {
4902                                         trip = <&cpu6_alert0>;
4903                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4906                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4907                                 };
4908                                 map1 {
4909                                         trip = <&cpu6_alert1>;
4910                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4911                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4912                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4913                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4914                                 };
4915                         };
4916                 };
4917
4918                 cpu7-thermal {
4919                         polling-delay-passive = <250>;
4920                         polling-delay = <1000>;
4921
4922                         thermal-sensors = <&tsens0 10>;
4923
4924                         trips {
4925                                 cpu7_alert0: trip-point0 {
4926                                         temperature = <90000>;
4927                                         hysteresis = <2000>;
4928                                         type = "passive";
4929                                 };
4930
4931                                 cpu7_alert1: trip-point1 {
4932                                         temperature = <95000>;
4933                                         hysteresis = <2000>;
4934                                         type = "passive";
4935                                 };
4936
4937                                 cpu7_crit: cpu_crit {
4938                                         temperature = <110000>;
4939                                         hysteresis = <1000>;
4940                                         type = "critical";
4941                                 };
4942                         };
4943
4944                         cooling-maps {
4945                                 map0 {
4946                                         trip = <&cpu7_alert0>;
4947                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4949                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4950                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4951                                 };
4952                                 map1 {
4953                                         trip = <&cpu7_alert1>;
4954                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4955                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4956                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4957                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4958                                 };
4959                         };
4960                 };
4961
4962                 aoss0-thermal {
4963                         polling-delay-passive = <250>;
4964                         polling-delay = <1000>;
4965
4966                         thermal-sensors = <&tsens0 0>;
4967
4968                         trips {
4969                                 aoss0_alert0: trip-point0 {
4970                                         temperature = <90000>;
4971                                         hysteresis = <2000>;
4972                                         type = "hot";
4973                                 };
4974                         };
4975                 };
4976
4977                 cluster0-thermal {
4978                         polling-delay-passive = <250>;
4979                         polling-delay = <1000>;
4980
4981                         thermal-sensors = <&tsens0 5>;
4982
4983                         trips {
4984                                 cluster0_alert0: trip-point0 {
4985                                         temperature = <90000>;
4986                                         hysteresis = <2000>;
4987                                         type = "hot";
4988                                 };
4989                                 cluster0_crit: cluster0_crit {
4990                                         temperature = <110000>;
4991                                         hysteresis = <2000>;
4992                                         type = "critical";
4993                                 };
4994                         };
4995                 };
4996
4997                 cluster1-thermal {
4998                         polling-delay-passive = <250>;
4999                         polling-delay = <1000>;
5000
5001                         thermal-sensors = <&tsens0 6>;
5002
5003                         trips {
5004                                 cluster1_alert0: trip-point0 {
5005                                         temperature = <90000>;
5006                                         hysteresis = <2000>;
5007                                         type = "hot";
5008                                 };
5009                                 cluster1_crit: cluster1_crit {
5010                                         temperature = <110000>;
5011                                         hysteresis = <2000>;
5012                                         type = "critical";
5013                                 };
5014                         };
5015                 };
5016
5017                 gpu-thermal-top {
5018                         polling-delay-passive = <250>;
5019                         polling-delay = <1000>;
5020
5021                         thermal-sensors = <&tsens0 11>;
5022
5023                         trips {
5024                                 gpu1_alert0: trip-point0 {
5025                                         temperature = <90000>;
5026                                         hysteresis = <2000>;
5027                                         type = "hot";
5028                                 };
5029                         };
5030                 };
5031
5032                 gpu-thermal-bottom {
5033                         polling-delay-passive = <250>;
5034                         polling-delay = <1000>;
5035
5036                         thermal-sensors = <&tsens0 12>;
5037
5038                         trips {
5039                                 gpu2_alert0: trip-point0 {
5040                                         temperature = <90000>;
5041                                         hysteresis = <2000>;
5042                                         type = "hot";
5043                                 };
5044                         };
5045                 };
5046
5047                 aoss1-thermal {
5048                         polling-delay-passive = <250>;
5049                         polling-delay = <1000>;
5050
5051                         thermal-sensors = <&tsens1 0>;
5052
5053                         trips {
5054                                 aoss1_alert0: trip-point0 {
5055                                         temperature = <90000>;
5056                                         hysteresis = <2000>;
5057                                         type = "hot";
5058                                 };
5059                         };
5060                 };
5061
5062                 q6-modem-thermal {
5063                         polling-delay-passive = <250>;
5064                         polling-delay = <1000>;
5065
5066                         thermal-sensors = <&tsens1 1>;
5067
5068                         trips {
5069                                 q6_modem_alert0: trip-point0 {
5070                                         temperature = <90000>;
5071                                         hysteresis = <2000>;
5072                                         type = "hot";
5073                                 };
5074                         };
5075                 };
5076
5077                 mem-thermal {
5078                         polling-delay-passive = <250>;
5079                         polling-delay = <1000>;
5080
5081                         thermal-sensors = <&tsens1 2>;
5082
5083                         trips {
5084                                 mem_alert0: trip-point0 {
5085                                         temperature = <90000>;
5086                                         hysteresis = <2000>;
5087                                         type = "hot";
5088                                 };
5089                         };
5090                 };
5091
5092                 wlan-thermal {
5093                         polling-delay-passive = <250>;
5094                         polling-delay = <1000>;
5095
5096                         thermal-sensors = <&tsens1 3>;
5097
5098                         trips {
5099                                 wlan_alert0: trip-point0 {
5100                                         temperature = <90000>;
5101                                         hysteresis = <2000>;
5102                                         type = "hot";
5103                                 };
5104                         };
5105                 };
5106
5107                 q6-hvx-thermal {
5108                         polling-delay-passive = <250>;
5109                         polling-delay = <1000>;
5110
5111                         thermal-sensors = <&tsens1 4>;
5112
5113                         trips {
5114                                 q6_hvx_alert0: trip-point0 {
5115                                         temperature = <90000>;
5116                                         hysteresis = <2000>;
5117                                         type = "hot";
5118                                 };
5119                         };
5120                 };
5121
5122                 camera-thermal {
5123                         polling-delay-passive = <250>;
5124                         polling-delay = <1000>;
5125
5126                         thermal-sensors = <&tsens1 5>;
5127
5128                         trips {
5129                                 camera_alert0: trip-point0 {
5130                                         temperature = <90000>;
5131                                         hysteresis = <2000>;
5132                                         type = "hot";
5133                                 };
5134                         };
5135                 };
5136
5137                 video-thermal {
5138                         polling-delay-passive = <250>;
5139                         polling-delay = <1000>;
5140
5141                         thermal-sensors = <&tsens1 6>;
5142
5143                         trips {
5144                                 video_alert0: trip-point0 {
5145                                         temperature = <90000>;
5146                                         hysteresis = <2000>;
5147                                         type = "hot";
5148                                 };
5149                         };
5150                 };
5151
5152                 modem-thermal {
5153                         polling-delay-passive = <250>;
5154                         polling-delay = <1000>;
5155
5156                         thermal-sensors = <&tsens1 7>;
5157
5158                         trips {
5159                                 modem_alert0: trip-point0 {
5160                                         temperature = <90000>;
5161                                         hysteresis = <2000>;
5162                                         type = "hot";
5163                                 };
5164                         };
5165                 };
5166         };
5167 };