1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sdm845.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,apr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
73 device_type = "memory";
74 /* We expect the bootloader to fill in the size */
75 reg = <0 0x80000000 0 0>;
83 hyp_mem: hyp-mem@85700000 {
84 reg = <0 0x85700000 0 0x600000>;
88 xbl_mem: xbl-mem@85e00000 {
89 reg = <0 0x85e00000 0 0x100000>;
93 aop_mem: aop-mem@85fc0000 {
94 reg = <0 0x85fc0000 0 0x20000>;
98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
99 compatible = "qcom,cmd-db";
100 reg = <0x0 0x85fe0000 0 0x20000>;
105 compatible = "qcom,smem";
106 reg = <0x0 0x86000000 0 0x200000>;
108 hwlocks = <&tcsr_mutex 3>;
111 tz_mem: tz@86200000 {
112 reg = <0 0x86200000 0 0x2d00000>;
116 rmtfs_mem: rmtfs@88f00000 {
117 compatible = "qcom,rmtfs-mem";
118 reg = <0 0x88f00000 0 0x200000>;
121 qcom,client-id = <1>;
125 qseecom_mem: qseecom@8ab00000 {
126 reg = <0 0x8ab00000 0 0x1400000>;
130 camera_mem: camera-mem@8bf00000 {
131 reg = <0 0x8bf00000 0 0x500000>;
135 ipa_fw_mem: ipa-fw@8c400000 {
136 reg = <0 0x8c400000 0 0x10000>;
140 ipa_gsi_mem: ipa-gsi@8c410000 {
141 reg = <0 0x8c410000 0 0x5000>;
145 gpu_mem: gpu@8c415000 {
146 reg = <0 0x8c415000 0 0x2000>;
150 adsp_mem: adsp@8c500000 {
151 reg = <0 0x8c500000 0 0x1a00000>;
155 wlan_msa_mem: wlan-msa@8df00000 {
156 reg = <0 0x8df00000 0 0x100000>;
160 mpss_region: mpss@8e000000 {
161 reg = <0 0x8e000000 0 0x7800000>;
165 venus_mem: venus@95800000 {
166 reg = <0 0x95800000 0 0x500000>;
170 cdsp_mem: cdsp@95d00000 {
171 reg = <0 0x95d00000 0 0x800000>;
175 mba_region: mba@96500000 {
176 reg = <0 0x96500000 0 0x200000>;
180 slpi_mem: slpi@96700000 {
181 reg = <0 0x96700000 0 0x1400000>;
185 spss_mem: spss@97b00000 {
186 reg = <0 0x97b00000 0 0x100000>;
192 #address-cells = <2>;
197 compatible = "qcom,kryo385";
199 enable-method = "psci";
200 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
203 capacity-dmips-mhz = <611>;
204 dynamic-power-coefficient = <290>;
205 qcom,freq-domain = <&cpufreq_hw 0>;
206 operating-points-v2 = <&cpu0_opp_table>;
207 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
209 #cooling-cells = <2>;
210 next-level-cache = <&L2_0>;
212 compatible = "cache";
213 next-level-cache = <&L3_0>;
215 compatible = "cache";
222 compatible = "qcom,kryo385";
224 enable-method = "psci";
225 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
228 capacity-dmips-mhz = <611>;
229 dynamic-power-coefficient = <290>;
230 qcom,freq-domain = <&cpufreq_hw 0>;
231 operating-points-v2 = <&cpu0_opp_table>;
232 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
233 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
234 #cooling-cells = <2>;
235 next-level-cache = <&L2_100>;
237 compatible = "cache";
238 next-level-cache = <&L3_0>;
244 compatible = "qcom,kryo385";
246 enable-method = "psci";
247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
250 capacity-dmips-mhz = <611>;
251 dynamic-power-coefficient = <290>;
252 qcom,freq-domain = <&cpufreq_hw 0>;
253 operating-points-v2 = <&cpu0_opp_table>;
254 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
255 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
256 #cooling-cells = <2>;
257 next-level-cache = <&L2_200>;
259 compatible = "cache";
260 next-level-cache = <&L3_0>;
266 compatible = "qcom,kryo385";
268 enable-method = "psci";
269 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
272 capacity-dmips-mhz = <611>;
273 dynamic-power-coefficient = <290>;
274 qcom,freq-domain = <&cpufreq_hw 0>;
275 operating-points-v2 = <&cpu0_opp_table>;
276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
278 #cooling-cells = <2>;
279 next-level-cache = <&L2_300>;
281 compatible = "cache";
282 next-level-cache = <&L3_0>;
288 compatible = "qcom,kryo385";
290 enable-method = "psci";
291 capacity-dmips-mhz = <1024>;
292 cpu-idle-states = <&BIG_CPU_SLEEP_0
295 dynamic-power-coefficient = <442>;
296 qcom,freq-domain = <&cpufreq_hw 1>;
297 operating-points-v2 = <&cpu4_opp_table>;
298 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
299 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
300 #cooling-cells = <2>;
301 next-level-cache = <&L2_400>;
303 compatible = "cache";
304 next-level-cache = <&L3_0>;
310 compatible = "qcom,kryo385";
312 enable-method = "psci";
313 capacity-dmips-mhz = <1024>;
314 cpu-idle-states = <&BIG_CPU_SLEEP_0
317 dynamic-power-coefficient = <442>;
318 qcom,freq-domain = <&cpufreq_hw 1>;
319 operating-points-v2 = <&cpu4_opp_table>;
320 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
321 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
322 #cooling-cells = <2>;
323 next-level-cache = <&L2_500>;
325 compatible = "cache";
326 next-level-cache = <&L3_0>;
332 compatible = "qcom,kryo385";
334 enable-method = "psci";
335 capacity-dmips-mhz = <1024>;
336 cpu-idle-states = <&BIG_CPU_SLEEP_0
339 dynamic-power-coefficient = <442>;
340 qcom,freq-domain = <&cpufreq_hw 1>;
341 operating-points-v2 = <&cpu4_opp_table>;
342 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
343 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
344 #cooling-cells = <2>;
345 next-level-cache = <&L2_600>;
347 compatible = "cache";
348 next-level-cache = <&L3_0>;
354 compatible = "qcom,kryo385";
356 enable-method = "psci";
357 capacity-dmips-mhz = <1024>;
358 cpu-idle-states = <&BIG_CPU_SLEEP_0
361 dynamic-power-coefficient = <442>;
362 qcom,freq-domain = <&cpufreq_hw 1>;
363 operating-points-v2 = <&cpu4_opp_table>;
364 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
365 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
366 #cooling-cells = <2>;
367 next-level-cache = <&L2_700>;
369 compatible = "cache";
370 next-level-cache = <&L3_0>;
411 entry-method = "psci";
413 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
414 compatible = "arm,idle-state";
415 idle-state-name = "little-power-down";
416 arm,psci-suspend-param = <0x40000003>;
417 entry-latency-us = <350>;
418 exit-latency-us = <461>;
419 min-residency-us = <1890>;
423 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
424 compatible = "arm,idle-state";
425 idle-state-name = "little-rail-power-down";
426 arm,psci-suspend-param = <0x40000004>;
427 entry-latency-us = <360>;
428 exit-latency-us = <531>;
429 min-residency-us = <3934>;
433 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
434 compatible = "arm,idle-state";
435 idle-state-name = "big-power-down";
436 arm,psci-suspend-param = <0x40000003>;
437 entry-latency-us = <264>;
438 exit-latency-us = <621>;
439 min-residency-us = <952>;
443 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
444 compatible = "arm,idle-state";
445 idle-state-name = "big-rail-power-down";
446 arm,psci-suspend-param = <0x40000004>;
447 entry-latency-us = <702>;
448 exit-latency-us = <1061>;
449 min-residency-us = <4488>;
453 CLUSTER_SLEEP_0: cluster-sleep-0 {
454 compatible = "arm,idle-state";
455 idle-state-name = "cluster-power-down";
456 arm,psci-suspend-param = <0x400000F4>;
457 entry-latency-us = <3263>;
458 exit-latency-us = <6562>;
459 min-residency-us = <9987>;
465 cpu0_opp_table: cpu0_opp_table {
466 compatible = "operating-points-v2";
469 cpu0_opp1: opp-300000000 {
470 opp-hz = /bits/ 64 <300000000>;
471 opp-peak-kBps = <800000 4800000>;
474 cpu0_opp2: opp-403200000 {
475 opp-hz = /bits/ 64 <403200000>;
476 opp-peak-kBps = <800000 4800000>;
479 cpu0_opp3: opp-480000000 {
480 opp-hz = /bits/ 64 <480000000>;
481 opp-peak-kBps = <800000 6451200>;
484 cpu0_opp4: opp-576000000 {
485 opp-hz = /bits/ 64 <576000000>;
486 opp-peak-kBps = <800000 6451200>;
489 cpu0_opp5: opp-652800000 {
490 opp-hz = /bits/ 64 <652800000>;
491 opp-peak-kBps = <800000 7680000>;
494 cpu0_opp6: opp-748800000 {
495 opp-hz = /bits/ 64 <748800000>;
496 opp-peak-kBps = <1804000 9216000>;
499 cpu0_opp7: opp-825600000 {
500 opp-hz = /bits/ 64 <825600000>;
501 opp-peak-kBps = <1804000 9216000>;
504 cpu0_opp8: opp-902400000 {
505 opp-hz = /bits/ 64 <902400000>;
506 opp-peak-kBps = <1804000 10444800>;
509 cpu0_opp9: opp-979200000 {
510 opp-hz = /bits/ 64 <979200000>;
511 opp-peak-kBps = <1804000 11980800>;
514 cpu0_opp10: opp-1056000000 {
515 opp-hz = /bits/ 64 <1056000000>;
516 opp-peak-kBps = <1804000 11980800>;
519 cpu0_opp11: opp-1132800000 {
520 opp-hz = /bits/ 64 <1132800000>;
521 opp-peak-kBps = <2188000 13516800>;
524 cpu0_opp12: opp-1228800000 {
525 opp-hz = /bits/ 64 <1228800000>;
526 opp-peak-kBps = <2188000 15052800>;
529 cpu0_opp13: opp-1324800000 {
530 opp-hz = /bits/ 64 <1324800000>;
531 opp-peak-kBps = <2188000 16588800>;
534 cpu0_opp14: opp-1420800000 {
535 opp-hz = /bits/ 64 <1420800000>;
536 opp-peak-kBps = <3072000 18124800>;
539 cpu0_opp15: opp-1516800000 {
540 opp-hz = /bits/ 64 <1516800000>;
541 opp-peak-kBps = <3072000 19353600>;
544 cpu0_opp16: opp-1612800000 {
545 opp-hz = /bits/ 64 <1612800000>;
546 opp-peak-kBps = <4068000 19353600>;
549 cpu0_opp17: opp-1689600000 {
550 opp-hz = /bits/ 64 <1689600000>;
551 opp-peak-kBps = <4068000 20889600>;
554 cpu0_opp18: opp-1766400000 {
555 opp-hz = /bits/ 64 <1766400000>;
556 opp-peak-kBps = <4068000 22425600>;
560 cpu4_opp_table: cpu4_opp_table {
561 compatible = "operating-points-v2";
564 cpu4_opp1: opp-300000000 {
565 opp-hz = /bits/ 64 <300000000>;
566 opp-peak-kBps = <800000 4800000>;
569 cpu4_opp2: opp-403200000 {
570 opp-hz = /bits/ 64 <403200000>;
571 opp-peak-kBps = <800000 4800000>;
574 cpu4_opp3: opp-480000000 {
575 opp-hz = /bits/ 64 <480000000>;
576 opp-peak-kBps = <1804000 4800000>;
579 cpu4_opp4: opp-576000000 {
580 opp-hz = /bits/ 64 <576000000>;
581 opp-peak-kBps = <1804000 4800000>;
584 cpu4_opp5: opp-652800000 {
585 opp-hz = /bits/ 64 <652800000>;
586 opp-peak-kBps = <1804000 4800000>;
589 cpu4_opp6: opp-748800000 {
590 opp-hz = /bits/ 64 <748800000>;
591 opp-peak-kBps = <1804000 4800000>;
594 cpu4_opp7: opp-825600000 {
595 opp-hz = /bits/ 64 <825600000>;
596 opp-peak-kBps = <2188000 9216000>;
599 cpu4_opp8: opp-902400000 {
600 opp-hz = /bits/ 64 <902400000>;
601 opp-peak-kBps = <2188000 9216000>;
604 cpu4_opp9: opp-979200000 {
605 opp-hz = /bits/ 64 <979200000>;
606 opp-peak-kBps = <2188000 9216000>;
609 cpu4_opp10: opp-1056000000 {
610 opp-hz = /bits/ 64 <1056000000>;
611 opp-peak-kBps = <3072000 9216000>;
614 cpu4_opp11: opp-1132800000 {
615 opp-hz = /bits/ 64 <1132800000>;
616 opp-peak-kBps = <3072000 11980800>;
619 cpu4_opp12: opp-1209600000 {
620 opp-hz = /bits/ 64 <1209600000>;
621 opp-peak-kBps = <4068000 11980800>;
624 cpu4_opp13: opp-1286400000 {
625 opp-hz = /bits/ 64 <1286400000>;
626 opp-peak-kBps = <4068000 11980800>;
629 cpu4_opp14: opp-1363200000 {
630 opp-hz = /bits/ 64 <1363200000>;
631 opp-peak-kBps = <4068000 15052800>;
634 cpu4_opp15: opp-1459200000 {
635 opp-hz = /bits/ 64 <1459200000>;
636 opp-peak-kBps = <4068000 15052800>;
639 cpu4_opp16: opp-1536000000 {
640 opp-hz = /bits/ 64 <1536000000>;
641 opp-peak-kBps = <5412000 15052800>;
644 cpu4_opp17: opp-1612800000 {
645 opp-hz = /bits/ 64 <1612800000>;
646 opp-peak-kBps = <5412000 15052800>;
649 cpu4_opp18: opp-1689600000 {
650 opp-hz = /bits/ 64 <1689600000>;
651 opp-peak-kBps = <5412000 19353600>;
654 cpu4_opp19: opp-1766400000 {
655 opp-hz = /bits/ 64 <1766400000>;
656 opp-peak-kBps = <6220000 19353600>;
659 cpu4_opp20: opp-1843200000 {
660 opp-hz = /bits/ 64 <1843200000>;
661 opp-peak-kBps = <6220000 19353600>;
664 cpu4_opp21: opp-1920000000 {
665 opp-hz = /bits/ 64 <1920000000>;
666 opp-peak-kBps = <7216000 19353600>;
669 cpu4_opp22: opp-1996800000 {
670 opp-hz = /bits/ 64 <1996800000>;
671 opp-peak-kBps = <7216000 20889600>;
674 cpu4_opp23: opp-2092800000 {
675 opp-hz = /bits/ 64 <2092800000>;
676 opp-peak-kBps = <7216000 20889600>;
679 cpu4_opp24: opp-2169600000 {
680 opp-hz = /bits/ 64 <2169600000>;
681 opp-peak-kBps = <7216000 20889600>;
684 cpu4_opp25: opp-2246400000 {
685 opp-hz = /bits/ 64 <2246400000>;
686 opp-peak-kBps = <7216000 20889600>;
689 cpu4_opp26: opp-2323200000 {
690 opp-hz = /bits/ 64 <2323200000>;
691 opp-peak-kBps = <7216000 20889600>;
694 cpu4_opp27: opp-2400000000 {
695 opp-hz = /bits/ 64 <2400000000>;
696 opp-peak-kBps = <7216000 22425600>;
699 cpu4_opp28: opp-2476800000 {
700 opp-hz = /bits/ 64 <2476800000>;
701 opp-peak-kBps = <7216000 22425600>;
704 cpu4_opp29: opp-2553600000 {
705 opp-hz = /bits/ 64 <2553600000>;
706 opp-peak-kBps = <7216000 22425600>;
709 cpu4_opp30: opp-2649600000 {
710 opp-hz = /bits/ 64 <2649600000>;
711 opp-peak-kBps = <7216000 22425600>;
714 cpu4_opp31: opp-2745600000 {
715 opp-hz = /bits/ 64 <2745600000>;
716 opp-peak-kBps = <7216000 25497600>;
719 cpu4_opp32: opp-2803200000 {
720 opp-hz = /bits/ 64 <2803200000>;
721 opp-peak-kBps = <7216000 25497600>;
726 compatible = "arm,armv8-pmuv3";
727 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
731 compatible = "arm,armv8-timer";
732 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
733 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
734 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
735 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
740 compatible = "fixed-clock";
742 clock-frequency = <38400000>;
743 clock-output-names = "xo_board";
746 sleep_clk: sleep-clk {
747 compatible = "fixed-clock";
749 clock-frequency = <32764>;
755 compatible = "qcom,scm-sdm845", "qcom,scm";
759 adsp_pas: remoteproc-adsp {
760 compatible = "qcom,sdm845-adsp-pas";
762 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
763 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
764 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
765 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
766 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
767 interrupt-names = "wdog", "fatal", "ready",
768 "handover", "stop-ack";
770 clocks = <&rpmhcc RPMH_CXO_CLK>;
773 memory-region = <&adsp_mem>;
775 qcom,qmp = <&aoss_qmp>;
777 qcom,smem-states = <&adsp_smp2p_out 0>;
778 qcom,smem-state-names = "stop";
783 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
785 qcom,remote-pid = <2>;
786 mboxes = <&apss_shared 8>;
789 compatible = "qcom,apr-v2";
790 qcom,glink-channels = "apr_audio_svc";
791 qcom,domain = <APR_DOMAIN_ADSP>;
792 #address-cells = <1>;
794 qcom,intents = <512 20>;
797 reg = <APR_SVC_ADSP_CORE>;
798 compatible = "qcom,q6core";
799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
802 q6afe: apr-service@4 {
803 compatible = "qcom,q6afe";
805 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
807 compatible = "qcom,q6afe-dais";
808 #address-cells = <1>;
810 #sound-dai-cells = <1>;
814 q6asm: apr-service@7 {
815 compatible = "qcom,q6asm";
817 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
819 compatible = "qcom,q6asm-dais";
820 #address-cells = <1>;
822 #sound-dai-cells = <1>;
823 iommus = <&apps_smmu 0x1821 0x0>;
827 q6adm: apr-service@8 {
828 compatible = "qcom,q6adm";
830 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
832 compatible = "qcom,q6adm-routing";
833 #sound-dai-cells = <0>;
839 compatible = "qcom,fastrpc";
840 qcom,glink-channels = "fastrpcglink-apps-dsp";
842 qcom,non-secure-domain;
843 #address-cells = <1>;
847 compatible = "qcom,fastrpc-compute-cb";
849 iommus = <&apps_smmu 0x1823 0x0>;
853 compatible = "qcom,fastrpc-compute-cb";
855 iommus = <&apps_smmu 0x1824 0x0>;
861 cdsp_pas: remoteproc-cdsp {
862 compatible = "qcom,sdm845-cdsp-pas";
864 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
865 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
866 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
867 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
868 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
869 interrupt-names = "wdog", "fatal", "ready",
870 "handover", "stop-ack";
872 clocks = <&rpmhcc RPMH_CXO_CLK>;
875 memory-region = <&cdsp_mem>;
877 qcom,qmp = <&aoss_qmp>;
879 qcom,smem-states = <&cdsp_smp2p_out 0>;
880 qcom,smem-state-names = "stop";
885 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
887 qcom,remote-pid = <5>;
888 mboxes = <&apss_shared 4>;
890 compatible = "qcom,fastrpc";
891 qcom,glink-channels = "fastrpcglink-apps-dsp";
893 qcom,non-secure-domain;
894 #address-cells = <1>;
898 compatible = "qcom,fastrpc-compute-cb";
900 iommus = <&apps_smmu 0x1401 0x30>;
904 compatible = "qcom,fastrpc-compute-cb";
906 iommus = <&apps_smmu 0x1402 0x30>;
910 compatible = "qcom,fastrpc-compute-cb";
912 iommus = <&apps_smmu 0x1403 0x30>;
916 compatible = "qcom,fastrpc-compute-cb";
918 iommus = <&apps_smmu 0x1404 0x30>;
922 compatible = "qcom,fastrpc-compute-cb";
924 iommus = <&apps_smmu 0x1405 0x30>;
928 compatible = "qcom,fastrpc-compute-cb";
930 iommus = <&apps_smmu 0x1406 0x30>;
934 compatible = "qcom,fastrpc-compute-cb";
936 iommus = <&apps_smmu 0x1407 0x30>;
940 compatible = "qcom,fastrpc-compute-cb";
942 iommus = <&apps_smmu 0x1408 0x30>;
949 compatible = "qcom,tcsr-mutex";
950 syscon = <&tcsr_mutex_regs 0 0x1000>;
955 compatible = "qcom,smp2p";
956 qcom,smem = <94>, <432>;
958 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
960 mboxes = <&apss_shared 6>;
962 qcom,local-pid = <0>;
963 qcom,remote-pid = <5>;
965 cdsp_smp2p_out: master-kernel {
966 qcom,entry-name = "master-kernel";
967 #qcom,smem-state-cells = <1>;
970 cdsp_smp2p_in: slave-kernel {
971 qcom,entry-name = "slave-kernel";
973 interrupt-controller;
974 #interrupt-cells = <2>;
979 compatible = "qcom,smp2p";
980 qcom,smem = <443>, <429>;
982 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
984 mboxes = <&apss_shared 10>;
986 qcom,local-pid = <0>;
987 qcom,remote-pid = <2>;
989 adsp_smp2p_out: master-kernel {
990 qcom,entry-name = "master-kernel";
991 #qcom,smem-state-cells = <1>;
994 adsp_smp2p_in: slave-kernel {
995 qcom,entry-name = "slave-kernel";
997 interrupt-controller;
998 #interrupt-cells = <2>;
1003 compatible = "qcom,smp2p";
1004 qcom,smem = <435>, <428>;
1005 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1006 mboxes = <&apss_shared 14>;
1007 qcom,local-pid = <0>;
1008 qcom,remote-pid = <1>;
1010 modem_smp2p_out: master-kernel {
1011 qcom,entry-name = "master-kernel";
1012 #qcom,smem-state-cells = <1>;
1015 modem_smp2p_in: slave-kernel {
1016 qcom,entry-name = "slave-kernel";
1017 interrupt-controller;
1018 #interrupt-cells = <2>;
1021 ipa_smp2p_out: ipa-ap-to-modem {
1022 qcom,entry-name = "ipa";
1023 #qcom,smem-state-cells = <1>;
1026 ipa_smp2p_in: ipa-modem-to-ap {
1027 qcom,entry-name = "ipa";
1028 interrupt-controller;
1029 #interrupt-cells = <2>;
1034 compatible = "qcom,smp2p";
1035 qcom,smem = <481>, <430>;
1036 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1037 mboxes = <&apss_shared 26>;
1038 qcom,local-pid = <0>;
1039 qcom,remote-pid = <3>;
1041 slpi_smp2p_out: master-kernel {
1042 qcom,entry-name = "master-kernel";
1043 #qcom,smem-state-cells = <1>;
1046 slpi_smp2p_in: slave-kernel {
1047 qcom,entry-name = "slave-kernel";
1048 interrupt-controller;
1049 #interrupt-cells = <2>;
1054 compatible = "arm,psci-1.0";
1059 #address-cells = <2>;
1061 ranges = <0 0 0 0 0x10 0>;
1062 dma-ranges = <0 0 0 0 0x10 0>;
1063 compatible = "simple-bus";
1065 gcc: clock-controller@100000 {
1066 compatible = "qcom,gcc-sdm845";
1067 reg = <0 0x00100000 0 0x1f0000>;
1068 clocks = <&rpmhcc RPMH_CXO_CLK>,
1069 <&rpmhcc RPMH_CXO_CLK_A>,
1073 clock-names = "bi_tcxo",
1080 #power-domain-cells = <1>;
1084 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1085 reg = <0 0x00784000 0 0x8ff>;
1086 #address-cells = <1>;
1089 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1094 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1101 compatible = "qcom,prng-ee";
1102 reg = <0 0x00793000 0 0x1000>;
1103 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1104 clock-names = "core";
1107 qup_opp_table: qup-opp-table {
1108 compatible = "operating-points-v2";
1111 opp-hz = /bits/ 64 <50000000>;
1112 required-opps = <&rpmhpd_opp_min_svs>;
1116 opp-hz = /bits/ 64 <75000000>;
1117 required-opps = <&rpmhpd_opp_low_svs>;
1121 opp-hz = /bits/ 64 <100000000>;
1122 required-opps = <&rpmhpd_opp_svs>;
1126 opp-hz = /bits/ 64 <128000000>;
1127 required-opps = <&rpmhpd_opp_nom>;
1131 gpi_dma0: dma-controller@800000 {
1133 compatible = "qcom,sdm845-gpi-dma";
1134 reg = <0 0x00800000 0 0x60000>;
1135 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1148 dma-channels = <13>;
1149 dma-channel-mask = <0xfa>;
1150 iommus = <&apps_smmu 0x0016 0x0>;
1151 status = "disabled";
1154 qupv3_id_0: geniqup@8c0000 {
1155 compatible = "qcom,geni-se-qup";
1156 reg = <0 0x008c0000 0 0x6000>;
1157 clock-names = "m-ahb", "s-ahb";
1158 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1159 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1160 iommus = <&apps_smmu 0x3 0x0>;
1161 #address-cells = <2>;
1164 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1165 interconnect-names = "qup-core";
1166 status = "disabled";
1169 compatible = "qcom,geni-i2c";
1170 reg = <0 0x00880000 0 0x4000>;
1172 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&qup_i2c0_default>;
1175 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1176 #address-cells = <1>;
1178 power-domains = <&rpmhpd SDM845_CX>;
1179 operating-points-v2 = <&qup_opp_table>;
1180 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1181 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1182 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1183 interconnect-names = "qup-core", "qup-config", "qup-memory";
1184 status = "disabled";
1188 compatible = "qcom,geni-spi";
1189 reg = <0 0x00880000 0 0x4000>;
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_spi0_default>;
1194 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>;
1197 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1198 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1199 interconnect-names = "qup-core", "qup-config";
1200 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1201 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1202 dma-names = "tx", "rx";
1203 status = "disabled";
1206 uart0: serial@880000 {
1207 compatible = "qcom,geni-uart";
1208 reg = <0 0x00880000 0 0x4000>;
1210 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_uart0_default>;
1213 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1214 power-domains = <&rpmhpd SDM845_CX>;
1215 operating-points-v2 = <&qup_opp_table>;
1216 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1217 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1218 interconnect-names = "qup-core", "qup-config";
1219 status = "disabled";
1223 compatible = "qcom,geni-i2c";
1224 reg = <0 0x00884000 0 0x4000>;
1226 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&qup_i2c1_default>;
1229 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1230 #address-cells = <1>;
1232 power-domains = <&rpmhpd SDM845_CX>;
1233 operating-points-v2 = <&qup_opp_table>;
1234 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1235 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1236 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1237 interconnect-names = "qup-core", "qup-config", "qup-memory";
1238 status = "disabled";
1242 compatible = "qcom,geni-spi";
1243 reg = <0 0x00884000 0 0x4000>;
1245 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&qup_spi1_default>;
1248 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1249 #address-cells = <1>;
1251 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1252 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1253 interconnect-names = "qup-core", "qup-config";
1254 status = "disabled";
1257 uart1: serial@884000 {
1258 compatible = "qcom,geni-uart";
1259 reg = <0 0x00884000 0 0x4000>;
1261 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&qup_uart1_default>;
1264 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1265 power-domains = <&rpmhpd SDM845_CX>;
1266 operating-points-v2 = <&qup_opp_table>;
1267 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1268 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1269 interconnect-names = "qup-core", "qup-config";
1270 status = "disabled";
1274 compatible = "qcom,geni-i2c";
1275 reg = <0 0x00888000 0 0x4000>;
1277 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_i2c2_default>;
1280 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1281 #address-cells = <1>;
1283 power-domains = <&rpmhpd SDM845_CX>;
1284 operating-points-v2 = <&qup_opp_table>;
1285 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1286 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1287 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1288 interconnect-names = "qup-core", "qup-config", "qup-memory";
1289 status = "disabled";
1293 compatible = "qcom,geni-spi";
1294 reg = <0 0x00888000 0 0x4000>;
1296 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_spi2_default>;
1299 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1300 #address-cells = <1>;
1302 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1303 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1304 interconnect-names = "qup-core", "qup-config";
1305 status = "disabled";
1308 uart2: serial@888000 {
1309 compatible = "qcom,geni-uart";
1310 reg = <0 0x00888000 0 0x4000>;
1312 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&qup_uart2_default>;
1315 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1316 power-domains = <&rpmhpd SDM845_CX>;
1317 operating-points-v2 = <&qup_opp_table>;
1318 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1319 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1320 interconnect-names = "qup-core", "qup-config";
1321 status = "disabled";
1325 compatible = "qcom,geni-i2c";
1326 reg = <0 0x0088c000 0 0x4000>;
1328 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&qup_i2c3_default>;
1331 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1332 #address-cells = <1>;
1334 power-domains = <&rpmhpd SDM845_CX>;
1335 operating-points-v2 = <&qup_opp_table>;
1336 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1337 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1338 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1339 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340 status = "disabled";
1344 compatible = "qcom,geni-spi";
1345 reg = <0 0x0088c000 0 0x4000>;
1347 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&qup_spi3_default>;
1350 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1351 #address-cells = <1>;
1353 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1354 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1355 interconnect-names = "qup-core", "qup-config";
1356 status = "disabled";
1359 uart3: serial@88c000 {
1360 compatible = "qcom,geni-uart";
1361 reg = <0 0x0088c000 0 0x4000>;
1363 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&qup_uart3_default>;
1366 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1367 power-domains = <&rpmhpd SDM845_CX>;
1368 operating-points-v2 = <&qup_opp_table>;
1369 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1370 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1371 interconnect-names = "qup-core", "qup-config";
1372 status = "disabled";
1376 compatible = "qcom,geni-i2c";
1377 reg = <0 0x00890000 0 0x4000>;
1379 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&qup_i2c4_default>;
1382 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1383 #address-cells = <1>;
1385 power-domains = <&rpmhpd SDM845_CX>;
1386 operating-points-v2 = <&qup_opp_table>;
1387 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1388 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1389 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1390 interconnect-names = "qup-core", "qup-config", "qup-memory";
1391 status = "disabled";
1395 compatible = "qcom,geni-spi";
1396 reg = <0 0x00890000 0 0x4000>;
1398 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1399 pinctrl-names = "default";
1400 pinctrl-0 = <&qup_spi4_default>;
1401 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1402 #address-cells = <1>;
1404 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1405 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1406 interconnect-names = "qup-core", "qup-config";
1407 status = "disabled";
1410 uart4: serial@890000 {
1411 compatible = "qcom,geni-uart";
1412 reg = <0 0x00890000 0 0x4000>;
1414 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_uart4_default>;
1417 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1418 power-domains = <&rpmhpd SDM845_CX>;
1419 operating-points-v2 = <&qup_opp_table>;
1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1422 interconnect-names = "qup-core", "qup-config";
1423 status = "disabled";
1427 compatible = "qcom,geni-i2c";
1428 reg = <0 0x00894000 0 0x4000>;
1430 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&qup_i2c5_default>;
1433 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1434 #address-cells = <1>;
1436 power-domains = <&rpmhpd SDM845_CX>;
1437 operating-points-v2 = <&qup_opp_table>;
1438 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1439 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1440 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1441 interconnect-names = "qup-core", "qup-config", "qup-memory";
1442 status = "disabled";
1446 compatible = "qcom,geni-spi";
1447 reg = <0 0x00894000 0 0x4000>;
1449 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_spi5_default>;
1452 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1453 #address-cells = <1>;
1455 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1456 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1457 interconnect-names = "qup-core", "qup-config";
1458 status = "disabled";
1461 uart5: serial@894000 {
1462 compatible = "qcom,geni-uart";
1463 reg = <0 0x00894000 0 0x4000>;
1465 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_uart5_default>;
1468 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1469 power-domains = <&rpmhpd SDM845_CX>;
1470 operating-points-v2 = <&qup_opp_table>;
1471 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1472 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1473 interconnect-names = "qup-core", "qup-config";
1474 status = "disabled";
1478 compatible = "qcom,geni-i2c";
1479 reg = <0 0x00898000 0 0x4000>;
1481 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1482 pinctrl-names = "default";
1483 pinctrl-0 = <&qup_i2c6_default>;
1484 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1485 #address-cells = <1>;
1487 power-domains = <&rpmhpd SDM845_CX>;
1488 operating-points-v2 = <&qup_opp_table>;
1489 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1490 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1491 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1492 interconnect-names = "qup-core", "qup-config", "qup-memory";
1493 status = "disabled";
1497 compatible = "qcom,geni-spi";
1498 reg = <0 0x00898000 0 0x4000>;
1500 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi6_default>;
1503 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1504 #address-cells = <1>;
1506 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1507 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1508 interconnect-names = "qup-core", "qup-config";
1509 status = "disabled";
1512 uart6: serial@898000 {
1513 compatible = "qcom,geni-uart";
1514 reg = <0 0x00898000 0 0x4000>;
1516 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_uart6_default>;
1519 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1520 power-domains = <&rpmhpd SDM845_CX>;
1521 operating-points-v2 = <&qup_opp_table>;
1522 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1523 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1524 interconnect-names = "qup-core", "qup-config";
1525 status = "disabled";
1529 compatible = "qcom,geni-i2c";
1530 reg = <0 0x0089c000 0 0x4000>;
1532 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1533 pinctrl-names = "default";
1534 pinctrl-0 = <&qup_i2c7_default>;
1535 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1536 #address-cells = <1>;
1538 power-domains = <&rpmhpd SDM845_CX>;
1539 operating-points-v2 = <&qup_opp_table>;
1540 status = "disabled";
1544 compatible = "qcom,geni-spi";
1545 reg = <0 0x0089c000 0 0x4000>;
1547 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&qup_spi7_default>;
1550 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1551 #address-cells = <1>;
1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1555 interconnect-names = "qup-core", "qup-config";
1556 status = "disabled";
1559 uart7: serial@89c000 {
1560 compatible = "qcom,geni-uart";
1561 reg = <0 0x0089c000 0 0x4000>;
1563 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_uart7_default>;
1566 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1567 power-domains = <&rpmhpd SDM845_CX>;
1568 operating-points-v2 = <&qup_opp_table>;
1569 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1570 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1571 interconnect-names = "qup-core", "qup-config";
1572 status = "disabled";
1576 gpi_dma1: dma-controller@0xa00000 {
1578 compatible = "qcom,sdm845-gpi-dma";
1579 reg = <0 0x00a00000 0 0x60000>;
1580 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1582 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1583 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1585 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1587 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1590 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1592 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1593 dma-channels = <13>;
1594 dma-channel-mask = <0xfa>;
1595 iommus = <&apps_smmu 0x06d6 0x0>;
1596 status = "disabled";
1599 qupv3_id_1: geniqup@ac0000 {
1600 compatible = "qcom,geni-se-qup";
1601 reg = <0 0x00ac0000 0 0x6000>;
1602 clock-names = "m-ahb", "s-ahb";
1603 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1604 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1605 iommus = <&apps_smmu 0x6c3 0x0>;
1606 #address-cells = <2>;
1609 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1610 interconnect-names = "qup-core";
1611 status = "disabled";
1614 compatible = "qcom,geni-i2c";
1615 reg = <0 0x00a80000 0 0x4000>;
1617 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_i2c8_default>;
1620 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1621 #address-cells = <1>;
1623 power-domains = <&rpmhpd SDM845_CX>;
1624 operating-points-v2 = <&qup_opp_table>;
1625 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1626 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1627 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1628 interconnect-names = "qup-core", "qup-config", "qup-memory";
1629 status = "disabled";
1633 compatible = "qcom,geni-spi";
1634 reg = <0 0x00a80000 0 0x4000>;
1636 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&qup_spi8_default>;
1639 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1640 #address-cells = <1>;
1642 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1643 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1644 interconnect-names = "qup-core", "qup-config";
1645 status = "disabled";
1648 uart8: serial@a80000 {
1649 compatible = "qcom,geni-uart";
1650 reg = <0 0x00a80000 0 0x4000>;
1652 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_uart8_default>;
1655 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1656 power-domains = <&rpmhpd SDM845_CX>;
1657 operating-points-v2 = <&qup_opp_table>;
1658 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1659 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1660 interconnect-names = "qup-core", "qup-config";
1661 status = "disabled";
1665 compatible = "qcom,geni-i2c";
1666 reg = <0 0x00a84000 0 0x4000>;
1668 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1669 pinctrl-names = "default";
1670 pinctrl-0 = <&qup_i2c9_default>;
1671 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cells = <1>;
1674 power-domains = <&rpmhpd SDM845_CX>;
1675 operating-points-v2 = <&qup_opp_table>;
1676 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1677 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1678 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1679 interconnect-names = "qup-core", "qup-config", "qup-memory";
1680 status = "disabled";
1684 compatible = "qcom,geni-spi";
1685 reg = <0 0x00a84000 0 0x4000>;
1687 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1688 pinctrl-names = "default";
1689 pinctrl-0 = <&qup_spi9_default>;
1690 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1691 #address-cells = <1>;
1693 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1694 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1695 interconnect-names = "qup-core", "qup-config";
1696 status = "disabled";
1699 uart9: serial@a84000 {
1700 compatible = "qcom,geni-debug-uart";
1701 reg = <0 0x00a84000 0 0x4000>;
1703 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1704 pinctrl-names = "default";
1705 pinctrl-0 = <&qup_uart9_default>;
1706 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1707 power-domains = <&rpmhpd SDM845_CX>;
1708 operating-points-v2 = <&qup_opp_table>;
1709 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1710 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1711 interconnect-names = "qup-core", "qup-config";
1712 status = "disabled";
1716 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00a88000 0 0x4000>;
1719 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_i2c10_default>;
1722 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1723 #address-cells = <1>;
1725 power-domains = <&rpmhpd SDM845_CX>;
1726 operating-points-v2 = <&qup_opp_table>;
1727 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1728 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1729 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1730 interconnect-names = "qup-core", "qup-config", "qup-memory";
1731 status = "disabled";
1735 compatible = "qcom,geni-spi";
1736 reg = <0 0x00a88000 0 0x4000>;
1738 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1739 pinctrl-names = "default";
1740 pinctrl-0 = <&qup_spi10_default>;
1741 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1742 #address-cells = <1>;
1744 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1745 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1746 interconnect-names = "qup-core", "qup-config";
1747 status = "disabled";
1750 uart10: serial@a88000 {
1751 compatible = "qcom,geni-uart";
1752 reg = <0 0x00a88000 0 0x4000>;
1754 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1755 pinctrl-names = "default";
1756 pinctrl-0 = <&qup_uart10_default>;
1757 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1758 power-domains = <&rpmhpd SDM845_CX>;
1759 operating-points-v2 = <&qup_opp_table>;
1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1761 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1762 interconnect-names = "qup-core", "qup-config";
1763 status = "disabled";
1767 compatible = "qcom,geni-i2c";
1768 reg = <0 0x00a8c000 0 0x4000>;
1770 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1771 pinctrl-names = "default";
1772 pinctrl-0 = <&qup_i2c11_default>;
1773 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1774 #address-cells = <1>;
1776 power-domains = <&rpmhpd SDM845_CX>;
1777 operating-points-v2 = <&qup_opp_table>;
1778 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1779 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1780 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1781 interconnect-names = "qup-core", "qup-config", "qup-memory";
1782 status = "disabled";
1786 compatible = "qcom,geni-spi";
1787 reg = <0 0x00a8c000 0 0x4000>;
1789 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1790 pinctrl-names = "default";
1791 pinctrl-0 = <&qup_spi11_default>;
1792 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cells = <1>;
1795 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect-names = "qup-core", "qup-config";
1798 status = "disabled";
1801 uart11: serial@a8c000 {
1802 compatible = "qcom,geni-uart";
1803 reg = <0 0x00a8c000 0 0x4000>;
1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1806 pinctrl-names = "default";
1807 pinctrl-0 = <&qup_uart11_default>;
1808 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1809 power-domains = <&rpmhpd SDM845_CX>;
1810 operating-points-v2 = <&qup_opp_table>;
1811 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1812 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1813 interconnect-names = "qup-core", "qup-config";
1814 status = "disabled";
1818 compatible = "qcom,geni-i2c";
1819 reg = <0 0x00a90000 0 0x4000>;
1821 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1822 pinctrl-names = "default";
1823 pinctrl-0 = <&qup_i2c12_default>;
1824 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1825 #address-cells = <1>;
1827 power-domains = <&rpmhpd SDM845_CX>;
1828 operating-points-v2 = <&qup_opp_table>;
1829 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1830 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1831 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1832 interconnect-names = "qup-core", "qup-config", "qup-memory";
1833 status = "disabled";
1837 compatible = "qcom,geni-spi";
1838 reg = <0 0x00a90000 0 0x4000>;
1840 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1841 pinctrl-names = "default";
1842 pinctrl-0 = <&qup_spi12_default>;
1843 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1844 #address-cells = <1>;
1846 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1847 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1848 interconnect-names = "qup-core", "qup-config";
1849 status = "disabled";
1852 uart12: serial@a90000 {
1853 compatible = "qcom,geni-uart";
1854 reg = <0 0x00a90000 0 0x4000>;
1856 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1857 pinctrl-names = "default";
1858 pinctrl-0 = <&qup_uart12_default>;
1859 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1860 power-domains = <&rpmhpd SDM845_CX>;
1861 operating-points-v2 = <&qup_opp_table>;
1862 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1863 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1864 interconnect-names = "qup-core", "qup-config";
1865 status = "disabled";
1869 compatible = "qcom,geni-i2c";
1870 reg = <0 0x00a94000 0 0x4000>;
1872 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1873 pinctrl-names = "default";
1874 pinctrl-0 = <&qup_i2c13_default>;
1875 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1876 #address-cells = <1>;
1878 power-domains = <&rpmhpd SDM845_CX>;
1879 operating-points-v2 = <&qup_opp_table>;
1880 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1881 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1882 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1883 interconnect-names = "qup-core", "qup-config", "qup-memory";
1884 status = "disabled";
1888 compatible = "qcom,geni-spi";
1889 reg = <0 0x00a94000 0 0x4000>;
1891 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1892 pinctrl-names = "default";
1893 pinctrl-0 = <&qup_spi13_default>;
1894 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1895 #address-cells = <1>;
1897 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1898 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1899 interconnect-names = "qup-core", "qup-config";
1900 status = "disabled";
1903 uart13: serial@a94000 {
1904 compatible = "qcom,geni-uart";
1905 reg = <0 0x00a94000 0 0x4000>;
1907 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1908 pinctrl-names = "default";
1909 pinctrl-0 = <&qup_uart13_default>;
1910 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1911 power-domains = <&rpmhpd SDM845_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
1913 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1914 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1915 interconnect-names = "qup-core", "qup-config";
1916 status = "disabled";
1920 compatible = "qcom,geni-i2c";
1921 reg = <0 0x00a98000 0 0x4000>;
1923 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1924 pinctrl-names = "default";
1925 pinctrl-0 = <&qup_i2c14_default>;
1926 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1927 #address-cells = <1>;
1929 power-domains = <&rpmhpd SDM845_CX>;
1930 operating-points-v2 = <&qup_opp_table>;
1931 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1932 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1933 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1934 interconnect-names = "qup-core", "qup-config", "qup-memory";
1935 status = "disabled";
1939 compatible = "qcom,geni-spi";
1940 reg = <0 0x00a98000 0 0x4000>;
1942 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1943 pinctrl-names = "default";
1944 pinctrl-0 = <&qup_spi14_default>;
1945 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1946 #address-cells = <1>;
1948 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1949 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1950 interconnect-names = "qup-core", "qup-config";
1951 status = "disabled";
1954 uart14: serial@a98000 {
1955 compatible = "qcom,geni-uart";
1956 reg = <0 0x00a98000 0 0x4000>;
1958 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1959 pinctrl-names = "default";
1960 pinctrl-0 = <&qup_uart14_default>;
1961 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1962 power-domains = <&rpmhpd SDM845_CX>;
1963 operating-points-v2 = <&qup_opp_table>;
1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1966 interconnect-names = "qup-core", "qup-config";
1967 status = "disabled";
1971 compatible = "qcom,geni-i2c";
1972 reg = <0 0x00a9c000 0 0x4000>;
1974 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1975 pinctrl-names = "default";
1976 pinctrl-0 = <&qup_i2c15_default>;
1977 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1978 #address-cells = <1>;
1980 power-domains = <&rpmhpd SDM845_CX>;
1981 operating-points-v2 = <&qup_opp_table>;
1982 status = "disabled";
1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1985 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1986 interconnect-names = "qup-core", "qup-config", "qup-memory";
1990 compatible = "qcom,geni-spi";
1991 reg = <0 0x00a9c000 0 0x4000>;
1993 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1994 pinctrl-names = "default";
1995 pinctrl-0 = <&qup_spi15_default>;
1996 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1997 #address-cells = <1>;
1999 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2000 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2001 interconnect-names = "qup-core", "qup-config";
2002 status = "disabled";
2005 uart15: serial@a9c000 {
2006 compatible = "qcom,geni-uart";
2007 reg = <0 0x00a9c000 0 0x4000>;
2009 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2010 pinctrl-names = "default";
2011 pinctrl-0 = <&qup_uart15_default>;
2012 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2013 power-domains = <&rpmhpd SDM845_CX>;
2014 operating-points-v2 = <&qup_opp_table>;
2015 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2016 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2017 interconnect-names = "qup-core", "qup-config";
2018 status = "disabled";
2022 llcc: system-cache-controller@1100000 {
2023 compatible = "qcom,sdm845-llcc";
2024 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2025 reg-names = "llcc_base", "llcc_broadcast_base";
2026 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2029 pcie0: pci@1c00000 {
2030 compatible = "qcom,pcie-sdm845";
2031 reg = <0 0x01c00000 0 0x2000>,
2032 <0 0x60000000 0 0xf1d>,
2033 <0 0x60000f20 0 0xa8>,
2034 <0 0x60100000 0 0x100000>;
2035 reg-names = "parf", "dbi", "elbi", "config";
2036 device_type = "pci";
2037 linux,pci-domain = <0>;
2038 bus-range = <0x00 0xff>;
2041 #address-cells = <3>;
2044 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2045 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2047 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2048 interrupt-names = "msi";
2049 #interrupt-cells = <1>;
2050 interrupt-map-mask = <0 0 0 0x7>;
2051 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2052 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2053 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2054 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2056 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2057 <&gcc GCC_PCIE_0_AUX_CLK>,
2058 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2059 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2060 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2061 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2062 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2063 clock-names = "pipe",
2071 iommus = <&apps_smmu 0x1c10 0xf>;
2072 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2073 <0x100 &apps_smmu 0x1c11 0x1>,
2074 <0x200 &apps_smmu 0x1c12 0x1>,
2075 <0x300 &apps_smmu 0x1c13 0x1>,
2076 <0x400 &apps_smmu 0x1c14 0x1>,
2077 <0x500 &apps_smmu 0x1c15 0x1>,
2078 <0x600 &apps_smmu 0x1c16 0x1>,
2079 <0x700 &apps_smmu 0x1c17 0x1>,
2080 <0x800 &apps_smmu 0x1c18 0x1>,
2081 <0x900 &apps_smmu 0x1c19 0x1>,
2082 <0xa00 &apps_smmu 0x1c1a 0x1>,
2083 <0xb00 &apps_smmu 0x1c1b 0x1>,
2084 <0xc00 &apps_smmu 0x1c1c 0x1>,
2085 <0xd00 &apps_smmu 0x1c1d 0x1>,
2086 <0xe00 &apps_smmu 0x1c1e 0x1>,
2087 <0xf00 &apps_smmu 0x1c1f 0x1>;
2089 resets = <&gcc GCC_PCIE_0_BCR>;
2090 reset-names = "pci";
2092 power-domains = <&gcc PCIE_0_GDSC>;
2094 phys = <&pcie0_lane>;
2095 phy-names = "pciephy";
2097 status = "disabled";
2100 pcie0_phy: phy@1c06000 {
2101 compatible = "qcom,sdm845-qmp-pcie-phy";
2102 reg = <0 0x01c06000 0 0x18c>;
2103 #address-cells = <2>;
2106 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2107 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2108 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2109 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2110 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2112 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2113 reset-names = "phy";
2115 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2116 assigned-clock-rates = <100000000>;
2118 status = "disabled";
2120 pcie0_lane: phy@1c06200 {
2121 reg = <0 0x01c06200 0 0x128>,
2122 <0 0x01c06400 0 0x1fc>,
2123 <0 0x01c06800 0 0x218>,
2124 <0 0x01c06600 0 0x70>;
2125 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2126 clock-names = "pipe0";
2130 clock-output-names = "pcie_0_pipe_clk";
2134 pcie1: pci@1c08000 {
2135 compatible = "qcom,pcie-sdm845";
2136 reg = <0 0x01c08000 0 0x2000>,
2137 <0 0x40000000 0 0xf1d>,
2138 <0 0x40000f20 0 0xa8>,
2139 <0 0x40100000 0 0x100000>;
2140 reg-names = "parf", "dbi", "elbi", "config";
2141 device_type = "pci";
2142 linux,pci-domain = <1>;
2143 bus-range = <0x00 0xff>;
2146 #address-cells = <3>;
2149 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2150 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2152 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2153 interrupt-names = "msi";
2154 #interrupt-cells = <1>;
2155 interrupt-map-mask = <0 0 0 0x7>;
2156 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2157 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2158 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2159 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2161 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2162 <&gcc GCC_PCIE_1_AUX_CLK>,
2163 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2164 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2165 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2166 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2167 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2168 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2169 clock-names = "pipe",
2178 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2179 assigned-clock-rates = <19200000>;
2181 iommus = <&apps_smmu 0x1c00 0xf>;
2182 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2183 <0x100 &apps_smmu 0x1c01 0x1>,
2184 <0x200 &apps_smmu 0x1c02 0x1>,
2185 <0x300 &apps_smmu 0x1c03 0x1>,
2186 <0x400 &apps_smmu 0x1c04 0x1>,
2187 <0x500 &apps_smmu 0x1c05 0x1>,
2188 <0x600 &apps_smmu 0x1c06 0x1>,
2189 <0x700 &apps_smmu 0x1c07 0x1>,
2190 <0x800 &apps_smmu 0x1c08 0x1>,
2191 <0x900 &apps_smmu 0x1c09 0x1>,
2192 <0xa00 &apps_smmu 0x1c0a 0x1>,
2193 <0xb00 &apps_smmu 0x1c0b 0x1>,
2194 <0xc00 &apps_smmu 0x1c0c 0x1>,
2195 <0xd00 &apps_smmu 0x1c0d 0x1>,
2196 <0xe00 &apps_smmu 0x1c0e 0x1>,
2197 <0xf00 &apps_smmu 0x1c0f 0x1>;
2199 resets = <&gcc GCC_PCIE_1_BCR>;
2200 reset-names = "pci";
2202 power-domains = <&gcc PCIE_1_GDSC>;
2204 phys = <&pcie1_lane>;
2205 phy-names = "pciephy";
2207 status = "disabled";
2210 pcie1_phy: phy@1c0a000 {
2211 compatible = "qcom,sdm845-qhp-pcie-phy";
2212 reg = <0 0x01c0a000 0 0x800>;
2213 #address-cells = <2>;
2216 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2217 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2218 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2219 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2220 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2222 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2223 reset-names = "phy";
2225 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2226 assigned-clock-rates = <100000000>;
2228 status = "disabled";
2230 pcie1_lane: phy@1c06200 {
2231 reg = <0 0x01c0a800 0 0x800>,
2232 <0 0x01c0a800 0 0x800>,
2233 <0 0x01c0b800 0 0x400>;
2234 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2235 clock-names = "pipe0";
2239 clock-output-names = "pcie_1_pipe_clk";
2243 mem_noc: interconnect@1380000 {
2244 compatible = "qcom,sdm845-mem-noc";
2245 reg = <0 0x01380000 0 0x27200>;
2246 #interconnect-cells = <2>;
2247 qcom,bcm-voters = <&apps_bcm_voter>;
2250 dc_noc: interconnect@14e0000 {
2251 compatible = "qcom,sdm845-dc-noc";
2252 reg = <0 0x014e0000 0 0x400>;
2253 #interconnect-cells = <2>;
2254 qcom,bcm-voters = <&apps_bcm_voter>;
2257 config_noc: interconnect@1500000 {
2258 compatible = "qcom,sdm845-config-noc";
2259 reg = <0 0x01500000 0 0x5080>;
2260 #interconnect-cells = <2>;
2261 qcom,bcm-voters = <&apps_bcm_voter>;
2264 system_noc: interconnect@1620000 {
2265 compatible = "qcom,sdm845-system-noc";
2266 reg = <0 0x01620000 0 0x18080>;
2267 #interconnect-cells = <2>;
2268 qcom,bcm-voters = <&apps_bcm_voter>;
2271 aggre1_noc: interconnect@16e0000 {
2272 compatible = "qcom,sdm845-aggre1-noc";
2273 reg = <0 0x016e0000 0 0x15080>;
2274 #interconnect-cells = <2>;
2275 qcom,bcm-voters = <&apps_bcm_voter>;
2278 aggre2_noc: interconnect@1700000 {
2279 compatible = "qcom,sdm845-aggre2-noc";
2280 reg = <0 0x01700000 0 0x1f300>;
2281 #interconnect-cells = <2>;
2282 qcom,bcm-voters = <&apps_bcm_voter>;
2285 mmss_noc: interconnect@1740000 {
2286 compatible = "qcom,sdm845-mmss-noc";
2287 reg = <0 0x01740000 0 0x1c100>;
2288 #interconnect-cells = <2>;
2289 qcom,bcm-voters = <&apps_bcm_voter>;
2292 ufs_mem_hc: ufshc@1d84000 {
2293 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2295 reg = <0 0x01d84000 0 0x2500>,
2296 <0 0x01d90000 0 0x8000>;
2297 reg-names = "std", "ice";
2298 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2299 phys = <&ufs_mem_phy_lanes>;
2300 phy-names = "ufsphy";
2301 lanes-per-direction = <2>;
2302 power-domains = <&gcc UFS_PHY_GDSC>;
2304 resets = <&gcc GCC_UFS_PHY_BCR>;
2305 reset-names = "rst";
2307 iommus = <&apps_smmu 0x100 0xf>;
2315 "tx_lane0_sync_clk",
2316 "rx_lane0_sync_clk",
2317 "rx_lane1_sync_clk",
2320 <&gcc GCC_UFS_PHY_AXI_CLK>,
2321 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2322 <&gcc GCC_UFS_PHY_AHB_CLK>,
2323 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2324 <&rpmhcc RPMH_CXO_CLK>,
2325 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2326 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2327 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2328 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2330 <50000000 200000000>,
2333 <37500000 150000000>,
2340 status = "disabled";
2343 ufs_mem_phy: phy@1d87000 {
2344 compatible = "qcom,sdm845-qmp-ufs-phy";
2345 reg = <0 0x01d87000 0 0x18c>;
2346 #address-cells = <2>;
2349 clock-names = "ref",
2351 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2352 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2354 resets = <&ufs_mem_hc 0>;
2355 reset-names = "ufsphy";
2356 status = "disabled";
2358 ufs_mem_phy_lanes: phy@1d87400 {
2359 reg = <0 0x01d87400 0 0x108>,
2360 <0 0x01d87600 0 0x1e0>,
2361 <0 0x01d87c00 0 0x1dc>,
2362 <0 0x01d87800 0 0x108>,
2363 <0 0x01d87a00 0 0x1e0>;
2368 cryptobam: dma-controller@1dc4000 {
2369 compatible = "qcom,bam-v1.7.0";
2370 reg = <0 0x01dc4000 0 0x24000>;
2371 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2372 clocks = <&rpmhcc RPMH_CE_CLK>;
2373 clock-names = "bam_clk";
2376 qcom,controlled-remotely;
2377 iommus = <&apps_smmu 0x704 0x1>,
2378 <&apps_smmu 0x706 0x1>,
2379 <&apps_smmu 0x714 0x1>,
2380 <&apps_smmu 0x716 0x1>;
2383 crypto: crypto@1dfa000 {
2384 compatible = "qcom,crypto-v5.4";
2385 reg = <0 0x01dfa000 0 0x6000>;
2386 clocks = <&gcc GCC_CE1_AHB_CLK>,
2387 <&gcc GCC_CE1_AXI_CLK>,
2388 <&rpmhcc RPMH_CE_CLK>;
2389 clock-names = "iface", "bus", "core";
2390 dmas = <&cryptobam 6>, <&cryptobam 7>;
2391 dma-names = "rx", "tx";
2392 iommus = <&apps_smmu 0x704 0x1>,
2393 <&apps_smmu 0x706 0x1>,
2394 <&apps_smmu 0x714 0x1>,
2395 <&apps_smmu 0x716 0x1>;
2399 compatible = "qcom,sdm845-ipa";
2401 iommus = <&apps_smmu 0x720 0x0>,
2402 <&apps_smmu 0x722 0x0>;
2403 reg = <0 0x1e40000 0 0x7000>,
2404 <0 0x1e47000 0 0x2000>,
2405 <0 0x1e04000 0 0x2c000>;
2406 reg-names = "ipa-reg",
2410 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2411 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2412 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2413 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2414 interrupt-names = "ipa",
2419 clocks = <&rpmhcc RPMH_IPA_CLK>;
2420 clock-names = "core";
2422 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2423 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2425 interconnect-names = "memory",
2429 qcom,smem-states = <&ipa_smp2p_out 0>,
2431 qcom,smem-state-names = "ipa-clock-enabled-valid",
2432 "ipa-clock-enabled";
2434 status = "disabled";
2437 tcsr_mutex_regs: syscon@1f40000 {
2438 compatible = "syscon";
2439 reg = <0 0x01f40000 0 0x40000>;
2442 tlmm: pinctrl@3400000 {
2443 compatible = "qcom,sdm845-pinctrl";
2444 reg = <0 0x03400000 0 0xc00000>;
2445 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2448 interrupt-controller;
2449 #interrupt-cells = <2>;
2450 gpio-ranges = <&tlmm 0 0 151>;
2451 wakeup-parent = <&pdc_intc>;
2453 cci0_default: cci0-default {
2455 pins = "gpio17", "gpio18";
2456 function = "cci_i2c";
2459 drive-strength = <2>; /* 2 mA */
2462 cci0_sleep: cci0-sleep {
2464 pins = "gpio17", "gpio18";
2465 function = "cci_i2c";
2467 drive-strength = <2>; /* 2 mA */
2471 cci1_default: cci1-default {
2473 pins = "gpio19", "gpio20";
2474 function = "cci_i2c";
2477 drive-strength = <2>; /* 2 mA */
2480 cci1_sleep: cci1-sleep {
2482 pins = "gpio19", "gpio20";
2483 function = "cci_i2c";
2485 drive-strength = <2>; /* 2 mA */
2489 qspi_clk: qspi-clk {
2492 function = "qspi_clk";
2496 qspi_cs0: qspi-cs0 {
2499 function = "qspi_cs";
2503 qspi_cs1: qspi-cs1 {
2506 function = "qspi_cs";
2510 qspi_data01: qspi-data01 {
2512 pins = "gpio91", "gpio92";
2513 function = "qspi_data";
2517 qspi_data12: qspi-data12 {
2519 pins = "gpio93", "gpio94";
2520 function = "qspi_data";
2524 qup_i2c0_default: qup-i2c0-default {
2526 pins = "gpio0", "gpio1";
2531 qup_i2c1_default: qup-i2c1-default {
2533 pins = "gpio17", "gpio18";
2538 qup_i2c2_default: qup-i2c2-default {
2540 pins = "gpio27", "gpio28";
2545 qup_i2c3_default: qup-i2c3-default {
2547 pins = "gpio41", "gpio42";
2552 qup_i2c4_default: qup-i2c4-default {
2554 pins = "gpio89", "gpio90";
2559 qup_i2c5_default: qup-i2c5-default {
2561 pins = "gpio85", "gpio86";
2566 qup_i2c6_default: qup-i2c6-default {
2568 pins = "gpio45", "gpio46";
2573 qup_i2c7_default: qup-i2c7-default {
2575 pins = "gpio93", "gpio94";
2580 qup_i2c8_default: qup-i2c8-default {
2582 pins = "gpio65", "gpio66";
2587 qup_i2c9_default: qup-i2c9-default {
2589 pins = "gpio6", "gpio7";
2594 qup_i2c10_default: qup-i2c10-default {
2596 pins = "gpio55", "gpio56";
2601 qup_i2c11_default: qup-i2c11-default {
2603 pins = "gpio31", "gpio32";
2608 qup_i2c12_default: qup-i2c12-default {
2610 pins = "gpio49", "gpio50";
2615 qup_i2c13_default: qup-i2c13-default {
2617 pins = "gpio105", "gpio106";
2622 qup_i2c14_default: qup-i2c14-default {
2624 pins = "gpio33", "gpio34";
2629 qup_i2c15_default: qup-i2c15-default {
2631 pins = "gpio81", "gpio82";
2636 qup_spi0_default: qup-spi0-default {
2638 pins = "gpio0", "gpio1",
2644 pins = "gpio0", "gpio1",
2646 drive-strength = <6>;
2651 qup_spi1_default: qup-spi1-default {
2653 pins = "gpio17", "gpio18",
2659 qup_spi2_default: qup-spi2-default {
2661 pins = "gpio27", "gpio28",
2667 qup_spi3_default: qup-spi3-default {
2669 pins = "gpio41", "gpio42",
2675 qup_spi4_default: qup-spi4-default {
2677 pins = "gpio89", "gpio90",
2683 qup_spi5_default: qup-spi5-default {
2685 pins = "gpio85", "gpio86",
2691 qup_spi6_default: qup-spi6-default {
2693 pins = "gpio45", "gpio46",
2699 qup_spi7_default: qup-spi7-default {
2701 pins = "gpio93", "gpio94",
2707 qup_spi8_default: qup-spi8-default {
2709 pins = "gpio65", "gpio66",
2715 qup_spi9_default: qup-spi9-default {
2717 pins = "gpio6", "gpio7",
2723 qup_spi10_default: qup-spi10-default {
2725 pins = "gpio55", "gpio56",
2731 qup_spi11_default: qup-spi11-default {
2733 pins = "gpio31", "gpio32",
2739 qup_spi12_default: qup-spi12-default {
2741 pins = "gpio49", "gpio50",
2747 qup_spi13_default: qup-spi13-default {
2749 pins = "gpio105", "gpio106",
2750 "gpio107", "gpio108";
2755 qup_spi14_default: qup-spi14-default {
2757 pins = "gpio33", "gpio34",
2763 qup_spi15_default: qup-spi15-default {
2765 pins = "gpio81", "gpio82",
2771 qup_uart0_default: qup-uart0-default {
2773 pins = "gpio2", "gpio3";
2778 qup_uart1_default: qup-uart1-default {
2780 pins = "gpio19", "gpio20";
2785 qup_uart2_default: qup-uart2-default {
2787 pins = "gpio29", "gpio30";
2792 qup_uart3_default: qup-uart3-default {
2794 pins = "gpio43", "gpio44";
2799 qup_uart4_default: qup-uart4-default {
2801 pins = "gpio91", "gpio92";
2806 qup_uart5_default: qup-uart5-default {
2808 pins = "gpio87", "gpio88";
2813 qup_uart6_default: qup-uart6-default {
2815 pins = "gpio47", "gpio48";
2820 qup_uart7_default: qup-uart7-default {
2822 pins = "gpio95", "gpio96";
2827 qup_uart8_default: qup-uart8-default {
2829 pins = "gpio67", "gpio68";
2834 qup_uart9_default: qup-uart9-default {
2836 pins = "gpio4", "gpio5";
2841 qup_uart10_default: qup-uart10-default {
2843 pins = "gpio53", "gpio54";
2848 qup_uart11_default: qup-uart11-default {
2850 pins = "gpio33", "gpio34";
2855 qup_uart12_default: qup-uart12-default {
2857 pins = "gpio51", "gpio52";
2862 qup_uart13_default: qup-uart13-default {
2864 pins = "gpio107", "gpio108";
2869 qup_uart14_default: qup-uart14-default {
2871 pins = "gpio31", "gpio32";
2876 qup_uart15_default: qup-uart15-default {
2878 pins = "gpio83", "gpio84";
2883 quat_mi2s_sleep: quat_mi2s_sleep {
2885 pins = "gpio58", "gpio59";
2890 pins = "gpio58", "gpio59";
2891 drive-strength = <2>;
2897 quat_mi2s_active: quat_mi2s_active {
2899 pins = "gpio58", "gpio59";
2900 function = "qua_mi2s";
2904 pins = "gpio58", "gpio59";
2905 drive-strength = <8>;
2911 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2919 drive-strength = <2>;
2925 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2928 function = "qua_mi2s";
2933 drive-strength = <8>;
2938 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2946 drive-strength = <2>;
2952 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2955 function = "qua_mi2s";
2960 drive-strength = <8>;
2965 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2973 drive-strength = <2>;
2979 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2982 function = "qua_mi2s";
2987 drive-strength = <8>;
2992 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3000 drive-strength = <2>;
3006 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3009 function = "qua_mi2s";
3014 drive-strength = <8>;
3020 mss_pil: remoteproc@4080000 {
3021 compatible = "qcom,sdm845-mss-pil";
3022 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3023 reg-names = "qdsp6", "rmb";
3025 interrupts-extended =
3026 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3027 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3028 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3029 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3030 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3031 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3032 interrupt-names = "wdog", "fatal", "ready",
3033 "handover", "stop-ack",
3036 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3037 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3038 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3039 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3040 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3041 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3042 <&gcc GCC_PRNG_AHB_CLK>,
3043 <&rpmhcc RPMH_CXO_CLK>;
3044 clock-names = "iface", "bus", "mem", "gpll0_mss",
3045 "snoc_axi", "mnoc_axi", "prng", "xo";
3047 qcom,qmp = <&aoss_qmp>;
3049 qcom,smem-states = <&modem_smp2p_out 0>;
3050 qcom,smem-state-names = "stop";
3052 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3053 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3054 reset-names = "mss_restart", "pdc_reset";
3056 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3058 power-domains = <&rpmhpd SDM845_CX>,
3059 <&rpmhpd SDM845_MX>,
3060 <&rpmhpd SDM845_MSS>;
3061 power-domain-names = "cx", "mx", "mss";
3063 status = "disabled";
3066 memory-region = <&mba_region>;
3070 memory-region = <&mpss_region>;
3074 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3076 qcom,remote-pid = <1>;
3077 mboxes = <&apss_shared 12>;
3081 gpucc: clock-controller@5090000 {
3082 compatible = "qcom,sdm845-gpucc";
3083 reg = <0 0x05090000 0 0x9000>;
3086 #power-domain-cells = <1>;
3087 clocks = <&rpmhcc RPMH_CXO_CLK>,
3088 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3089 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3090 clock-names = "bi_tcxo",
3091 "gcc_gpu_gpll0_clk_src",
3092 "gcc_gpu_gpll0_div_clk_src";
3096 compatible = "arm,coresight-stm", "arm,primecell";
3097 reg = <0 0x06002000 0 0x1000>,
3098 <0 0x16280000 0 0x180000>;
3099 reg-names = "stm-base", "stm-stimulus-base";
3101 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pclk";
3115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3116 reg = <0 0x06041000 0 0x1000>;
3118 clocks = <&aoss_qmp>;
3119 clock-names = "apb_pclk";
3123 funnel0_out: endpoint {
3125 <&merge_funnel_in0>;
3131 #address-cells = <1>;
3136 funnel0_in7: endpoint {
3137 remote-endpoint = <&stm_out>;
3144 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3145 reg = <0 0x06043000 0 0x1000>;
3147 clocks = <&aoss_qmp>;
3148 clock-names = "apb_pclk";
3152 funnel2_out: endpoint {
3154 <&merge_funnel_in2>;
3160 #address-cells = <1>;
3165 funnel2_in5: endpoint {
3167 <&apss_merge_funnel_out>;
3174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3175 reg = <0 0x06045000 0 0x1000>;
3177 clocks = <&aoss_qmp>;
3178 clock-names = "apb_pclk";
3182 merge_funnel_out: endpoint {
3183 remote-endpoint = <&etf_in>;
3189 #address-cells = <1>;
3194 merge_funnel_in0: endpoint {
3202 merge_funnel_in2: endpoint {
3210 replicator@6046000 {
3211 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3212 reg = <0 0x06046000 0 0x1000>;
3214 clocks = <&aoss_qmp>;
3215 clock-names = "apb_pclk";
3219 replicator_out: endpoint {
3220 remote-endpoint = <&etr_in>;
3227 replicator_in: endpoint {
3228 remote-endpoint = <&etf_out>;
3235 compatible = "arm,coresight-tmc", "arm,primecell";
3236 reg = <0 0x06047000 0 0x1000>;
3238 clocks = <&aoss_qmp>;
3239 clock-names = "apb_pclk";
3251 #address-cells = <1>;
3258 <&merge_funnel_out>;
3265 compatible = "arm,coresight-tmc", "arm,primecell";
3266 reg = <0 0x06048000 0 0x1000>;
3268 clocks = <&aoss_qmp>;
3269 clock-names = "apb_pclk";
3283 compatible = "arm,coresight-etm4x", "arm,primecell";
3284 reg = <0 0x07040000 0 0x1000>;
3288 clocks = <&aoss_qmp>;
3289 clock-names = "apb_pclk";
3290 arm,coresight-loses-context-with-cpu;
3294 etm0_out: endpoint {
3303 compatible = "arm,coresight-etm4x", "arm,primecell";
3304 reg = <0 0x07140000 0 0x1000>;
3308 clocks = <&aoss_qmp>;
3309 clock-names = "apb_pclk";
3310 arm,coresight-loses-context-with-cpu;
3314 etm1_out: endpoint {
3323 compatible = "arm,coresight-etm4x", "arm,primecell";
3324 reg = <0 0x07240000 0 0x1000>;
3328 clocks = <&aoss_qmp>;
3329 clock-names = "apb_pclk";
3330 arm,coresight-loses-context-with-cpu;
3334 etm2_out: endpoint {
3343 compatible = "arm,coresight-etm4x", "arm,primecell";
3344 reg = <0 0x07340000 0 0x1000>;
3348 clocks = <&aoss_qmp>;
3349 clock-names = "apb_pclk";
3350 arm,coresight-loses-context-with-cpu;
3354 etm3_out: endpoint {
3363 compatible = "arm,coresight-etm4x", "arm,primecell";
3364 reg = <0 0x07440000 0 0x1000>;
3368 clocks = <&aoss_qmp>;
3369 clock-names = "apb_pclk";
3370 arm,coresight-loses-context-with-cpu;
3374 etm4_out: endpoint {
3383 compatible = "arm,coresight-etm4x", "arm,primecell";
3384 reg = <0 0x07540000 0 0x1000>;
3388 clocks = <&aoss_qmp>;
3389 clock-names = "apb_pclk";
3390 arm,coresight-loses-context-with-cpu;
3394 etm5_out: endpoint {
3403 compatible = "arm,coresight-etm4x", "arm,primecell";
3404 reg = <0 0x07640000 0 0x1000>;
3408 clocks = <&aoss_qmp>;
3409 clock-names = "apb_pclk";
3410 arm,coresight-loses-context-with-cpu;
3414 etm6_out: endpoint {
3423 compatible = "arm,coresight-etm4x", "arm,primecell";
3424 reg = <0 0x07740000 0 0x1000>;
3428 clocks = <&aoss_qmp>;
3429 clock-names = "apb_pclk";
3430 arm,coresight-loses-context-with-cpu;
3434 etm7_out: endpoint {
3442 funnel@7800000 { /* APSS Funnel */
3443 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3444 reg = <0 0x07800000 0 0x1000>;
3446 clocks = <&aoss_qmp>;
3447 clock-names = "apb_pclk";
3451 apss_funnel_out: endpoint {
3453 <&apss_merge_funnel_in>;
3459 #address-cells = <1>;
3464 apss_funnel_in0: endpoint {
3472 apss_funnel_in1: endpoint {
3480 apss_funnel_in2: endpoint {
3488 apss_funnel_in3: endpoint {
3496 apss_funnel_in4: endpoint {
3504 apss_funnel_in5: endpoint {
3512 apss_funnel_in6: endpoint {
3520 apss_funnel_in7: endpoint {
3529 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3530 reg = <0 0x07810000 0 0x1000>;
3532 clocks = <&aoss_qmp>;
3533 clock-names = "apb_pclk";
3537 apss_merge_funnel_out: endpoint {
3546 apss_merge_funnel_in: endpoint {
3554 sdhc_2: sdhci@8804000 {
3555 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3556 reg = <0 0x08804000 0 0x1000>;
3558 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3560 interrupt-names = "hc_irq", "pwr_irq";
3562 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3563 <&gcc GCC_SDCC2_APPS_CLK>,
3564 <&rpmhcc RPMH_CXO_CLK>;
3565 clock-names = "iface", "core", "xo";
3566 iommus = <&apps_smmu 0xa0 0xf>;
3567 power-domains = <&rpmhpd SDM845_CX>;
3568 operating-points-v2 = <&sdhc2_opp_table>;
3570 status = "disabled";
3572 sdhc2_opp_table: sdhc2-opp-table {
3573 compatible = "operating-points-v2";
3576 opp-hz = /bits/ 64 <9600000>;
3577 required-opps = <&rpmhpd_opp_min_svs>;
3581 opp-hz = /bits/ 64 <19200000>;
3582 required-opps = <&rpmhpd_opp_low_svs>;
3586 opp-hz = /bits/ 64 <100000000>;
3587 required-opps = <&rpmhpd_opp_svs>;
3591 opp-hz = /bits/ 64 <201500000>;
3592 required-opps = <&rpmhpd_opp_svs_l1>;
3597 qspi_opp_table: qspi-opp-table {
3598 compatible = "operating-points-v2";
3601 opp-hz = /bits/ 64 <19200000>;
3602 required-opps = <&rpmhpd_opp_min_svs>;
3606 opp-hz = /bits/ 64 <100000000>;
3607 required-opps = <&rpmhpd_opp_low_svs>;
3611 opp-hz = /bits/ 64 <150000000>;
3612 required-opps = <&rpmhpd_opp_svs>;
3616 opp-hz = /bits/ 64 <300000000>;
3617 required-opps = <&rpmhpd_opp_nom>;
3622 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3623 reg = <0 0x088df000 0 0x600>;
3624 #address-cells = <1>;
3626 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3627 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3628 <&gcc GCC_QSPI_CORE_CLK>;
3629 clock-names = "iface", "core";
3630 power-domains = <&rpmhpd SDM845_CX>;
3631 operating-points-v2 = <&qspi_opp_table>;
3632 status = "disabled";
3635 slim: slim@171c0000 {
3636 compatible = "qcom,slim-ngd-v2.1.0";
3637 reg = <0 0x171c0000 0 0x2c000>;
3638 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3640 qcom,apps-ch-pipes = <0x780000>;
3641 qcom,ea-pc = <0x270>;
3643 dmas = <&slimbam 3>, <&slimbam 4>,
3644 <&slimbam 5>, <&slimbam 6>;
3645 dma-names = "rx", "tx", "tx2", "rx2";
3647 iommus = <&apps_smmu 0x1806 0x0>;
3648 #address-cells = <1>;
3653 #address-cells = <2>;
3657 compatible = "slim217,250";
3662 compatible = "slim217,250";
3664 slim-ifc-dev = <&wcd9340_ifd>;
3666 #sound-dai-cells = <1>;
3668 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3669 interrupt-controller;
3670 #interrupt-cells = <1>;
3673 clock-frequency = <9600000>;
3674 clock-output-names = "mclk";
3675 qcom,micbias1-microvolt = <1800000>;
3676 qcom,micbias2-microvolt = <1800000>;
3677 qcom,micbias3-microvolt = <1800000>;
3678 qcom,micbias4-microvolt = <1800000>;
3680 #address-cells = <1>;
3683 wcdgpio: gpio-controller@42 {
3684 compatible = "qcom,wcd9340-gpio";
3691 compatible = "qcom,soundwire-v1.3.0";
3693 interrupts-extended = <&wcd9340 20>;
3695 qcom,dout-ports = <6>;
3696 qcom,din-ports = <2>;
3697 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3698 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3699 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3701 #sound-dai-cells = <1>;
3702 clocks = <&wcd9340>;
3703 clock-names = "iface";
3704 #address-cells = <2>;
3713 lmh_cluster1: lmh@17d70800 {
3714 compatible = "qcom,sdm845-lmh";
3715 reg = <0 0x17d70800 0 0x400>;
3716 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3718 qcom,lmh-temp-arm-millicelsius = <65000>;
3719 qcom,lmh-temp-low-millicelsius = <94500>;
3720 qcom,lmh-temp-high-millicelsius = <95000>;
3721 interrupt-controller;
3722 #interrupt-cells = <1>;
3725 lmh_cluster0: lmh@17d78800 {
3726 compatible = "qcom,sdm845-lmh";
3727 reg = <0 0x17d78800 0 0x400>;
3728 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3730 qcom,lmh-temp-arm-millicelsius = <65000>;
3731 qcom,lmh-temp-low-millicelsius = <94500>;
3732 qcom,lmh-temp-high-millicelsius = <95000>;
3733 interrupt-controller;
3734 #interrupt-cells = <1>;
3740 usb_1_hsphy: phy@88e2000 {
3741 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3742 reg = <0 0x088e2000 0 0x400>;
3743 status = "disabled";
3746 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3747 <&rpmhcc RPMH_CXO_CLK>;
3748 clock-names = "cfg_ahb", "ref";
3750 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3752 nvmem-cells = <&qusb2p_hstx_trim>;
3755 usb_2_hsphy: phy@88e3000 {
3756 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3757 reg = <0 0x088e3000 0 0x400>;
3758 status = "disabled";
3761 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3762 <&rpmhcc RPMH_CXO_CLK>;
3763 clock-names = "cfg_ahb", "ref";
3765 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3767 nvmem-cells = <&qusb2s_hstx_trim>;
3770 usb_1_qmpphy: phy@88e9000 {
3771 compatible = "qcom,sdm845-qmp-usb3-phy";
3772 reg = <0 0x088e9000 0 0x18c>,
3773 <0 0x088e8000 0 0x10>;
3774 status = "disabled";
3775 #address-cells = <2>;
3779 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3780 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3781 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3782 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3783 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3785 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3786 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3787 reset-names = "phy", "common";
3789 usb_1_ssphy: phy@88e9200 {
3790 reg = <0 0x088e9200 0 0x128>,
3791 <0 0x088e9400 0 0x200>,
3792 <0 0x088e9c00 0 0x218>,
3793 <0 0x088e9600 0 0x128>,
3794 <0 0x088e9800 0 0x200>,
3795 <0 0x088e9a00 0 0x100>;
3798 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3799 clock-names = "pipe0";
3800 clock-output-names = "usb3_phy_pipe_clk_src";
3804 usb_2_qmpphy: phy@88eb000 {
3805 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3806 reg = <0 0x088eb000 0 0x18c>;
3807 status = "disabled";
3808 #address-cells = <2>;
3812 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3813 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3814 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3815 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3816 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3818 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3819 <&gcc GCC_USB3_PHY_SEC_BCR>;
3820 reset-names = "phy", "common";
3822 usb_2_ssphy: phy@88eb200 {
3823 reg = <0 0x088eb200 0 0x128>,
3824 <0 0x088eb400 0 0x1fc>,
3825 <0 0x088eb800 0 0x218>,
3826 <0 0x088eb600 0 0x70>;
3829 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3830 clock-names = "pipe0";
3831 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3835 usb_1: usb@a6f8800 {
3836 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3837 reg = <0 0x0a6f8800 0 0x400>;
3838 status = "disabled";
3839 #address-cells = <2>;
3844 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3845 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3846 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3847 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3848 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3849 clock-names = "cfg_noc",
3855 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3856 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3857 assigned-clock-rates = <19200000>, <150000000>;
3859 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3860 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3861 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3862 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3863 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3864 "dm_hs_phy_irq", "dp_hs_phy_irq";
3866 power-domains = <&gcc USB30_PRIM_GDSC>;
3868 resets = <&gcc GCC_USB30_PRIM_BCR>;
3870 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3871 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3872 interconnect-names = "usb-ddr", "apps-usb";
3874 usb_1_dwc3: usb@a600000 {
3875 compatible = "snps,dwc3";
3876 reg = <0 0x0a600000 0 0xcd00>;
3877 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3878 iommus = <&apps_smmu 0x740 0>;
3879 snps,dis_u2_susphy_quirk;
3880 snps,dis_enblslpm_quirk;
3881 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3882 phy-names = "usb2-phy", "usb3-phy";
3886 usb_2: usb@a8f8800 {
3887 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3888 reg = <0 0x0a8f8800 0 0x400>;
3889 status = "disabled";
3890 #address-cells = <2>;
3895 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3896 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3897 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3898 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3899 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3900 clock-names = "cfg_noc",
3906 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3907 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3908 assigned-clock-rates = <19200000>, <150000000>;
3910 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3911 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3912 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3913 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3914 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3915 "dm_hs_phy_irq", "dp_hs_phy_irq";
3917 power-domains = <&gcc USB30_SEC_GDSC>;
3919 resets = <&gcc GCC_USB30_SEC_BCR>;
3921 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3922 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3923 interconnect-names = "usb-ddr", "apps-usb";
3925 usb_2_dwc3: usb@a800000 {
3926 compatible = "snps,dwc3";
3927 reg = <0 0x0a800000 0 0xcd00>;
3928 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3929 iommus = <&apps_smmu 0x760 0>;
3930 snps,dis_u2_susphy_quirk;
3931 snps,dis_enblslpm_quirk;
3932 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3933 phy-names = "usb2-phy", "usb3-phy";
3937 venus: video-codec@aa00000 {
3938 compatible = "qcom,sdm845-venus-v2";
3939 reg = <0 0x0aa00000 0 0xff000>;
3940 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3941 power-domains = <&videocc VENUS_GDSC>,
3942 <&videocc VCODEC0_GDSC>,
3943 <&videocc VCODEC1_GDSC>,
3944 <&rpmhpd SDM845_CX>;
3945 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3946 operating-points-v2 = <&venus_opp_table>;
3947 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3948 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3949 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3950 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3951 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3952 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3953 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3954 clock-names = "core", "iface", "bus",
3955 "vcodec0_core", "vcodec0_bus",
3956 "vcodec1_core", "vcodec1_bus";
3957 iommus = <&apps_smmu 0x10a0 0x8>,
3958 <&apps_smmu 0x10b0 0x0>;
3959 memory-region = <&venus_mem>;
3960 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3961 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3962 interconnect-names = "video-mem", "cpu-cfg";
3964 status = "disabled";
3967 compatible = "venus-decoder";
3971 compatible = "venus-encoder";
3974 venus_opp_table: venus-opp-table {
3975 compatible = "operating-points-v2";
3978 opp-hz = /bits/ 64 <100000000>;
3979 required-opps = <&rpmhpd_opp_min_svs>;
3983 opp-hz = /bits/ 64 <200000000>;
3984 required-opps = <&rpmhpd_opp_low_svs>;
3988 opp-hz = /bits/ 64 <320000000>;
3989 required-opps = <&rpmhpd_opp_svs>;
3993 opp-hz = /bits/ 64 <380000000>;
3994 required-opps = <&rpmhpd_opp_svs_l1>;
3998 opp-hz = /bits/ 64 <444000000>;
3999 required-opps = <&rpmhpd_opp_nom>;
4003 opp-hz = /bits/ 64 <533000097>;
4004 required-opps = <&rpmhpd_opp_turbo>;
4009 videocc: clock-controller@ab00000 {
4010 compatible = "qcom,sdm845-videocc";
4011 reg = <0 0x0ab00000 0 0x10000>;
4012 clocks = <&rpmhcc RPMH_CXO_CLK>;
4013 clock-names = "bi_tcxo";
4015 #power-domain-cells = <1>;
4019 camss: camss@a00000 {
4020 compatible = "qcom,sdm845-camss";
4022 reg = <0 0xacb3000 0 0x1000>,
4023 <0 0xacba000 0 0x1000>,
4024 <0 0xacc8000 0 0x1000>,
4025 <0 0xac65000 0 0x1000>,
4026 <0 0xac66000 0 0x1000>,
4027 <0 0xac67000 0 0x1000>,
4028 <0 0xac68000 0 0x1000>,
4029 <0 0xacaf000 0 0x4000>,
4030 <0 0xacb6000 0 0x4000>,
4031 <0 0xacc4000 0 0x4000>;
4032 reg-names = "csid0",
4043 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4044 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4045 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4046 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4047 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4048 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4049 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4050 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4051 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4052 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4053 interrupt-names = "csid0",
4064 power-domains = <&clock_camcc IFE_0_GDSC>,
4065 <&clock_camcc IFE_1_GDSC>,
4066 <&clock_camcc TITAN_TOP_GDSC>;
4068 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4069 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4070 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4071 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4072 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4073 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4074 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4075 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4076 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4077 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4078 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4079 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4080 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4081 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4082 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4083 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4084 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4085 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4086 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4087 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4088 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4089 <&gcc GCC_CAMERA_AHB_CLK>,
4090 <&gcc GCC_CAMERA_AXI_CLK>,
4091 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4092 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4093 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4094 <&clock_camcc CAM_CC_IFE_0_CLK>,
4095 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4096 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4097 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4098 <&clock_camcc CAM_CC_IFE_1_CLK>,
4099 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4100 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4101 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4102 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4103 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4104 clock-names = "camnoc_axi",
4115 "csiphy0_timer_src",
4118 "csiphy1_timer_src",
4121 "csiphy2_timer_src",
4124 "csiphy3_timer_src",
4141 iommus = <&apps_smmu 0x0808 0x0>,
4142 <&apps_smmu 0x0810 0x8>,
4143 <&apps_smmu 0x0c08 0x0>,
4144 <&apps_smmu 0x0c10 0x8>;
4146 status = "disabled";
4149 #address-cells = <1>;
4155 compatible = "qcom,sdm845-cci";
4156 #address-cells = <1>;
4159 reg = <0 0x0ac4a000 0 0x4000>;
4160 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4161 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4163 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4164 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4165 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4166 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4167 <&clock_camcc CAM_CC_CCI_CLK>,
4168 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4169 clock-names = "camnoc_axi",
4176 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4177 <&clock_camcc CAM_CC_CCI_CLK>;
4178 assigned-clock-rates = <80000000>, <37500000>;
4180 pinctrl-names = "default", "sleep";
4181 pinctrl-0 = <&cci0_default &cci1_default>;
4182 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4184 status = "disabled";
4186 cci_i2c0: i2c-bus@0 {
4188 clock-frequency = <1000000>;
4189 #address-cells = <1>;
4193 cci_i2c1: i2c-bus@1 {
4195 clock-frequency = <1000000>;
4196 #address-cells = <1>;
4201 clock_camcc: clock-controller@ad00000 {
4202 compatible = "qcom,sdm845-camcc";
4203 reg = <0 0x0ad00000 0 0x10000>;
4206 #power-domain-cells = <1>;
4207 clocks = <&rpmhcc RPMH_CXO_CLK>;
4208 clock-names = "bi_tcxo";
4211 dsi_opp_table: dsi-opp-table {
4212 compatible = "operating-points-v2";
4215 opp-hz = /bits/ 64 <19200000>;
4216 required-opps = <&rpmhpd_opp_min_svs>;
4220 opp-hz = /bits/ 64 <180000000>;
4221 required-opps = <&rpmhpd_opp_low_svs>;
4225 opp-hz = /bits/ 64 <275000000>;
4226 required-opps = <&rpmhpd_opp_svs>;
4230 opp-hz = /bits/ 64 <328580000>;
4231 required-opps = <&rpmhpd_opp_svs_l1>;
4235 opp-hz = /bits/ 64 <358000000>;
4236 required-opps = <&rpmhpd_opp_nom>;
4240 mdss: mdss@ae00000 {
4241 compatible = "qcom,sdm845-mdss";
4242 reg = <0 0x0ae00000 0 0x1000>;
4245 power-domains = <&dispcc MDSS_GDSC>;
4247 clocks = <&gcc GCC_DISP_AHB_CLK>,
4248 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4249 clock-names = "iface", "core";
4251 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4252 assigned-clock-rates = <300000000>;
4254 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4255 interrupt-controller;
4256 #interrupt-cells = <1>;
4258 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4259 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4260 interconnect-names = "mdp0-mem", "mdp1-mem";
4262 iommus = <&apps_smmu 0x880 0x8>,
4263 <&apps_smmu 0xc80 0x8>;
4265 status = "disabled";
4267 #address-cells = <2>;
4271 mdss_mdp: mdp@ae01000 {
4272 compatible = "qcom,sdm845-dpu";
4273 reg = <0 0x0ae01000 0 0x8f000>,
4274 <0 0x0aeb0000 0 0x2008>;
4275 reg-names = "mdp", "vbif";
4277 clocks = <&gcc GCC_DISP_AXI_CLK>,
4278 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4279 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4280 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4281 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4282 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4284 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4285 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4286 assigned-clock-rates = <300000000>,
4288 operating-points-v2 = <&mdp_opp_table>;
4289 power-domains = <&rpmhpd SDM845_CX>;
4291 interrupt-parent = <&mdss>;
4295 #address-cells = <1>;
4300 dpu_intf1_out: endpoint {
4301 remote-endpoint = <&dsi0_in>;
4307 dpu_intf2_out: endpoint {
4308 remote-endpoint = <&dsi1_in>;
4313 mdp_opp_table: mdp-opp-table {
4314 compatible = "operating-points-v2";
4317 opp-hz = /bits/ 64 <19200000>;
4318 required-opps = <&rpmhpd_opp_min_svs>;
4322 opp-hz = /bits/ 64 <171428571>;
4323 required-opps = <&rpmhpd_opp_low_svs>;
4327 opp-hz = /bits/ 64 <344000000>;
4328 required-opps = <&rpmhpd_opp_svs_l1>;
4332 opp-hz = /bits/ 64 <430000000>;
4333 required-opps = <&rpmhpd_opp_nom>;
4339 compatible = "qcom,mdss-dsi-ctrl";
4340 reg = <0 0x0ae94000 0 0x400>;
4341 reg-names = "dsi_ctrl";
4343 interrupt-parent = <&mdss>;
4346 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4347 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4348 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4349 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4350 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4351 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4352 clock-names = "byte",
4358 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4359 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4361 operating-points-v2 = <&dsi_opp_table>;
4362 power-domains = <&rpmhpd SDM845_CX>;
4367 status = "disabled";
4369 #address-cells = <1>;
4373 #address-cells = <1>;
4379 remote-endpoint = <&dpu_intf1_out>;
4385 dsi0_out: endpoint {
4391 dsi0_phy: dsi-phy@ae94400 {
4392 compatible = "qcom,dsi-phy-10nm";
4393 reg = <0 0x0ae94400 0 0x200>,
4394 <0 0x0ae94600 0 0x280>,
4395 <0 0x0ae94a00 0 0x1e0>;
4396 reg-names = "dsi_phy",
4403 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4404 <&rpmhcc RPMH_CXO_CLK>;
4405 clock-names = "iface", "ref";
4407 status = "disabled";
4411 compatible = "qcom,mdss-dsi-ctrl";
4412 reg = <0 0x0ae96000 0 0x400>;
4413 reg-names = "dsi_ctrl";
4415 interrupt-parent = <&mdss>;
4418 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4419 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4420 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4421 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4422 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4423 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4424 clock-names = "byte",
4430 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4431 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4433 operating-points-v2 = <&dsi_opp_table>;
4434 power-domains = <&rpmhpd SDM845_CX>;
4439 status = "disabled";
4441 #address-cells = <1>;
4445 #address-cells = <1>;
4451 remote-endpoint = <&dpu_intf2_out>;
4457 dsi1_out: endpoint {
4463 dsi1_phy: dsi-phy@ae96400 {
4464 compatible = "qcom,dsi-phy-10nm";
4465 reg = <0 0x0ae96400 0 0x200>,
4466 <0 0x0ae96600 0 0x280>,
4467 <0 0x0ae96a00 0 0x10e>;
4468 reg-names = "dsi_phy",
4475 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4476 <&rpmhcc RPMH_CXO_CLK>;
4477 clock-names = "iface", "ref";
4479 status = "disabled";
4484 compatible = "qcom,adreno-630.2", "qcom,adreno";
4486 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4487 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4490 * Look ma, no clocks! The GPU clocks and power are
4491 * controlled entirely by the GMU
4494 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4496 iommus = <&adreno_smmu 0>;
4498 operating-points-v2 = <&gpu_opp_table>;
4502 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4503 interconnect-names = "gfx-mem";
4505 status = "disabled";
4507 gpu_opp_table: opp-table {
4508 compatible = "operating-points-v2";
4511 opp-hz = /bits/ 64 <710000000>;
4512 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4513 opp-peak-kBps = <7216000>;
4517 opp-hz = /bits/ 64 <675000000>;
4518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4519 opp-peak-kBps = <7216000>;
4523 opp-hz = /bits/ 64 <596000000>;
4524 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4525 opp-peak-kBps = <6220000>;
4529 opp-hz = /bits/ 64 <520000000>;
4530 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4531 opp-peak-kBps = <6220000>;
4535 opp-hz = /bits/ 64 <414000000>;
4536 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4537 opp-peak-kBps = <4068000>;
4541 opp-hz = /bits/ 64 <342000000>;
4542 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4543 opp-peak-kBps = <2724000>;
4547 opp-hz = /bits/ 64 <257000000>;
4548 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4549 opp-peak-kBps = <1648000>;
4554 adreno_smmu: iommu@5040000 {
4555 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4556 reg = <0 0x5040000 0 0x10000>;
4558 #global-interrupts = <2>;
4559 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4560 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4561 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4562 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4563 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4564 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4565 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4566 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4567 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4568 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4569 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4570 <&gcc GCC_GPU_CFG_AHB_CLK>;
4571 clock-names = "bus", "iface";
4573 power-domains = <&gpucc GPU_CX_GDSC>;
4577 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4579 reg = <0 0x506a000 0 0x30000>,
4580 <0 0xb280000 0 0x10000>,
4581 <0 0xb480000 0 0x10000>;
4582 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4584 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4586 interrupt-names = "hfi", "gmu";
4588 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4589 <&gpucc GPU_CC_CXO_CLK>,
4590 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4591 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4592 clock-names = "gmu", "cxo", "axi", "memnoc";
4594 power-domains = <&gpucc GPU_CX_GDSC>,
4595 <&gpucc GPU_GX_GDSC>;
4596 power-domain-names = "cx", "gx";
4598 iommus = <&adreno_smmu 5>;
4600 operating-points-v2 = <&gmu_opp_table>;
4602 status = "disabled";
4604 gmu_opp_table: opp-table {
4605 compatible = "operating-points-v2";
4608 opp-hz = /bits/ 64 <400000000>;
4609 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4613 opp-hz = /bits/ 64 <200000000>;
4614 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4619 dispcc: clock-controller@af00000 {
4620 compatible = "qcom,sdm845-dispcc";
4621 reg = <0 0x0af00000 0 0x10000>;
4622 clocks = <&rpmhcc RPMH_CXO_CLK>,
4623 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4624 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4631 clock-names = "bi_tcxo",
4632 "gcc_disp_gpll0_clk_src",
4633 "gcc_disp_gpll0_div_clk_src",
4634 "dsi0_phy_pll_out_byteclk",
4635 "dsi0_phy_pll_out_dsiclk",
4636 "dsi1_phy_pll_out_byteclk",
4637 "dsi1_phy_pll_out_dsiclk",
4638 "dp_link_clk_divsel_ten",
4639 "dp_vco_divided_clk_src_mux";
4642 #power-domain-cells = <1>;
4645 pdc_intc: interrupt-controller@b220000 {
4646 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4647 reg = <0 0x0b220000 0 0x30000>;
4648 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4649 #interrupt-cells = <2>;
4650 interrupt-parent = <&intc>;
4651 interrupt-controller;
4654 pdc_reset: reset-controller@b2e0000 {
4655 compatible = "qcom,sdm845-pdc-global";
4656 reg = <0 0x0b2e0000 0 0x20000>;
4660 tsens0: thermal-sensor@c263000 {
4661 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4662 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4663 <0 0x0c222000 0 0x1ff>; /* SROT */
4664 #qcom,sensors = <13>;
4665 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4666 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4667 interrupt-names = "uplow", "critical";
4668 #thermal-sensor-cells = <1>;
4671 tsens1: thermal-sensor@c265000 {
4672 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4673 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4674 <0 0x0c223000 0 0x1ff>; /* SROT */
4675 #qcom,sensors = <8>;
4676 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4677 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4678 interrupt-names = "uplow", "critical";
4679 #thermal-sensor-cells = <1>;
4682 aoss_reset: reset-controller@c2a0000 {
4683 compatible = "qcom,sdm845-aoss-cc";
4684 reg = <0 0x0c2a0000 0 0x31000>;
4688 aoss_qmp: power-controller@c300000 {
4689 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4690 reg = <0 0x0c300000 0 0x100000>;
4691 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4692 mboxes = <&apss_shared 0>;
4697 #cooling-cells = <2>;
4701 #cooling-cells = <2>;
4705 spmi_bus: spmi@c440000 {
4706 compatible = "qcom,spmi-pmic-arb";
4707 reg = <0 0x0c440000 0 0x1100>,
4708 <0 0x0c600000 0 0x2000000>,
4709 <0 0x0e600000 0 0x100000>,
4710 <0 0x0e700000 0 0xa0000>,
4711 <0 0x0c40a000 0 0x26000>;
4712 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4713 interrupt-names = "periph_irq";
4714 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4717 #address-cells = <2>;
4719 interrupt-controller;
4720 #interrupt-cells = <4>;
4725 compatible = "simple-mfd";
4726 reg = <0 0x146bf000 0 0x1000>;
4728 #address-cells = <1>;
4731 ranges = <0 0 0x146bf000 0x1000>;
4734 compatible = "qcom,pil-reloc-info";
4739 apps_smmu: iommu@15000000 {
4740 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4741 reg = <0 0x15000000 0 0x80000>;
4743 #global-interrupts = <1>;
4744 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4745 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4746 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4747 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4748 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4749 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4750 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4751 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4752 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4753 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4754 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4755 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4756 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4757 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4758 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4759 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4760 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4761 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4762 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4763 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4764 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4765 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4766 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4767 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4768 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4769 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4770 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4771 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4772 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4773 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4774 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4775 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4776 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4777 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4778 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4779 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4780 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4781 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4782 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4783 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4784 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4785 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4786 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4787 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4788 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4789 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4790 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4791 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4792 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4793 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4794 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4795 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4796 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4797 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4798 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4799 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4800 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4801 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4802 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4803 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4804 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4805 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4806 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4807 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4808 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4811 lpasscc: clock-controller@17014000 {
4812 compatible = "qcom,sdm845-lpasscc";
4813 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4814 reg-names = "cc", "qdsp6ss";
4816 status = "disabled";
4819 gladiator_noc: interconnect@17900000 {
4820 compatible = "qcom,sdm845-gladiator-noc";
4821 reg = <0 0x17900000 0 0xd080>;
4822 #interconnect-cells = <2>;
4823 qcom,bcm-voters = <&apps_bcm_voter>;
4827 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4828 reg = <0 0x17980000 0 0x1000>;
4829 clocks = <&sleep_clk>;
4830 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4833 apss_shared: mailbox@17990000 {
4834 compatible = "qcom,sdm845-apss-shared";
4835 reg = <0 0x17990000 0 0x1000>;
4839 apps_rsc: rsc@179c0000 {
4841 compatible = "qcom,rpmh-rsc";
4842 reg = <0 0x179c0000 0 0x10000>,
4843 <0 0x179d0000 0 0x10000>,
4844 <0 0x179e0000 0 0x10000>;
4845 reg-names = "drv-0", "drv-1", "drv-2";
4846 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4847 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4848 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4849 qcom,tcs-offset = <0xd00>;
4851 qcom,tcs-config = <ACTIVE_TCS 2>,
4856 apps_bcm_voter: bcm-voter {
4857 compatible = "qcom,bcm-voter";
4860 rpmhcc: clock-controller {
4861 compatible = "qcom,sdm845-rpmh-clk";
4864 clocks = <&xo_board>;
4867 rpmhpd: power-controller {
4868 compatible = "qcom,sdm845-rpmhpd";
4869 #power-domain-cells = <1>;
4870 operating-points-v2 = <&rpmhpd_opp_table>;
4872 rpmhpd_opp_table: opp-table {
4873 compatible = "operating-points-v2";
4875 rpmhpd_opp_ret: opp1 {
4876 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4879 rpmhpd_opp_min_svs: opp2 {
4880 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4883 rpmhpd_opp_low_svs: opp3 {
4884 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4887 rpmhpd_opp_svs: opp4 {
4888 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4891 rpmhpd_opp_svs_l1: opp5 {
4892 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4895 rpmhpd_opp_nom: opp6 {
4896 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4899 rpmhpd_opp_nom_l1: opp7 {
4900 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4903 rpmhpd_opp_nom_l2: opp8 {
4904 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4907 rpmhpd_opp_turbo: opp9 {
4908 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4911 rpmhpd_opp_turbo_l1: opp10 {
4912 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4918 intc: interrupt-controller@17a00000 {
4919 compatible = "arm,gic-v3";
4920 #address-cells = <2>;
4923 #interrupt-cells = <3>;
4924 interrupt-controller;
4925 reg = <0 0x17a00000 0 0x10000>, /* GICD */
4926 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
4927 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4929 msi-controller@17a40000 {
4930 compatible = "arm,gic-v3-its";
4933 reg = <0 0x17a40000 0 0x20000>;
4934 status = "disabled";
4938 slimbam: dma-controller@17184000 {
4939 compatible = "qcom,bam-v1.7.0";
4940 qcom,controlled-remotely;
4941 reg = <0 0x17184000 0 0x2a000>;
4942 num-channels = <31>;
4943 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4947 iommus = <&apps_smmu 0x1806 0x0>;
4951 #address-cells = <2>;
4954 compatible = "arm,armv7-timer-mem";
4955 reg = <0 0x17c90000 0 0x1000>;
4959 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4960 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4961 reg = <0 0x17ca0000 0 0x1000>,
4962 <0 0x17cb0000 0 0x1000>;
4967 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4968 reg = <0 0x17cc0000 0 0x1000>;
4969 status = "disabled";
4974 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4975 reg = <0 0x17cd0000 0 0x1000>;
4976 status = "disabled";
4981 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4982 reg = <0 0x17ce0000 0 0x1000>;
4983 status = "disabled";
4988 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4989 reg = <0 0x17cf0000 0 0x1000>;
4990 status = "disabled";
4995 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4996 reg = <0 0x17d00000 0 0x1000>;
4997 status = "disabled";
5002 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5003 reg = <0 0x17d10000 0 0x1000>;
5004 status = "disabled";
5008 osm_l3: interconnect@17d41000 {
5009 compatible = "qcom,sdm845-osm-l3";
5010 reg = <0 0x17d41000 0 0x1400>;
5012 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5013 clock-names = "xo", "alternate";
5015 #interconnect-cells = <1>;
5018 cpufreq_hw: cpufreq@17d43000 {
5019 compatible = "qcom,cpufreq-hw";
5020 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5021 reg-names = "freq-domain0", "freq-domain1";
5023 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5025 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5026 clock-names = "xo", "alternate";
5028 #freq-domain-cells = <1>;
5031 wifi: wifi@18800000 {
5032 compatible = "qcom,wcn3990-wifi";
5033 status = "disabled";
5034 reg = <0 0x18800000 0 0x800000>;
5035 reg-names = "membase";
5036 memory-region = <&wlan_msa_mem>;
5037 clock-names = "cxo_ref_clk_pin";
5038 clocks = <&rpmhcc RPMH_RF_CLK2>;
5040 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5041 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5042 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5043 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5045 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5046 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5047 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5048 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5049 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5050 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5051 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5052 iommus = <&apps_smmu 0x0040 0x1>;
5058 polling-delay-passive = <250>;
5059 polling-delay = <1000>;
5061 thermal-sensors = <&tsens0 1>;
5064 cpu0_alert0: trip-point0 {
5065 temperature = <90000>;
5066 hysteresis = <2000>;
5070 cpu0_alert1: trip-point1 {
5071 temperature = <95000>;
5072 hysteresis = <2000>;
5076 cpu0_crit: cpu_crit {
5077 temperature = <110000>;
5078 hysteresis = <1000>;
5085 polling-delay-passive = <250>;
5086 polling-delay = <1000>;
5088 thermal-sensors = <&tsens0 2>;
5091 cpu1_alert0: trip-point0 {
5092 temperature = <90000>;
5093 hysteresis = <2000>;
5097 cpu1_alert1: trip-point1 {
5098 temperature = <95000>;
5099 hysteresis = <2000>;
5103 cpu1_crit: cpu_crit {
5104 temperature = <110000>;
5105 hysteresis = <1000>;
5112 polling-delay-passive = <250>;
5113 polling-delay = <1000>;
5115 thermal-sensors = <&tsens0 3>;
5118 cpu2_alert0: trip-point0 {
5119 temperature = <90000>;
5120 hysteresis = <2000>;
5124 cpu2_alert1: trip-point1 {
5125 temperature = <95000>;
5126 hysteresis = <2000>;
5130 cpu2_crit: cpu_crit {
5131 temperature = <110000>;
5132 hysteresis = <1000>;
5139 polling-delay-passive = <250>;
5140 polling-delay = <1000>;
5142 thermal-sensors = <&tsens0 4>;
5145 cpu3_alert0: trip-point0 {
5146 temperature = <90000>;
5147 hysteresis = <2000>;
5151 cpu3_alert1: trip-point1 {
5152 temperature = <95000>;
5153 hysteresis = <2000>;
5157 cpu3_crit: cpu_crit {
5158 temperature = <110000>;
5159 hysteresis = <1000>;
5166 polling-delay-passive = <250>;
5167 polling-delay = <1000>;
5169 thermal-sensors = <&tsens0 7>;
5172 cpu4_alert0: trip-point0 {
5173 temperature = <90000>;
5174 hysteresis = <2000>;
5178 cpu4_alert1: trip-point1 {
5179 temperature = <95000>;
5180 hysteresis = <2000>;
5184 cpu4_crit: cpu_crit {
5185 temperature = <110000>;
5186 hysteresis = <1000>;
5193 polling-delay-passive = <250>;
5194 polling-delay = <1000>;
5196 thermal-sensors = <&tsens0 8>;
5199 cpu5_alert0: trip-point0 {
5200 temperature = <90000>;
5201 hysteresis = <2000>;
5205 cpu5_alert1: trip-point1 {
5206 temperature = <95000>;
5207 hysteresis = <2000>;
5211 cpu5_crit: cpu_crit {
5212 temperature = <110000>;
5213 hysteresis = <1000>;
5220 polling-delay-passive = <250>;
5221 polling-delay = <1000>;
5223 thermal-sensors = <&tsens0 9>;
5226 cpu6_alert0: trip-point0 {
5227 temperature = <90000>;
5228 hysteresis = <2000>;
5232 cpu6_alert1: trip-point1 {
5233 temperature = <95000>;
5234 hysteresis = <2000>;
5238 cpu6_crit: cpu_crit {
5239 temperature = <110000>;
5240 hysteresis = <1000>;
5247 polling-delay-passive = <250>;
5248 polling-delay = <1000>;
5250 thermal-sensors = <&tsens0 10>;
5253 cpu7_alert0: trip-point0 {
5254 temperature = <90000>;
5255 hysteresis = <2000>;
5259 cpu7_alert1: trip-point1 {
5260 temperature = <95000>;
5261 hysteresis = <2000>;
5265 cpu7_crit: cpu_crit {
5266 temperature = <110000>;
5267 hysteresis = <1000>;
5274 polling-delay-passive = <250>;
5275 polling-delay = <1000>;
5277 thermal-sensors = <&tsens0 0>;
5280 aoss0_alert0: trip-point0 {
5281 temperature = <90000>;
5282 hysteresis = <2000>;
5289 polling-delay-passive = <250>;
5290 polling-delay = <1000>;
5292 thermal-sensors = <&tsens0 5>;
5295 cluster0_alert0: trip-point0 {
5296 temperature = <90000>;
5297 hysteresis = <2000>;
5300 cluster0_crit: cluster0_crit {
5301 temperature = <110000>;
5302 hysteresis = <2000>;
5309 polling-delay-passive = <250>;
5310 polling-delay = <1000>;
5312 thermal-sensors = <&tsens0 6>;
5315 cluster1_alert0: trip-point0 {
5316 temperature = <90000>;
5317 hysteresis = <2000>;
5320 cluster1_crit: cluster1_crit {
5321 temperature = <110000>;
5322 hysteresis = <2000>;
5329 polling-delay-passive = <250>;
5330 polling-delay = <1000>;
5332 thermal-sensors = <&tsens0 11>;
5335 gpu1_alert0: trip-point0 {
5336 temperature = <90000>;
5337 hysteresis = <2000>;
5343 gpu-bottom-thermal {
5344 polling-delay-passive = <250>;
5345 polling-delay = <1000>;
5347 thermal-sensors = <&tsens0 12>;
5350 gpu2_alert0: trip-point0 {
5351 temperature = <90000>;
5352 hysteresis = <2000>;
5359 polling-delay-passive = <250>;
5360 polling-delay = <1000>;
5362 thermal-sensors = <&tsens1 0>;
5365 aoss1_alert0: trip-point0 {
5366 temperature = <90000>;
5367 hysteresis = <2000>;
5374 polling-delay-passive = <250>;
5375 polling-delay = <1000>;
5377 thermal-sensors = <&tsens1 1>;
5380 q6_modem_alert0: trip-point0 {
5381 temperature = <90000>;
5382 hysteresis = <2000>;
5389 polling-delay-passive = <250>;
5390 polling-delay = <1000>;
5392 thermal-sensors = <&tsens1 2>;
5395 mem_alert0: trip-point0 {
5396 temperature = <90000>;
5397 hysteresis = <2000>;
5404 polling-delay-passive = <250>;
5405 polling-delay = <1000>;
5407 thermal-sensors = <&tsens1 3>;
5410 wlan_alert0: trip-point0 {
5411 temperature = <90000>;
5412 hysteresis = <2000>;
5419 polling-delay-passive = <250>;
5420 polling-delay = <1000>;
5422 thermal-sensors = <&tsens1 4>;
5425 q6_hvx_alert0: trip-point0 {
5426 temperature = <90000>;
5427 hysteresis = <2000>;
5434 polling-delay-passive = <250>;
5435 polling-delay = <1000>;
5437 thermal-sensors = <&tsens1 5>;
5440 camera_alert0: trip-point0 {
5441 temperature = <90000>;
5442 hysteresis = <2000>;
5449 polling-delay-passive = <250>;
5450 polling-delay = <1000>;
5452 thermal-sensors = <&tsens1 6>;
5455 video_alert0: trip-point0 {
5456 temperature = <90000>;
5457 hysteresis = <2000>;
5464 polling-delay-passive = <250>;
5465 polling-delay = <1000>;
5467 thermal-sensors = <&tsens1 7>;
5470 modem_alert0: trip-point0 {
5471 temperature = <90000>;
5472 hysteresis = <2000>;