1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018, Craig Tatlor.
4 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
11 interrupt-parent = <&intc>;
20 compatible = "fixed-clock";
22 clock-frequency = <19200000>;
23 clock-output-names = "xo_board";
26 sleep_clk: sleep_clk {
27 compatible = "fixed-clock";
29 clock-frequency = <32764>;
30 clock-output-names = "sleep_clk";
40 compatible = "qcom,kryo260";
42 enable-method = "psci";
43 capacity-dmips-mhz = <1024>;
44 next-level-cache = <&L2_1>;
59 compatible = "qcom,kryo260";
61 enable-method = "psci";
62 capacity-dmips-mhz = <1024>;
63 next-level-cache = <&L2_1>;
74 compatible = "qcom,kryo260";
76 enable-method = "psci";
77 capacity-dmips-mhz = <1024>;
78 next-level-cache = <&L2_1>;
89 compatible = "qcom,kryo260";
91 enable-method = "psci";
92 capacity-dmips-mhz = <1024>;
93 next-level-cache = <&L2_1>;
104 compatible = "qcom,kryo260";
106 enable-method = "psci";
107 capacity-dmips-mhz = <640>;
108 next-level-cache = <&L2_0>;
110 compatible = "cache";
114 compatible = "cache";
117 compatible = "cache";
123 compatible = "qcom,kryo260";
125 enable-method = "psci";
126 capacity-dmips-mhz = <640>;
127 next-level-cache = <&L2_0>;
129 compatible = "cache";
132 compatible = "cache";
138 compatible = "qcom,kryo260";
140 enable-method = "psci";
141 capacity-dmips-mhz = <640>;
142 next-level-cache = <&L2_0>;
144 compatible = "cache";
147 compatible = "cache";
153 compatible = "qcom,kryo260";
155 enable-method = "psci";
156 capacity-dmips-mhz = <640>;
157 next-level-cache = <&L2_0>;
159 compatible = "cache";
162 compatible = "cache";
207 compatible = "qcom,scm";
212 device_type = "memory";
213 /* We expect the bootloader to fill in the reg */
218 compatible = "arm,psci-1.0";
223 compatible = "arm,armv8-timer";
224 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
225 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
226 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
227 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
231 #address-cells = <1>;
233 ranges = <0 0 0 0xffffffff>;
234 compatible = "simple-bus";
236 gcc: clock-controller@100000 {
237 compatible = "qcom,gcc-sdm660";
240 #power-domain-cells = <1>;
241 reg = <0x00100000 0x94000>;
244 tlmm: pinctrl@3100000 {
245 compatible = "qcom,sdm660-pinctrl";
246 reg = <0x03100000 0x400000>,
247 <0x03500000 0x400000>,
248 <0x03900000 0x400000>;
249 reg-names = "south", "center", "north";
250 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
252 gpio-ranges = <&tlmm 0 0 114>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
257 uart_console_active: uart_console_active {
259 pins = "gpio4", "gpio5";
260 function = "blsp_uart2";
264 pins = "gpio4", "gpio5";
265 drive-strength = <2>;
271 spmi_bus: spmi@800f000 {
272 compatible = "qcom,spmi-pmic-arb";
273 reg = <0x0800f000 0x1000>,
274 <0x08400000 0x1000000>,
275 <0x09400000 0x1000000>,
276 <0x0a400000 0x220000>,
278 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
279 interrupt-names = "periph_irq";
280 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <2>;
285 interrupt-controller;
286 #interrupt-cells = <4>;
290 blsp1_uart2: serial@c170000 {
291 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
292 reg = <0x0c170000 0x1000>;
293 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
295 <&gcc GCC_BLSP1_AHB_CLK>;
296 clock-names = "core", "iface";
301 #address-cells = <1>;
304 compatible = "arm,armv7-timer-mem";
305 reg = <0x17920000 0x1000>;
309 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
311 reg = <0x17921000 0x1000>,
317 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
318 reg = <0x17923000 0x1000>;
324 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
325 reg = <0x17924000 0x1000>;
331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
332 reg = <0x17925000 0x1000>;
338 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
339 reg = <0x17926000 0x1000>;
345 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
346 reg = <0x17927000 0x1000>;
352 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
353 reg = <0x17928000 0x1000>;
358 intc: interrupt-controller@17a00000 {
359 compatible = "arm,gic-v3";
360 reg = <0x17a00000 0x10000>,
361 <0x17b00000 0x100000>;
362 #interrupt-cells = <3>;
363 #address-cells = <1>;
366 interrupt-controller;
367 #redistributor-regions = <1>;
368 redistributor-stride = <0x0 0x20000>;
369 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;