arch/arm64/boot/dts/qcom/sdm630.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Konrad Dybcio
   4  */
   5
   6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         clocks {
  20                 xo_board: xo_board {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <19200000>;
  24                         clock-output-names = "xo_board";
  25                 };
  26
  27                 sleep_clk: sleep_clk {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <32764>;
  31                         clock-output-names = "sleep_clk";
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <2>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@100 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         reg = <0x0 0x100>;
  43                         enable-method = "psci";
  44                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  45                                                 &PERF_CPU_SLEEP_1
  46                                                 &PERF_CLUSTER_SLEEP_0
  47                                                 &PERF_CLUSTER_SLEEP_1
  48                                                 &PERF_CLUSTER_SLEEP_2>;
  49                         capacity-dmips-mhz = <1126>;
  50                         #cooling-cells = <2>;
  51                         next-level-cache = <&L2_1>;
  52                         L2_1: l2-cache {
  53                                 compatible = "cache";
  54                                 cache-level = <2>;
  55                         };
  56                 };
  57
  58                 CPU1: cpu@101 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61                         reg = <0x0 0x101>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  64                                                 &PERF_CPU_SLEEP_1
  65                                                 &PERF_CLUSTER_SLEEP_0
  66                                                 &PERF_CLUSTER_SLEEP_1
  67                                                 &PERF_CLUSTER_SLEEP_2>;
  68                         capacity-dmips-mhz = <1126>;
  69                         #cooling-cells = <2>;
  70                         next-level-cache = <&L2_1>;
  71                 };
  72
  73                 CPU2: cpu@102 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53";
  76                         reg = <0x0 0x102>;
  77                         enable-method = "psci";
  78                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  79                                                 &PERF_CPU_SLEEP_1
  80                                                 &PERF_CLUSTER_SLEEP_0
  81                                                 &PERF_CLUSTER_SLEEP_1
  82                                                 &PERF_CLUSTER_SLEEP_2>;
  83                         capacity-dmips-mhz = <1126>;
  84                         #cooling-cells = <2>;
  85                         next-level-cache = <&L2_1>;
  86                 };
  87
  88                 CPU3: cpu@103 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53";
  91                         reg = <0x0 0x103>;
  92                         enable-method = "psci";
  93                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  94                                                 &PERF_CPU_SLEEP_1
  95                                                 &PERF_CLUSTER_SLEEP_0
  96                                                 &PERF_CLUSTER_SLEEP_1
  97                                                 &PERF_CLUSTER_SLEEP_2>;
  98                         capacity-dmips-mhz = <1126>;
  99                         #cooling-cells = <2>;
 100                         next-level-cache = <&L2_1>;
 101                 };
 102
 103                 CPU4: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53";
 106                         reg = <0x0 0x0>;
 107                         enable-method = "psci";
 108                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 109                                                 &PWR_CPU_SLEEP_1
 110                                                 &PWR_CLUSTER_SLEEP_0
 111                                                 &PWR_CLUSTER_SLEEP_1
 112                                                 &PWR_CLUSTER_SLEEP_2>;
 113                         capacity-dmips-mhz = <1024>;
 114                         #cooling-cells = <2>;
 115                         next-level-cache = <&L2_0>;
 116                         L2_0: l2-cache {
 117                                 compatible = "cache";
 118                                 cache-level = <2>;
 119                         };
 120                 };
 121
 122                 CPU5: cpu@1 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53";
 125                         reg = <0x0 0x1>;
 126                         enable-method = "psci";
 127                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 128                                                 &PWR_CPU_SLEEP_1
 129                                                 &PWR_CLUSTER_SLEEP_0
 130                                                 &PWR_CLUSTER_SLEEP_1
 131                                                 &PWR_CLUSTER_SLEEP_2>;
 132                         capacity-dmips-mhz = <1024>;
 133                         #cooling-cells = <2>;
 134                         next-level-cache = <&L2_0>;
 135                 };
 136
 137                 CPU6: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 143                                                 &PWR_CPU_SLEEP_1
 144                                                 &PWR_CLUSTER_SLEEP_0
 145                                                 &PWR_CLUSTER_SLEEP_1
 146                                                 &PWR_CLUSTER_SLEEP_2>;
 147                         capacity-dmips-mhz = <1024>;
 148                         #cooling-cells = <2>;
 149                         next-level-cache = <&L2_0>;
 150                 };
 151
 152                 CPU7: cpu@3 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a53";
 155                         reg = <0x0 0x3>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 158                                                 &PWR_CPU_SLEEP_1
 159                                                 &PWR_CLUSTER_SLEEP_0
 160                                                 &PWR_CLUSTER_SLEEP_1
 161                                                 &PWR_CLUSTER_SLEEP_2>;
 162                         capacity-dmips-mhz = <1024>;
 163                         #cooling-cells = <2>;
 164                         next-level-cache = <&L2_0>;
 165                 };
 166
 167                 cpu-map {
 168                         cluster0 {
 169                                 core0 {
 170                                         cpu = <&CPU4>;
 171                                 };
 172
 173                                 core1 {
 174                                         cpu = <&CPU5>;
 175                                 };
 176
 177                                 core2 {
 178                                         cpu = <&CPU6>;
 179                                 };
 180
 181                                 core3 {
 182                                         cpu = <&CPU7>;
 183                                 };
 184                         };
 185
 186                         cluster1 {
 187                                 core0 {
 188                                         cpu = <&CPU0>;
 189                                 };
 190
 191                                 core1 {
 192                                         cpu = <&CPU1>;
 193                                 };
 194
 195                                 core2 {
 196                                         cpu = <&CPU2>;
 197                                 };
 198
 199                                 core3 {
 200                                         cpu = <&CPU3>;
 201                                 };
 202                         };
 203                 };
 204
 205                 idle-states {
 206                         entry-method = "psci";
 207
 208                         PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
 209                                 compatible = "arm,idle-state";
 210                                 idle-state-name = "pwr-retention";
 211                                 arm,psci-suspend-param = <0x40000002>;
 212                                 entry-latency-us = <338>;
 213                                 exit-latency-us = <423>;
 214                                 min-residency-us = <200>;
 215                         };
 216
 217                         PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
 218                                 compatible = "arm,idle-state";
 219                                 idle-state-name = "pwr-power-collapse";
 220                                 arm,psci-suspend-param = <0x40000003>;
 221                                 entry-latency-us = <515>;
 222                                 exit-latency-us = <1821>;
 223                                 min-residency-us = <1000>;
 224                                 local-timer-stop;
 225                         };
 226
 227                         PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
 228                                 compatible = "arm,idle-state";
 229                                 idle-state-name = "perf-retention";
 230                                 arm,psci-suspend-param = <0x40000002>;
 231                                 entry-latency-us = <154>;
 232                                 exit-latency-us = <87>;
 233                                 min-residency-us = <200>;
 234                         };
 235
 236                         PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
 237                                 compatible = "arm,idle-state";
 238                                 idle-state-name = "perf-power-collapse";
 239                                 arm,psci-suspend-param = <0x40000003>;
 240                                 entry-latency-us = <262>;
 241                                 exit-latency-us = <301>;
 242                                 min-residency-us = <1000>;
 243                                 local-timer-stop;
 244                         };
 245
 246                         PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
 247                                 compatible = "arm,idle-state";
 248                                 idle-state-name = "pwr-cluster-dynamic-retention";
 249                                 arm,psci-suspend-param = <0x400000F2>;
 250                                 entry-latency-us = <284>;
 251                                 exit-latency-us = <384>;
 252                                 min-residency-us = <9987>;
 253                                 local-timer-stop;
 254                         };
 255
 256                         PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
 257                                 compatible = "arm,idle-state";
 258                                 idle-state-name = "pwr-cluster-retention";
 259                                 arm,psci-suspend-param = <0x400000F3>;
 260                                 entry-latency-us = <338>;
 261                                 exit-latency-us = <423>;
 262                                 min-residency-us = <9987>;
 263                                 local-timer-stop;
 264                         };
 265
 266                         PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
 267                                 compatible = "arm,idle-state";
 268                                 idle-state-name = "pwr-cluster-retention";
 269                                 arm,psci-suspend-param = <0x400000F4>;
 270                                 entry-latency-us = <515>;
 271                                 exit-latency-us = <1821>;
 272                                 min-residency-us = <9987>;
 273                                 local-timer-stop;
 274                         };
 275
 276                         PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
 277                                 compatible = "arm,idle-state";
 278                                 idle-state-name = "perf-cluster-dynamic-retention";
 279                                 arm,psci-suspend-param = <0x400000F2>;
 280                                 entry-latency-us = <272>;
 281                                 exit-latency-us = <329>;
 282                                 min-residency-us = <9987>;
 283                                 local-timer-stop;
 284                         };
 285
 286                         PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
 287                                 compatible = "arm,idle-state";
 288                                 idle-state-name = "perf-cluster-retention";
 289                                 arm,psci-suspend-param = <0x400000F3>;
 290                                 entry-latency-us = <332>;
 291                                 exit-latency-us = <368>;
 292                                 min-residency-us = <9987>;
 293                                 local-timer-stop;
 294                         };
 295
 296                         PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
 297                                 compatible = "arm,idle-state";
 298                                 idle-state-name = "perf-cluster-retention";
 299                                 arm,psci-suspend-param = <0x400000F4>;
 300                                 entry-latency-us = <545>;
 301                                 exit-latency-us = <1609>;
 302                                 min-residency-us = <9987>;
 303                                 local-timer-stop;
 304                         };
 305                 };
 306         };
 307
 308         firmware {
 309                 scm {
 310                         compatible = "qcom,scm-msm8998", "qcom,scm";
 311                 };
 312         };
 313
 314         memory {
 315                 device_type = "memory";
 316                 /* We expect the bootloader to fill in the reg */
 317                 reg = <0 0 0 0>;
 318         };
 319
 320         pmu {
 321                 compatible = "arm,armv8-pmuv3";
 322                 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 323         };
 324
 325         psci {
 326                 compatible = "arm,psci-1.0";
 327                 method = "smc";
 328         };
 329
 330         reserved-memory {
 331                 #address-cells = <2>;
 332                 #size-cells = <2>;
 333                 ranges;
 334
 335                 wlan_msa_guard: wlan-msa-guard@85600000 {
 336                         reg = <0x0 0x85600000 0x0 0x100000>;
 337                         no-map;
 338                 };
 339
 340                 wlan_msa_mem: wlan-msa-mem@85700000 {
 341                         reg = <0x0 0x85700000 0x0 0x100000>;
 342                         no-map;
 343                 };
 344
 345                 qhee_code: qhee-code@85800000 {
 346                         reg = <0x0 0x85800000 0x0 0x3700000>;
 347                         no-map;
 348                 };
 349
 350                 smem_region: smem-mem@86000000 {
 351                         reg = <0 0x86000000 0 0x200000>;
 352                         no-map;
 353                 };
 354
 355                 tz_mem: memory@86200000 {
 356                         reg = <0x0 0x86200000 0x0 0x3300000>;
 357                         no-map;
 358                 };
 359
 360                 modem_fw_mem: modem-fw-region@8ac00000 {
 361                         reg = <0x0 0x8ac00000 0x0 0x7e00000>;
 362                         no-map;
 363                 };
 364
 365                 adsp_fw_mem: adsp-fw-region@92a00000 {
 366                         reg = <0x0 0x92a00000 0x0 0x1e00000>;
 367                         no-map;
 368                 };
 369
 370                 pil_mba_mem: pil-mba-region@94800000 {
 371                         reg = <0x0 0x94800000 0x0 0x200000>;
 372                         no-map;
 373                 };
 374
 375                 buffer_mem: buffer-region@94a00000 {
 376                         reg = <0x0 0x94a00000 0x0 0x100000>;
 377                         no-map;
 378                 };
 379
 380                 venus_fw_mem: venus-fw-region@9f800000 {
 381                         reg = <0x0 0x9f800000 0x0 0x800000>;
 382                         no-map;
 383                 };
 384
 385                 secure_region2: secure-region2@f7c00000 {
 386                         reg = <0x0 0xf7c00000 0x0 0x5c00000>;
 387                         no-map;
 388                 };
 389
 390                 adsp_mem: adsp-region@f6000000 {
 391                         reg = <0x0 0xf6000000 0x0 0x800000>;
 392                         no-map;
 393                 };
 394
 395                 qseecom_ta_mem: qseecom-ta-region@fec00000 {
 396                         reg = <0x0 0xfec00000 0x0 0x1000000>;
 397                         no-map;
 398                 };
 399
 400                 qseecom_mem: qseecom-region@f6800000 {
 401                         reg = <0x0 0xf6800000 0x0 0x1400000>;
 402                         no-map;
 403                 };
 404
 405                 secure_display_memory: secure-region@f5c00000 {
 406                         reg = <0x0 0xf5c00000 0x0 0x5c00000>;
 407                         no-map;
 408                 };
 409
 410                 cont_splash_mem: cont-splash-region@9d400000 {
 411                         reg = <0x0 0x9d400000 0x0 0x23ff000>;
 412                         no-map;
 413                 };
 414         };
 415
 416         rpm-glink {
 417                 compatible = "qcom,glink-rpm";
 418
 419                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 420                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 421                 mboxes = <&apcs_glb 0>;
 422
 423                 rpm_requests: rpm-requests {
 424                         compatible = "qcom,rpm-sdm660";
 425                         qcom,glink-channels = "rpm_requests";
 426
 427                         rpmcc: clock-controller {
 428                                 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
 429                                 #clock-cells = <1>;
 430                         };
 431                 };
 432         };
 433
 434         smem: smem {
 435                 compatible = "qcom,smem";
 436                 memory-region = <&smem_region>;
 437                 hwlocks = <&tcsr_mutex 3>;
 438         };
 439
 440         soc {
 441                 #address-cells = <1>;
 442                 #size-cells = <1>;
 443                 ranges = <0 0 0 0xffffffff>;
 444                 compatible = "simple-bus";
 445
 446                 gcc: clock-controller@100000 {
 447                         compatible = "qcom,gcc-sdm630";
 448                         #clock-cells = <1>;
 449                         #reset-cells = <1>;
 450                         #power-domain-cells = <1>;
 451                         reg = <0x00100000 0x94000>;
 452
 453                         clock-names = "xo", "sleep_clk";
 454                         clocks = <&xo_board>,
 455                                         <&sleep_clk>;
 456                 };
 457
 458                 rpm_msg_ram: memory@778000 {
 459                         compatible = "qcom,rpm-msg-ram";
 460                         reg = <0x00778000 0x7000>;
 461                 };
 462
 463                 qfprom: qfprom@780000 {
 464                         compatible = "qcom,qfprom";
 465                         reg = <0x00780000 0x621c>;
 466                         #address-cells = <1>;
 467                         #size-cells = <1>;
 468                 };
 469
 470                 rng: rng@793000 {
 471                         compatible = "qcom,prng-ee";
 472                         reg = <0x00793000 0x1000>;
 473                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 474                         clock-names = "core";
 475                 };
 476
 477                 restart@10ac000 {
 478                         compatible = "qcom,pshold";
 479                         reg = <0x010ac000 0x4>;
 480                 };
 481
 482                 anoc2_smmu: iommu@16c0000 {
 483                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
 484                         reg = <0x016c0000 0x40000>;
 485                         #iommu-cells = <1>;
 486
 487                         #global-interrupts = <2>;
 488                         interrupts =
 489                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 490                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 491
 492                                 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
 493                                 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
 494                                 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
 495                                 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
 496                                 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
 497                                 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
 498                                 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 499                                 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 500                                 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 501                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 502                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 503                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 504                                 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 505                                 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 506                                 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 507                                 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
 508                                 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
 509                                 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 510                                 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 511                                 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 512                                 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
 513                                 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
 514                                 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
 515                                 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
 516                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 517                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 518                                 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 519                                 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 520                                 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
 521
 522                         status = "disabled";
 523                 };
 524
 525                 tcsr_mutex_regs: syscon@1f40000 {
 526                         compatible = "syscon";
 527                         reg = <0x01f40000 0x20000>;
 528                 };
 529
 530                 tlmm: pinctrl@3000000 {
 531                         compatible = "qcom,sdm630-pinctrl";
 532                         reg = <0x03000000 0xc00000>;
 533                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 534                         gpio-controller;
 535                         #gpio-cells = <0x2>;
 536                         interrupt-controller;
 537                         #interrupt-cells = <0x2>;
 538
 539                         blsp1_uart1_default: blsp1-uart1-default {
 540                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 541                                 drive-strength = <2>;
 542                                 bias-disable;
 543                         };
 544
 545                         blsp1_uart1_sleep: blsp1-uart1-sleep {
 546                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 547                                 drive-strength = <2>;
 548                                 bias-disable;
 549                         };
 550
 551                         blsp1_uart2_default: blsp1-uart2-default {
 552                                 pins = "gpio4", "gpio5";
 553                                 drive-strength = <2>;
 554                                 bias-disable;
 555                         };
 556
 557                         blsp2_uart1_tx_active: blsp2-uart1-tx-active {
 558                                 pins = "gpio16";
 559                                 drive-strength = <2>;
 560                                 bias-disable;
 561                         };
 562
 563                         blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
 564                                 pins = "gpio16";
 565                                 drive-strength = <2>;
 566                                 bias-pull-up;
 567                         };
 568
 569                         blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
 570                                 pins = "gpio17", "gpio18";
 571                                 drive-strength = <2>;
 572                                 bias-disable;
 573                         };
 574
 575                         blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
 576                                 pins = "gpio17", "gpio18";
 577                                 drive-strength = <2>;
 578                                 bias-no-pull;
 579                         };
 580
 581                         blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
 582                                 pins = "gpio19";
 583                                 drive-strength = <2>;
 584                                 bias-disable;
 585                         };
 586
 587                         blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
 588                                 pins = "gpio19";
 589                                 drive-strength = <2>;
 590                                 bias-no-pull;
 591                         };
 592
 593                         i2c1_default: i2c1-default {
 594                                 pins = "gpio2", "gpio3";
 595                                 drive-strength = <2>;
 596                                 bias-disable;
 597                         };
 598
 599                         i2c1_sleep: i2c1-sleep {
 600                                 pins = "gpio2", "gpio3";
 601                                 drive-strength = <2>;
 602                                 bias-pull-up;
 603                         };
 604
 605                         i2c2_default: i2c2-default {
 606                                 pins = "gpio6", "gpio7";
 607                                 drive-strength = <2>;
 608                                 bias-disable;
 609                         };
 610
 611                         i2c2_sleep: i2c2-sleep {
 612                                 pins = "gpio6", "gpio7";
 613                                 drive-strength = <2>;
 614                                 bias-pull-up;
 615                         };
 616
 617                         i2c3_default: i2c3-default {
 618                                 pins = "gpio10", "gpio11";
 619                                 drive-strength = <2>;
 620                                 bias-disable;
 621                         };
 622
 623                         i2c3_sleep: i2c3-sleep {
 624                                 pins = "gpio10", "gpio11";
 625                                 drive-strength = <2>;
 626                                 bias-pull-up;
 627                         };
 628
 629                         i2c4_default: i2c4-default {
 630                                 pins = "gpio14", "gpio15";
 631                                 drive-strength = <2>;
 632                                 bias-disable;
 633                         };
 634
 635                         i2c4_sleep: i2c4-sleep {
 636                                 pins = "gpio14", "gpio15";
 637                                 drive-strength = <2>;
 638                                 bias-pull-up;
 639                         };
 640
 641                         i2c5_default: i2c5-default {
 642                                 pins = "gpio18", "gpio19";
 643                                 drive-strength = <2>;
 644                                 bias-disable;
 645                         };
 646
 647                         i2c5_sleep: i2c5-sleep {
 648                                 pins = "gpio18", "gpio19";
 649                                 drive-strength = <2>;
 650                                 bias-pull-up;
 651                         };
 652
 653                         i2c6_default: i2c6-default {
 654                                 pins = "gpio22", "gpio23";
 655                                 drive-strength = <2>;
 656                                 bias-disable;
 657                         };
 658
 659                         i2c6_sleep: i2c6-sleep {
 660                                 pins = "gpio22", "gpio23";
 661                                 drive-strength = <2>;
 662                                 bias-pull-up;
 663                         };
 664
 665                         i2c7_default: i2c7-default {
 666                                 pins = "gpio26", "gpio27";
 667                                 drive-strength = <2>;
 668                                 bias-disable;
 669                         };
 670
 671                         i2c7_sleep: i2c7-sleep {
 672                                 pins = "gpio26", "gpio27";
 673                                 drive-strength = <2>;
 674                                 bias-pull-up;
 675                         };
 676
 677                         i2c8_default: i2c8-default {
 678                                 pins = "gpio30", "gpio31";
 679                                 drive-strength = <2>;
 680                                 bias-disable;
 681                         };
 682
 683                         i2c8_sleep: i2c8-sleep {
 684                                 pins = "gpio30", "gpio31";
 685                                 drive-strength = <2>;
 686                                 bias-pull-up;
 687                         };
 688
 689                         sdc1_clk_on: sdc1-clk-on {
 690                                 pins = "sdc1_clk";
 691                                 bias-disable;
 692                                 drive-strength = <16>;
 693                         };
 694
 695                         sdc1_clk_off: sdc1-clk-off {
 696                                 pins = "sdc1_clk";
 697                                 bias-disable;
 698                                 drive-strength = <2>;
 699                         };
 700
 701                         sdc1_cmd_on: sdc1-cmd-on {
 702                                 pins = "sdc1_cmd";
 703                                 bias-pull-up;
 704                                 drive-strength = <10>;
 705                         };
 706
 707                         sdc1_cmd_off: sdc1-cmd-off {
 708                                 pins = "sdc1_cmd";
 709                                 bias-pull-up;
 710                                 drive-strength = <2>;
 711                         };
 712
 713                         sdc1_data_on: sdc1-data-on {
 714                                 pins = "sdc1_data";
 715                                 bias-pull-up;
 716                                 drive-strength = <8>;
 717                         };
 718
 719                         sdc1_data_off: sdc1-data-off {
 720                                 pins = "sdc1_data";
 721                                 bias-pull-up;
 722                                 drive-strength = <2>;
 723                         };
 724
 725                         sdc1_rclk_on: sdc1-rclk-on {
 726                                 pins = "sdc1_rclk";
 727                                 bias-pull-down;
 728                         };
 729
 730                         sdc1_rclk_off: sdc1-rclk-off {
 731                                 pins = "sdc1_rclk";
 732                                 bias-pull-down;
 733                         };
 734                 };
 735
 736                 kgsl_smmu: iommu@5040000 {
 737                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
 738                         reg = <0x05040000 0x10000>;
 739                         #iommu-cells = <1>;
 740
 741                         #global-interrupts = <2>;
 742                         interrupts =
 743                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 744                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 745
 746                                 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 747                                 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 748                                 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 749                                 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 750                                 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 751                                 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 752                                 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
 753                                 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
 754
 755                         status = "disabled";
 756                 };
 757
 758                 lpass_smmu: iommu@5100000 {
 759                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
 760                         reg = <0x05100000 0x40000>;
 761                         #iommu-cells = <1>;
 762
 763                         #global-interrupts = <2>;
 764                         interrupts =
 765                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 766                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 767
 768                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 769                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 770                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 771                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 772                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 773                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 774                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 775                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 776                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 777                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 778                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 779                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 780                                 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 781                                 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
 782                                 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
 783                                 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
 784                                 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 785
 786                         status = "disabled";
 787                 };
 788
 789                 spmi_bus: spmi@800f000 {
 790                         compatible = "qcom,spmi-pmic-arb";
 791                         reg =   <0x0800f000 0x1000>,
 792                                 <0x08400000 0x1000000>,
 793                                 <0x09400000 0x1000000>,
 794                                 <0x0a400000 0x220000>,
 795                                 <0x0800a000 0x3000>;
 796                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 797                         interrupt-names = "periph_irq";
 798                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 799                         qcom,ee = <0>;
 800                         qcom,channel = <0>;
 801                         #address-cells = <2>;
 802                         #size-cells = <0>;
 803                         interrupt-controller;
 804                         #interrupt-cells = <4>;
 805                         cell-index = <0>;
 806                 };
 807
 808                 sdhc_1: sdhci@c0c4000 {
 809                         compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
 810                         reg = <0x0c0c4000 0x1000>,
 811                               <0x0c0c5000 0x1000>,
 812                               <0x0c0c8000 0x8000>;
 813                         reg-names = "hc", "cqhci", "ice";
 814
 815                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 816                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 817                         interrupt-names = "hc_irq", "pwr_irq";
 818
 819                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 820                                  <&gcc GCC_SDCC1_AHB_CLK>,
 821                                  <&xo_board>,
 822                                  <&gcc GCC_SDCC1_ICE_CORE_CLK>;
 823                         clock-names = "core", "iface", "xo", "ice";
 824
 825                         pinctrl-names = "default", "sleep";
 826                         pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
 827                         pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
 828
 829                         bus-width = <8>;
 830                         non-removable;
 831
 832                         status = "disabled";
 833                 };
 834
 835                 blsp1_dma: dma-controller@c144000 {
 836                         compatible = "qcom,bam-v1.7.0";
 837                         reg = <0x0c144000 0x1f000>;
 838                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 839                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 840                         clock-names = "bam_clk";
 841                         #dma-cells = <1>;
 842                         qcom,ee = <0>;
 843                         qcom,controlled-remotely;
 844                         num-channels = <18>;
 845                         qcom,num-ees = <4>;
 846                 };
 847
 848                 blsp1_uart1: serial@c16f000 {
 849                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 850                         reg = <0x0c16f000 0x200>;
 851                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 852                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 853                                  <&gcc GCC_BLSP1_AHB_CLK>;
 854                         clock-names = "core", "iface";
 855                         dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
 856                         dma-names = "tx", "rx";
 857                         pinctrl-names = "default", "sleep";
 858                         pinctrl-0 = <&blsp1_uart1_default>;
 859                         pinctrl-1 = <&blsp1_uart1_sleep>;
 860                         status = "disabled";
 861                 };
 862
 863                 blsp1_uart2: serial@c170000 {
 864                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 865                         reg = <0x0c170000 0x1000>;
 866                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 867                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 868                                  <&gcc GCC_BLSP1_AHB_CLK>;
 869                         clock-names = "core", "iface";
 870                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
 871                         dma-names = "tx", "rx";
 872                         pinctrl-names = "default";
 873                         pinctrl-0 = <&blsp1_uart2_default>;
 874                         status = "disabled";
 875                 };
 876
 877                 blsp_i2c1: i2c@c175000 {
 878                         compatible = "qcom,i2c-qup-v2.2.1";
 879                         reg = <0x0c175000 0x600>;
 880                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 881
 882                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
 883                                         <&gcc GCC_BLSP1_AHB_CLK>;
 884                         clock-names = "core", "iface";
 885                         clock-frequency = <400000>;
 886
 887                         pinctrl-names = "default", "sleep";
 888                         pinctrl-0 = <&i2c1_default>;
 889                         pinctrl-1 = <&i2c1_sleep>;
 890                         #address-cells = <1>;
 891                         #size-cells = <0>;
 892                         status = "disabled";
 893                 };
 894
 895                 blsp_i2c2: i2c@c176000 {
 896                         compatible = "qcom,i2c-qup-v2.2.1";
 897                         reg = <0x0c176000 0x600>;
 898                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 899
 900                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 901                                  <&gcc GCC_BLSP1_AHB_CLK>;
 902                         clock-names = "core", "iface";
 903                         clock-frequency = <400000>;
 904
 905                         pinctrl-names = "default", "sleep";
 906                         pinctrl-0 = <&i2c2_default>;
 907                         pinctrl-1 = <&i2c2_sleep>;
 908                         #address-cells = <1>;
 909                         #size-cells = <0>;
 910                         status = "disabled";
 911                 };
 912
 913                 blsp_i2c3: i2c@c177000 {
 914                         compatible = "qcom,i2c-qup-v2.2.1";
 915                         reg = <0x0c177000 0x600>;
 916                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 917
 918                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 919                                  <&gcc GCC_BLSP1_AHB_CLK>;
 920                         clock-names = "core", "iface";
 921                         clock-frequency = <400000>;
 922
 923                         pinctrl-names = "default", "sleep";
 924                         pinctrl-0 = <&i2c3_default>;
 925                         pinctrl-1 = <&i2c3_sleep>;
 926                         #address-cells = <1>;
 927                         #size-cells = <0>;
 928                         status = "disabled";
 929                 };
 930
 931                 blsp_i2c4: i2c@c178000 {
 932                         compatible = "qcom,i2c-qup-v2.2.1";
 933                         reg = <0x0c178000 0x600>;
 934                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 935
 936                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 937                                  <&gcc GCC_BLSP1_AHB_CLK>;
 938                         clock-names = "core", "iface";
 939                         clock-frequency = <400000>;
 940
 941                         pinctrl-names = "default", "sleep";
 942                         pinctrl-0 = <&i2c4_default>;
 943                         pinctrl-1 = <&i2c4_sleep>;
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         status = "disabled";
 947                 };
 948
 949                 blsp2_dma: dma-controller@c184000 {
 950                         compatible = "qcom,bam-v1.7.0";
 951                         reg = <0x0c184000 0x1f000>;
 952                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 953                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 954                         clock-names = "bam_clk";
 955                         #dma-cells = <1>;
 956                         qcom,ee = <0>;
 957                         qcom,controlled-remotely;
 958                         num-channels = <18>;
 959                         qcom,num-ees = <4>;
 960                 };
 961
 962                 blsp2_uart1: serial@c1af000 {
 963                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 964                         reg = <0x0c1af000 0x200>;
 965                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 966                         clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
 967                                  <&gcc GCC_BLSP2_AHB_CLK>;
 968                         clock-names = "core", "iface";
 969                         dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
 970                         dma-names = "tx", "rx";
 971                         pinctrl-names = "default", "sleep";
 972                         pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
 973                                 &blsp2_uart1_rfr_active>;
 974                         pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
 975                                 &blsp2_uart1_rfr_sleep>;
 976                         status = "disabled";
 977                 };
 978
 979                 blsp_i2c5: i2c@c1b5000 {
 980                         compatible = "qcom,i2c-qup-v2.2.1";
 981                         reg = <0x0c1b5000 0x600>;
 982                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 983
 984                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
 985                                  <&gcc GCC_BLSP2_AHB_CLK>;
 986                         clock-names = "core", "iface";
 987                         clock-frequency = <400000>;
 988
 989                         pinctrl-names = "default", "sleep";
 990                         pinctrl-0 = <&i2c5_default>;
 991                         pinctrl-1 = <&i2c5_sleep>;
 992                         #address-cells = <1>;
 993                         #size-cells = <0>;
 994                         status = "disabled";
 995                 };
 996
 997                 blsp_i2c6: i2c@c1b6000 {
 998                         compatible = "qcom,i2c-qup-v2.2.1";
 999                         reg = <0x0c1b6000 0x600>;
1000                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1001
1002                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1003                                  <&gcc GCC_BLSP2_AHB_CLK>;
1004                         clock-names = "core", "iface";
1005                         clock-frequency = <400000>;
1006
1007                         pinctrl-names = "default", "sleep";
1008                         pinctrl-0 = <&i2c6_default>;
1009                         pinctrl-1 = <&i2c6_sleep>;
1010                         #address-cells = <1>;
1011                         #size-cells = <0>;
1012                         status = "disabled";
1013                 };
1014
1015                 blsp_i2c7: i2c@c1b7000 {
1016                         compatible = "qcom,i2c-qup-v2.2.1";
1017                         reg = <0x0c1b7000 0x600>;
1018                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1019
1020                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1021                                  <&gcc GCC_BLSP2_AHB_CLK>;
1022                         clock-names = "core", "iface";
1023                         clock-frequency = <400000>;
1024
1025                         pinctrl-names = "default", "sleep";
1026                         pinctrl-0 = <&i2c7_default>;
1027                         pinctrl-1 = <&i2c7_sleep>;
1028                         #address-cells = <1>;
1029                         #size-cells = <0>;
1030                         status = "disabled";
1031                 };
1032
1033                 blsp_i2c8: i2c@c1b8000 {
1034                         compatible = "qcom,i2c-qup-v2.2.1";
1035                         reg = <0x0c1b8000 0x600>;
1036                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1037
1038                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1039                                  <&gcc GCC_BLSP2_AHB_CLK>;
1040                         clock-names = "core", "iface";
1041                         clock-frequency = <400000>;
1042
1043                         pinctrl-names = "default", "sleep";
1044                         pinctrl-0 = <&i2c8_default>;
1045                         pinctrl-1 = <&i2c8_sleep>;
1046                         #address-cells = <1>;
1047                         #size-cells = <0>;
1048                         status = "disabled";
1049                 };
1050
1051                 mmss_smmu: iommu@cd00000 {
1052                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1053                         reg = <0x0cd00000 0x40000>;
1054                         #iommu-cells = <1>;
1055
1056                         #global-interrupts = <2>;
1057                         interrupts =
1058                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1059                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1060
1061                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1062                                 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1063                                 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1064                                 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1065                                 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1066                                 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1067                                 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1068                                 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1069                                 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1070                                 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1071                                 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1072                                 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1073                                 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1074                                 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1075                                 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1076                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1077                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1078                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
1079                                 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1080                                 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1081                                 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1082                                 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1083                                 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1084                                 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
1085
1086                         status = "disabled";
1087                 };
1088
1089                 apcs_glb: mailbox@17911000 {
1090                         compatible = "qcom,sdm660-apcs-hmss-global";
1091                         reg = <0x17911000 0x1000>;
1092
1093                         #mbox-cells = <1>;
1094                 };
1095
1096                 timer@17920000 {
1097                         #address-cells = <1>;
1098                         #size-cells = <1>;
1099                         ranges;
1100                         compatible = "arm,armv7-timer-mem";
1101                         reg = <0x17920000 0x1000>;
1102                         clock-frequency = <19200000>;
1103
1104                         frame@17921000 {
1105                                 frame-number = <0>;
1106                                 interrupts = <0 8 0x4>,
1107                                                 <0 7 0x4>;
1108                                 reg = <0x17921000 0x1000>,
1109                                         <0x17922000 0x1000>;
1110                         };
1111
1112                         frame@17923000 {
1113                                 frame-number = <1>;
1114                                 interrupts = <0 9 0x4>;
1115                                 reg = <0x17923000 0x1000>;
1116                                 status = "disabled";
1117                         };
1118
1119                         frame@17924000 {
1120                                 frame-number = <2>;
1121                                 interrupts = <0 10 0x4>;
1122                                 reg = <0x17924000 0x1000>;
1123                                 status = "disabled";
1124                         };
1125
1126                         frame@17925000 {
1127                                 frame-number = <3>;
1128                                 interrupts = <0 11 0x4>;
1129                                 reg = <0x17925000 0x1000>;
1130                                 status = "disabled";
1131                         };
1132
1133                         frame@17926000 {
1134                                 frame-number = <4>;
1135                                 interrupts = <0 12 0x4>;
1136                                 reg = <0x17926000 0x1000>;
1137                                 status = "disabled";
1138                         };
1139
1140                         frame@17927000 {
1141                                 frame-number = <5>;
1142                                 interrupts = <0 13 0x4>;
1143                                 reg = <0x17927000 0x1000>;
1144                                 status = "disabled";
1145                         };
1146
1147                         frame@17928000 {
1148                                 frame-number = <6>;
1149                                 interrupts = <0 14 0x4>;
1150                                 reg = <0x17928000 0x1000>;
1151                                 status = "disabled";
1152                         };
1153                 };
1154
1155                 intc: interrupt-controller@17a00000 {
1156                         compatible = "arm,gic-v3";
1157                         reg = <0x17a00000 0x10000>,        /* GICD */
1158                                   <0x17b00000 0x100000>;          /* GICR * 8 */
1159                         #interrupt-cells = <3>;
1160                         #address-cells = <1>;
1161                         #size-cells = <1>;
1162                         ranges;
1163                         interrupt-controller;
1164                         #redistributor-regions = <1>;
1165                         redistributor-stride = <0x0 0x20000>;
1166                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1167                 };
1168         };
1169
1170         tcsr_mutex: hwlock {
1171                 compatible = "qcom,tcsr-mutex";
1172                 syscon = <&tcsr_mutex_regs 0 0x1000>;
1173                 #hwlock-cells = <1>;
1174         };
1175
1176         timer {
1177                 compatible = "arm,armv8-timer";
1178                 interrupts = <GIC_PPI 1 0xf08>,
1179                                  <GIC_PPI 2 0xf08>,
1180                                  <GIC_PPI 3 0xf08>,
1181                                  <GIC_PPI 0 0xf08>;
1182         };
1183 };
1184