arch/arm64/boot/dts/qcom/sc8280xp.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  10 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/mailbox/qcom-ipcc.h>
  13 #include <dt-bindings/phy/phy-qcom-qmp.h>
  14 #include <dt-bindings/power/qcom-rpmpd.h>
  15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         clocks {
  25                 xo_board_clk: xo-board-clk {
  26                         compatible = "fixed-clock";
  27                         #clock-cells = <0>;
  28                 };
  29
  30                 sleep_clk: sleep-clk {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <32764>;
  34                 };
  35         };
  36
  37         cpu0_opp_table: cpu0-opp-table {
  38                 compatible = "operating-points-v2";
  39                 opp-shared;
  40
  41                 opp-300000000 {
  42                         opp-hz = /bits/ 64 <300000000>;
  43                         opp-peak-kBps = <(300000 * 32)>;
  44                 };
  45                 opp-403200000 {
  46                         opp-hz = /bits/ 64 <403200000>;
  47                         opp-peak-kBps = <(384000 * 32)>;
  48                 };
  49                 opp-499200000 {
  50                         opp-hz = /bits/ 64 <499200000>;
  51                         opp-peak-kBps = <(480000 * 32)>;
  52                 };
  53                 opp-595200000 {
  54                         opp-hz = /bits/ 64 <595200000>;
  55                         opp-peak-kBps = <(576000 * 32)>;
  56                 };
  57                 opp-691200000 {
  58                         opp-hz = /bits/ 64 <691200000>;
  59                         opp-peak-kBps = <(672000 * 32)>;
  60                 };
  61                 opp-806400000 {
  62                         opp-hz = /bits/ 64 <806400000>;
  63                         opp-peak-kBps = <(768000 * 32)>;
  64                 };
  65                 opp-902400000 {
  66                         opp-hz = /bits/ 64 <902400000>;
  67                         opp-peak-kBps = <(864000 * 32)>;
  68                 };
  69                 opp-1017600000 {
  70                         opp-hz = /bits/ 64 <1017600000>;
  71                         opp-peak-kBps = <(960000 * 32)>;
  72                 };
  73                 opp-1113600000 {
  74                         opp-hz = /bits/ 64 <1113600000>;
  75                         opp-peak-kBps = <(1075200 * 32)>;
  76                 };
  77                 opp-1209600000 {
  78                         opp-hz = /bits/ 64 <1209600000>;
  79                         opp-peak-kBps = <(1171200 * 32)>;
  80                 };
  81                 opp-1324800000 {
  82                         opp-hz = /bits/ 64 <1324800000>;
  83                         opp-peak-kBps = <(1267200 * 32)>;
  84                 };
  85                 opp-1440000000 {
  86                         opp-hz = /bits/ 64 <1440000000>;
  87                         opp-peak-kBps = <(1363200 * 32)>;
  88                 };
  89                 opp-1555200000 {
  90                         opp-hz = /bits/ 64 <1555200000>;
  91                         opp-peak-kBps = <(1536000 * 32)>;
  92                 };
  93                 opp-1670400000 {
  94                         opp-hz = /bits/ 64 <1670400000>;
  95                         opp-peak-kBps = <(1612800 * 32)>;
  96                 };
  97                 opp-1785600000 {
  98                         opp-hz = /bits/ 64 <1785600000>;
  99                         opp-peak-kBps = <(1689600 * 32)>;
 100                 };
 101                 opp-1881600000 {
 102                         opp-hz = /bits/ 64 <1881600000>;
 103                         opp-peak-kBps = <(1689600 * 32)>;
 104                 };
 105                 opp-1996800000 {
 106                         opp-hz = /bits/ 64 <1996800000>;
 107                         opp-peak-kBps = <(1689600 * 32)>;
 108                 };
 109                 opp-2112000000 {
 110                         opp-hz = /bits/ 64 <2112000000>;
 111                         opp-peak-kBps = <(1689600 * 32)>;
 112                 };
 113                 opp-2227200000 {
 114                         opp-hz = /bits/ 64 <2227200000>;
 115                         opp-peak-kBps = <(1689600 * 32)>;
 116                 };
 117                 opp-2342400000 {
 118                         opp-hz = /bits/ 64 <2342400000>;
 119                         opp-peak-kBps = <(1689600 * 32)>;
 120                 };
 121                 opp-2438400000 {
 122                         opp-hz = /bits/ 64 <2438400000>;
 123                         opp-peak-kBps = <(1689600 * 32)>;
 124                 };
 125         };
 126
 127         cpu4_opp_table: cpu4-opp-table {
 128                 compatible = "operating-points-v2";
 129                 opp-shared;
 130
 131                 opp-825600000 {
 132                         opp-hz = /bits/ 64 <825600000>;
 133                         opp-peak-kBps = <(768000 * 32)>;
 134                 };
 135                 opp-940800000 {
 136                         opp-hz = /bits/ 64 <940800000>;
 137                         opp-peak-kBps = <(864000 * 32)>;
 138                 };
 139                 opp-1056000000 {
 140                         opp-hz = /bits/ 64 <1056000000>;
 141                         opp-peak-kBps = <(960000 * 32)>;
 142                 };
 143                 opp-1171200000 {
 144                         opp-hz = /bits/ 64 <1171200000>;
 145                         opp-peak-kBps = <(1171200 * 32)>;
 146                 };
 147                 opp-1286400000 {
 148                         opp-hz = /bits/ 64 <1286400000>;
 149                         opp-peak-kBps = <(1267200 * 32)>;
 150                 };
 151                 opp-1401600000 {
 152                         opp-hz = /bits/ 64 <1401600000>;
 153                         opp-peak-kBps = <(1363200 * 32)>;
 154                 };
 155                 opp-1516800000 {
 156                         opp-hz = /bits/ 64 <1516800000>;
 157                         opp-peak-kBps = <(1459200 * 32)>;
 158                 };
 159                 opp-1632000000 {
 160                         opp-hz = /bits/ 64 <1632000000>;
 161                         opp-peak-kBps = <(1612800 * 32)>;
 162                 };
 163                 opp-1747200000 {
 164                         opp-hz = /bits/ 64 <1747200000>;
 165                         opp-peak-kBps = <(1689600 * 32)>;
 166                 };
 167                 opp-1862400000 {
 168                         opp-hz = /bits/ 64 <1862400000>;
 169                         opp-peak-kBps = <(1689600 * 32)>;
 170                 };
 171                 opp-1977600000 {
 172                         opp-hz = /bits/ 64 <1977600000>;
 173                         opp-peak-kBps = <(1689600 * 32)>;
 174                 };
 175                 opp-2073600000 {
 176                         opp-hz = /bits/ 64 <2073600000>;
 177                         opp-peak-kBps = <(1689600 * 32)>;
 178                 };
 179                 opp-2169600000 {
 180                         opp-hz = /bits/ 64 <2169600000>;
 181                         opp-peak-kBps = <(1689600 * 32)>;
 182                 };
 183                 opp-2284800000 {
 184                         opp-hz = /bits/ 64 <2284800000>;
 185                         opp-peak-kBps = <(1689600 * 32)>;
 186                 };
 187                 opp-2400000000 {
 188                         opp-hz = /bits/ 64 <2400000000>;
 189                         opp-peak-kBps = <(1689600 * 32)>;
 190                 };
 191                 opp-2496000000 {
 192                         opp-hz = /bits/ 64 <2496000000>;
 193                         opp-peak-kBps = <(1689600 * 32)>;
 194                 };
 195                 opp-2592000000 {
 196                         opp-hz = /bits/ 64 <2592000000>;
 197                         opp-peak-kBps = <(1689600 * 32)>;
 198                 };
 199                 opp-2688000000 {
 200                         opp-hz = /bits/ 64 <2688000000>;
 201                         opp-peak-kBps = <(1689600 * 32)>;
 202                 };
 203                 opp-2803200000 {
 204                         opp-hz = /bits/ 64 <2803200000>;
 205                         opp-peak-kBps = <(1689600 * 32)>;
 206                 };
 207                 opp-2899200000 {
 208                         opp-hz = /bits/ 64 <2899200000>;
 209                         opp-peak-kBps = <(1689600 * 32)>;
 210                 };
 211                 opp-2995200000 {
 212                         opp-hz = /bits/ 64 <2995200000>;
 213                         opp-peak-kBps = <(1689600 * 32)>;
 214                 };
 215         };
 216
 217         cpus {
 218                 #address-cells = <2>;
 219                 #size-cells = <0>;
 220
 221                 CPU0: cpu@0 {
 222                         device_type = "cpu";
 223                         compatible = "qcom,kryo";
 224                         reg = <0x0 0x0>;
 225                         enable-method = "psci";
 226                         capacity-dmips-mhz = <602>;
 227                         next-level-cache = <&L2_0>;
 228                         power-domains = <&CPU_PD0>;
 229                         power-domain-names = "psci";
 230                         qcom,freq-domain = <&cpufreq_hw 0>;
 231                         operating-points-v2 = <&cpu0_opp_table>;
 232                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 233                         #cooling-cells = <2>;
 234                         L2_0: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                                 L3_0: l3-cache {
 238                                       compatible = "cache";
 239                                 };
 240                         };
 241                 };
 242
 243                 CPU1: cpu@100 {
 244                         device_type = "cpu";
 245                         compatible = "qcom,kryo";
 246                         reg = <0x0 0x100>;
 247                         enable-method = "psci";
 248                         capacity-dmips-mhz = <602>;
 249                         next-level-cache = <&L2_100>;
 250                         power-domains = <&CPU_PD1>;
 251                         power-domain-names = "psci";
 252                         qcom,freq-domain = <&cpufreq_hw 0>;
 253                         operating-points-v2 = <&cpu0_opp_table>;
 254                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 255                         #cooling-cells = <2>;
 256                         L2_100: l2-cache {
 257                                 compatible = "cache";
 258                                 next-level-cache = <&L3_0>;
 259                         };
 260                 };
 261
 262                 CPU2: cpu@200 {
 263                         device_type = "cpu";
 264                         compatible = "qcom,kryo";
 265                         reg = <0x0 0x200>;
 266                         enable-method = "psci";
 267                         capacity-dmips-mhz = <602>;
 268                         next-level-cache = <&L2_200>;
 269                         power-domains = <&CPU_PD2>;
 270                         power-domain-names = "psci";
 271                         qcom,freq-domain = <&cpufreq_hw 0>;
 272                         operating-points-v2 = <&cpu0_opp_table>;
 273                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 274                         #cooling-cells = <2>;
 275                         L2_200: l2-cache {
 276                                 compatible = "cache";
 277                                 next-level-cache = <&L3_0>;
 278                         };
 279                 };
 280
 281                 CPU3: cpu@300 {
 282                         device_type = "cpu";
 283                         compatible = "qcom,kryo";
 284                         reg = <0x0 0x300>;
 285                         enable-method = "psci";
 286                         capacity-dmips-mhz = <602>;
 287                         next-level-cache = <&L2_300>;
 288                         power-domains = <&CPU_PD3>;
 289                         power-domain-names = "psci";
 290                         qcom,freq-domain = <&cpufreq_hw 0>;
 291                         operating-points-v2 = <&cpu0_opp_table>;
 292                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 293                         #cooling-cells = <2>;
 294                         L2_300: l2-cache {
 295                                 compatible = "cache";
 296                                 next-level-cache = <&L3_0>;
 297                         };
 298                 };
 299
 300                 CPU4: cpu@400 {
 301                         device_type = "cpu";
 302                         compatible = "qcom,kryo";
 303                         reg = <0x0 0x400>;
 304                         enable-method = "psci";
 305                         capacity-dmips-mhz = <1024>;
 306                         next-level-cache = <&L2_400>;
 307                         power-domains = <&CPU_PD4>;
 308                         power-domain-names = "psci";
 309                         qcom,freq-domain = <&cpufreq_hw 1>;
 310                         operating-points-v2 = <&cpu4_opp_table>;
 311                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 312                         #cooling-cells = <2>;
 313                         L2_400: l2-cache {
 314                                 compatible = "cache";
 315                                 next-level-cache = <&L3_0>;
 316                         };
 317                 };
 318
 319                 CPU5: cpu@500 {
 320                         device_type = "cpu";
 321                         compatible = "qcom,kryo";
 322                         reg = <0x0 0x500>;
 323                         enable-method = "psci";
 324                         capacity-dmips-mhz = <1024>;
 325                         next-level-cache = <&L2_500>;
 326                         power-domains = <&CPU_PD5>;
 327                         power-domain-names = "psci";
 328                         qcom,freq-domain = <&cpufreq_hw 1>;
 329                         operating-points-v2 = <&cpu4_opp_table>;
 330                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 331                         #cooling-cells = <2>;
 332                         L2_500: l2-cache {
 333                                 compatible = "cache";
 334                                 next-level-cache = <&L3_0>;
 335                         };
 336                 };
 337
 338                 CPU6: cpu@600 {
 339                         device_type = "cpu";
 340                         compatible = "qcom,kryo";
 341                         reg = <0x0 0x600>;
 342                         enable-method = "psci";
 343                         capacity-dmips-mhz = <1024>;
 344                         next-level-cache = <&L2_600>;
 345                         power-domains = <&CPU_PD6>;
 346                         power-domain-names = "psci";
 347                         qcom,freq-domain = <&cpufreq_hw 1>;
 348                         operating-points-v2 = <&cpu4_opp_table>;
 349                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 350                         #cooling-cells = <2>;
 351                         L2_600: l2-cache {
 352                                 compatible = "cache";
 353                                 next-level-cache = <&L3_0>;
 354                         };
 355                 };
 356
 357                 CPU7: cpu@700 {
 358                         device_type = "cpu";
 359                         compatible = "qcom,kryo";
 360                         reg = <0x0 0x700>;
 361                         enable-method = "psci";
 362                         capacity-dmips-mhz = <1024>;
 363                         next-level-cache = <&L2_700>;
 364                         power-domains = <&CPU_PD7>;
 365                         power-domain-names = "psci";
 366                         qcom,freq-domain = <&cpufreq_hw 1>;
 367                         operating-points-v2 = <&cpu4_opp_table>;
 368                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 369                         #cooling-cells = <2>;
 370                         L2_700: l2-cache {
 371                                 compatible = "cache";
 372                                 next-level-cache = <&L3_0>;
 373                         };
 374                 };
 375
 376                 cpu-map {
 377                         cluster0 {
 378                                 core0 {
 379                                         cpu = <&CPU0>;
 380                                 };
 381
 382                                 core1 {
 383                                         cpu = <&CPU1>;
 384                                 };
 385
 386                                 core2 {
 387                                         cpu = <&CPU2>;
 388                                 };
 389
 390                                 core3 {
 391                                         cpu = <&CPU3>;
 392                                 };
 393
 394                                 core4 {
 395                                         cpu = <&CPU4>;
 396                                 };
 397
 398                                 core5 {
 399                                         cpu = <&CPU5>;
 400                                 };
 401
 402                                 core6 {
 403                                         cpu = <&CPU6>;
 404                                 };
 405
 406                                 core7 {
 407                                         cpu = <&CPU7>;
 408                                 };
 409                         };
 410                 };
 411
 412                 idle-states {
 413                         entry-method = "psci";
 414
 415                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 416                                 compatible = "arm,idle-state";
 417                                 idle-state-name = "little-rail-power-collapse";
 418                                 arm,psci-suspend-param = <0x40000004>;
 419                                 entry-latency-us = <355>;
 420                                 exit-latency-us = <909>;
 421                                 min-residency-us = <3934>;
 422                                 local-timer-stop;
 423                         };
 424
 425                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 426                                 compatible = "arm,idle-state";
 427                                 idle-state-name = "big-rail-power-collapse";
 428                                 arm,psci-suspend-param = <0x40000004>;
 429                                 entry-latency-us = <241>;
 430                                 exit-latency-us = <1461>;
 431                                 min-residency-us = <4488>;
 432                                 local-timer-stop;
 433                         };
 434                 };
 435
 436                 domain-idle-states {
 437                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 438                                 compatible = "domain-idle-state";
 439                                 idle-state-name = "cluster-power-collapse";
 440                                 arm,psci-suspend-param = <0x4100c344>;
 441                                 entry-latency-us = <3263>;
 442                                 exit-latency-us = <6562>;
 443                                 min-residency-us = <9987>;
 444                         };
 445                 };
 446         };
 447
 448         firmware {
 449                 scm: scm {
 450                         compatible = "qcom,scm-sc8280xp", "qcom,scm";
 451                 };
 452         };
 453
 454         aggre1_noc: interconnect-aggre1-noc {
 455                 compatible = "qcom,sc8280xp-aggre1-noc";
 456                 #interconnect-cells = <2>;
 457                 qcom,bcm-voters = <&apps_bcm_voter>;
 458         };
 459
 460         aggre2_noc: interconnect-aggre2-noc {
 461                 compatible = "qcom,sc8280xp-aggre2-noc";
 462                 #interconnect-cells = <2>;
 463                 qcom,bcm-voters = <&apps_bcm_voter>;
 464         };
 465
 466         clk_virt: interconnect-clk-virt {
 467                 compatible = "qcom,sc8280xp-clk-virt";
 468                 #interconnect-cells = <2>;
 469                 qcom,bcm-voters = <&apps_bcm_voter>;
 470         };
 471
 472         config_noc: interconnect-config-noc {
 473                 compatible = "qcom,sc8280xp-config-noc";
 474                 #interconnect-cells = <2>;
 475                 qcom,bcm-voters = <&apps_bcm_voter>;
 476         };
 477
 478         dc_noc: interconnect-dc-noc {
 479                 compatible = "qcom,sc8280xp-dc-noc";
 480                 #interconnect-cells = <2>;
 481                 qcom,bcm-voters = <&apps_bcm_voter>;
 482         };
 483
 484         gem_noc: interconnect-gem-noc {
 485                 compatible = "qcom,sc8280xp-gem-noc";
 486                 #interconnect-cells = <2>;
 487                 qcom,bcm-voters = <&apps_bcm_voter>;
 488         };
 489
 490         lpass_noc: interconnect-lpass-ag-noc {
 491                 compatible = "qcom,sc8280xp-lpass-ag-noc";
 492                 #interconnect-cells = <2>;
 493                 qcom,bcm-voters = <&apps_bcm_voter>;
 494         };
 495
 496         mc_virt: interconnect-mc-virt {
 497                 compatible = "qcom,sc8280xp-mc-virt";
 498                 #interconnect-cells = <2>;
 499                 qcom,bcm-voters = <&apps_bcm_voter>;
 500         };
 501
 502         mmss_noc: interconnect-mmss-noc {
 503                 compatible = "qcom,sc8280xp-mmss-noc";
 504                 #interconnect-cells = <2>;
 505                 qcom,bcm-voters = <&apps_bcm_voter>;
 506         };
 507
 508         nspa_noc: interconnect-nspa-noc {
 509                 compatible = "qcom,sc8280xp-nspa-noc";
 510                 #interconnect-cells = <2>;
 511                 qcom,bcm-voters = <&apps_bcm_voter>;
 512         };
 513
 514         nspb_noc: interconnect-nspb-noc {
 515                 compatible = "qcom,sc8280xp-nspb-noc";
 516                 #interconnect-cells = <2>;
 517                 qcom,bcm-voters = <&apps_bcm_voter>;
 518         };
 519
 520         system_noc: interconnect-system-noc {
 521                 compatible = "qcom,sc8280xp-system-noc";
 522                 #interconnect-cells = <2>;
 523                 qcom,bcm-voters = <&apps_bcm_voter>;
 524         };
 525
 526         memory@80000000 {
 527                 device_type = "memory";
 528                 /* We expect the bootloader to fill in the size */
 529                 reg = <0x0 0x80000000 0x0 0x0>;
 530         };
 531
 532         pmu {
 533                 compatible = "arm,armv8-pmuv3";
 534                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 535         };
 536
 537         psci {
 538                 compatible = "arm,psci-1.0";
 539                 method = "smc";
 540
 541                 CPU_PD0: cpu0 {
 542                         #power-domain-cells = <0>;
 543                         power-domains = <&CLUSTER_PD>;
 544                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 545                 };
 546
 547                 CPU_PD1: cpu1 {
 548                         #power-domain-cells = <0>;
 549                         power-domains = <&CLUSTER_PD>;
 550                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 551                 };
 552
 553                 CPU_PD2: cpu2 {
 554                         #power-domain-cells = <0>;
 555                         power-domains = <&CLUSTER_PD>;
 556                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 557                 };
 558
 559                 CPU_PD3: cpu3 {
 560                         #power-domain-cells = <0>;
 561                         power-domains = <&CLUSTER_PD>;
 562                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 563                 };
 564
 565                 CPU_PD4: cpu4 {
 566                         #power-domain-cells = <0>;
 567                         power-domains = <&CLUSTER_PD>;
 568                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 569                 };
 570
 571                 CPU_PD5: cpu5 {
 572                         #power-domain-cells = <0>;
 573                         power-domains = <&CLUSTER_PD>;
 574                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 575                 };
 576
 577                 CPU_PD6: cpu6 {
 578                         #power-domain-cells = <0>;
 579                         power-domains = <&CLUSTER_PD>;
 580                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 581                 };
 582
 583                 CPU_PD7: cpu7 {
 584                         #power-domain-cells = <0>;
 585                         power-domains = <&CLUSTER_PD>;
 586                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 587                 };
 588
 589                 CLUSTER_PD: cpu-cluster0 {
 590                         #power-domain-cells = <0>;
 591                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 592                 };
 593         };
 594
 595         qup_opp_table_100mhz: qup-100mhz-opp-table {
 596                 compatible = "operating-points-v2";
 597
 598                 opp-75000000 {
 599                         opp-hz = /bits/ 64 <75000000>;
 600                         required-opps = <&rpmhpd_opp_low_svs>;
 601                 };
 602
 603                 opp-100000000 {
 604                         opp-hz = /bits/ 64 <100000000>;
 605                         required-opps = <&rpmhpd_opp_svs>;
 606                 };
 607         };
 608
 609         reserved-memory {
 610                 #address-cells = <2>;
 611                 #size-cells = <2>;
 612                 ranges;
 613
 614                 reserved-region@80000000 {
 615                         reg = <0 0x80000000 0 0x860000>;
 616                         no-map;
 617                 };
 618
 619                 cmd_db: cmd-db-region@80860000 {
 620                         compatible = "qcom,cmd-db";
 621                         reg = <0 0x80860000 0 0x20000>;
 622                         no-map;
 623                 };
 624
 625                 reserved-region@80880000 {
 626                         reg = <0 0x80880000 0 0x80000>;
 627                         no-map;
 628                 };
 629
 630                 smem_mem: smem-region@80900000 {
 631                         compatible = "qcom,smem";
 632                         reg = <0 0x80900000 0 0x200000>;
 633                         no-map;
 634                         hwlocks = <&tcsr_mutex 3>;
 635                 };
 636
 637                 reserved-region@80b00000 {
 638                         reg = <0 0x80b00000 0 0x100000>;
 639                         no-map;
 640                 };
 641
 642                 reserved-region@83b00000 {
 643                         reg = <0 0x83b00000 0 0x1700000>;
 644                         no-map;
 645                 };
 646
 647                 reserved-region@85b00000 {
 648                         reg = <0 0x85b00000 0 0xc00000>;
 649                         no-map;
 650                 };
 651
 652                 pil_adsp_mem: adsp-region@86c00000 {
 653                         reg = <0 0x86c00000 0 0x2000000>;
 654                         no-map;
 655                 };
 656
 657                 pil_nsp0_mem: cdsp0-region@8a100000 {
 658                         reg = <0 0x8a100000 0 0x1e00000>;
 659                         no-map;
 660                 };
 661
 662                 pil_nsp1_mem: cdsp1-region@8c600000 {
 663                         reg = <0 0x8c600000 0 0x1e00000>;
 664                         no-map;
 665                 };
 666
 667                 reserved-region@aeb00000 {
 668                         reg = <0 0xaeb00000 0 0x16600000>;
 669                         no-map;
 670                 };
 671         };
 672
 673         smp2p-adsp {
 674                 compatible = "qcom,smp2p";
 675                 qcom,smem = <443>, <429>;
 676                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 677                                              IPCC_MPROC_SIGNAL_SMP2P
 678                                              IRQ_TYPE_EDGE_RISING>;
 679                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 680                                 IPCC_MPROC_SIGNAL_SMP2P>;
 681
 682                 qcom,local-pid = <0>;
 683                 qcom,remote-pid = <2>;
 684
 685                 smp2p_adsp_out: master-kernel {
 686                         qcom,entry-name = "master-kernel";
 687                         #qcom,smem-state-cells = <1>;
 688                 };
 689
 690                 smp2p_adsp_in: slave-kernel {
 691                         qcom,entry-name = "slave-kernel";
 692                         interrupt-controller;
 693                         #interrupt-cells = <2>;
 694                 };
 695         };
 696
 697         smp2p-nsp0 {
 698                 compatible = "qcom,smp2p";
 699                 qcom,smem = <94>, <432>;
 700                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 701                                              IPCC_MPROC_SIGNAL_SMP2P
 702                                              IRQ_TYPE_EDGE_RISING>;
 703                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 704                                 IPCC_MPROC_SIGNAL_SMP2P>;
 705
 706                 qcom,local-pid = <0>;
 707                 qcom,remote-pid = <5>;
 708
 709                 smp2p_nsp0_out: master-kernel {
 710                         qcom,entry-name = "master-kernel";
 711                         #qcom,smem-state-cells = <1>;
 712                 };
 713
 714                 smp2p_nsp0_in: slave-kernel {
 715                         qcom,entry-name = "slave-kernel";
 716                         interrupt-controller;
 717                         #interrupt-cells = <2>;
 718                 };
 719         };
 720
 721         smp2p-nsp1 {
 722                 compatible = "qcom,smp2p";
 723                 qcom,smem = <617>, <616>;
 724                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
 725                                              IPCC_MPROC_SIGNAL_SMP2P
 726                                              IRQ_TYPE_EDGE_RISING>;
 727                 mboxes = <&ipcc IPCC_CLIENT_NSP1
 728                                 IPCC_MPROC_SIGNAL_SMP2P>;
 729
 730                 qcom,local-pid = <0>;
 731                 qcom,remote-pid = <12>;
 732
 733                 smp2p_nsp1_out: master-kernel {
 734                         qcom,entry-name = "master-kernel";
 735                         #qcom,smem-state-cells = <1>;
 736                 };
 737
 738                 smp2p_nsp1_in: slave-kernel {
 739                         qcom,entry-name = "slave-kernel";
 740                         interrupt-controller;
 741                         #interrupt-cells = <2>;
 742                 };
 743         };
 744
 745         soc: soc@0 {
 746                 compatible = "simple-bus";
 747                 #address-cells = <2>;
 748                 #size-cells = <2>;
 749                 ranges = <0 0 0 0 0x10 0>;
 750                 dma-ranges = <0 0 0 0 0x10 0>;
 751
 752                 gcc: clock-controller@100000 {
 753                         compatible = "qcom,gcc-sc8280xp";
 754                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 755                         #clock-cells = <1>;
 756                         #reset-cells = <1>;
 757                         #power-domain-cells = <1>;
 758                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 759                                  <&sleep_clk>,
 760                                  <0>,
 761                                  <0>,
 762                                  <0>,
 763                                  <0>,
 764                                  <0>,
 765                                  <0>,
 766                                  <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 767                                  <0>,
 768                                  <0>,
 769                                  <0>,
 770                                  <0>,
 771                                  <0>,
 772                                  <0>,
 773                                  <0>,
 774                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 775                                  <0>,
 776                                  <0>,
 777                                  <0>,
 778                                  <0>,
 779                                  <0>,
 780                                  <0>,
 781                                  <0>,
 782                                  <0>,
 783                                  <0>,
 784                                  <&pcie2a_phy>,
 785                                  <&pcie2b_phy>,
 786                                  <&pcie3a_phy>,
 787                                  <&pcie3b_phy>,
 788                                  <&pcie4_phy>,
 789                                  <0>,
 790                                  <0>;
 791                         power-domains = <&rpmhpd SC8280XP_CX>;
 792                 };
 793
 794                 ipcc: mailbox@408000 {
 795                         compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
 796                         reg = <0 0x00408000 0 0x1000>;
 797                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 798                         interrupt-controller;
 799                         #interrupt-cells = <3>;
 800                         #mbox-cells = <2>;
 801                 };
 802
 803                 qup2: geniqup@8c0000 {
 804                         compatible = "qcom,geni-se-qup";
 805                         reg = <0 0x008c0000 0 0x2000>;
 806                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 807                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 808                         clock-names = "m-ahb", "s-ahb";
 809                         iommus = <&apps_smmu 0xa3 0>;
 810
 811                         #address-cells = <2>;
 812                         #size-cells = <2>;
 813                         ranges;
 814
 815                         status = "disabled";
 816
 817                         qup2_uart17: serial@884000 {
 818                                 compatible = "qcom,geni-uart";
 819                                 reg = <0 0x00884000 0 0x4000>;
 820                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 821                                 clock-names = "se";
 822                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 823                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 824                                 power-domains = <&rpmhpd SC8280XP_CX>;
 825                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 826                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
 827                                 interconnect-names = "qup-core", "qup-config";
 828                                 status = "disabled";
 829                         };
 830
 831                         qup2_i2c5: i2c@894000 {
 832                                 compatible = "qcom,geni-i2c";
 833                                 reg = <0 0x00894000 0 0x4000>;
 834                                 clock-names = "se";
 835                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 836                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 837                                 #address-cells = <1>;
 838                                 #size-cells = <0>;
 839                                 power-domains = <&rpmhpd SC8280XP_CX>;
 840                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 841                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 842                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 843                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 844                                 status = "disabled";
 845                         };
 846                 };
 847
 848                 qup0: geniqup@9c0000 {
 849                         compatible = "qcom,geni-se-qup";
 850                         reg = <0 0x009c0000 0 0x6000>;
 851                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 852                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 853                         clock-names = "m-ahb", "s-ahb";
 854                         iommus = <&apps_smmu 0x563 0>;
 855
 856                         #address-cells = <2>;
 857                         #size-cells = <2>;
 858                         ranges;
 859
 860                         status = "disabled";
 861
 862                         qup0_i2c4: i2c@990000 {
 863                                 compatible = "qcom,geni-i2c";
 864                                 reg = <0 0x00990000 0 0x4000>;
 865                                 clock-names = "se";
 866                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 867                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 868                                 #address-cells = <1>;
 869                                 #size-cells = <0>;
 870                                 power-domains = <&rpmhpd SC8280XP_CX>;
 871                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 872                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 873                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 874                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 875                                 status = "disabled";
 876                         };
 877                 };
 878
 879                 qup1: geniqup@ac0000 {
 880                         compatible = "qcom,geni-se-qup";
 881                         reg = <0 0x00ac0000 0 0x6000>;
 882                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 883                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 884                         clock-names = "m-ahb", "s-ahb";
 885                         iommus = <&apps_smmu 0x83 0>;
 886
 887                         #address-cells = <2>;
 888                         #size-cells = <2>;
 889                         ranges;
 890
 891                         status = "disabled";
 892                 };
 893
 894                 pcie4: pcie@1c00000 {
 895                         device_type = "pci";
 896                         compatible = "qcom,pcie-sc8280xp";
 897                         reg = <0x0 0x01c00000 0x0 0x3000>,
 898                               <0x0 0x30000000 0x0 0xf1d>,
 899                               <0x0 0x30000f20 0x0 0xa8>,
 900                               <0x0 0x30001000 0x0 0x1000>,
 901                               <0x0 0x30100000 0x0 0x100000>;
 902                         reg-names = "parf", "dbi", "elbi", "atu", "config";
 903                         #address-cells = <3>;
 904                         #size-cells = <2>;
 905                         ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
 906                                  <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
 907                         bus-range = <0x00 0xff>;
 908
 909                         dma-coherent;
 910
 911                         linux,pci-domain = <6>;
 912                         num-lanes = <1>;
 913
 914                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 918                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
 919
 920                         #interrupt-cells = <1>;
 921                         interrupt-map-mask = <0 0 0 0x7>;
 922                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 923                                         <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 924                                         <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 925                                         <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 926
 927                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
 928                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
 929                                  <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
 930                                  <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
 931                                  <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
 932                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
 933                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
 934                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
 935                                  <&gcc GCC_CNOC_PCIE4_QX_CLK>;
 936                         clock-names = "aux",
 937                                       "cfg",
 938                                       "bus_master",
 939                                       "bus_slave",
 940                                       "slave_q2a",
 941                                       "ddrss_sf_tbu",
 942                                       "noc_aggr_4",
 943                                       "noc_aggr_south_sf",
 944                                       "cnoc_qx";
 945
 946                         assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
 947                         assigned-clock-rates = <19200000>;
 948
 949                         interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
 950                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
 951                         interconnect-names = "pcie-mem", "cpu-pcie";
 952
 953                         resets = <&gcc GCC_PCIE_4_BCR>;
 954                         reset-names = "pci";
 955
 956                         power-domains = <&gcc PCIE_4_GDSC>;
 957
 958                         phys = <&pcie4_phy>;
 959                         phy-names = "pciephy";
 960
 961                         status = "disabled";
 962                 };
 963
 964                 pcie4_phy: phy@1c06000 {
 965                         compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
 966                         reg = <0x0 0x01c06000 0x0 0x2000>;
 967
 968                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
 969                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
 970                                  <&gcc GCC_PCIE_4_CLKREF_CLK>,
 971                                  <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
 972                                  <&gcc GCC_PCIE_4_PIPE_CLK>,
 973                                  <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
 974                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
 975                                       "pipe", "pipediv2";
 976
 977                         assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
 978                         assigned-clock-rates = <100000000>;
 979
 980                         power-domains = <&gcc PCIE_4_GDSC>;
 981
 982                         resets = <&gcc GCC_PCIE_4_PHY_BCR>;
 983                         reset-names = "phy";
 984
 985                         #clock-cells = <0>;
 986                         clock-output-names = "pcie_4_pipe_clk";
 987
 988                         #phy-cells = <0>;
 989
 990                         status = "disabled";
 991                 };
 992
 993                 pcie3b: pcie@1c08000 {
 994                         device_type = "pci";
 995                         compatible = "qcom,pcie-sc8280xp";
 996                         reg = <0x0 0x01c08000 0x0 0x3000>,
 997                               <0x0 0x32000000 0x0 0xf1d>,
 998                               <0x0 0x32000f20 0x0 0xa8>,
 999                               <0x0 0x32001000 0x0 0x1000>,
1000                               <0x0 0x32100000 0x0 0x100000>;
1001                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1002                         #address-cells = <3>;
1003                         #size-cells = <2>;
1004                         ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
1005                                  <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1006                         bus-range = <0x00 0xff>;
1007
1008                         dma-coherent;
1009
1010                         linux,pci-domain = <5>;
1011                         num-lanes = <2>;
1012
1013                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1014                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1015                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1016                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1017                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1018
1019                         #interrupt-cells = <1>;
1020                         interrupt-map-mask = <0 0 0 0x7>;
1021                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1022                                         <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1023                                         <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1024                                         <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1025
1026                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1027                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1028                                  <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1029                                  <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1030                                  <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1031                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1032                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1033                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1034                         clock-names = "aux",
1035                                       "cfg",
1036                                       "bus_master",
1037                                       "bus_slave",
1038                                       "slave_q2a",
1039                                       "ddrss_sf_tbu",
1040                                       "noc_aggr_4",
1041                                       "noc_aggr_south_sf";
1042
1043                         assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1044                         assigned-clock-rates = <19200000>;
1045
1046                         interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1047                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1048                         interconnect-names = "pcie-mem", "cpu-pcie";
1049
1050                         resets = <&gcc GCC_PCIE_3B_BCR>;
1051                         reset-names = "pci";
1052
1053                         power-domains = <&gcc PCIE_3B_GDSC>;
1054
1055                         phys = <&pcie3b_phy>;
1056                         phy-names = "pciephy";
1057
1058                         status = "disabled";
1059                 };
1060
1061                 pcie3b_phy: phy@1c0e000 {
1062                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1063                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1064
1065                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1066                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1067                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1068                                  <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1069                                  <&gcc GCC_PCIE_3B_PIPE_CLK>,
1070                                  <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1071                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1072                                       "pipe", "pipediv2";
1073
1074                         assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1075                         assigned-clock-rates = <100000000>;
1076
1077                         power-domains = <&gcc PCIE_3B_GDSC>;
1078
1079                         resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1080                         reset-names = "phy";
1081
1082                         #clock-cells = <0>;
1083                         clock-output-names = "pcie_3b_pipe_clk";
1084
1085                         #phy-cells = <0>;
1086
1087                         status = "disabled";
1088                 };
1089
1090                 pcie3a: pcie@1c10000 {
1091                         device_type = "pci";
1092                         compatible = "qcom,pcie-sc8280xp";
1093                         reg = <0x0 0x01c10000 0x0 0x3000>,
1094                               <0x0 0x34000000 0x0 0xf1d>,
1095                               <0x0 0x34000f20 0x0 0xa8>,
1096                               <0x0 0x34001000 0x0 0x1000>,
1097                               <0x0 0x34100000 0x0 0x100000>;
1098                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1099                         #address-cells = <3>;
1100                         #size-cells = <2>;
1101                         ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
1102                                  <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1103                         bus-range = <0x00 0xff>;
1104
1105                         dma-coherent;
1106
1107                         linux,pci-domain = <4>;
1108                         num-lanes = <4>;
1109
1110                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1111                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1112                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1113                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1114                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1115
1116                         #interrupt-cells = <1>;
1117                         interrupt-map-mask = <0 0 0 0x7>;
1118                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1119                                         <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1120                                         <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1121                                         <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1122
1123                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1124                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1125                                  <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1126                                  <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1127                                  <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1128                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1129                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1130                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1131                         clock-names = "aux",
1132                                       "cfg",
1133                                       "bus_master",
1134                                       "bus_slave",
1135                                       "slave_q2a",
1136                                       "ddrss_sf_tbu",
1137                                       "noc_aggr_4",
1138                                       "noc_aggr_south_sf";
1139
1140                         assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1141                         assigned-clock-rates = <19200000>;
1142
1143                         interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1144                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1145                         interconnect-names = "pcie-mem", "cpu-pcie";
1146
1147                         resets = <&gcc GCC_PCIE_3A_BCR>;
1148                         reset-names = "pci";
1149
1150                         power-domains = <&gcc PCIE_3A_GDSC>;
1151
1152                         phys = <&pcie3a_phy>;
1153                         phy-names = "pciephy";
1154
1155                         status = "disabled";
1156                 };
1157
1158                 pcie3a_phy: phy@1c14000 {
1159                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1160                         reg = <0x0 0x01c14000 0x0 0x2000>,
1161                               <0x0 0x01c16000 0x0 0x2000>;
1162
1163                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1164                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1165                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1166                                  <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1167                                  <&gcc GCC_PCIE_3A_PIPE_CLK>,
1168                                  <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1169                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1170                                       "pipe", "pipediv2";
1171
1172                         assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1173                         assigned-clock-rates = <100000000>;
1174
1175                         power-domains = <&gcc PCIE_3A_GDSC>;
1176
1177                         resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
1178                         reset-names = "phy";
1179
1180                         qcom,4ln-config-sel = <&tcsr 0xa044 1>;
1181
1182                         #clock-cells = <0>;
1183                         clock-output-names = "pcie_3a_pipe_clk";
1184
1185                         #phy-cells = <0>;
1186
1187                         status = "disabled";
1188                 };
1189
1190                 pcie2b: pcie@1c18000 {
1191                         device_type = "pci";
1192                         compatible = "qcom,pcie-sc8280xp";
1193                         reg = <0x0 0x01c18000 0x0 0x3000>,
1194                               <0x0 0x38000000 0x0 0xf1d>,
1195                               <0x0 0x38000f20 0x0 0xa8>,
1196                               <0x0 0x38001000 0x0 0x1000>,
1197                               <0x0 0x38100000 0x0 0x100000>;
1198                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1199                         #address-cells = <3>;
1200                         #size-cells = <2>;
1201                         ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
1202                                  <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
1203                         bus-range = <0x00 0xff>;
1204
1205                         dma-coherent;
1206
1207                         linux,pci-domain = <3>;
1208                         num-lanes = <2>;
1209
1210                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1214                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1215
1216                         #interrupt-cells = <1>;
1217                         interrupt-map-mask = <0 0 0 0x7>;
1218                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
1219                                         <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1220                                         <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1221                                         <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1222
1223                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1224                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1225                                  <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
1226                                  <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
1227                                  <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
1228                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1229                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1230                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1231                         clock-names = "aux",
1232                                       "cfg",
1233                                       "bus_master",
1234                                       "bus_slave",
1235                                       "slave_q2a",
1236                                       "ddrss_sf_tbu",
1237                                       "noc_aggr_4",
1238                                       "noc_aggr_south_sf";
1239
1240                         assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
1241                         assigned-clock-rates = <19200000>;
1242
1243                         interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
1244                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
1245                         interconnect-names = "pcie-mem", "cpu-pcie";
1246
1247                         resets = <&gcc GCC_PCIE_2B_BCR>;
1248                         reset-names = "pci";
1249
1250                         power-domains = <&gcc PCIE_2B_GDSC>;
1251
1252                         phys = <&pcie2b_phy>;
1253                         phy-names = "pciephy";
1254
1255                         status = "disabled";
1256                 };
1257
1258                 pcie2b_phy: phy@1c1e000 {
1259                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1260                         reg = <0x0 0x01c1e000 0x0 0x2000>;
1261
1262                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1263                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1264                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1265                                  <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
1266                                  <&gcc GCC_PCIE_2B_PIPE_CLK>,
1267                                  <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
1268                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1269                                       "pipe", "pipediv2";
1270
1271                         assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
1272                         assigned-clock-rates = <100000000>;
1273
1274                         power-domains = <&gcc PCIE_2B_GDSC>;
1275
1276                         resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
1277                         reset-names = "phy";
1278
1279                         #clock-cells = <0>;
1280                         clock-output-names = "pcie_2b_pipe_clk";
1281
1282                         #phy-cells = <0>;
1283
1284                         status = "disabled";
1285                 };
1286
1287                 pcie2a: pcie@1c20000 {
1288                         device_type = "pci";
1289                         compatible = "qcom,pcie-sc8280xp";
1290                         reg = <0x0 0x01c20000 0x0 0x3000>,
1291                               <0x0 0x3c000000 0x0 0xf1d>,
1292                               <0x0 0x3c000f20 0x0 0xa8>,
1293                               <0x0 0x3c001000 0x0 0x1000>,
1294                               <0x0 0x3c100000 0x0 0x100000>;
1295                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1296                         #address-cells = <3>;
1297                         #size-cells = <2>;
1298                         ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
1299                                  <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
1300                         bus-range = <0x00 0xff>;
1301
1302                         dma-coherent;
1303
1304                         linux,pci-domain = <2>;
1305                         num-lanes = <4>;
1306
1307                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1308                                      <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
1309                                      <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
1310                                      <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
1311                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1312
1313                         #interrupt-cells = <1>;
1314                         interrupt-map-mask = <0 0 0 0x7>;
1315                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
1316                                         <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
1317                                         <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
1318                                         <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
1319
1320                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1321                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1322                                  <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
1323                                  <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
1324                                  <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
1325                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1326                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1327                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1328                         clock-names = "aux",
1329                                       "cfg",
1330                                       "bus_master",
1331                                       "bus_slave",
1332                                       "slave_q2a",
1333                                       "ddrss_sf_tbu",
1334                                       "noc_aggr_4",
1335                                       "noc_aggr_south_sf";
1336
1337                         assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
1338                         assigned-clock-rates = <19200000>;
1339
1340                         interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
1341                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
1342                         interconnect-names = "pcie-mem", "cpu-pcie";
1343
1344                         resets = <&gcc GCC_PCIE_2A_BCR>;
1345                         reset-names = "pci";
1346
1347                         power-domains = <&gcc PCIE_2A_GDSC>;
1348
1349                         phys = <&pcie2a_phy>;
1350                         phy-names = "pciephy";
1351
1352                         status = "disabled";
1353                 };
1354
1355                 pcie2a_phy: phy@1c24000 {
1356                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1357                         reg = <0x0 0x01c24000 0x0 0x2000>,
1358                               <0x0 0x01c26000 0x0 0x2000>;
1359
1360                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1361                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1362                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1363                                  <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
1364                                  <&gcc GCC_PCIE_2A_PIPE_CLK>,
1365                                  <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
1366                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1367                                       "pipe", "pipediv2";
1368
1369                         assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
1370                         assigned-clock-rates = <100000000>;
1371
1372                         power-domains = <&gcc PCIE_2A_GDSC>;
1373
1374                         resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
1375                         reset-names = "phy";
1376
1377                         qcom,4ln-config-sel = <&tcsr 0xa044 0>;
1378
1379                         #clock-cells = <0>;
1380                         clock-output-names = "pcie_2a_pipe_clk";
1381
1382                         #phy-cells = <0>;
1383
1384                         status = "disabled";
1385                 };
1386
1387                 ufs_mem_hc: ufs@1d84000 {
1388                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1389                                      "jedec,ufs-2.0";
1390                         reg = <0 0x01d84000 0 0x3000>;
1391                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1392                         phys = <&ufs_mem_phy>;
1393                         phy-names = "ufsphy";
1394                         lanes-per-direction = <2>;
1395                         #reset-cells = <1>;
1396                         resets = <&gcc GCC_UFS_PHY_BCR>;
1397                         reset-names = "rst";
1398
1399                         power-domains = <&gcc UFS_PHY_GDSC>;
1400                         required-opps = <&rpmhpd_opp_nom>;
1401
1402                         iommus = <&apps_smmu 0xe0 0x0>;
1403                         dma-coherent;
1404
1405                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1406                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1407                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1408                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1409                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
1410                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1411                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1412                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1413                         clock-names = "core_clk",
1414                                       "bus_aggr_clk",
1415                                       "iface_clk",
1416                                       "core_clk_unipro",
1417                                       "ref_clk",
1418                                       "tx_lane0_sync_clk",
1419                                       "rx_lane0_sync_clk",
1420                                       "rx_lane1_sync_clk";
1421                         freq-table-hz = <75000000 300000000>,
1422                                         <0 0>,
1423                                         <0 0>,
1424                                         <75000000 300000000>,
1425                                         <0 0>,
1426                                         <0 0>,
1427                                         <0 0>,
1428                                         <0 0>;
1429                         status = "disabled";
1430                 };
1431
1432                 ufs_mem_phy: phy@1d87000 {
1433                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
1434                         reg = <0 0x01d87000 0 0x1000>;
1435
1436                         clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
1437                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1438                         clock-names = "ref", "ref_aux";
1439
1440                         power-domains = <&gcc UFS_PHY_GDSC>;
1441
1442                         resets = <&ufs_mem_hc 0>;
1443                         reset-names = "ufsphy";
1444
1445                         #phy-cells = <0>;
1446
1447                         status = "disabled";
1448                 };
1449
1450                 ufs_card_hc: ufs@1da4000 {
1451                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1452                                      "jedec,ufs-2.0";
1453                         reg = <0 0x01da4000 0 0x3000>;
1454                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1455                         phys = <&ufs_card_phy>;
1456                         phy-names = "ufsphy";
1457                         lanes-per-direction = <2>;
1458                         #reset-cells = <1>;
1459                         resets = <&gcc GCC_UFS_CARD_BCR>;
1460                         reset-names = "rst";
1461
1462                         power-domains = <&gcc UFS_CARD_GDSC>;
1463
1464                         iommus = <&apps_smmu 0x4a0 0x0>;
1465                         dma-coherent;
1466
1467                         clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
1468                                  <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
1469                                  <&gcc GCC_UFS_CARD_AHB_CLK>,
1470                                  <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
1471                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
1472                                  <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
1473                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
1474                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
1475                         clock-names = "core_clk",
1476                                       "bus_aggr_clk",
1477                                       "iface_clk",
1478                                       "core_clk_unipro",
1479                                       "ref_clk",
1480                                       "tx_lane0_sync_clk",
1481                                       "rx_lane0_sync_clk",
1482                                       "rx_lane1_sync_clk";
1483                         freq-table-hz = <75000000 300000000>,
1484                                         <0 0>,
1485                                         <0 0>,
1486                                         <75000000 300000000>,
1487                                         <0 0>,
1488                                         <0 0>,
1489                                         <0 0>,
1490                                         <0 0>;
1491                         status = "disabled";
1492                 };
1493
1494                 ufs_card_phy: phy@1da7000 {
1495                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
1496                         reg = <0 0x01da7000 0 0x1000>;
1497
1498                         clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
1499                                  <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
1500                         clock-names = "ref", "ref_aux";
1501
1502                         power-domains = <&gcc UFS_CARD_GDSC>;
1503
1504                         resets = <&ufs_card_hc 0>;
1505                         reset-names = "ufsphy";
1506
1507                         #phy-cells = <0>;
1508
1509                         status = "disabled";
1510                 };
1511
1512                 tcsr_mutex: hwlock@1f40000 {
1513                         compatible = "qcom,tcsr-mutex";
1514                         reg = <0x0 0x01f40000 0x0 0x20000>;
1515                         #hwlock-cells = <1>;
1516                 };
1517
1518                 tcsr: syscon@1fc0000 {
1519                         compatible = "qcom,sc8280xp-tcsr", "syscon";
1520                         reg = <0x0 0x01fc0000 0x0 0x30000>;
1521                 };
1522
1523                 usb_0_hsphy: phy@88e5000 {
1524                         compatible = "qcom,sc8280xp-usb-hs-phy",
1525                                      "qcom,usb-snps-hs-5nm-phy";
1526                         reg = <0 0x088e5000 0 0x400>;
1527                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1528                         clock-names = "ref";
1529                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1530
1531                         #phy-cells = <0>;
1532
1533                         status = "disabled";
1534                 };
1535
1536                 usb_2_hsphy0: phy@88e7000 {
1537                         compatible = "qcom,sc8280xp-usb-hs-phy",
1538                                      "qcom,usb-snps-hs-5nm-phy";
1539                         reg = <0 0x088e7000 0 0x400>;
1540                         clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1541                         clock-names = "ref";
1542                         resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1543
1544                         #phy-cells = <0>;
1545
1546                         status = "disabled";
1547                 };
1548
1549                 usb_2_hsphy1: phy@88e8000 {
1550                         compatible = "qcom,sc8280xp-usb-hs-phy",
1551                                      "qcom,usb-snps-hs-5nm-phy";
1552                         reg = <0 0x088e8000 0 0x400>;
1553                         clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1554                         clock-names = "ref";
1555                         resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1556
1557                         #phy-cells = <0>;
1558
1559                         status = "disabled";
1560                 };
1561
1562                 usb_2_hsphy2: phy@88e9000 {
1563                         compatible = "qcom,sc8280xp-usb-hs-phy",
1564                                      "qcom,usb-snps-hs-5nm-phy";
1565                         reg = <0 0x088e9000 0 0x400>;
1566                         clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1567                         clock-names = "ref";
1568                         resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1569
1570                         #phy-cells = <0>;
1571
1572                         status = "disabled";
1573                 };
1574
1575                 usb_2_hsphy3: phy@88ea000 {
1576                         compatible = "qcom,sc8280xp-usb-hs-phy",
1577                                      "qcom,usb-snps-hs-5nm-phy";
1578                         reg = <0 0x088ea000 0 0x400>;
1579                         clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1580                         clock-names = "ref";
1581                         resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1582
1583                         #phy-cells = <0>;
1584
1585                         status = "disabled";
1586                 };
1587
1588                 usb_2_qmpphy0: phy@88ef000 {
1589                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1590                         reg = <0 0x088ef000 0 0x2000>;
1591
1592                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1593                                  <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1594                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1595                                  <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1596                         clock-names = "aux", "ref", "com_aux", "pipe";
1597
1598                         resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1599                                  <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1600                         reset-names = "phy", "phy_phy";
1601
1602                         power-domains = <&gcc USB30_MP_GDSC>;
1603
1604                         #clock-cells = <0>;
1605                         clock-output-names = "usb2_phy0_pipe_clk";
1606
1607                         #phy-cells = <0>;
1608
1609                         status = "disabled";
1610                 };
1611
1612                 usb_2_qmpphy1: phy@88f1000 {
1613                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1614                         reg = <0 0x088f1000 0 0x2000>;
1615
1616                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1617                                  <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1618                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1619                                  <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1620                         clock-names = "aux", "ref", "com_aux", "pipe";
1621
1622                         resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1623                                  <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1624                         reset-names = "phy", "phy_phy";
1625
1626                         power-domains = <&gcc USB30_MP_GDSC>;
1627
1628                         #clock-cells = <0>;
1629                         clock-output-names = "usb2_phy1_pipe_clk";
1630
1631                         #phy-cells = <0>;
1632
1633                         status = "disabled";
1634                 };
1635
1636                 remoteproc_adsp: remoteproc@3000000 {
1637                         compatible = "qcom,sc8280xp-adsp-pas";
1638                         reg = <0 0x03000000 0 0x100>;
1639
1640                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1641                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1642                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1643                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1644                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1645                                               <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1646                         interrupt-names = "wdog", "fatal", "ready",
1647                                           "handover", "stop-ack", "shutdown-ack";
1648
1649                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1650                         clock-names = "xo";
1651
1652                         power-domains = <&rpmhpd SC8280XP_LCX>,
1653                                         <&rpmhpd SC8280XP_LMX>;
1654                         power-domain-names = "lcx", "lmx";
1655
1656                         memory-region = <&pil_adsp_mem>;
1657
1658                         qcom,qmp = <&aoss_qmp>;
1659
1660                         qcom,smem-states = <&smp2p_adsp_out 0>;
1661                         qcom,smem-state-names = "stop";
1662
1663                         status = "disabled";
1664
1665                         remoteproc_adsp_glink: glink-edge {
1666                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1667                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1668                                                              IRQ_TYPE_EDGE_RISING>;
1669                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
1670                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1671
1672                                 label = "lpass";
1673                                 qcom,remote-pid = <2>;
1674                         };
1675                 };
1676
1677                 usb_0_qmpphy: phy@88eb000 {
1678                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1679                         reg = <0 0x088eb000 0 0x4000>;
1680
1681                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1682                                  <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1683                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1684                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1685                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1686
1687                         power-domains = <&gcc USB30_PRIM_GDSC>;
1688
1689                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1690                                  <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
1691                         reset-names = "phy", "common";
1692
1693                         #clock-cells = <1>;
1694                         #phy-cells = <1>;
1695
1696                         status = "disabled";
1697                 };
1698
1699                 usb_1_hsphy: phy@8902000 {
1700                         compatible = "qcom,sc8280xp-usb-hs-phy",
1701                                      "qcom,usb-snps-hs-5nm-phy";
1702                         reg = <0 0x08902000 0 0x400>;
1703                         #phy-cells = <0>;
1704
1705                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1706                         clock-names = "ref";
1707
1708                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1709
1710                         status = "disabled";
1711                 };
1712
1713                 usb_1_qmpphy: phy@8903000 {
1714                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1715                         reg = <0 0x08903000 0 0x4000>;
1716
1717                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1718                                  <&gcc GCC_USB4_CLKREF_CLK>,
1719                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1720                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1721                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1722
1723                         power-domains = <&gcc USB30_SEC_GDSC>;
1724
1725                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1726                                  <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1727                         reset-names = "phy", "common";
1728
1729                         #clock-cells = <1>;
1730                         #phy-cells = <1>;
1731
1732                         status = "disabled";
1733                 };
1734
1735                 pmu@9091000 {
1736                         compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
1737                         reg = <0 0x9091000 0 0x1000>;
1738
1739                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1740
1741                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
1742
1743                         operating-points-v2 = <&llcc_bwmon_opp_table>;
1744
1745                         llcc_bwmon_opp_table: opp-table {
1746                                 compatible = "operating-points-v2";
1747
1748                                 opp-0 {
1749                                         opp-peak-kBps = <762000>;
1750                                 };
1751                                 opp-1 {
1752                                         opp-peak-kBps = <1720000>;
1753                                 };
1754                                 opp-2 {
1755                                         opp-peak-kBps = <2086000>;
1756                                 };
1757                                 opp-3 {
1758                                         opp-peak-kBps = <2597000>;
1759                                 };
1760                                 opp-4 {
1761                                         opp-peak-kBps = <2929000>;
1762                                 };
1763                                 opp-5 {
1764                                         opp-peak-kBps = <3879000>;
1765                                 };
1766                                 opp-6 {
1767                                         opp-peak-kBps = <5161000>;
1768                                 };
1769                                 opp-7 {
1770                                         opp-peak-kBps = <5931000>;
1771                                 };
1772                                 opp-8 {
1773                                         opp-peak-kBps = <6515000>;
1774                                 };
1775                                 opp-9 {
1776                                         opp-peak-kBps = <7980000>;
1777                                 };
1778                                 opp-10 {
1779                                         opp-peak-kBps = <8136000>;
1780                                 };
1781                                 opp-11 {
1782                                         opp-peak-kBps = <10437000>;
1783                                 };
1784                                 opp-12 {
1785                                         opp-peak-kBps = <12191000>;
1786                                 };
1787                         };
1788                 };
1789
1790                 pmu@90b6400 {
1791                         compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
1792                         reg = <0 0x090b6400 0 0x600>;
1793
1794                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
1795
1796                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
1797                         operating-points-v2 = <&cpu_bwmon_opp_table>;
1798
1799                         cpu_bwmon_opp_table: opp-table {
1800                                 compatible = "operating-points-v2";
1801
1802                                 opp-0 {
1803                                         opp-peak-kBps = <2288000>;
1804                                 };
1805                                 opp-1 {
1806                                         opp-peak-kBps = <4577000>;
1807                                 };
1808                                 opp-2 {
1809                                         opp-peak-kBps = <7110000>;
1810                                 };
1811                                 opp-3 {
1812                                         opp-peak-kBps = <9155000>;
1813                                 };
1814                                 opp-4 {
1815                                         opp-peak-kBps = <12298000>;
1816                                 };
1817                                 opp-5 {
1818                                         opp-peak-kBps = <14236000>;
1819                                 };
1820                                 opp-6 {
1821                                         opp-peak-kBps = <15258001>;
1822                                 };
1823                         };
1824                 };
1825
1826                 system-cache-controller@9200000 {
1827                         compatible = "qcom,sc8280xp-llcc";
1828                         reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1829                         reg-names = "llcc_base", "llcc_broadcast_base";
1830                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1831                 };
1832
1833                 usb_0: usb@a6f8800 {
1834                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1835                         reg = <0 0x0a6f8800 0 0x400>;
1836                         #address-cells = <2>;
1837                         #size-cells = <2>;
1838                         ranges;
1839
1840                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1841                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1842                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1843                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1844                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1845                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1846                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1847                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1848                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1849                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1850                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1851
1852                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1853                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1854                         assigned-clock-rates = <19200000>, <200000000>;
1855
1856                         interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1857                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1858                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1859                                               <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
1860                         interrupt-names = "pwr_event",
1861                                           "dp_hs_phy_irq",
1862                                           "dm_hs_phy_irq",
1863                                           "ss_phy_irq";
1864
1865                         power-domains = <&gcc USB30_PRIM_GDSC>;
1866
1867                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1868
1869                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1870                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1871                         interconnect-names = "usb-ddr", "apps-usb";
1872
1873                         wakeup-source;
1874
1875                         status = "disabled";
1876
1877                         usb_0_dwc3: usb@a600000 {
1878                                 compatible = "snps,dwc3";
1879                                 reg = <0 0x0a600000 0 0xcd00>;
1880                                 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1881                                 iommus = <&apps_smmu 0x820 0x0>;
1882                                 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
1883                                 phy-names = "usb2-phy", "usb3-phy";
1884                         };
1885                 };
1886
1887                 usb_1: usb@a8f8800 {
1888                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1889                         reg = <0 0x0a8f8800 0 0x400>;
1890                         #address-cells = <2>;
1891                         #size-cells = <2>;
1892                         ranges;
1893
1894                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1895                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1896                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1897                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1898                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1899                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1900                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1901                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1902                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1903                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1904                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1905
1906                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1907                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1908                         assigned-clock-rates = <19200000>, <200000000>;
1909
1910                         interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1911                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1912                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1913                                               <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
1914                         interrupt-names = "pwr_event",
1915                                           "dp_hs_phy_irq",
1916                                           "dm_hs_phy_irq",
1917                                           "ss_phy_irq";
1918
1919                         power-domains = <&gcc USB30_SEC_GDSC>;
1920
1921                         resets = <&gcc GCC_USB30_SEC_BCR>;
1922
1923                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1924                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1925                         interconnect-names = "usb-ddr", "apps-usb";
1926
1927                         wakeup-source;
1928
1929                         status = "disabled";
1930
1931                         usb_1_dwc3: usb@a800000 {
1932                                 compatible = "snps,dwc3";
1933                                 reg = <0 0x0a800000 0 0xcd00>;
1934                                 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1935                                 iommus = <&apps_smmu 0x860 0x0>;
1936                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
1937                                 phy-names = "usb2-phy", "usb3-phy";
1938                         };
1939                 };
1940
1941                 pdc: interrupt-controller@b220000 {
1942                         compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1943                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1944                         qcom,pdc-ranges = <0 480 40>,
1945                                           <40 140 14>,
1946                                           <54 263 1>,
1947                                           <55 306 4>,
1948                                           <59 312 3>,
1949                                           <62 374 2>,
1950                                           <64 434 2>,
1951                                           <66 438 3>,
1952                                           <69 86 1>,
1953                                           <70 520 54>,
1954                                           <124 609 28>,
1955                                           <159 638 1>,
1956                                           <160 720 8>,
1957                                           <168 801 1>,
1958                                           <169 728 30>,
1959                                           <199 416 2>,
1960                                           <201 449 1>,
1961                                           <202 89 1>,
1962                                           <203 451 1>,
1963                                           <204 462 1>,
1964                                           <205 264 1>,
1965                                           <206 579 1>,
1966                                           <207 653 1>,
1967                                           <208 656 1>,
1968                                           <209 659 1>,
1969                                           <210 122 1>,
1970                                           <211 699 1>,
1971                                           <212 705 1>,
1972                                           <213 450 1>,
1973                                           <214 643 1>,
1974                                           <216 646 5>,
1975                                           <221 390 5>,
1976                                           <226 700 3>,
1977                                           <229 240 3>,
1978                                           <232 269 1>,
1979                                           <233 377 1>,
1980                                           <234 372 1>,
1981                                           <235 138 1>,
1982                                           <236 857 1>,
1983                                           <237 860 1>,
1984                                           <238 137 1>,
1985                                           <239 668 1>,
1986                                           <240 366 1>,
1987                                           <241 949 1>,
1988                                           <242 815 5>,
1989                                           <247 769 1>,
1990                                           <248 768 1>,
1991                                           <249 663 1>,
1992                                           <250 799 2>,
1993                                           <252 798 1>,
1994                                           <253 765 1>,
1995                                           <254 763 1>,
1996                                           <255 454 1>,
1997                                           <258 139 1>,
1998                                           <259 786 2>,
1999                                           <261 370 2>,
2000                                           <263 158 2>;
2001                         #interrupt-cells = <2>;
2002                         interrupt-parent = <&intc>;
2003                         interrupt-controller;
2004                 };
2005
2006                 tsens0: thermal-sensor@c263000 {
2007                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2008                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2009                               <0 0x0c222000 0 0x8>; /* SROT */
2010                         #qcom,sensors = <14>;
2011                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2012                                               <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2013                         interrupt-names = "uplow", "critical";
2014                         #thermal-sensor-cells = <1>;
2015                 };
2016
2017                 tsens1: thermal-sensor@c265000 {
2018                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2019                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2020                               <0 0x0c223000 0 0x8>; /* SROT */
2021                         #qcom,sensors = <16>;
2022                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2023                                               <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2024                         interrupt-names = "uplow", "critical";
2025                         #thermal-sensor-cells = <1>;
2026                 };
2027
2028                 aoss_qmp: power-controller@c300000 {
2029                         compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
2030                         reg = <0 0x0c300000 0 0x400>;
2031                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
2032                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2033
2034                         #clock-cells = <0>;
2035                 };
2036
2037                 sram@c3f0000 {
2038                         compatible = "qcom,rpmh-stats";
2039                         reg = <0 0x0c3f0000 0 0x400>;
2040                 };
2041
2042                 spmi_bus: spmi@c440000 {
2043                         compatible = "qcom,spmi-pmic-arb";
2044                         reg = <0 0x0c440000 0 0x1100>,
2045                               <0 0x0c600000 0 0x2000000>,
2046                               <0 0x0e600000 0 0x100000>,
2047                               <0 0x0e700000 0 0xa0000>,
2048                               <0 0x0c40a000 0 0x26000>;
2049                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2050                         interrupt-names = "periph_irq";
2051                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2052                         qcom,ee = <0>;
2053                         qcom,channel = <0>;
2054                         #address-cells = <1>;
2055                         #size-cells = <1>;
2056                         interrupt-controller;
2057                         #interrupt-cells = <4>;
2058                 };
2059
2060                 tlmm: pinctrl@f100000 {
2061                         compatible = "qcom,sc8280xp-tlmm";
2062                         reg = <0 0x0f100000 0 0x300000>;
2063                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2064                         gpio-controller;
2065                         #gpio-cells = <2>;
2066                         interrupt-controller;
2067                         #interrupt-cells = <2>;
2068                         gpio-ranges = <&tlmm 0 0 230>;
2069                 };
2070
2071                 apps_smmu: iommu@15000000 {
2072                         compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
2073                         reg = <0 0x15000000 0 0x100000>;
2074                         #iommu-cells = <2>;
2075                         #global-interrupts = <2>;
2076                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2077                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2078                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2079                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2080                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2081                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2082                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2083                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2084                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2085                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2086                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2087                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2088                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2089                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2090                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2091                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2092                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2093                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2094                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2095                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2096                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2097                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2098                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2099                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2100                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2101                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2102                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2103                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2104                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2105                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2106                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2107                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2108                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2109                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2110                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2111                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2112                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2113                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2114                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2115                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2116                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2117                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2118                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2119                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2120                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2121                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2122                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2123                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2124                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2125                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2126                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2127                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2128                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2129                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2130                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2131                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2132                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2133                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2134                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2135                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2136                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2137                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2138                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2139                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2140                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2141                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2142                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2143                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2144                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2145                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2146                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2147                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2148                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2149                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2150                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2151                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2152                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2153                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2154                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2155                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2156                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
2157                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2158                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2159                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2160                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2161                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2162                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2163                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2164                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2165                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2166                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2167                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2168                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2169                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2170                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2171                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2172                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2173                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2174                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2175                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2176                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2177                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2178                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2179                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2180                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2181                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2182                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2183                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2184                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2185                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2186                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2187                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2188                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2189                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2190                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2191                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2192                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2193                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2194                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2195                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2196                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2197                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2198                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2199                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2200                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2201                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2202                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2203                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2204                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
2205                                      <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
2206                 };
2207
2208                 intc: interrupt-controller@17a00000 {
2209                         compatible = "arm,gic-v3";
2210                         interrupt-controller;
2211                         #interrupt-cells = <3>;
2212                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2213                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2214                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2215                         #redistributor-regions = <1>;
2216                         redistributor-stride = <0 0x20000>;
2217
2218                         #address-cells = <2>;
2219                         #size-cells = <2>;
2220                         ranges;
2221
2222                         gic-its@17a40000 {
2223                                 compatible = "arm,gic-v3-its";
2224                                 reg = <0 0x17a40000 0 0x20000>;
2225                                 msi-controller;
2226                                 #msi-cells = <1>;
2227                         };
2228                 };
2229
2230                 watchdog@17c10000 {
2231                         compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
2232                         reg = <0 0x17c10000 0 0x1000>;
2233                         clocks = <&sleep_clk>;
2234                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2235                 };
2236
2237                 timer@17c20000 {
2238                         compatible = "arm,armv7-timer-mem";
2239                         reg = <0x0 0x17c20000 0x0 0x1000>;
2240                         #address-cells = <1>;
2241                         #size-cells = <1>;
2242                         ranges = <0x0 0x0 0x0 0x20000000>;
2243
2244                         frame@17c21000 {
2245                                 frame-number = <0>;
2246                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2247                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2248                                 reg = <0x17c21000 0x1000>,
2249                                       <0x17c22000 0x1000>;
2250                         };
2251
2252                         frame@17c23000 {
2253                                 frame-number = <1>;
2254                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2255                                 reg = <0x17c23000 0x1000>;
2256                                 status = "disabled";
2257                         };
2258
2259                         frame@17c25000 {
2260                                 frame-number = <2>;
2261                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2262                                 reg = <0x17c25000 0x1000>;
2263                                 status = "disabled";
2264                         };
2265
2266                         frame@17c27000 {
2267                                 frame-number = <3>;
2268                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2269                                 reg = <0x17c26000 0x1000>;
2270                                 status = "disabled";
2271                         };
2272
2273                         frame@17c29000 {
2274                                 frame-number = <4>;
2275                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2276                                 reg = <0x17c29000 0x1000>;
2277                                 status = "disabled";
2278                         };
2279
2280                         frame@17c2b000 {
2281                                 frame-number = <5>;
2282                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2283                                 reg = <0x17c2b000 0x1000>;
2284                                 status = "disabled";
2285                         };
2286
2287                         frame@17c2d000 {
2288                                 frame-number = <6>;
2289                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2290                                 reg = <0x17c2d000 0x1000>;
2291                                 status = "disabled";
2292                         };
2293                 };
2294
2295                 apps_rsc: rsc@18200000 {
2296                         compatible = "qcom,rpmh-rsc";
2297                         reg = <0x0 0x18200000 0x0 0x10000>,
2298                                 <0x0 0x18210000 0x0 0x10000>,
2299                                 <0x0 0x18220000 0x0 0x10000>;
2300                         reg-names = "drv-0", "drv-1", "drv-2";
2301                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2302                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2303                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2304                         qcom,tcs-offset = <0xd00>;
2305                         qcom,drv-id = <2>;
2306                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2307                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
2308                         label = "apps_rsc";
2309
2310                         apps_bcm_voter: bcm-voter {
2311                                 compatible = "qcom,bcm-voter";
2312                         };
2313
2314                         rpmhcc: clock-controller {
2315                                 compatible = "qcom,sc8280xp-rpmh-clk";
2316                                 #clock-cells = <1>;
2317                                 clock-names = "xo";
2318                                 clocks = <&xo_board_clk>;
2319                         };
2320
2321                         rpmhpd: power-controller {
2322                                 compatible = "qcom,sc8280xp-rpmhpd";
2323                                 #power-domain-cells = <1>;
2324                                 operating-points-v2 = <&rpmhpd_opp_table>;
2325
2326                                 rpmhpd_opp_table: opp-table {
2327                                         compatible = "operating-points-v2";
2328
2329                                         rpmhpd_opp_ret: opp1 {
2330                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2331                                         };
2332
2333                                         rpmhpd_opp_min_svs: opp2 {
2334                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2335                                         };
2336
2337                                         rpmhpd_opp_low_svs: opp3 {
2338                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2339                                         };
2340
2341                                         rpmhpd_opp_svs: opp4 {
2342                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2343                                         };
2344
2345                                         rpmhpd_opp_svs_l1: opp5 {
2346                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2347                                         };
2348
2349                                         rpmhpd_opp_nom: opp6 {
2350                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2351                                         };
2352
2353                                         rpmhpd_opp_nom_l1: opp7 {
2354                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2355                                         };
2356
2357                                         rpmhpd_opp_nom_l2: opp8 {
2358                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2359                                         };
2360
2361                                         rpmhpd_opp_turbo: opp9 {
2362                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2363                                         };
2364
2365                                         rpmhpd_opp_turbo_l1: opp10 {
2366                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2367                                         };
2368                                 };
2369                         };
2370                 };
2371
2372                 epss_l3: interconnect@18590000 {
2373                         compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
2374                         reg = <0 0x18590000 0 0x1000>;
2375
2376                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2377                         clock-names = "xo", "alternate";
2378
2379                         #interconnect-cells = <1>;
2380                 };
2381
2382                 cpufreq_hw: cpufreq@18591000 {
2383                         compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
2384                         reg = <0 0x18591000 0 0x1000>,
2385                               <0 0x18592000 0 0x1000>;
2386                         reg-names = "freq-domain0", "freq-domain1";
2387
2388                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2389                         clock-names = "xo", "alternate";
2390
2391                         #freq-domain-cells = <1>;
2392                 };
2393
2394                 remoteproc_nsp0: remoteproc@1b300000 {
2395                         compatible = "qcom,sc8280xp-nsp0-pas";
2396                         reg = <0 0x1b300000 0 0x100>;
2397
2398                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2399                                               <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
2400                                               <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
2401                                               <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
2402                                               <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
2403                         interrupt-names = "wdog", "fatal", "ready",
2404                                           "handover", "stop-ack";
2405
2406                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2407                         clock-names = "xo";
2408
2409                         power-domains = <&rpmhpd SC8280XP_NSP>;
2410                         power-domain-names = "nsp";
2411
2412                         memory-region = <&pil_nsp0_mem>;
2413
2414                         qcom,smem-states = <&smp2p_nsp0_out 0>;
2415                         qcom,smem-state-names = "stop";
2416
2417                         interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
2418
2419                         status = "disabled";
2420
2421                         glink-edge {
2422                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2423                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2424                                                              IRQ_TYPE_EDGE_RISING>;
2425                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2426                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2427
2428                                 label = "nsp0";
2429                                 qcom,remote-pid = <5>;
2430
2431                                 fastrpc {
2432                                         compatible = "qcom,fastrpc";
2433                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2434                                         label = "cdsp";
2435                                         #address-cells = <1>;
2436                                         #size-cells = <0>;
2437
2438                                         compute-cb@1 {
2439                                                 compatible = "qcom,fastrpc-compute-cb";
2440                                                 reg = <1>;
2441                                                 iommus = <&apps_smmu 0x3181 0x0420>;
2442                                         };
2443
2444                                         compute-cb@2 {
2445                                                 compatible = "qcom,fastrpc-compute-cb";
2446                                                 reg = <2>;
2447                                                 iommus = <&apps_smmu 0x3182 0x0420>;
2448                                         };
2449
2450                                         compute-cb@3 {
2451                                                 compatible = "qcom,fastrpc-compute-cb";
2452                                                 reg = <3>;
2453                                                 iommus = <&apps_smmu 0x3183 0x0420>;
2454                                         };
2455
2456                                         compute-cb@4 {
2457                                                 compatible = "qcom,fastrpc-compute-cb";
2458                                                 reg = <4>;
2459                                                 iommus = <&apps_smmu 0x3184 0x0420>;
2460                                         };
2461
2462                                         compute-cb@5 {
2463                                                 compatible = "qcom,fastrpc-compute-cb";
2464                                                 reg = <5>;
2465                                                 iommus = <&apps_smmu 0x3185 0x0420>;
2466                                         };
2467
2468                                         compute-cb@6 {
2469                                                 compatible = "qcom,fastrpc-compute-cb";
2470                                                 reg = <6>;
2471                                                 iommus = <&apps_smmu 0x3186 0x0420>;
2472                                         };
2473
2474                                         compute-cb@7 {
2475                                                 compatible = "qcom,fastrpc-compute-cb";
2476                                                 reg = <7>;
2477                                                 iommus = <&apps_smmu 0x3187 0x0420>;
2478                                         };
2479
2480                                         compute-cb@8 {
2481                                                 compatible = "qcom,fastrpc-compute-cb";
2482                                                 reg = <8>;
2483                                                 iommus = <&apps_smmu 0x3188 0x0420>;
2484                                         };
2485
2486                                         compute-cb@9 {
2487                                                 compatible = "qcom,fastrpc-compute-cb";
2488                                                 reg = <9>;
2489                                                 iommus = <&apps_smmu 0x318b 0x0420>;
2490                                         };
2491
2492                                         compute-cb@10 {
2493                                                 compatible = "qcom,fastrpc-compute-cb";
2494                                                 reg = <10>;
2495                                                 iommus = <&apps_smmu 0x318b 0x0420>;
2496                                         };
2497
2498                                         compute-cb@11 {
2499                                                 compatible = "qcom,fastrpc-compute-cb";
2500                                                 reg = <11>;
2501                                                 iommus = <&apps_smmu 0x318c 0x0420>;
2502                                         };
2503
2504                                         compute-cb@12 {
2505                                                 compatible = "qcom,fastrpc-compute-cb";
2506                                                 reg = <12>;
2507                                                 iommus = <&apps_smmu 0x318d 0x0420>;
2508                                         };
2509
2510                                         compute-cb@13 {
2511                                                 compatible = "qcom,fastrpc-compute-cb";
2512                                                 reg = <13>;
2513                                                 iommus = <&apps_smmu 0x318e 0x0420>;
2514                                         };
2515
2516                                         compute-cb@14 {
2517                                                 compatible = "qcom,fastrpc-compute-cb";
2518                                                 reg = <14>;
2519                                                 iommus = <&apps_smmu 0x318f 0x0420>;
2520                                         };
2521                                 };
2522                         };
2523                 };
2524
2525                 remoteproc_nsp1: remoteproc@21300000 {
2526                         compatible = "qcom,sc8280xp-nsp1-pas";
2527                         reg = <0 0x21300000 0 0x100>;
2528
2529                         interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
2530                                               <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
2531                                               <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
2532                                               <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
2533                                               <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
2534                         interrupt-names = "wdog", "fatal", "ready",
2535                                           "handover", "stop-ack";
2536
2537                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2538                         clock-names = "xo";
2539
2540                         power-domains = <&rpmhpd SC8280XP_NSP>;
2541                         power-domain-names = "nsp";
2542
2543                         memory-region = <&pil_nsp1_mem>;
2544
2545                         qcom,smem-states = <&smp2p_nsp1_out 0>;
2546                         qcom,smem-state-names = "stop";
2547
2548                         interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
2549
2550                         status = "disabled";
2551
2552                         glink-edge {
2553                                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
2554                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2555                                                              IRQ_TYPE_EDGE_RISING>;
2556                                 mboxes = <&ipcc IPCC_CLIENT_NSP1
2557                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2558
2559                                 label = "nsp1";
2560                                 qcom,remote-pid = <12>;
2561                         };
2562                 };
2563         };
2564
2565         thermal-zones {
2566                 cpu0-thermal {
2567                         polling-delay-passive = <250>;
2568                         polling-delay = <1000>;
2569
2570                         thermal-sensors = <&tsens0 1>;
2571
2572                         trips {
2573                                 cpu-crit {
2574                                         temperature = <110000>;
2575                                         hysteresis = <1000>;
2576                                         type = "critical";
2577                                 };
2578                         };
2579                 };
2580
2581                 cpu1-thermal {
2582                         polling-delay-passive = <250>;
2583                         polling-delay = <1000>;
2584
2585                         thermal-sensors = <&tsens0 2>;
2586
2587                         trips {
2588                                 cpu-crit {
2589                                         temperature = <110000>;
2590                                         hysteresis = <1000>;
2591                                         type = "critical";
2592                                 };
2593                         };
2594                 };
2595
2596                 cpu2-thermal {
2597                         polling-delay-passive = <250>;
2598                         polling-delay = <1000>;
2599
2600                         thermal-sensors = <&tsens0 3>;
2601
2602                         trips {
2603                                 cpu-crit {
2604                                         temperature = <110000>;
2605                                         hysteresis = <1000>;
2606                                         type = "critical";
2607                                 };
2608                         };
2609                 };
2610
2611                 cpu3-thermal {
2612                         polling-delay-passive = <250>;
2613                         polling-delay = <1000>;
2614
2615                         thermal-sensors = <&tsens0 4>;
2616
2617                         trips {
2618                                 cpu-crit {
2619                                         temperature = <110000>;
2620                                         hysteresis = <1000>;
2621                                         type = "critical";
2622                                 };
2623                         };
2624                 };
2625
2626                 cpu4-thermal {
2627                         polling-delay-passive = <250>;
2628                         polling-delay = <1000>;
2629
2630                         thermal-sensors = <&tsens0 5>;
2631
2632                         trips {
2633                                 cpu-crit {
2634                                         temperature = <110000>;
2635                                         hysteresis = <1000>;
2636                                         type = "critical";
2637                                 };
2638                         };
2639                 };
2640
2641                 cpu5-thermal {
2642                         polling-delay-passive = <250>;
2643                         polling-delay = <1000>;
2644
2645                         thermal-sensors = <&tsens0 6>;
2646
2647                         trips {
2648                                 cpu-crit {
2649                                         temperature = <110000>;
2650                                         hysteresis = <1000>;
2651                                         type = "critical";
2652                                 };
2653                         };
2654                 };
2655
2656                 cpu6-thermal {
2657                         polling-delay-passive = <250>;
2658                         polling-delay = <1000>;
2659
2660                         thermal-sensors = <&tsens0 7>;
2661
2662                         trips {
2663                                 cpu-crit {
2664                                         temperature = <110000>;
2665                                         hysteresis = <1000>;
2666                                         type = "critical";
2667                                 };
2668                         };
2669                 };
2670
2671                 cpu7-thermal {
2672                         polling-delay-passive = <250>;
2673                         polling-delay = <1000>;
2674
2675                         thermal-sensors = <&tsens0 8>;
2676
2677                         trips {
2678                                 cpu-crit {
2679                                         temperature = <110000>;
2680                                         hysteresis = <1000>;
2681                                         type = "critical";
2682                                 };
2683                         };
2684                 };
2685
2686                 cluster0-thermal {
2687                         polling-delay-passive = <250>;
2688                         polling-delay = <1000>;
2689
2690                         thermal-sensors = <&tsens0 9>;
2691
2692                         trips {
2693                                 cpu-crit {
2694                                         temperature = <110000>;
2695                                         hysteresis = <1000>;
2696                                         type = "critical";
2697                                 };
2698                         };
2699                 };
2700
2701                 mem-thermal {
2702                         polling-delay-passive = <250>;
2703                         polling-delay = <1000>;
2704
2705                         thermal-sensors = <&tsens1 15>;
2706
2707                         trips {
2708                                 trip-point0 {
2709                                         temperature = <90000>;
2710                                         hysteresis = <2000>;
2711                                         type = "hot";
2712                                 };
2713                         };
2714                 };
2715         };
2716
2717         timer {
2718                 compatible = "arm,armv8-timer";
2719                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2720                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2721                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2722                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2723         };
2724 };