arch/arm64/boot/dts/qcom/sc8280xp.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
   8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  11 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/mailbox/qcom-ipcc.h>
  14 #include <dt-bindings/phy/phy-qcom-qmp.h>
  15 #include <dt-bindings/power/qcom-rpmpd.h>
  16 #include <dt-bindings/soc/qcom,gpr.h>
  17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  18 #include <dt-bindings/sound/qcom,q6afe.h>
  19 #include <dt-bindings/thermal/thermal.h>
  20
  21 / {
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         clocks {
  28                 xo_board_clk: xo-board-clk {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <32764>;
  37                 };
  38         };
  39
  40         cpu0_opp_table: cpu0-opp-table {
  41                 compatible = "operating-points-v2";
  42                 opp-shared;
  43
  44                 opp-300000000 {
  45                         opp-hz = /bits/ 64 <300000000>;
  46                         opp-peak-kBps = <(300000 * 32)>;
  47                 };
  48                 opp-403200000 {
  49                         opp-hz = /bits/ 64 <403200000>;
  50                         opp-peak-kBps = <(384000 * 32)>;
  51                 };
  52                 opp-499200000 {
  53                         opp-hz = /bits/ 64 <499200000>;
  54                         opp-peak-kBps = <(480000 * 32)>;
  55                 };
  56                 opp-595200000 {
  57                         opp-hz = /bits/ 64 <595200000>;
  58                         opp-peak-kBps = <(576000 * 32)>;
  59                 };
  60                 opp-691200000 {
  61                         opp-hz = /bits/ 64 <691200000>;
  62                         opp-peak-kBps = <(672000 * 32)>;
  63                 };
  64                 opp-806400000 {
  65                         opp-hz = /bits/ 64 <806400000>;
  66                         opp-peak-kBps = <(768000 * 32)>;
  67                 };
  68                 opp-902400000 {
  69                         opp-hz = /bits/ 64 <902400000>;
  70                         opp-peak-kBps = <(864000 * 32)>;
  71                 };
  72                 opp-1017600000 {
  73                         opp-hz = /bits/ 64 <1017600000>;
  74                         opp-peak-kBps = <(960000 * 32)>;
  75                 };
  76                 opp-1113600000 {
  77                         opp-hz = /bits/ 64 <1113600000>;
  78                         opp-peak-kBps = <(1075200 * 32)>;
  79                 };
  80                 opp-1209600000 {
  81                         opp-hz = /bits/ 64 <1209600000>;
  82                         opp-peak-kBps = <(1171200 * 32)>;
  83                 };
  84                 opp-1324800000 {
  85                         opp-hz = /bits/ 64 <1324800000>;
  86                         opp-peak-kBps = <(1267200 * 32)>;
  87                 };
  88                 opp-1440000000 {
  89                         opp-hz = /bits/ 64 <1440000000>;
  90                         opp-peak-kBps = <(1363200 * 32)>;
  91                 };
  92                 opp-1555200000 {
  93                         opp-hz = /bits/ 64 <1555200000>;
  94                         opp-peak-kBps = <(1536000 * 32)>;
  95                 };
  96                 opp-1670400000 {
  97                         opp-hz = /bits/ 64 <1670400000>;
  98                         opp-peak-kBps = <(1612800 * 32)>;
  99                 };
 100                 opp-1785600000 {
 101                         opp-hz = /bits/ 64 <1785600000>;
 102                         opp-peak-kBps = <(1689600 * 32)>;
 103                 };
 104                 opp-1881600000 {
 105                         opp-hz = /bits/ 64 <1881600000>;
 106                         opp-peak-kBps = <(1689600 * 32)>;
 107                 };
 108                 opp-1996800000 {
 109                         opp-hz = /bits/ 64 <1996800000>;
 110                         opp-peak-kBps = <(1689600 * 32)>;
 111                 };
 112                 opp-2112000000 {
 113                         opp-hz = /bits/ 64 <2112000000>;
 114                         opp-peak-kBps = <(1689600 * 32)>;
 115                 };
 116                 opp-2227200000 {
 117                         opp-hz = /bits/ 64 <2227200000>;
 118                         opp-peak-kBps = <(1689600 * 32)>;
 119                 };
 120                 opp-2342400000 {
 121                         opp-hz = /bits/ 64 <2342400000>;
 122                         opp-peak-kBps = <(1689600 * 32)>;
 123                 };
 124                 opp-2438400000 {
 125                         opp-hz = /bits/ 64 <2438400000>;
 126                         opp-peak-kBps = <(1689600 * 32)>;
 127                 };
 128         };
 129
 130         cpu4_opp_table: cpu4-opp-table {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 opp-825600000 {
 135                         opp-hz = /bits/ 64 <825600000>;
 136                         opp-peak-kBps = <(768000 * 32)>;
 137                 };
 138                 opp-940800000 {
 139                         opp-hz = /bits/ 64 <940800000>;
 140                         opp-peak-kBps = <(864000 * 32)>;
 141                 };
 142                 opp-1056000000 {
 143                         opp-hz = /bits/ 64 <1056000000>;
 144                         opp-peak-kBps = <(960000 * 32)>;
 145                 };
 146                 opp-1171200000 {
 147                         opp-hz = /bits/ 64 <1171200000>;
 148                         opp-peak-kBps = <(1171200 * 32)>;
 149                 };
 150                 opp-1286400000 {
 151                         opp-hz = /bits/ 64 <1286400000>;
 152                         opp-peak-kBps = <(1267200 * 32)>;
 153                 };
 154                 opp-1401600000 {
 155                         opp-hz = /bits/ 64 <1401600000>;
 156                         opp-peak-kBps = <(1363200 * 32)>;
 157                 };
 158                 opp-1516800000 {
 159                         opp-hz = /bits/ 64 <1516800000>;
 160                         opp-peak-kBps = <(1459200 * 32)>;
 161                 };
 162                 opp-1632000000 {
 163                         opp-hz = /bits/ 64 <1632000000>;
 164                         opp-peak-kBps = <(1612800 * 32)>;
 165                 };
 166                 opp-1747200000 {
 167                         opp-hz = /bits/ 64 <1747200000>;
 168                         opp-peak-kBps = <(1689600 * 32)>;
 169                 };
 170                 opp-1862400000 {
 171                         opp-hz = /bits/ 64 <1862400000>;
 172                         opp-peak-kBps = <(1689600 * 32)>;
 173                 };
 174                 opp-1977600000 {
 175                         opp-hz = /bits/ 64 <1977600000>;
 176                         opp-peak-kBps = <(1689600 * 32)>;
 177                 };
 178                 opp-2073600000 {
 179                         opp-hz = /bits/ 64 <2073600000>;
 180                         opp-peak-kBps = <(1689600 * 32)>;
 181                 };
 182                 opp-2169600000 {
 183                         opp-hz = /bits/ 64 <2169600000>;
 184                         opp-peak-kBps = <(1689600 * 32)>;
 185                 };
 186                 opp-2284800000 {
 187                         opp-hz = /bits/ 64 <2284800000>;
 188                         opp-peak-kBps = <(1689600 * 32)>;
 189                 };
 190                 opp-2400000000 {
 191                         opp-hz = /bits/ 64 <2400000000>;
 192                         opp-peak-kBps = <(1689600 * 32)>;
 193                 };
 194                 opp-2496000000 {
 195                         opp-hz = /bits/ 64 <2496000000>;
 196                         opp-peak-kBps = <(1689600 * 32)>;
 197                 };
 198                 opp-2592000000 {
 199                         opp-hz = /bits/ 64 <2592000000>;
 200                         opp-peak-kBps = <(1689600 * 32)>;
 201                 };
 202                 opp-2688000000 {
 203                         opp-hz = /bits/ 64 <2688000000>;
 204                         opp-peak-kBps = <(1689600 * 32)>;
 205                 };
 206                 opp-2803200000 {
 207                         opp-hz = /bits/ 64 <2803200000>;
 208                         opp-peak-kBps = <(1689600 * 32)>;
 209                 };
 210                 opp-2899200000 {
 211                         opp-hz = /bits/ 64 <2899200000>;
 212                         opp-peak-kBps = <(1689600 * 32)>;
 213                 };
 214                 opp-2995200000 {
 215                         opp-hz = /bits/ 64 <2995200000>;
 216                         opp-peak-kBps = <(1689600 * 32)>;
 217                 };
 218         };
 219
 220         cpus {
 221                 #address-cells = <2>;
 222                 #size-cells = <0>;
 223
 224                 CPU0: cpu@0 {
 225                         device_type = "cpu";
 226                         compatible = "qcom,kryo";
 227                         reg = <0x0 0x0>;
 228                         enable-method = "psci";
 229                         capacity-dmips-mhz = <602>;
 230                         next-level-cache = <&L2_0>;
 231                         power-domains = <&CPU_PD0>;
 232                         power-domain-names = "psci";
 233                         qcom,freq-domain = <&cpufreq_hw 0>;
 234                         operating-points-v2 = <&cpu0_opp_table>;
 235                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 236                         #cooling-cells = <2>;
 237                         L2_0: l2-cache {
 238                                 compatible = "cache";
 239                                 cache-level = <2>;
 240                                 next-level-cache = <&L3_0>;
 241                                 L3_0: l3-cache {
 242                                       compatible = "cache";
 243                                       cache-level = <3>;
 244                                 };
 245                         };
 246                 };
 247
 248                 CPU1: cpu@100 {
 249                         device_type = "cpu";
 250                         compatible = "qcom,kryo";
 251                         reg = <0x0 0x100>;
 252                         enable-method = "psci";
 253                         capacity-dmips-mhz = <602>;
 254                         next-level-cache = <&L2_100>;
 255                         power-domains = <&CPU_PD1>;
 256                         power-domain-names = "psci";
 257                         qcom,freq-domain = <&cpufreq_hw 0>;
 258                         operating-points-v2 = <&cpu0_opp_table>;
 259                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 260                         #cooling-cells = <2>;
 261                         L2_100: l2-cache {
 262                                 compatible = "cache";
 263                                 cache-level = <2>;
 264                                 next-level-cache = <&L3_0>;
 265                         };
 266                 };
 267
 268                 CPU2: cpu@200 {
 269                         device_type = "cpu";
 270                         compatible = "qcom,kryo";
 271                         reg = <0x0 0x200>;
 272                         enable-method = "psci";
 273                         capacity-dmips-mhz = <602>;
 274                         next-level-cache = <&L2_200>;
 275                         power-domains = <&CPU_PD2>;
 276                         power-domain-names = "psci";
 277                         qcom,freq-domain = <&cpufreq_hw 0>;
 278                         operating-points-v2 = <&cpu0_opp_table>;
 279                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 280                         #cooling-cells = <2>;
 281                         L2_200: l2-cache {
 282                                 compatible = "cache";
 283                                 cache-level = <2>;
 284                                 next-level-cache = <&L3_0>;
 285                         };
 286                 };
 287
 288                 CPU3: cpu@300 {
 289                         device_type = "cpu";
 290                         compatible = "qcom,kryo";
 291                         reg = <0x0 0x300>;
 292                         enable-method = "psci";
 293                         capacity-dmips-mhz = <602>;
 294                         next-level-cache = <&L2_300>;
 295                         power-domains = <&CPU_PD3>;
 296                         power-domain-names = "psci";
 297                         qcom,freq-domain = <&cpufreq_hw 0>;
 298                         operating-points-v2 = <&cpu0_opp_table>;
 299                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 300                         #cooling-cells = <2>;
 301                         L2_300: l2-cache {
 302                                 compatible = "cache";
 303                                 cache-level = <2>;
 304                                 next-level-cache = <&L3_0>;
 305                         };
 306                 };
 307
 308                 CPU4: cpu@400 {
 309                         device_type = "cpu";
 310                         compatible = "qcom,kryo";
 311                         reg = <0x0 0x400>;
 312                         enable-method = "psci";
 313                         capacity-dmips-mhz = <1024>;
 314                         next-level-cache = <&L2_400>;
 315                         power-domains = <&CPU_PD4>;
 316                         power-domain-names = "psci";
 317                         qcom,freq-domain = <&cpufreq_hw 1>;
 318                         operating-points-v2 = <&cpu4_opp_table>;
 319                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 320                         #cooling-cells = <2>;
 321                         L2_400: l2-cache {
 322                                 compatible = "cache";
 323                                 cache-level = <2>;
 324                                 next-level-cache = <&L3_0>;
 325                         };
 326                 };
 327
 328                 CPU5: cpu@500 {
 329                         device_type = "cpu";
 330                         compatible = "qcom,kryo";
 331                         reg = <0x0 0x500>;
 332                         enable-method = "psci";
 333                         capacity-dmips-mhz = <1024>;
 334                         next-level-cache = <&L2_500>;
 335                         power-domains = <&CPU_PD5>;
 336                         power-domain-names = "psci";
 337                         qcom,freq-domain = <&cpufreq_hw 1>;
 338                         operating-points-v2 = <&cpu4_opp_table>;
 339                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 340                         #cooling-cells = <2>;
 341                         L2_500: l2-cache {
 342                                 compatible = "cache";
 343                                 cache-level = <2>;
 344                                 next-level-cache = <&L3_0>;
 345                         };
 346                 };
 347
 348                 CPU6: cpu@600 {
 349                         device_type = "cpu";
 350                         compatible = "qcom,kryo";
 351                         reg = <0x0 0x600>;
 352                         enable-method = "psci";
 353                         capacity-dmips-mhz = <1024>;
 354                         next-level-cache = <&L2_600>;
 355                         power-domains = <&CPU_PD6>;
 356                         power-domain-names = "psci";
 357                         qcom,freq-domain = <&cpufreq_hw 1>;
 358                         operating-points-v2 = <&cpu4_opp_table>;
 359                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 360                         #cooling-cells = <2>;
 361                         L2_600: l2-cache {
 362                                 compatible = "cache";
 363                                 cache-level = <2>;
 364                                 next-level-cache = <&L3_0>;
 365                         };
 366                 };
 367
 368                 CPU7: cpu@700 {
 369                         device_type = "cpu";
 370                         compatible = "qcom,kryo";
 371                         reg = <0x0 0x700>;
 372                         enable-method = "psci";
 373                         capacity-dmips-mhz = <1024>;
 374                         next-level-cache = <&L2_700>;
 375                         power-domains = <&CPU_PD7>;
 376                         power-domain-names = "psci";
 377                         qcom,freq-domain = <&cpufreq_hw 1>;
 378                         operating-points-v2 = <&cpu4_opp_table>;
 379                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 380                         #cooling-cells = <2>;
 381                         L2_700: l2-cache {
 382                                 compatible = "cache";
 383                                 cache-level = <2>;
 384                                 next-level-cache = <&L3_0>;
 385                         };
 386                 };
 387
 388                 cpu-map {
 389                         cluster0 {
 390                                 core0 {
 391                                         cpu = <&CPU0>;
 392                                 };
 393
 394                                 core1 {
 395                                         cpu = <&CPU1>;
 396                                 };
 397
 398                                 core2 {
 399                                         cpu = <&CPU2>;
 400                                 };
 401
 402                                 core3 {
 403                                         cpu = <&CPU3>;
 404                                 };
 405
 406                                 core4 {
 407                                         cpu = <&CPU4>;
 408                                 };
 409
 410                                 core5 {
 411                                         cpu = <&CPU5>;
 412                                 };
 413
 414                                 core6 {
 415                                         cpu = <&CPU6>;
 416                                 };
 417
 418                                 core7 {
 419                                         cpu = <&CPU7>;
 420                                 };
 421                         };
 422                 };
 423
 424                 idle-states {
 425                         entry-method = "psci";
 426
 427                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 428                                 compatible = "arm,idle-state";
 429                                 idle-state-name = "little-rail-power-collapse";
 430                                 arm,psci-suspend-param = <0x40000004>;
 431                                 entry-latency-us = <355>;
 432                                 exit-latency-us = <909>;
 433                                 min-residency-us = <3934>;
 434                                 local-timer-stop;
 435                         };
 436
 437                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 438                                 compatible = "arm,idle-state";
 439                                 idle-state-name = "big-rail-power-collapse";
 440                                 arm,psci-suspend-param = <0x40000004>;
 441                                 entry-latency-us = <241>;
 442                                 exit-latency-us = <1461>;
 443                                 min-residency-us = <4488>;
 444                                 local-timer-stop;
 445                         };
 446                 };
 447
 448                 domain-idle-states {
 449                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 450                                 compatible = "domain-idle-state";
 451                                 idle-state-name = "cluster-power-collapse";
 452                                 arm,psci-suspend-param = <0x4100c344>;
 453                                 entry-latency-us = <3263>;
 454                                 exit-latency-us = <6562>;
 455                                 min-residency-us = <9987>;
 456                         };
 457                 };
 458         };
 459
 460         firmware {
 461                 scm: scm {
 462                         compatible = "qcom,scm-sc8280xp", "qcom,scm";
 463                 };
 464         };
 465
 466         aggre1_noc: interconnect-aggre1-noc {
 467                 compatible = "qcom,sc8280xp-aggre1-noc";
 468                 #interconnect-cells = <2>;
 469                 qcom,bcm-voters = <&apps_bcm_voter>;
 470         };
 471
 472         aggre2_noc: interconnect-aggre2-noc {
 473                 compatible = "qcom,sc8280xp-aggre2-noc";
 474                 #interconnect-cells = <2>;
 475                 qcom,bcm-voters = <&apps_bcm_voter>;
 476         };
 477
 478         clk_virt: interconnect-clk-virt {
 479                 compatible = "qcom,sc8280xp-clk-virt";
 480                 #interconnect-cells = <2>;
 481                 qcom,bcm-voters = <&apps_bcm_voter>;
 482         };
 483
 484         config_noc: interconnect-config-noc {
 485                 compatible = "qcom,sc8280xp-config-noc";
 486                 #interconnect-cells = <2>;
 487                 qcom,bcm-voters = <&apps_bcm_voter>;
 488         };
 489
 490         dc_noc: interconnect-dc-noc {
 491                 compatible = "qcom,sc8280xp-dc-noc";
 492                 #interconnect-cells = <2>;
 493                 qcom,bcm-voters = <&apps_bcm_voter>;
 494         };
 495
 496         gem_noc: interconnect-gem-noc {
 497                 compatible = "qcom,sc8280xp-gem-noc";
 498                 #interconnect-cells = <2>;
 499                 qcom,bcm-voters = <&apps_bcm_voter>;
 500         };
 501
 502         lpass_noc: interconnect-lpass-ag-noc {
 503                 compatible = "qcom,sc8280xp-lpass-ag-noc";
 504                 #interconnect-cells = <2>;
 505                 qcom,bcm-voters = <&apps_bcm_voter>;
 506         };
 507
 508         mc_virt: interconnect-mc-virt {
 509                 compatible = "qcom,sc8280xp-mc-virt";
 510                 #interconnect-cells = <2>;
 511                 qcom,bcm-voters = <&apps_bcm_voter>;
 512         };
 513
 514         mmss_noc: interconnect-mmss-noc {
 515                 compatible = "qcom,sc8280xp-mmss-noc";
 516                 #interconnect-cells = <2>;
 517                 qcom,bcm-voters = <&apps_bcm_voter>;
 518         };
 519
 520         nspa_noc: interconnect-nspa-noc {
 521                 compatible = "qcom,sc8280xp-nspa-noc";
 522                 #interconnect-cells = <2>;
 523                 qcom,bcm-voters = <&apps_bcm_voter>;
 524         };
 525
 526         nspb_noc: interconnect-nspb-noc {
 527                 compatible = "qcom,sc8280xp-nspb-noc";
 528                 #interconnect-cells = <2>;
 529                 qcom,bcm-voters = <&apps_bcm_voter>;
 530         };
 531
 532         system_noc: interconnect-system-noc {
 533                 compatible = "qcom,sc8280xp-system-noc";
 534                 #interconnect-cells = <2>;
 535                 qcom,bcm-voters = <&apps_bcm_voter>;
 536         };
 537
 538         memory@80000000 {
 539                 device_type = "memory";
 540                 /* We expect the bootloader to fill in the size */
 541                 reg = <0x0 0x80000000 0x0 0x0>;
 542         };
 543
 544         pmu {
 545                 compatible = "arm,armv8-pmuv3";
 546                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 547         };
 548
 549         psci {
 550                 compatible = "arm,psci-1.0";
 551                 method = "smc";
 552
 553                 CPU_PD0: power-domain-cpu0 {
 554                         #power-domain-cells = <0>;
 555                         power-domains = <&CLUSTER_PD>;
 556                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 557                 };
 558
 559                 CPU_PD1: power-domain-cpu1 {
 560                         #power-domain-cells = <0>;
 561                         power-domains = <&CLUSTER_PD>;
 562                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 563                 };
 564
 565                 CPU_PD2: power-domain-cpu2 {
 566                         #power-domain-cells = <0>;
 567                         power-domains = <&CLUSTER_PD>;
 568                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 569                 };
 570
 571                 CPU_PD3: power-domain-cpu3 {
 572                         #power-domain-cells = <0>;
 573                         power-domains = <&CLUSTER_PD>;
 574                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 575                 };
 576
 577                 CPU_PD4: power-domain-cpu4 {
 578                         #power-domain-cells = <0>;
 579                         power-domains = <&CLUSTER_PD>;
 580                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 581                 };
 582
 583                 CPU_PD5: power-domain-cpu5 {
 584                         #power-domain-cells = <0>;
 585                         power-domains = <&CLUSTER_PD>;
 586                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 587                 };
 588
 589                 CPU_PD6: power-domain-cpu6 {
 590                         #power-domain-cells = <0>;
 591                         power-domains = <&CLUSTER_PD>;
 592                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 593                 };
 594
 595                 CPU_PD7: power-domain-cpu7 {
 596                         #power-domain-cells = <0>;
 597                         power-domains = <&CLUSTER_PD>;
 598                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 599                 };
 600
 601                 CLUSTER_PD: power-domain-cpu-cluster0 {
 602                         #power-domain-cells = <0>;
 603                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 604                 };
 605         };
 606
 607         qup_opp_table_100mhz: qup-100mhz-opp-table {
 608                 compatible = "operating-points-v2";
 609
 610                 opp-75000000 {
 611                         opp-hz = /bits/ 64 <75000000>;
 612                         required-opps = <&rpmhpd_opp_low_svs>;
 613                 };
 614
 615                 opp-100000000 {
 616                         opp-hz = /bits/ 64 <100000000>;
 617                         required-opps = <&rpmhpd_opp_svs>;
 618                 };
 619         };
 620
 621         reserved-memory {
 622                 #address-cells = <2>;
 623                 #size-cells = <2>;
 624                 ranges;
 625
 626                 reserved-region@80000000 {
 627                         reg = <0 0x80000000 0 0x860000>;
 628                         no-map;
 629                 };
 630
 631                 cmd_db: cmd-db-region@80860000 {
 632                         compatible = "qcom,cmd-db";
 633                         reg = <0 0x80860000 0 0x20000>;
 634                         no-map;
 635                 };
 636
 637                 reserved-region@80880000 {
 638                         reg = <0 0x80880000 0 0x80000>;
 639                         no-map;
 640                 };
 641
 642                 smem_mem: smem-region@80900000 {
 643                         compatible = "qcom,smem";
 644                         reg = <0 0x80900000 0 0x200000>;
 645                         no-map;
 646                         hwlocks = <&tcsr_mutex 3>;
 647                 };
 648
 649                 reserved-region@80b00000 {
 650                         reg = <0 0x80b00000 0 0x100000>;
 651                         no-map;
 652                 };
 653
 654                 reserved-region@83b00000 {
 655                         reg = <0 0x83b00000 0 0x1700000>;
 656                         no-map;
 657                 };
 658
 659                 reserved-region@85b00000 {
 660                         reg = <0 0x85b00000 0 0xc00000>;
 661                         no-map;
 662                 };
 663
 664                 pil_adsp_mem: adsp-region@86c00000 {
 665                         reg = <0 0x86c00000 0 0x2000000>;
 666                         no-map;
 667                 };
 668
 669                 pil_nsp0_mem: cdsp0-region@8a100000 {
 670                         reg = <0 0x8a100000 0 0x1e00000>;
 671                         no-map;
 672                 };
 673
 674                 pil_nsp1_mem: cdsp1-region@8c600000 {
 675                         reg = <0 0x8c600000 0 0x1e00000>;
 676                         no-map;
 677                 };
 678
 679                 reserved-region@aeb00000 {
 680                         reg = <0 0xaeb00000 0 0x16600000>;
 681                         no-map;
 682                 };
 683         };
 684
 685         smp2p-adsp {
 686                 compatible = "qcom,smp2p";
 687                 qcom,smem = <443>, <429>;
 688                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 689                                              IPCC_MPROC_SIGNAL_SMP2P
 690                                              IRQ_TYPE_EDGE_RISING>;
 691                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 692                                 IPCC_MPROC_SIGNAL_SMP2P>;
 693
 694                 qcom,local-pid = <0>;
 695                 qcom,remote-pid = <2>;
 696
 697                 smp2p_adsp_out: master-kernel {
 698                         qcom,entry-name = "master-kernel";
 699                         #qcom,smem-state-cells = <1>;
 700                 };
 701
 702                 smp2p_adsp_in: slave-kernel {
 703                         qcom,entry-name = "slave-kernel";
 704                         interrupt-controller;
 705                         #interrupt-cells = <2>;
 706                 };
 707         };
 708
 709         smp2p-nsp0 {
 710                 compatible = "qcom,smp2p";
 711                 qcom,smem = <94>, <432>;
 712                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 713                                              IPCC_MPROC_SIGNAL_SMP2P
 714                                              IRQ_TYPE_EDGE_RISING>;
 715                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 716                                 IPCC_MPROC_SIGNAL_SMP2P>;
 717
 718                 qcom,local-pid = <0>;
 719                 qcom,remote-pid = <5>;
 720
 721                 smp2p_nsp0_out: master-kernel {
 722                         qcom,entry-name = "master-kernel";
 723                         #qcom,smem-state-cells = <1>;
 724                 };
 725
 726                 smp2p_nsp0_in: slave-kernel {
 727                         qcom,entry-name = "slave-kernel";
 728                         interrupt-controller;
 729                         #interrupt-cells = <2>;
 730                 };
 731         };
 732
 733         smp2p-nsp1 {
 734                 compatible = "qcom,smp2p";
 735                 qcom,smem = <617>, <616>;
 736                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
 737                                              IPCC_MPROC_SIGNAL_SMP2P
 738                                              IRQ_TYPE_EDGE_RISING>;
 739                 mboxes = <&ipcc IPCC_CLIENT_NSP1
 740                                 IPCC_MPROC_SIGNAL_SMP2P>;
 741
 742                 qcom,local-pid = <0>;
 743                 qcom,remote-pid = <12>;
 744
 745                 smp2p_nsp1_out: master-kernel {
 746                         qcom,entry-name = "master-kernel";
 747                         #qcom,smem-state-cells = <1>;
 748                 };
 749
 750                 smp2p_nsp1_in: slave-kernel {
 751                         qcom,entry-name = "slave-kernel";
 752                         interrupt-controller;
 753                         #interrupt-cells = <2>;
 754                 };
 755         };
 756
 757         soc: soc@0 {
 758                 compatible = "simple-bus";
 759                 #address-cells = <2>;
 760                 #size-cells = <2>;
 761                 ranges = <0 0 0 0 0x10 0>;
 762                 dma-ranges = <0 0 0 0 0x10 0>;
 763
 764                 gcc: clock-controller@100000 {
 765                         compatible = "qcom,gcc-sc8280xp";
 766                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 767                         #clock-cells = <1>;
 768                         #reset-cells = <1>;
 769                         #power-domain-cells = <1>;
 770                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 771                                  <&sleep_clk>,
 772                                  <0>,
 773                                  <0>,
 774                                  <0>,
 775                                  <0>,
 776                                  <0>,
 777                                  <0>,
 778                                  <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 779                                  <0>,
 780                                  <0>,
 781                                  <0>,
 782                                  <0>,
 783                                  <0>,
 784                                  <0>,
 785                                  <0>,
 786                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 787                                  <0>,
 788                                  <0>,
 789                                  <0>,
 790                                  <0>,
 791                                  <0>,
 792                                  <0>,
 793                                  <0>,
 794                                  <0>,
 795                                  <0>,
 796                                  <&pcie2a_phy>,
 797                                  <&pcie2b_phy>,
 798                                  <&pcie3a_phy>,
 799                                  <&pcie3b_phy>,
 800                                  <&pcie4_phy>,
 801                                  <0>,
 802                                  <0>;
 803                         power-domains = <&rpmhpd SC8280XP_CX>;
 804                 };
 805
 806                 ipcc: mailbox@408000 {
 807                         compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
 808                         reg = <0 0x00408000 0 0x1000>;
 809                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 810                         interrupt-controller;
 811                         #interrupt-cells = <3>;
 812                         #mbox-cells = <2>;
 813                 };
 814
 815                 qup2: geniqup@8c0000 {
 816                         compatible = "qcom,geni-se-qup";
 817                         reg = <0 0x008c0000 0 0x2000>;
 818                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 819                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 820                         clock-names = "m-ahb", "s-ahb";
 821                         iommus = <&apps_smmu 0xa3 0>;
 822
 823                         #address-cells = <2>;
 824                         #size-cells = <2>;
 825                         ranges;
 826
 827                         status = "disabled";
 828
 829                         qup2_uart17: serial@884000 {
 830                                 compatible = "qcom,geni-uart";
 831                                 reg = <0 0x00884000 0 0x4000>;
 832                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 833                                 clock-names = "se";
 834                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 835                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 836                                 power-domains = <&rpmhpd SC8280XP_CX>;
 837                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 838                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
 839                                 interconnect-names = "qup-core", "qup-config";
 840                                 status = "disabled";
 841                         };
 842
 843                         qup2_i2c5: i2c@894000 {
 844                                 compatible = "qcom,geni-i2c";
 845                                 reg = <0 0x00894000 0 0x4000>;
 846                                 clock-names = "se";
 847                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 848                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 849                                 #address-cells = <1>;
 850                                 #size-cells = <0>;
 851                                 power-domains = <&rpmhpd SC8280XP_CX>;
 852                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 853                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 854                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 855                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 856                                 status = "disabled";
 857                         };
 858                 };
 859
 860                 qup0: geniqup@9c0000 {
 861                         compatible = "qcom,geni-se-qup";
 862                         reg = <0 0x009c0000 0 0x6000>;
 863                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 864                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 865                         clock-names = "m-ahb", "s-ahb";
 866                         iommus = <&apps_smmu 0x563 0>;
 867
 868                         #address-cells = <2>;
 869                         #size-cells = <2>;
 870                         ranges;
 871
 872                         status = "disabled";
 873
 874                         qup0_i2c4: i2c@990000 {
 875                                 compatible = "qcom,geni-i2c";
 876                                 reg = <0 0x00990000 0 0x4000>;
 877                                 clock-names = "se";
 878                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 879                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 880                                 #address-cells = <1>;
 881                                 #size-cells = <0>;
 882                                 power-domains = <&rpmhpd SC8280XP_CX>;
 883                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 884                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 885                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 886                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 887                                 status = "disabled";
 888                         };
 889                 };
 890
 891                 qup1: geniqup@ac0000 {
 892                         compatible = "qcom,geni-se-qup";
 893                         reg = <0 0x00ac0000 0 0x6000>;
 894                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 895                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 896                         clock-names = "m-ahb", "s-ahb";
 897                         iommus = <&apps_smmu 0x83 0>;
 898
 899                         #address-cells = <2>;
 900                         #size-cells = <2>;
 901                         ranges;
 902
 903                         status = "disabled";
 904                 };
 905
 906                 pcie4: pcie@1c00000 {
 907                         device_type = "pci";
 908                         compatible = "qcom,pcie-sc8280xp";
 909                         reg = <0x0 0x01c00000 0x0 0x3000>,
 910                               <0x0 0x30000000 0x0 0xf1d>,
 911                               <0x0 0x30000f20 0x0 0xa8>,
 912                               <0x0 0x30001000 0x0 0x1000>,
 913                               <0x0 0x30100000 0x0 0x100000>;
 914                         reg-names = "parf", "dbi", "elbi", "atu", "config";
 915                         #address-cells = <3>;
 916                         #size-cells = <2>;
 917                         ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
 918                                  <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
 919                         bus-range = <0x00 0xff>;
 920
 921                         dma-coherent;
 922
 923                         linux,pci-domain = <6>;
 924                         num-lanes = <1>;
 925
 926                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 930                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
 931
 932                         #interrupt-cells = <1>;
 933                         interrupt-map-mask = <0 0 0 0x7>;
 934                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 935                                         <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 936                                         <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 937                                         <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 938
 939                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
 940                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
 941                                  <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
 942                                  <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
 943                                  <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
 944                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
 945                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
 946                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
 947                                  <&gcc GCC_CNOC_PCIE4_QX_CLK>;
 948                         clock-names = "aux",
 949                                       "cfg",
 950                                       "bus_master",
 951                                       "bus_slave",
 952                                       "slave_q2a",
 953                                       "ddrss_sf_tbu",
 954                                       "noc_aggr_4",
 955                                       "noc_aggr_south_sf",
 956                                       "cnoc_qx";
 957
 958                         assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
 959                         assigned-clock-rates = <19200000>;
 960
 961                         interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
 962                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
 963                         interconnect-names = "pcie-mem", "cpu-pcie";
 964
 965                         resets = <&gcc GCC_PCIE_4_BCR>;
 966                         reset-names = "pci";
 967
 968                         power-domains = <&gcc PCIE_4_GDSC>;
 969
 970                         phys = <&pcie4_phy>;
 971                         phy-names = "pciephy";
 972
 973                         status = "disabled";
 974                 };
 975
 976                 pcie4_phy: phy@1c06000 {
 977                         compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
 978                         reg = <0x0 0x01c06000 0x0 0x2000>;
 979
 980                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
 981                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
 982                                  <&gcc GCC_PCIE_4_CLKREF_CLK>,
 983                                  <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
 984                                  <&gcc GCC_PCIE_4_PIPE_CLK>,
 985                                  <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
 986                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
 987                                       "pipe", "pipediv2";
 988
 989                         assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
 990                         assigned-clock-rates = <100000000>;
 991
 992                         power-domains = <&gcc PCIE_4_GDSC>;
 993
 994                         resets = <&gcc GCC_PCIE_4_PHY_BCR>;
 995                         reset-names = "phy";
 996
 997                         #clock-cells = <0>;
 998                         clock-output-names = "pcie_4_pipe_clk";
 999
1000                         #phy-cells = <0>;
1001
1002                         status = "disabled";
1003                 };
1004
1005                 pcie3b: pcie@1c08000 {
1006                         device_type = "pci";
1007                         compatible = "qcom,pcie-sc8280xp";
1008                         reg = <0x0 0x01c08000 0x0 0x3000>,
1009                               <0x0 0x32000000 0x0 0xf1d>,
1010                               <0x0 0x32000f20 0x0 0xa8>,
1011                               <0x0 0x32001000 0x0 0x1000>,
1012                               <0x0 0x32100000 0x0 0x100000>;
1013                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1014                         #address-cells = <3>;
1015                         #size-cells = <2>;
1016                         ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
1017                                  <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1018                         bus-range = <0x00 0xff>;
1019
1020                         dma-coherent;
1021
1022                         linux,pci-domain = <5>;
1023                         num-lanes = <2>;
1024
1025                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1027                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1028                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1029                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1030
1031                         #interrupt-cells = <1>;
1032                         interrupt-map-mask = <0 0 0 0x7>;
1033                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1034                                         <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1035                                         <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1036                                         <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1037
1038                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1039                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1040                                  <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1041                                  <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1042                                  <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1043                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1044                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1045                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1046                         clock-names = "aux",
1047                                       "cfg",
1048                                       "bus_master",
1049                                       "bus_slave",
1050                                       "slave_q2a",
1051                                       "ddrss_sf_tbu",
1052                                       "noc_aggr_4",
1053                                       "noc_aggr_south_sf";
1054
1055                         assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1056                         assigned-clock-rates = <19200000>;
1057
1058                         interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1059                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1060                         interconnect-names = "pcie-mem", "cpu-pcie";
1061
1062                         resets = <&gcc GCC_PCIE_3B_BCR>;
1063                         reset-names = "pci";
1064
1065                         power-domains = <&gcc PCIE_3B_GDSC>;
1066
1067                         phys = <&pcie3b_phy>;
1068                         phy-names = "pciephy";
1069
1070                         status = "disabled";
1071                 };
1072
1073                 pcie3b_phy: phy@1c0e000 {
1074                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1075                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1076
1077                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1078                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1079                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1080                                  <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1081                                  <&gcc GCC_PCIE_3B_PIPE_CLK>,
1082                                  <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1083                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1084                                       "pipe", "pipediv2";
1085
1086                         assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1087                         assigned-clock-rates = <100000000>;
1088
1089                         power-domains = <&gcc PCIE_3B_GDSC>;
1090
1091                         resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1092                         reset-names = "phy";
1093
1094                         #clock-cells = <0>;
1095                         clock-output-names = "pcie_3b_pipe_clk";
1096
1097                         #phy-cells = <0>;
1098
1099                         status = "disabled";
1100                 };
1101
1102                 pcie3a: pcie@1c10000 {
1103                         device_type = "pci";
1104                         compatible = "qcom,pcie-sc8280xp";
1105                         reg = <0x0 0x01c10000 0x0 0x3000>,
1106                               <0x0 0x34000000 0x0 0xf1d>,
1107                               <0x0 0x34000f20 0x0 0xa8>,
1108                               <0x0 0x34001000 0x0 0x1000>,
1109                               <0x0 0x34100000 0x0 0x100000>;
1110                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1111                         #address-cells = <3>;
1112                         #size-cells = <2>;
1113                         ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
1114                                  <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1115                         bus-range = <0x00 0xff>;
1116
1117                         dma-coherent;
1118
1119                         linux,pci-domain = <4>;
1120                         num-lanes = <4>;
1121
1122                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1123                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1124                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1125                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1126                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1127
1128                         #interrupt-cells = <1>;
1129                         interrupt-map-mask = <0 0 0 0x7>;
1130                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1131                                         <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1132                                         <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1133                                         <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1134
1135                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1136                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1137                                  <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1138                                  <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1139                                  <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1140                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1141                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1142                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1143                         clock-names = "aux",
1144                                       "cfg",
1145                                       "bus_master",
1146                                       "bus_slave",
1147                                       "slave_q2a",
1148                                       "ddrss_sf_tbu",
1149                                       "noc_aggr_4",
1150                                       "noc_aggr_south_sf";
1151
1152                         assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1153                         assigned-clock-rates = <19200000>;
1154
1155                         interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1156                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1157                         interconnect-names = "pcie-mem", "cpu-pcie";
1158
1159                         resets = <&gcc GCC_PCIE_3A_BCR>;
1160                         reset-names = "pci";
1161
1162                         power-domains = <&gcc PCIE_3A_GDSC>;
1163
1164                         phys = <&pcie3a_phy>;
1165                         phy-names = "pciephy";
1166
1167                         status = "disabled";
1168                 };
1169
1170                 pcie3a_phy: phy@1c14000 {
1171                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1172                         reg = <0x0 0x01c14000 0x0 0x2000>,
1173                               <0x0 0x01c16000 0x0 0x2000>;
1174
1175                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1176                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1177                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1178                                  <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1179                                  <&gcc GCC_PCIE_3A_PIPE_CLK>,
1180                                  <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1181                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1182                                       "pipe", "pipediv2";
1183
1184                         assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1185                         assigned-clock-rates = <100000000>;
1186
1187                         power-domains = <&gcc PCIE_3A_GDSC>;
1188
1189                         resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
1190                         reset-names = "phy";
1191
1192                         qcom,4ln-config-sel = <&tcsr 0xa044 1>;
1193
1194                         #clock-cells = <0>;
1195                         clock-output-names = "pcie_3a_pipe_clk";
1196
1197                         #phy-cells = <0>;
1198
1199                         status = "disabled";
1200                 };
1201
1202                 pcie2b: pcie@1c18000 {
1203                         device_type = "pci";
1204                         compatible = "qcom,pcie-sc8280xp";
1205                         reg = <0x0 0x01c18000 0x0 0x3000>,
1206                               <0x0 0x38000000 0x0 0xf1d>,
1207                               <0x0 0x38000f20 0x0 0xa8>,
1208                               <0x0 0x38001000 0x0 0x1000>,
1209                               <0x0 0x38100000 0x0 0x100000>;
1210                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1211                         #address-cells = <3>;
1212                         #size-cells = <2>;
1213                         ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
1214                                  <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
1215                         bus-range = <0x00 0xff>;
1216
1217                         dma-coherent;
1218
1219                         linux,pci-domain = <3>;
1220                         num-lanes = <2>;
1221
1222                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1225                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1226                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1227
1228                         #interrupt-cells = <1>;
1229                         interrupt-map-mask = <0 0 0 0x7>;
1230                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
1231                                         <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1232                                         <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1233                                         <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1234
1235                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1236                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1237                                  <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
1238                                  <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
1239                                  <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
1240                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1241                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1242                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1243                         clock-names = "aux",
1244                                       "cfg",
1245                                       "bus_master",
1246                                       "bus_slave",
1247                                       "slave_q2a",
1248                                       "ddrss_sf_tbu",
1249                                       "noc_aggr_4",
1250                                       "noc_aggr_south_sf";
1251
1252                         assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
1253                         assigned-clock-rates = <19200000>;
1254
1255                         interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
1256                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
1257                         interconnect-names = "pcie-mem", "cpu-pcie";
1258
1259                         resets = <&gcc GCC_PCIE_2B_BCR>;
1260                         reset-names = "pci";
1261
1262                         power-domains = <&gcc PCIE_2B_GDSC>;
1263
1264                         phys = <&pcie2b_phy>;
1265                         phy-names = "pciephy";
1266
1267                         status = "disabled";
1268                 };
1269
1270                 pcie2b_phy: phy@1c1e000 {
1271                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1272                         reg = <0x0 0x01c1e000 0x0 0x2000>;
1273
1274                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1275                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1276                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1277                                  <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
1278                                  <&gcc GCC_PCIE_2B_PIPE_CLK>,
1279                                  <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
1280                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1281                                       "pipe", "pipediv2";
1282
1283                         assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
1284                         assigned-clock-rates = <100000000>;
1285
1286                         power-domains = <&gcc PCIE_2B_GDSC>;
1287
1288                         resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
1289                         reset-names = "phy";
1290
1291                         #clock-cells = <0>;
1292                         clock-output-names = "pcie_2b_pipe_clk";
1293
1294                         #phy-cells = <0>;
1295
1296                         status = "disabled";
1297                 };
1298
1299                 pcie2a: pcie@1c20000 {
1300                         device_type = "pci";
1301                         compatible = "qcom,pcie-sc8280xp";
1302                         reg = <0x0 0x01c20000 0x0 0x3000>,
1303                               <0x0 0x3c000000 0x0 0xf1d>,
1304                               <0x0 0x3c000f20 0x0 0xa8>,
1305                               <0x0 0x3c001000 0x0 0x1000>,
1306                               <0x0 0x3c100000 0x0 0x100000>;
1307                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1308                         #address-cells = <3>;
1309                         #size-cells = <2>;
1310                         ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
1311                                  <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
1312                         bus-range = <0x00 0xff>;
1313
1314                         dma-coherent;
1315
1316                         linux,pci-domain = <2>;
1317                         num-lanes = <4>;
1318
1319                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1320                                      <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
1321                                      <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
1322                                      <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
1323                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1324
1325                         #interrupt-cells = <1>;
1326                         interrupt-map-mask = <0 0 0 0x7>;
1327                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
1328                                         <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
1329                                         <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
1330                                         <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
1331
1332                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1333                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1334                                  <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
1335                                  <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
1336                                  <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
1337                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1338                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1339                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1340                         clock-names = "aux",
1341                                       "cfg",
1342                                       "bus_master",
1343                                       "bus_slave",
1344                                       "slave_q2a",
1345                                       "ddrss_sf_tbu",
1346                                       "noc_aggr_4",
1347                                       "noc_aggr_south_sf";
1348
1349                         assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
1350                         assigned-clock-rates = <19200000>;
1351
1352                         interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
1353                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
1354                         interconnect-names = "pcie-mem", "cpu-pcie";
1355
1356                         resets = <&gcc GCC_PCIE_2A_BCR>;
1357                         reset-names = "pci";
1358
1359                         power-domains = <&gcc PCIE_2A_GDSC>;
1360
1361                         phys = <&pcie2a_phy>;
1362                         phy-names = "pciephy";
1363
1364                         status = "disabled";
1365                 };
1366
1367                 pcie2a_phy: phy@1c24000 {
1368                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1369                         reg = <0x0 0x01c24000 0x0 0x2000>,
1370                               <0x0 0x01c26000 0x0 0x2000>;
1371
1372                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1373                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1374                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1375                                  <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
1376                                  <&gcc GCC_PCIE_2A_PIPE_CLK>,
1377                                  <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
1378                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1379                                       "pipe", "pipediv2";
1380
1381                         assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
1382                         assigned-clock-rates = <100000000>;
1383
1384                         power-domains = <&gcc PCIE_2A_GDSC>;
1385
1386                         resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
1387                         reset-names = "phy";
1388
1389                         qcom,4ln-config-sel = <&tcsr 0xa044 0>;
1390
1391                         #clock-cells = <0>;
1392                         clock-output-names = "pcie_2a_pipe_clk";
1393
1394                         #phy-cells = <0>;
1395
1396                         status = "disabled";
1397                 };
1398
1399                 ufs_mem_hc: ufs@1d84000 {
1400                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1401                                      "jedec,ufs-2.0";
1402                         reg = <0 0x01d84000 0 0x3000>;
1403                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1404                         phys = <&ufs_mem_phy>;
1405                         phy-names = "ufsphy";
1406                         lanes-per-direction = <2>;
1407                         #reset-cells = <1>;
1408                         resets = <&gcc GCC_UFS_PHY_BCR>;
1409                         reset-names = "rst";
1410
1411                         power-domains = <&gcc UFS_PHY_GDSC>;
1412                         required-opps = <&rpmhpd_opp_nom>;
1413
1414                         iommus = <&apps_smmu 0xe0 0x0>;
1415                         dma-coherent;
1416
1417                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1418                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1419                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1420                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1421                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
1422                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1423                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1424                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1425                         clock-names = "core_clk",
1426                                       "bus_aggr_clk",
1427                                       "iface_clk",
1428                                       "core_clk_unipro",
1429                                       "ref_clk",
1430                                       "tx_lane0_sync_clk",
1431                                       "rx_lane0_sync_clk",
1432                                       "rx_lane1_sync_clk";
1433                         freq-table-hz = <75000000 300000000>,
1434                                         <0 0>,
1435                                         <0 0>,
1436                                         <75000000 300000000>,
1437                                         <0 0>,
1438                                         <0 0>,
1439                                         <0 0>,
1440                                         <0 0>;
1441                         status = "disabled";
1442                 };
1443
1444                 ufs_mem_phy: phy@1d87000 {
1445                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
1446                         reg = <0 0x01d87000 0 0x1000>;
1447
1448                         clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
1449                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1450                         clock-names = "ref", "ref_aux";
1451
1452                         power-domains = <&gcc UFS_PHY_GDSC>;
1453
1454                         resets = <&ufs_mem_hc 0>;
1455                         reset-names = "ufsphy";
1456
1457                         #phy-cells = <0>;
1458
1459                         status = "disabled";
1460                 };
1461
1462                 ufs_card_hc: ufs@1da4000 {
1463                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1464                                      "jedec,ufs-2.0";
1465                         reg = <0 0x01da4000 0 0x3000>;
1466                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1467                         phys = <&ufs_card_phy>;
1468                         phy-names = "ufsphy";
1469                         lanes-per-direction = <2>;
1470                         #reset-cells = <1>;
1471                         resets = <&gcc GCC_UFS_CARD_BCR>;
1472                         reset-names = "rst";
1473
1474                         power-domains = <&gcc UFS_CARD_GDSC>;
1475
1476                         iommus = <&apps_smmu 0x4a0 0x0>;
1477                         dma-coherent;
1478
1479                         clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
1480                                  <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
1481                                  <&gcc GCC_UFS_CARD_AHB_CLK>,
1482                                  <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
1483                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
1484                                  <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
1485                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
1486                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
1487                         clock-names = "core_clk",
1488                                       "bus_aggr_clk",
1489                                       "iface_clk",
1490                                       "core_clk_unipro",
1491                                       "ref_clk",
1492                                       "tx_lane0_sync_clk",
1493                                       "rx_lane0_sync_clk",
1494                                       "rx_lane1_sync_clk";
1495                         freq-table-hz = <75000000 300000000>,
1496                                         <0 0>,
1497                                         <0 0>,
1498                                         <75000000 300000000>,
1499                                         <0 0>,
1500                                         <0 0>,
1501                                         <0 0>,
1502                                         <0 0>;
1503                         status = "disabled";
1504                 };
1505
1506                 ufs_card_phy: phy@1da7000 {
1507                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
1508                         reg = <0 0x01da7000 0 0x1000>;
1509
1510                         clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
1511                                  <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
1512                         clock-names = "ref", "ref_aux";
1513
1514                         power-domains = <&gcc UFS_CARD_GDSC>;
1515
1516                         resets = <&ufs_card_hc 0>;
1517                         reset-names = "ufsphy";
1518
1519                         #phy-cells = <0>;
1520
1521                         status = "disabled";
1522                 };
1523
1524                 tcsr_mutex: hwlock@1f40000 {
1525                         compatible = "qcom,tcsr-mutex";
1526                         reg = <0x0 0x01f40000 0x0 0x20000>;
1527                         #hwlock-cells = <1>;
1528                 };
1529
1530                 tcsr: syscon@1fc0000 {
1531                         compatible = "qcom,sc8280xp-tcsr", "syscon";
1532                         reg = <0x0 0x01fc0000 0x0 0x30000>;
1533                 };
1534
1535                 usb_0_hsphy: phy@88e5000 {
1536                         compatible = "qcom,sc8280xp-usb-hs-phy",
1537                                      "qcom,usb-snps-hs-5nm-phy";
1538                         reg = <0 0x088e5000 0 0x400>;
1539                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1540                         clock-names = "ref";
1541                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1542
1543                         #phy-cells = <0>;
1544
1545                         status = "disabled";
1546                 };
1547
1548                 usb_2_hsphy0: phy@88e7000 {
1549                         compatible = "qcom,sc8280xp-usb-hs-phy",
1550                                      "qcom,usb-snps-hs-5nm-phy";
1551                         reg = <0 0x088e7000 0 0x400>;
1552                         clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1553                         clock-names = "ref";
1554                         resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1555
1556                         #phy-cells = <0>;
1557
1558                         status = "disabled";
1559                 };
1560
1561                 usb_2_hsphy1: phy@88e8000 {
1562                         compatible = "qcom,sc8280xp-usb-hs-phy",
1563                                      "qcom,usb-snps-hs-5nm-phy";
1564                         reg = <0 0x088e8000 0 0x400>;
1565                         clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1566                         clock-names = "ref";
1567                         resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1568
1569                         #phy-cells = <0>;
1570
1571                         status = "disabled";
1572                 };
1573
1574                 usb_2_hsphy2: phy@88e9000 {
1575                         compatible = "qcom,sc8280xp-usb-hs-phy",
1576                                      "qcom,usb-snps-hs-5nm-phy";
1577                         reg = <0 0x088e9000 0 0x400>;
1578                         clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1579                         clock-names = "ref";
1580                         resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1581
1582                         #phy-cells = <0>;
1583
1584                         status = "disabled";
1585                 };
1586
1587                 usb_2_hsphy3: phy@88ea000 {
1588                         compatible = "qcom,sc8280xp-usb-hs-phy",
1589                                      "qcom,usb-snps-hs-5nm-phy";
1590                         reg = <0 0x088ea000 0 0x400>;
1591                         clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1592                         clock-names = "ref";
1593                         resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1594
1595                         #phy-cells = <0>;
1596
1597                         status = "disabled";
1598                 };
1599
1600                 usb_2_qmpphy0: phy@88ef000 {
1601                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1602                         reg = <0 0x088ef000 0 0x2000>;
1603
1604                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1605                                  <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1606                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1607                                  <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1608                         clock-names = "aux", "ref", "com_aux", "pipe";
1609
1610                         resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1611                                  <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1612                         reset-names = "phy", "phy_phy";
1613
1614                         power-domains = <&gcc USB30_MP_GDSC>;
1615
1616                         #clock-cells = <0>;
1617                         clock-output-names = "usb2_phy0_pipe_clk";
1618
1619                         #phy-cells = <0>;
1620
1621                         status = "disabled";
1622                 };
1623
1624                 usb_2_qmpphy1: phy@88f1000 {
1625                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1626                         reg = <0 0x088f1000 0 0x2000>;
1627
1628                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1629                                  <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1630                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1631                                  <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1632                         clock-names = "aux", "ref", "com_aux", "pipe";
1633
1634                         resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1635                                  <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1636                         reset-names = "phy", "phy_phy";
1637
1638                         power-domains = <&gcc USB30_MP_GDSC>;
1639
1640                         #clock-cells = <0>;
1641                         clock-output-names = "usb2_phy1_pipe_clk";
1642
1643                         #phy-cells = <0>;
1644
1645                         status = "disabled";
1646                 };
1647
1648                 remoteproc_adsp: remoteproc@3000000 {
1649                         compatible = "qcom,sc8280xp-adsp-pas";
1650                         reg = <0 0x03000000 0 0x100>;
1651
1652                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1653                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1654                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1655                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1656                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1657                                               <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1658                         interrupt-names = "wdog", "fatal", "ready",
1659                                           "handover", "stop-ack", "shutdown-ack";
1660
1661                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1662                         clock-names = "xo";
1663
1664                         power-domains = <&rpmhpd SC8280XP_LCX>,
1665                                         <&rpmhpd SC8280XP_LMX>;
1666                         power-domain-names = "lcx", "lmx";
1667
1668                         memory-region = <&pil_adsp_mem>;
1669
1670                         qcom,qmp = <&aoss_qmp>;
1671
1672                         qcom,smem-states = <&smp2p_adsp_out 0>;
1673                         qcom,smem-state-names = "stop";
1674
1675                         status = "disabled";
1676
1677                         remoteproc_adsp_glink: glink-edge {
1678                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1679                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1680                                                              IRQ_TYPE_EDGE_RISING>;
1681                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
1682                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1683
1684                                 label = "lpass";
1685                                 qcom,remote-pid = <2>;
1686
1687                                 gpr {
1688                                         compatible = "qcom,gpr";
1689                                         qcom,glink-channels = "adsp_apps";
1690                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
1691                                         qcom,intents = <512 20>;
1692                                         #address-cells = <1>;
1693                                         #size-cells = <0>;
1694
1695                                         q6apm: service@1 {
1696                                                 compatible = "qcom,q6apm";
1697                                                 reg = <GPR_APM_MODULE_IID>;
1698                                                 #sound-dai-cells = <0>;
1699                                                 qcom,protection-domain = "avs/audio",
1700                                                                          "msm/adsp/audio_pd";
1701                                                 q6apmdai: dais {
1702                                                         compatible = "qcom,q6apm-dais";
1703                                                         iommus = <&apps_smmu 0x0c01 0x0>;
1704                                                 };
1705
1706                                                 q6apmbedai: bedais {
1707                                                         compatible = "qcom,q6apm-lpass-dais";
1708                                                         #sound-dai-cells = <1>;
1709                                                 };
1710                                         };
1711
1712                                         q6prm: service@2 {
1713                                                 compatible = "qcom,q6prm";
1714                                                 reg = <GPR_PRM_MODULE_IID>;
1715                                                 qcom,protection-domain = "avs/audio",
1716                                                                          "msm/adsp/audio_pd";
1717                                                 q6prmcc: clock-controller {
1718                                                         compatible = "qcom,q6prm-lpass-clocks";
1719                                                         #clock-cells = <2>;
1720                                                 };
1721                                         };
1722                                 };
1723                         };
1724                 };
1725
1726                 rxmacro: rxmacro@3200000 {
1727                         compatible = "qcom,sc8280xp-lpass-rx-macro";
1728                         reg = <0 0x03200000 0 0x1000>;
1729                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1730                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1731                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1732                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1733                                  <&vamacro>;
1734                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
1735                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1736                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1737                         assigned-clock-rates = <19200000>, <19200000>;
1738
1739                         clock-output-names = "mclk";
1740                         #clock-cells = <0>;
1741                         #sound-dai-cells = <1>;
1742
1743                         pinctrl-names = "default";
1744                         pinctrl-0 = <&rx_swr_default>;
1745
1746                         status = "disabled";
1747                 };
1748
1749                 /* RX */
1750                 swr1: soundwire-controller@3210000 {
1751                         compatible = "qcom,soundwire-v1.6.0";
1752                         reg = <0 0x03210000 0 0x2000>;
1753                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1754                         clocks = <&rxmacro>;
1755                         clock-names = "iface";
1756                         label = "RX";
1757
1758                         qcom,din-ports = <0>;
1759                         qcom,dout-ports = <5>;
1760
1761                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
1762                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
1763                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
1764                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
1765                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
1766                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
1767                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
1768                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
1769                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
1770
1771                         #sound-dai-cells = <1>;
1772                         #address-cells = <2>;
1773                         #size-cells = <0>;
1774
1775                         status = "disabled";
1776                 };
1777
1778                 txmacro: txmacro@3220000 {
1779                         compatible = "qcom,sc8280xp-lpass-tx-macro";
1780                         reg = <0 0x03220000 0 0x1000>;
1781                         pinctrl-names = "default";
1782                         pinctrl-0 = <&tx_swr_default>;
1783                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1784                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1785                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1786                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1787                                  <&vamacro>;
1788
1789                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
1790                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1791                                           <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1792                         assigned-clock-rates = <19200000>, <19200000>;
1793                         clock-output-names = "mclk";
1794
1795                         #clock-cells = <0>;
1796                         #sound-dai-cells = <1>;
1797
1798                         status = "disabled";
1799                 };
1800
1801                 wsamacro: codec@3240000 {
1802                         compatible = "qcom,sc8280xp-lpass-wsa-macro";
1803                         reg = <0 0x03240000 0 0x1000>;
1804                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1805                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1806                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1807                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1808                                  <&vamacro>;
1809                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
1810                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1811                                           <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1812                         assigned-clock-rates = <19200000>, <19200000>;
1813
1814                         #clock-cells = <0>;
1815                         clock-output-names = "mclk";
1816                         #sound-dai-cells = <1>;
1817
1818                         pinctrl-names = "default";
1819                         pinctrl-0 = <&wsa_swr_default>;
1820
1821                         status = "disabled";
1822                 };
1823
1824                 /* WSA */
1825                 swr0: soundwire-controller@3250000 {
1826                         reg = <0 0x03250000 0 0x2000>;
1827                         compatible = "qcom,soundwire-v1.6.0";
1828                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1829                         clocks = <&wsamacro>;
1830                         clock-names = "iface";
1831
1832                         qcom,din-ports = <2>;
1833                         qcom,dout-ports = <6>;
1834
1835                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1836                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1837                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1838                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
1839                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
1840                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
1841                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
1842                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
1843                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
1844
1845                         #sound-dai-cells = <1>;
1846                         #address-cells = <2>;
1847                         #size-cells = <0>;
1848
1849                         status = "disabled";
1850                 };
1851
1852                 /* TX */
1853                 swr2: soundwire-controller@3330000 {
1854                         compatible = "qcom,soundwire-v1.6.0";
1855                         reg = <0 0x03330000 0 0x2000>;
1856                         interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
1857                                               <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
1858                         interrupt-names = "core", "wake";
1859
1860                         clocks = <&vamacro>;
1861                         clock-names = "iface";
1862                         label = "TX";
1863                         #sound-dai-cells = <1>;
1864                         #address-cells = <2>;
1865                         #size-cells = <0>;
1866
1867                         qcom,din-ports = <4>;
1868                         qcom,dout-ports = <0>;
1869                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x03 0x03 0x03>;
1870                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02 0x01>;
1871                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
1872                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
1873                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
1874                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
1875                         qcom,ports-word-length =        /bits/ 8 <0xff 0x00 0xff 0xff>;
1876                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
1877                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00 0x00>;
1878
1879                         status = "disabled";
1880                 };
1881
1882                 vamacro: codec@3370000 {
1883                         compatible = "qcom,sc8280xp-lpass-va-macro";
1884                         reg = <0 0x03370000 0 0x1000>;
1885                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1886                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1887                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1888                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1889                         clock-names = "mclk", "macro", "dcodec", "npl";
1890                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1891                         assigned-clock-rates = <19200000>;
1892
1893                         #clock-cells = <0>;
1894                         clock-output-names = "fsgen";
1895                         #sound-dai-cells = <1>;
1896
1897                         status = "disabled";
1898                 };
1899
1900                 lpass_tlmm: pinctrl@33c0000 {
1901                         compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
1902                         reg = <0 0x33c0000 0x0 0x20000>,
1903                               <0 0x3550000 0x0 0x10000>;
1904                         gpio-controller;
1905                         #gpio-cells = <2>;
1906                         gpio-ranges = <&lpass_tlmm 0 0 18>;
1907
1908                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1909                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1910                         clock-names = "core", "audio";
1911
1912                         status = "disabled";
1913
1914                         tx_swr_default: tx-swr-default-state {
1915                                 clk-pins {
1916                                         pins = "gpio0";
1917                                         function = "swr_tx_clk";
1918                                         drive-strength = <2>;
1919                                         slew-rate = <1>;
1920                                         bias-disable;
1921                                 };
1922
1923                                 data-pins {
1924                                         pins = "gpio1", "gpio2";
1925                                         function = "swr_tx_data";
1926                                         drive-strength = <2>;
1927                                         slew-rate = <1>;
1928                                         bias-bus-hold;
1929                                 };
1930                         };
1931
1932                         rx_swr_default: rx-swr-default-state {
1933                                 clk-pins {
1934                                         pins = "gpio3";
1935                                         function = "swr_rx_clk";
1936                                         drive-strength = <2>;
1937                                         slew-rate = <1>;
1938                                         bias-disable;
1939                                 };
1940
1941                                 data-pins {
1942                                         pins = "gpio4", "gpio5";
1943                                         function = "swr_rx_data";
1944                                         drive-strength = <2>;
1945                                         slew-rate = <1>;
1946                                         bias-bus-hold;
1947                                 };
1948                         };
1949
1950                         dmic01_default: dmic01-default-state {
1951                                 clk-pins {
1952                                         pins = "gpio6";
1953                                         function = "dmic1_clk";
1954                                         drive-strength = <8>;
1955                                         output-high;
1956                                 };
1957
1958                                 data-pins {
1959                                         pins = "gpio7";
1960                                         function = "dmic1_data";
1961                                         drive-strength = <8>;
1962                                         input-enable;
1963                                 };
1964                         };
1965
1966                         dmic01_sleep: dmic01-sleep-state {
1967                                 clk-pins {
1968                                         pins = "gpio6";
1969                                         function = "dmic1_clk";
1970                                         drive-strength = <2>;
1971                                         bias-disable;
1972                                         output-low;
1973                                 };
1974
1975                                 data-pins {
1976                                         pins = "gpio7";
1977                                         function = "dmic1_data";
1978                                         drive-strength = <2>;
1979                                         bias-pull-down;
1980                                         input-enable;
1981                                 };
1982                         };
1983
1984                         dmic02_default: dmic02-default-state {
1985                                 clk-pins {
1986                                         pins = "gpio8";
1987                                         function = "dmic2_clk";
1988                                         drive-strength = <8>;
1989                                         output-high;
1990                                 };
1991
1992                                 data-pins {
1993                                         pins = "gpio9";
1994                                         function = "dmic2_data";
1995                                         drive-strength = <8>;
1996                                         input-enable;
1997                                 };
1998                         };
1999
2000                         dmic02_sleep: dmic02-sleep-state {
2001                                 clk-pins {
2002                                         pins = "gpio8";
2003                                         function = "dmic2_clk";
2004                                         drive-strength = <2>;
2005                                         bias-disable;
2006                                         output-low;
2007                                 };
2008
2009                                 data-pins {
2010                                         pins = "gpio9";
2011                                         function = "dmic2_data";
2012                                         drive-strength = <2>;
2013                                         bias-pull-down;
2014                                         input-enable;
2015                                 };
2016                         };
2017
2018                         wsa_swr_default: wsa-swr-default-state {
2019                                 clk-pins {
2020                                         pins = "gpio10";
2021                                         function = "wsa_swr_clk";
2022                                         drive-strength = <2>;
2023                                         slew-rate = <1>;
2024                                         bias-disable;
2025                                 };
2026
2027                                 data-pins {
2028                                         pins = "gpio11";
2029                                         function = "wsa_swr_data";
2030                                         drive-strength = <2>;
2031                                         slew-rate = <1>;
2032                                         bias-bus-hold;
2033
2034                                 };
2035                         };
2036
2037                         wsa2_swr_default: wsa2-swr-default-state {
2038                                 clk-pins {
2039                                         pins = "gpio15";
2040                                         function = "wsa2_swr_clk";
2041                                         drive-strength = <2>;
2042                                         slew-rate = <1>;
2043                                         bias-disable;
2044                                 };
2045
2046                                 data-pins {
2047                                         pins = "gpio16";
2048                                         function = "wsa2_swr_data";
2049                                         drive-strength = <2>;
2050                                         slew-rate = <1>;
2051                                         bias-bus-hold;
2052                                 };
2053                         };
2054                 };
2055
2056                 usb_0_qmpphy: phy@88eb000 {
2057                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
2058                         reg = <0 0x088eb000 0 0x4000>;
2059
2060                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2061                                  <&gcc GCC_USB4_EUD_CLKREF_CLK>,
2062                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2063                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2064                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2065
2066                         power-domains = <&gcc USB30_PRIM_GDSC>;
2067
2068                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2069                                  <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
2070                         reset-names = "phy", "common";
2071
2072                         #clock-cells = <1>;
2073                         #phy-cells = <1>;
2074
2075                         status = "disabled";
2076                 };
2077
2078                 usb_1_hsphy: phy@8902000 {
2079                         compatible = "qcom,sc8280xp-usb-hs-phy",
2080                                      "qcom,usb-snps-hs-5nm-phy";
2081                         reg = <0 0x08902000 0 0x400>;
2082                         #phy-cells = <0>;
2083
2084                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2085                         clock-names = "ref";
2086
2087                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2088
2089                         status = "disabled";
2090                 };
2091
2092                 usb_1_qmpphy: phy@8903000 {
2093                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
2094                         reg = <0 0x08903000 0 0x4000>;
2095
2096                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2097                                  <&gcc GCC_USB4_CLKREF_CLK>,
2098                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2099                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2100                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2101
2102                         power-domains = <&gcc USB30_SEC_GDSC>;
2103
2104                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2105                                  <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
2106                         reset-names = "phy", "common";
2107
2108                         #clock-cells = <1>;
2109                         #phy-cells = <1>;
2110
2111                         status = "disabled";
2112                 };
2113
2114                 mdss1_dp0_phy: phy@8909a00 {
2115                         compatible = "qcom,sc8280xp-dp-phy";
2116                         reg = <0 0x08909a00 0 0x19c>,
2117                               <0 0x08909200 0 0xec>,
2118                               <0 0x08909600 0 0xec>,
2119                               <0 0x08909000 0 0x1c8>;
2120
2121                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
2122                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
2123                         clock-names = "aux", "cfg_ahb";
2124                         power-domains = <&rpmhpd SC8280XP_MX>;
2125
2126                         #clock-cells = <1>;
2127                         #phy-cells = <0>;
2128
2129                         status = "disabled";
2130                 };
2131
2132                 mdss1_dp1_phy: phy@890ca00 {
2133                         compatible = "qcom,sc8280xp-dp-phy";
2134                         reg = <0 0x0890ca00 0 0x19c>,
2135                               <0 0x0890c200 0 0xec>,
2136                               <0 0x0890c600 0 0xec>,
2137                               <0 0x0890c000 0 0x1c8>;
2138
2139                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
2140                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
2141                         clock-names = "aux", "cfg_ahb";
2142                         power-domains = <&rpmhpd SC8280XP_MX>;
2143
2144                         #clock-cells = <1>;
2145                         #phy-cells = <0>;
2146
2147                         status = "disabled";
2148                 };
2149
2150                 pmu@9091000 {
2151                         compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2152                         reg = <0 0x9091000 0 0x1000>;
2153
2154                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2155
2156                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
2157
2158                         operating-points-v2 = <&llcc_bwmon_opp_table>;
2159
2160                         llcc_bwmon_opp_table: opp-table {
2161                                 compatible = "operating-points-v2";
2162
2163                                 opp-0 {
2164                                         opp-peak-kBps = <762000>;
2165                                 };
2166                                 opp-1 {
2167                                         opp-peak-kBps = <1720000>;
2168                                 };
2169                                 opp-2 {
2170                                         opp-peak-kBps = <2086000>;
2171                                 };
2172                                 opp-3 {
2173                                         opp-peak-kBps = <2597000>;
2174                                 };
2175                                 opp-4 {
2176                                         opp-peak-kBps = <2929000>;
2177                                 };
2178                                 opp-5 {
2179                                         opp-peak-kBps = <3879000>;
2180                                 };
2181                                 opp-6 {
2182                                         opp-peak-kBps = <5161000>;
2183                                 };
2184                                 opp-7 {
2185                                         opp-peak-kBps = <5931000>;
2186                                 };
2187                                 opp-8 {
2188                                         opp-peak-kBps = <6515000>;
2189                                 };
2190                                 opp-9 {
2191                                         opp-peak-kBps = <7980000>;
2192                                 };
2193                                 opp-10 {
2194                                         opp-peak-kBps = <8136000>;
2195                                 };
2196                                 opp-11 {
2197                                         opp-peak-kBps = <10437000>;
2198                                 };
2199                                 opp-12 {
2200                                         opp-peak-kBps = <12191000>;
2201                                 };
2202                         };
2203                 };
2204
2205                 pmu@90b6400 {
2206                         compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
2207                         reg = <0 0x090b6400 0 0x600>;
2208
2209                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2210
2211                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
2212                         operating-points-v2 = <&cpu_bwmon_opp_table>;
2213
2214                         cpu_bwmon_opp_table: opp-table {
2215                                 compatible = "operating-points-v2";
2216
2217                                 opp-0 {
2218                                         opp-peak-kBps = <2288000>;
2219                                 };
2220                                 opp-1 {
2221                                         opp-peak-kBps = <4577000>;
2222                                 };
2223                                 opp-2 {
2224                                         opp-peak-kBps = <7110000>;
2225                                 };
2226                                 opp-3 {
2227                                         opp-peak-kBps = <9155000>;
2228                                 };
2229                                 opp-4 {
2230                                         opp-peak-kBps = <12298000>;
2231                                 };
2232                                 opp-5 {
2233                                         opp-peak-kBps = <14236000>;
2234                                 };
2235                                 opp-6 {
2236                                         opp-peak-kBps = <15258001>;
2237                                 };
2238                         };
2239                 };
2240
2241                 system-cache-controller@9200000 {
2242                         compatible = "qcom,sc8280xp-llcc";
2243                         reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
2244                         reg-names = "llcc_base", "llcc_broadcast_base";
2245                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2246                 };
2247
2248                 usb_0: usb@a6f8800 {
2249                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
2250                         reg = <0 0x0a6f8800 0 0x400>;
2251                         #address-cells = <2>;
2252                         #size-cells = <2>;
2253                         ranges;
2254
2255                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2256                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2257                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2258                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2259                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2260                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
2261                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
2262                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
2263                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
2264                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
2265                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
2266
2267                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2268                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2269                         assigned-clock-rates = <19200000>, <200000000>;
2270
2271                         interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
2272                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2273                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2274                                               <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
2275                         interrupt-names = "pwr_event",
2276                                           "dp_hs_phy_irq",
2277                                           "dm_hs_phy_irq",
2278                                           "ss_phy_irq";
2279
2280                         power-domains = <&gcc USB30_PRIM_GDSC>;
2281                         required-opps = <&rpmhpd_opp_nom>;
2282
2283                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2284
2285                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2286                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2287                         interconnect-names = "usb-ddr", "apps-usb";
2288
2289                         wakeup-source;
2290
2291                         status = "disabled";
2292
2293                         usb_0_dwc3: usb@a600000 {
2294                                 compatible = "snps,dwc3";
2295                                 reg = <0 0x0a600000 0 0xcd00>;
2296                                 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
2297                                 iommus = <&apps_smmu 0x820 0x0>;
2298                                 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
2299                                 phy-names = "usb2-phy", "usb3-phy";
2300                         };
2301                 };
2302
2303                 usb_1: usb@a8f8800 {
2304                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
2305                         reg = <0 0x0a8f8800 0 0x400>;
2306                         #address-cells = <2>;
2307                         #size-cells = <2>;
2308                         ranges;
2309
2310                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2311                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2312                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2313                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2314                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2315                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
2316                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
2317                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
2318                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
2319                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
2320                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
2321
2322                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2323                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2324                         assigned-clock-rates = <19200000>, <200000000>;
2325
2326                         interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
2327                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2328                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2329                                               <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
2330                         interrupt-names = "pwr_event",
2331                                           "dp_hs_phy_irq",
2332                                           "dm_hs_phy_irq",
2333                                           "ss_phy_irq";
2334
2335                         power-domains = <&gcc USB30_SEC_GDSC>;
2336                         required-opps = <&rpmhpd_opp_nom>;
2337
2338                         resets = <&gcc GCC_USB30_SEC_BCR>;
2339
2340                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2341                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2342                         interconnect-names = "usb-ddr", "apps-usb";
2343
2344                         wakeup-source;
2345
2346                         status = "disabled";
2347
2348                         usb_1_dwc3: usb@a800000 {
2349                                 compatible = "snps,dwc3";
2350                                 reg = <0 0x0a800000 0 0xcd00>;
2351                                 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
2352                                 iommus = <&apps_smmu 0x860 0x0>;
2353                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
2354                                 phy-names = "usb2-phy", "usb3-phy";
2355                         };
2356                 };
2357
2358                 mdss0: display-subsystem@ae00000 {
2359                         compatible = "qcom,sc8280xp-mdss";
2360                         reg = <0 0x0ae00000 0 0x1000>;
2361                         reg-names = "mdss";
2362
2363                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2364                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
2365                                  <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
2366                         clock-names = "iface",
2367                                       "ahb",
2368                                       "core";
2369                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2370                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2371                                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2372                         interconnect-names = "mdp0-mem", "mdp1-mem";
2373                         iommus = <&apps_smmu 0x1000 0x402>;
2374                         power-domains = <&dispcc0 MDSS_GDSC>;
2375                         resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
2376
2377                         interrupt-controller;
2378                         #interrupt-cells = <1>;
2379                         #address-cells = <2>;
2380                         #size-cells = <2>;
2381                         ranges;
2382
2383                         status = "disabled";
2384
2385                         mdss0_mdp: display-controller@ae01000 {
2386                                 compatible = "qcom,sc8280xp-dpu";
2387                                 reg = <0 0x0ae01000 0 0x8f000>,
2388                                       <0 0x0aeb0000 0 0x2008>;
2389                                 reg-names = "mdp", "vbif";
2390
2391                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2392                                          <&gcc GCC_DISP_SF_AXI_CLK>,
2393                                          <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
2394                                          <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
2395                                          <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
2396                                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
2397                                 clock-names = "bus",
2398                                               "nrt_bus",
2399                                               "iface",
2400                                               "lut",
2401                                               "core",
2402                                               "vsync";
2403                                 interrupt-parent = <&mdss0>;
2404                                 interrupts = <0>;
2405                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
2406
2407                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
2408                                 assigned-clock-rates = <19200000>;
2409                                 operating-points-v2 = <&mdss0_mdp_opp_table>;
2410
2411                                 ports {
2412                                         #address-cells = <1>;
2413                                         #size-cells = <0>;
2414
2415                                         port@5 {
2416                                                 reg = <5>;
2417                                                 mdss0_intf5_out: endpoint {
2418                                                         remote-endpoint = <&mdss0_dp3_in>;
2419                                                 };
2420                                         };
2421
2422                                         port@6 {
2423                                                 reg = <6>;
2424                                                 mdss0_intf6_out: endpoint {
2425                                                         remote-endpoint = <&mdss0_dp2_in>;
2426                                                 };
2427                                         };
2428                                 };
2429
2430                                 mdss0_mdp_opp_table: opp-table {
2431                                         compatible = "operating-points-v2";
2432
2433                                         opp-200000000 {
2434                                                 opp-hz = /bits/ 64 <200000000>;
2435                                                 required-opps = <&rpmhpd_opp_low_svs>;
2436                                         };
2437
2438                                         opp-300000000 {
2439                                                 opp-hz = /bits/ 64 <300000000>;
2440                                                 required-opps = <&rpmhpd_opp_svs>;
2441                                         };
2442
2443                                         opp-375000000 {
2444                                                 opp-hz = /bits/ 64 <375000000>;
2445                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2446                                         };
2447
2448                                         opp-500000000 {
2449                                                 opp-hz = /bits/ 64 <500000000>;
2450                                                 required-opps = <&rpmhpd_opp_nom>;
2451                                         };
2452                                         opp-600000000 {
2453                                                 opp-hz = /bits/ 64 <600000000>;
2454                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
2455                                         };
2456                                 };
2457                         };
2458
2459                         mdss0_dp2: displayport-controller@ae9a000 {
2460                                 compatible = "qcom,sc8280xp-dp";
2461                                 reg = <0 0xae9a000 0 0x200>,
2462                                       <0 0xae9a200 0 0x200>,
2463                                       <0 0xae9a400 0 0x600>,
2464                                       <0 0xae9b000 0 0x400>;
2465
2466                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
2467                                          <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
2468                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
2469                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
2470                                          <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
2471                                 clock-names = "core_iface", "core_aux",
2472                                               "ctrl_link",
2473                                               "ctrl_link_iface", "stream_pixel";
2474                                 interrupt-parent = <&mdss0>;
2475                                 interrupts = <14>;
2476                                 phys = <&mdss0_dp2_phy>;
2477                                 phy-names = "dp";
2478                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
2479
2480                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
2481                                                   <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
2482                                 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
2483                                 operating-points-v2 = <&mdss0_dp2_opp_table>;
2484
2485                                 #sound-dai-cells = <0>;
2486
2487                                 status = "disabled";
2488
2489                                 ports {
2490                                         #address-cells = <1>;
2491                                         #size-cells = <0>;
2492
2493                                         port@0 {
2494                                                 reg = <0>;
2495                                                 mdss0_dp2_in: endpoint {
2496                                                         remote-endpoint = <&mdss0_intf6_out>;
2497                                                 };
2498                                         };
2499
2500                                         port@1 {
2501                                                 reg = <1>;
2502                                         };
2503                                 };
2504
2505                                 mdss0_dp2_opp_table: opp-table {
2506                                         compatible = "operating-points-v2";
2507
2508                                         opp-160000000 {
2509                                                 opp-hz = /bits/ 64 <160000000>;
2510                                                 required-opps = <&rpmhpd_opp_low_svs>;
2511                                         };
2512
2513                                         opp-270000000 {
2514                                                 opp-hz = /bits/ 64 <270000000>;
2515                                                 required-opps = <&rpmhpd_opp_svs>;
2516                                         };
2517
2518                                         opp-540000000 {
2519                                                 opp-hz = /bits/ 64 <540000000>;
2520                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2521                                         };
2522
2523                                         opp-810000000 {
2524                                                 opp-hz = /bits/ 64 <810000000>;
2525                                                 required-opps = <&rpmhpd_opp_nom>;
2526                                         };
2527                                 };
2528                         };
2529
2530                         mdss0_dp3: displayport-controller@aea0000 {
2531                                 compatible = "qcom,sc8280xp-dp";
2532                                 reg = <0 0xaea0000 0 0x200>,
2533                                       <0 0xaea0200 0 0x200>,
2534                                       <0 0xaea0400 0 0x600>,
2535                                       <0 0xaea1000 0 0x400>;
2536
2537                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
2538                                          <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
2539                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
2540                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
2541                                          <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
2542                                 clock-names = "core_iface", "core_aux",
2543                                               "ctrl_link",
2544                                               "ctrl_link_iface", "stream_pixel";
2545                                 interrupt-parent = <&mdss0>;
2546                                 interrupts = <15>;
2547                                 phys = <&mdss0_dp3_phy>;
2548                                 phy-names = "dp";
2549                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
2550
2551                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
2552                                                   <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
2553                                 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
2554                                 operating-points-v2 = <&mdss0_dp3_opp_table>;
2555
2556                                 #sound-dai-cells = <0>;
2557
2558                                 status = "disabled";
2559
2560                                 ports {
2561                                         #address-cells = <1>;
2562                                         #size-cells = <0>;
2563
2564                                         port@0 {
2565                                                 reg = <0>;
2566                                                 mdss0_dp3_in: endpoint {
2567                                                         remote-endpoint = <&mdss0_intf5_out>;
2568                                                 };
2569                                         };
2570
2571                                         port@1 {
2572                                                 reg = <1>;
2573                                         };
2574                                 };
2575
2576                                 mdss0_dp3_opp_table: opp-table {
2577                                         compatible = "operating-points-v2";
2578
2579                                         opp-160000000 {
2580                                                 opp-hz = /bits/ 64 <160000000>;
2581                                                 required-opps = <&rpmhpd_opp_low_svs>;
2582                                         };
2583
2584                                         opp-270000000 {
2585                                                 opp-hz = /bits/ 64 <270000000>;
2586                                                 required-opps = <&rpmhpd_opp_svs>;
2587                                         };
2588
2589                                         opp-540000000 {
2590                                                 opp-hz = /bits/ 64 <540000000>;
2591                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2592                                         };
2593
2594                                         opp-810000000 {
2595                                                 opp-hz = /bits/ 64 <810000000>;
2596                                                 required-opps = <&rpmhpd_opp_nom>;
2597                                         };
2598                                 };
2599                         };
2600                 };
2601
2602                 mdss0_dp2_phy: phy@aec2a00 {
2603                         compatible = "qcom,sc8280xp-dp-phy";
2604                         reg = <0 0x0aec2a00 0 0x19c>,
2605                               <0 0x0aec2200 0 0xec>,
2606                               <0 0x0aec2600 0 0xec>,
2607                               <0 0x0aec2000 0 0x1c8>;
2608
2609                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
2610                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
2611                         clock-names = "aux", "cfg_ahb";
2612                         power-domains = <&rpmhpd SC8280XP_MX>;
2613
2614                         #clock-cells = <1>;
2615                         #phy-cells = <0>;
2616
2617                         status = "disabled";
2618                 };
2619
2620                 mdss0_dp3_phy: phy@aec5a00 {
2621                         compatible = "qcom,sc8280xp-dp-phy";
2622                         reg = <0 0x0aec5a00 0 0x19c>,
2623                               <0 0x0aec5200 0 0xec>,
2624                               <0 0x0aec5600 0 0xec>,
2625                               <0 0x0aec5000 0 0x1c8>;
2626
2627                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
2628                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
2629                         clock-names = "aux", "cfg_ahb";
2630                         power-domains = <&rpmhpd SC8280XP_MX>;
2631
2632                         #clock-cells = <1>;
2633                         #phy-cells = <0>;
2634
2635                         status = "disabled";
2636                 };
2637
2638                 dispcc0: clock-controller@af00000 {
2639                         compatible = "qcom,sc8280xp-dispcc0";
2640                         reg = <0 0x0af00000 0 0x20000>;
2641
2642                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2643                                  <&rpmhcc RPMH_CXO_CLK>,
2644                                  <&sleep_clk>,
2645                                  <0>,
2646                                  <0>,
2647                                  <0>,
2648                                  <0>,
2649                                  <&mdss0_dp2_phy 0>,
2650                                  <&mdss0_dp2_phy 1>,
2651                                  <&mdss0_dp3_phy 0>,
2652                                  <&mdss0_dp3_phy 1>,
2653                                  <0>,
2654                                  <0>,
2655                                  <0>,
2656                                  <0>;
2657                         power-domains = <&rpmhpd SC8280XP_MMCX>;
2658
2659                         #clock-cells = <1>;
2660                         #power-domain-cells = <1>;
2661                         #reset-cells = <1>;
2662
2663                         status = "disabled";
2664                 };
2665
2666                 pdc: interrupt-controller@b220000 {
2667                         compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
2668                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2669                         qcom,pdc-ranges = <0 480 40>,
2670                                           <40 140 14>,
2671                                           <54 263 1>,
2672                                           <55 306 4>,
2673                                           <59 312 3>,
2674                                           <62 374 2>,
2675                                           <64 434 2>,
2676                                           <66 438 3>,
2677                                           <69 86 1>,
2678                                           <70 520 54>,
2679                                           <124 609 28>,
2680                                           <159 638 1>,
2681                                           <160 720 8>,
2682                                           <168 801 1>,
2683                                           <169 728 30>,
2684                                           <199 416 2>,
2685                                           <201 449 1>,
2686                                           <202 89 1>,
2687                                           <203 451 1>,
2688                                           <204 462 1>,
2689                                           <205 264 1>,
2690                                           <206 579 1>,
2691                                           <207 653 1>,
2692                                           <208 656 1>,
2693                                           <209 659 1>,
2694                                           <210 122 1>,
2695                                           <211 699 1>,
2696                                           <212 705 1>,
2697                                           <213 450 1>,
2698                                           <214 643 1>,
2699                                           <216 646 5>,
2700                                           <221 390 5>,
2701                                           <226 700 3>,
2702                                           <229 240 3>,
2703                                           <232 269 1>,
2704                                           <233 377 1>,
2705                                           <234 372 1>,
2706                                           <235 138 1>,
2707                                           <236 857 1>,
2708                                           <237 860 1>,
2709                                           <238 137 1>,
2710                                           <239 668 1>,
2711                                           <240 366 1>,
2712                                           <241 949 1>,
2713                                           <242 815 5>,
2714                                           <247 769 1>,
2715                                           <248 768 1>,
2716                                           <249 663 1>,
2717                                           <250 799 2>,
2718                                           <252 798 1>,
2719                                           <253 765 1>,
2720                                           <254 763 1>,
2721                                           <255 454 1>,
2722                                           <258 139 1>,
2723                                           <259 786 2>,
2724                                           <261 370 2>,
2725                                           <263 158 2>;
2726                         #interrupt-cells = <2>;
2727                         interrupt-parent = <&intc>;
2728                         interrupt-controller;
2729                 };
2730
2731                 tsens0: thermal-sensor@c263000 {
2732                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2733                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2734                               <0 0x0c222000 0 0x8>; /* SROT */
2735                         #qcom,sensors = <14>;
2736                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2737                                               <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2738                         interrupt-names = "uplow", "critical";
2739                         #thermal-sensor-cells = <1>;
2740                 };
2741
2742                 tsens1: thermal-sensor@c265000 {
2743                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2744                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2745                               <0 0x0c223000 0 0x8>; /* SROT */
2746                         #qcom,sensors = <16>;
2747                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2748                                               <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2749                         interrupt-names = "uplow", "critical";
2750                         #thermal-sensor-cells = <1>;
2751                 };
2752
2753                 aoss_qmp: power-management@c300000 {
2754                         compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
2755                         reg = <0 0x0c300000 0 0x400>;
2756                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
2757                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2758
2759                         #clock-cells = <0>;
2760                 };
2761
2762                 sram@c3f0000 {
2763                         compatible = "qcom,rpmh-stats";
2764                         reg = <0 0x0c3f0000 0 0x400>;
2765                 };
2766
2767                 spmi_bus: spmi@c440000 {
2768                         compatible = "qcom,spmi-pmic-arb";
2769                         reg = <0 0x0c440000 0 0x1100>,
2770                               <0 0x0c600000 0 0x2000000>,
2771                               <0 0x0e600000 0 0x100000>,
2772                               <0 0x0e700000 0 0xa0000>,
2773                               <0 0x0c40a000 0 0x26000>;
2774                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2775                         interrupt-names = "periph_irq";
2776                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2777                         qcom,ee = <0>;
2778                         qcom,channel = <0>;
2779                         #address-cells = <2>;
2780                         #size-cells = <0>;
2781                         interrupt-controller;
2782                         #interrupt-cells = <4>;
2783                 };
2784
2785                 tlmm: pinctrl@f100000 {
2786                         compatible = "qcom,sc8280xp-tlmm";
2787                         reg = <0 0x0f100000 0 0x300000>;
2788                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2789                         gpio-controller;
2790                         #gpio-cells = <2>;
2791                         interrupt-controller;
2792                         #interrupt-cells = <2>;
2793                         gpio-ranges = <&tlmm 0 0 230>;
2794                 };
2795
2796                 apps_smmu: iommu@15000000 {
2797                         compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
2798                         reg = <0 0x15000000 0 0x100000>;
2799                         #iommu-cells = <2>;
2800                         #global-interrupts = <2>;
2801                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2802                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2803                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2804                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2805                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2806                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2807                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2808                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2809                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2810                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2811                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2812                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2813                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2814                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2815                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2816                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2817                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2818                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2819                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2820                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2821                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2822                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2823                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2824                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2825                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2826                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2827                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2828                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2829                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2830                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2831                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2832                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2833                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2834                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2835                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2836                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2837                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2838                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2839                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2840                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2841                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2842                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2843                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2844                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2845                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2846                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2847                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2848                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2849                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2850                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2851                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2852                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2853                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2854                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2855                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2856                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2857                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2858                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2859                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2860                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2861                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2862                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2863                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2864                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2865                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2866                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2867                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2868                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2869                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2870                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2871                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2872                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2873                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2874                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2875                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2876                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2877                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2878                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2879                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2880                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2881                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
2882                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2883                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2884                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2885                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2886                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2887                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2888                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2889                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2890                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2891                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2892                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2893                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2894                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2895                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2896                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2897                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2898                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2899                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2900                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2901                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2902                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2903                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2904                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2905                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2906                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2907                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2908                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2909                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2910                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2911                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2912                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2913                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2914                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2915                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2916                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2917                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2918                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2919                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2920                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2921                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2922                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2923                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2924                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2925                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2926                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2927                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2928                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2929                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
2930                                      <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
2931                 };
2932
2933                 intc: interrupt-controller@17a00000 {
2934                         compatible = "arm,gic-v3";
2935                         interrupt-controller;
2936                         #interrupt-cells = <3>;
2937                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2938                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2939                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2940                         #redistributor-regions = <1>;
2941                         redistributor-stride = <0 0x20000>;
2942
2943                         #address-cells = <2>;
2944                         #size-cells = <2>;
2945                         ranges;
2946
2947                         gic-its@17a40000 {
2948                                 compatible = "arm,gic-v3-its";
2949                                 reg = <0 0x17a40000 0 0x20000>;
2950                                 msi-controller;
2951                                 #msi-cells = <1>;
2952                         };
2953                 };
2954
2955                 watchdog@17c10000 {
2956                         compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
2957                         reg = <0 0x17c10000 0 0x1000>;
2958                         clocks = <&sleep_clk>;
2959                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2960                 };
2961
2962                 timer@17c20000 {
2963                         compatible = "arm,armv7-timer-mem";
2964                         reg = <0x0 0x17c20000 0x0 0x1000>;
2965                         #address-cells = <1>;
2966                         #size-cells = <1>;
2967                         ranges = <0x0 0x0 0x0 0x20000000>;
2968
2969                         frame@17c21000 {
2970                                 frame-number = <0>;
2971                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2972                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2973                                 reg = <0x17c21000 0x1000>,
2974                                       <0x17c22000 0x1000>;
2975                         };
2976
2977                         frame@17c23000 {
2978                                 frame-number = <1>;
2979                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2980                                 reg = <0x17c23000 0x1000>;
2981                                 status = "disabled";
2982                         };
2983
2984                         frame@17c25000 {
2985                                 frame-number = <2>;
2986                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2987                                 reg = <0x17c25000 0x1000>;
2988                                 status = "disabled";
2989                         };
2990
2991                         frame@17c27000 {
2992                                 frame-number = <3>;
2993                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2994                                 reg = <0x17c26000 0x1000>;
2995                                 status = "disabled";
2996                         };
2997
2998                         frame@17c29000 {
2999                                 frame-number = <4>;
3000                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3001                                 reg = <0x17c29000 0x1000>;
3002                                 status = "disabled";
3003                         };
3004
3005                         frame@17c2b000 {
3006                                 frame-number = <5>;
3007                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3008                                 reg = <0x17c2b000 0x1000>;
3009                                 status = "disabled";
3010                         };
3011
3012                         frame@17c2d000 {
3013                                 frame-number = <6>;
3014                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3015                                 reg = <0x17c2d000 0x1000>;
3016                                 status = "disabled";
3017                         };
3018                 };
3019
3020                 apps_rsc: rsc@18200000 {
3021                         compatible = "qcom,rpmh-rsc";
3022                         reg = <0x0 0x18200000 0x0 0x10000>,
3023                                 <0x0 0x18210000 0x0 0x10000>,
3024                                 <0x0 0x18220000 0x0 0x10000>;
3025                         reg-names = "drv-0", "drv-1", "drv-2";
3026                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3027                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3028                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3029                         qcom,tcs-offset = <0xd00>;
3030                         qcom,drv-id = <2>;
3031                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3032                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
3033                         label = "apps_rsc";
3034
3035                         apps_bcm_voter: bcm-voter {
3036                                 compatible = "qcom,bcm-voter";
3037                         };
3038
3039                         rpmhcc: clock-controller {
3040                                 compatible = "qcom,sc8280xp-rpmh-clk";
3041                                 #clock-cells = <1>;
3042                                 clock-names = "xo";
3043                                 clocks = <&xo_board_clk>;
3044                         };
3045
3046                         rpmhpd: power-controller {
3047                                 compatible = "qcom,sc8280xp-rpmhpd";
3048                                 #power-domain-cells = <1>;
3049                                 operating-points-v2 = <&rpmhpd_opp_table>;
3050
3051                                 rpmhpd_opp_table: opp-table {
3052                                         compatible = "operating-points-v2";
3053
3054                                         rpmhpd_opp_ret: opp1 {
3055                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3056                                         };
3057
3058                                         rpmhpd_opp_min_svs: opp2 {
3059                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3060                                         };
3061
3062                                         rpmhpd_opp_low_svs: opp3 {
3063                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3064                                         };
3065
3066                                         rpmhpd_opp_svs: opp4 {
3067                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3068                                         };
3069
3070                                         rpmhpd_opp_svs_l1: opp5 {
3071                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3072                                         };
3073
3074                                         rpmhpd_opp_nom: opp6 {
3075                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3076                                         };
3077
3078                                         rpmhpd_opp_nom_l1: opp7 {
3079                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3080                                         };
3081
3082                                         rpmhpd_opp_nom_l2: opp8 {
3083                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3084                                         };
3085
3086                                         rpmhpd_opp_turbo: opp9 {
3087                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3088                                         };
3089
3090                                         rpmhpd_opp_turbo_l1: opp10 {
3091                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3092                                         };
3093                                 };
3094                         };
3095                 };
3096
3097                 epss_l3: interconnect@18590000 {
3098                         compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
3099                         reg = <0 0x18590000 0 0x1000>;
3100
3101                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3102                         clock-names = "xo", "alternate";
3103
3104                         #interconnect-cells = <1>;
3105                 };
3106
3107                 cpufreq_hw: cpufreq@18591000 {
3108                         compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
3109                         reg = <0 0x18591000 0 0x1000>,
3110                               <0 0x18592000 0 0x1000>;
3111                         reg-names = "freq-domain0", "freq-domain1";
3112
3113                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3114                         clock-names = "xo", "alternate";
3115
3116                         #freq-domain-cells = <1>;
3117                 };
3118
3119                 remoteproc_nsp0: remoteproc@1b300000 {
3120                         compatible = "qcom,sc8280xp-nsp0-pas";
3121                         reg = <0 0x1b300000 0 0x100>;
3122
3123                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3124                                               <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
3125                                               <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
3126                                               <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
3127                                               <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
3128                         interrupt-names = "wdog", "fatal", "ready",
3129                                           "handover", "stop-ack";
3130
3131                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3132                         clock-names = "xo";
3133
3134                         power-domains = <&rpmhpd SC8280XP_NSP>;
3135                         power-domain-names = "nsp";
3136
3137                         memory-region = <&pil_nsp0_mem>;
3138
3139                         qcom,smem-states = <&smp2p_nsp0_out 0>;
3140                         qcom,smem-state-names = "stop";
3141
3142                         interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3143
3144                         status = "disabled";
3145
3146                         glink-edge {
3147                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3148                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3149                                                              IRQ_TYPE_EDGE_RISING>;
3150                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3151                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3152
3153                                 label = "nsp0";
3154                                 qcom,remote-pid = <5>;
3155
3156                                 fastrpc {
3157                                         compatible = "qcom,fastrpc";
3158                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3159                                         label = "cdsp";
3160                                         #address-cells = <1>;
3161                                         #size-cells = <0>;
3162
3163                                         compute-cb@1 {
3164                                                 compatible = "qcom,fastrpc-compute-cb";
3165                                                 reg = <1>;
3166                                                 iommus = <&apps_smmu 0x3181 0x0420>;
3167                                         };
3168
3169                                         compute-cb@2 {
3170                                                 compatible = "qcom,fastrpc-compute-cb";
3171                                                 reg = <2>;
3172                                                 iommus = <&apps_smmu 0x3182 0x0420>;
3173                                         };
3174
3175                                         compute-cb@3 {
3176                                                 compatible = "qcom,fastrpc-compute-cb";
3177                                                 reg = <3>;
3178                                                 iommus = <&apps_smmu 0x3183 0x0420>;
3179                                         };
3180
3181                                         compute-cb@4 {
3182                                                 compatible = "qcom,fastrpc-compute-cb";
3183                                                 reg = <4>;
3184                                                 iommus = <&apps_smmu 0x3184 0x0420>;
3185                                         };
3186
3187                                         compute-cb@5 {
3188                                                 compatible = "qcom,fastrpc-compute-cb";
3189                                                 reg = <5>;
3190                                                 iommus = <&apps_smmu 0x3185 0x0420>;
3191                                         };
3192
3193                                         compute-cb@6 {
3194                                                 compatible = "qcom,fastrpc-compute-cb";
3195                                                 reg = <6>;
3196                                                 iommus = <&apps_smmu 0x3186 0x0420>;
3197                                         };
3198
3199                                         compute-cb@7 {
3200                                                 compatible = "qcom,fastrpc-compute-cb";
3201                                                 reg = <7>;
3202                                                 iommus = <&apps_smmu 0x3187 0x0420>;
3203                                         };
3204
3205                                         compute-cb@8 {
3206                                                 compatible = "qcom,fastrpc-compute-cb";
3207                                                 reg = <8>;
3208                                                 iommus = <&apps_smmu 0x3188 0x0420>;
3209                                         };
3210
3211                                         compute-cb@9 {
3212                                                 compatible = "qcom,fastrpc-compute-cb";
3213                                                 reg = <9>;
3214                                                 iommus = <&apps_smmu 0x318b 0x0420>;
3215                                         };
3216
3217                                         compute-cb@10 {
3218                                                 compatible = "qcom,fastrpc-compute-cb";
3219                                                 reg = <10>;
3220                                                 iommus = <&apps_smmu 0x318b 0x0420>;
3221                                         };
3222
3223                                         compute-cb@11 {
3224                                                 compatible = "qcom,fastrpc-compute-cb";
3225                                                 reg = <11>;
3226                                                 iommus = <&apps_smmu 0x318c 0x0420>;
3227                                         };
3228
3229                                         compute-cb@12 {
3230                                                 compatible = "qcom,fastrpc-compute-cb";
3231                                                 reg = <12>;
3232                                                 iommus = <&apps_smmu 0x318d 0x0420>;
3233                                         };
3234
3235                                         compute-cb@13 {
3236                                                 compatible = "qcom,fastrpc-compute-cb";
3237                                                 reg = <13>;
3238                                                 iommus = <&apps_smmu 0x318e 0x0420>;
3239                                         };
3240
3241                                         compute-cb@14 {
3242                                                 compatible = "qcom,fastrpc-compute-cb";
3243                                                 reg = <14>;
3244                                                 iommus = <&apps_smmu 0x318f 0x0420>;
3245                                         };
3246                                 };
3247                         };
3248                 };
3249
3250                 remoteproc_nsp1: remoteproc@21300000 {
3251                         compatible = "qcom,sc8280xp-nsp1-pas";
3252                         reg = <0 0x21300000 0 0x100>;
3253
3254                         interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
3255                                               <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
3256                                               <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
3257                                               <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
3258                                               <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
3259                         interrupt-names = "wdog", "fatal", "ready",
3260                                           "handover", "stop-ack";
3261
3262                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3263                         clock-names = "xo";
3264
3265                         power-domains = <&rpmhpd SC8280XP_NSP>;
3266                         power-domain-names = "nsp";
3267
3268                         memory-region = <&pil_nsp1_mem>;
3269
3270                         qcom,smem-states = <&smp2p_nsp1_out 0>;
3271                         qcom,smem-state-names = "stop";
3272
3273                         interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
3274
3275                         status = "disabled";
3276
3277                         glink-edge {
3278                                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
3279                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3280                                                              IRQ_TYPE_EDGE_RISING>;
3281                                 mboxes = <&ipcc IPCC_CLIENT_NSP1
3282                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3283
3284                                 label = "nsp1";
3285                                 qcom,remote-pid = <12>;
3286                         };
3287                 };
3288
3289                 mdss1: display-subsystem@22000000 {
3290                         compatible = "qcom,sc8280xp-mdss";
3291                         reg = <0 0x22000000 0 0x1000>;
3292                         reg-names = "mdss";
3293
3294                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3295                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
3296                                  <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
3297                         clock-names = "iface",
3298                                       "ahb",
3299                                       "core";
3300                         interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
3301                                         <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
3302                         interconnect-names = "mdp0-mem", "mdp1-mem";
3303                         interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
3304
3305                         iommus = <&apps_smmu 0x1800 0x402>;
3306                         power-domains = <&dispcc1 MDSS_GDSC>;
3307                         resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
3308
3309                         interrupt-controller;
3310                         #interrupt-cells = <1>;
3311                         #address-cells = <2>;
3312                         #size-cells = <2>;
3313                         ranges;
3314
3315                         status = "disabled";
3316
3317                         mdss1_mdp: display-controller@22001000 {
3318                                 compatible = "qcom,sc8280xp-dpu";
3319                                 reg = <0 0x22001000 0 0x8f000>,
3320                                       <0 0x220b0000 0 0x2008>;
3321                                 reg-names = "mdp", "vbif";
3322
3323                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3324                                          <&gcc GCC_DISP_SF_AXI_CLK>,
3325                                          <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
3326                                          <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
3327                                          <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
3328                                          <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
3329                                 clock-names = "bus",
3330                                               "nrt_bus",
3331                                               "iface",
3332                                               "lut",
3333                                               "core",
3334                                               "vsync";
3335                                 interrupt-parent = <&mdss1>;
3336                                 interrupts = <0>;
3337                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3338
3339                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
3340                                 assigned-clock-rates = <19200000>;
3341                                 operating-points-v2 = <&mdss1_mdp_opp_table>;
3342
3343                                 ports {
3344                                         #address-cells = <1>;
3345                                         #size-cells = <0>;
3346
3347                                         port@0 {
3348                                                 reg = <0>;
3349                                                 mdss1_intf0_out: endpoint {
3350                                                         remote-endpoint = <&mdss1_dp0_in>;
3351                                                 };
3352                                         };
3353
3354                                         port@4 {
3355                                                 reg = <4>;
3356                                                 mdss1_intf4_out: endpoint {
3357                                                         remote-endpoint = <&mdss1_dp1_in>;
3358                                                 };
3359                                         };
3360
3361                                         port@5 {
3362                                                 reg = <5>;
3363                                                 mdss1_intf5_out: endpoint {
3364                                                         remote-endpoint = <&mdss1_dp3_in>;
3365                                                 };
3366                                         };
3367
3368                                         port@6 {
3369                                                 reg = <6>;
3370                                                 mdss1_intf6_out: endpoint {
3371                                                         remote-endpoint = <&mdss1_dp2_in>;
3372                                                 };
3373                                         };
3374                                 };
3375
3376                                 mdss1_mdp_opp_table: opp-table {
3377                                         compatible = "operating-points-v2";
3378
3379                                         opp-200000000 {
3380                                                 opp-hz = /bits/ 64 <200000000>;
3381                                                 required-opps = <&rpmhpd_opp_low_svs>;
3382                                         };
3383
3384                                         opp-300000000 {
3385                                                 opp-hz = /bits/ 64 <300000000>;
3386                                                 required-opps = <&rpmhpd_opp_svs>;
3387                                         };
3388
3389                                         opp-375000000 {
3390                                                 opp-hz = /bits/ 64 <375000000>;
3391                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3392                                         };
3393
3394                                         opp-500000000 {
3395                                                 opp-hz = /bits/ 64 <500000000>;
3396                                                 required-opps = <&rpmhpd_opp_nom>;
3397                                         };
3398                                         opp-600000000 {
3399                                                 opp-hz = /bits/ 64 <600000000>;
3400                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
3401                                         };
3402                                 };
3403                         };
3404
3405                         mdss1_dp0: displayport-controller@22090000 {
3406                                 compatible = "qcom,sc8280xp-dp";
3407                                 reg = <0 0x22090000 0 0x200>,
3408                                       <0 0x22090200 0 0x200>,
3409                                       <0 0x22090400 0 0x600>,
3410                                       <0 0x22091000 0 0x400>;
3411
3412                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
3413                                          <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3414                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
3415                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3416                                          <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3417                                 clock-names = "core_iface", "core_aux",
3418                                               "ctrl_link",
3419                                               "ctrl_link_iface", "stream_pixel";
3420                                 interrupt-parent = <&mdss1>;
3421                                 interrupts = <12>;
3422                                 phys = <&mdss1_dp0_phy>;
3423                                 phy-names = "dp";
3424                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3425
3426                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3427                                                   <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3428                                 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
3429                                 operating-points-v2 = <&mdss1_dp0_opp_table>;
3430
3431                                 #sound-dai-cells = <0>;
3432
3433                                 status = "disabled";
3434
3435                                 ports {
3436                                         #address-cells = <1>;
3437                                         #size-cells = <0>;
3438
3439                                         port@0 {
3440                                                 reg = <0>;
3441                                                 mdss1_dp0_in: endpoint {
3442                                                         remote-endpoint = <&mdss1_intf0_out>;
3443                                                 };
3444                                         };
3445
3446                                         port@1 {
3447                                                 reg = <1>;
3448                                         };
3449                                 };
3450
3451                                 mdss1_dp0_opp_table: opp-table {
3452                                         compatible = "operating-points-v2";
3453
3454                                         opp-160000000 {
3455                                                 opp-hz = /bits/ 64 <160000000>;
3456                                                 required-opps = <&rpmhpd_opp_low_svs>;
3457                                         };
3458
3459                                         opp-270000000 {
3460                                                 opp-hz = /bits/ 64 <270000000>;
3461                                                 required-opps = <&rpmhpd_opp_svs>;
3462                                         };
3463
3464                                         opp-540000000 {
3465                                                 opp-hz = /bits/ 64 <540000000>;
3466                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3467                                         };
3468
3469                                         opp-810000000 {
3470                                                 opp-hz = /bits/ 64 <810000000>;
3471                                                 required-opps = <&rpmhpd_opp_nom>;
3472                                         };
3473                                 };
3474
3475                         };
3476
3477                         mdss1_dp1: displayport-controller@22098000 {
3478                                 compatible = "qcom,sc8280xp-dp";
3479                                 reg = <0 0x22098000 0 0x200>,
3480                                       <0 0x22098200 0 0x200>,
3481                                       <0 0x22098400 0 0x600>,
3482                                       <0 0x22099000 0 0x400>;
3483
3484                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
3485                                          <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3486                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
3487                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
3488                                          <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
3489                                 clock-names = "core_iface", "core_aux",
3490                                               "ctrl_link",
3491                                               "ctrl_link_iface", "stream_pixel";
3492                                 interrupt-parent = <&mdss1>;
3493                                 interrupts = <13>;
3494                                 phys = <&mdss1_dp1_phy>;
3495                                 phy-names = "dp";
3496                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3497
3498                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
3499                                                   <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
3500                                 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
3501                                 operating-points-v2 = <&mdss1_dp1_opp_table>;
3502
3503                                 #sound-dai-cells = <0>;
3504
3505                                 status = "disabled";
3506
3507                                 ports {
3508                                         #address-cells = <1>;
3509                                         #size-cells = <0>;
3510
3511                                         port@0 {
3512                                                 reg = <0>;
3513                                                 mdss1_dp1_in: endpoint {
3514                                                         remote-endpoint = <&mdss1_intf4_out>;
3515                                                 };
3516                                         };
3517
3518                                         port@1 {
3519                                                 reg = <1>;
3520                                         };
3521                                 };
3522
3523                                 mdss1_dp1_opp_table: opp-table {
3524                                         compatible = "operating-points-v2";
3525
3526                                         opp-160000000 {
3527                                                 opp-hz = /bits/ 64 <160000000>;
3528                                                 required-opps = <&rpmhpd_opp_low_svs>;
3529                                         };
3530
3531                                         opp-270000000 {
3532                                                 opp-hz = /bits/ 64 <270000000>;
3533                                                 required-opps = <&rpmhpd_opp_svs>;
3534                                         };
3535
3536                                         opp-540000000 {
3537                                                 opp-hz = /bits/ 64 <540000000>;
3538                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3539                                         };
3540
3541                                         opp-810000000 {
3542                                                 opp-hz = /bits/ 64 <810000000>;
3543                                                 required-opps = <&rpmhpd_opp_nom>;
3544                                         };
3545                                 };
3546                         };
3547
3548                         mdss1_dp2: displayport-controller@2209a000 {
3549                                 compatible = "qcom,sc8280xp-dp";
3550                                 reg = <0 0x2209a000 0 0x200>,
3551                                       <0 0x2209a200 0 0x200>,
3552                                       <0 0x2209a400 0 0x600>,
3553                                       <0 0x2209b000 0 0x400>;
3554
3555                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
3556                                          <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
3557                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
3558                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
3559                                          <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
3560                                 clock-names = "core_iface", "core_aux",
3561                                               "ctrl_link",
3562                                               "ctrl_link_iface", "stream_pixel";
3563                                 interrupt-parent = <&mdss1>;
3564                                 interrupts = <14>;
3565                                 phys = <&mdss1_dp2_phy>;
3566                                 phy-names = "dp";
3567                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3568
3569                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
3570                                                   <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
3571                                 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
3572                                 operating-points-v2 = <&mdss1_dp2_opp_table>;
3573
3574                                 #sound-dai-cells = <0>;
3575
3576                                 status = "disabled";
3577
3578                                 ports {
3579                                         #address-cells = <1>;
3580                                         #size-cells = <0>;
3581
3582                                         port@0 {
3583                                                 reg = <0>;
3584                                                 mdss1_dp2_in: endpoint {
3585                                                         remote-endpoint = <&mdss1_intf6_out>;
3586                                                 };
3587                                         };
3588
3589                                         port@1 {
3590                                                 reg = <1>;
3591                                         };
3592                                 };
3593
3594                                 mdss1_dp2_opp_table: opp-table {
3595                                         compatible = "operating-points-v2";
3596
3597                                         opp-160000000 {
3598                                                 opp-hz = /bits/ 64 <160000000>;
3599                                                 required-opps = <&rpmhpd_opp_low_svs>;
3600                                         };
3601
3602                                         opp-270000000 {
3603                                                 opp-hz = /bits/ 64 <270000000>;
3604                                                 required-opps = <&rpmhpd_opp_svs>;
3605                                         };
3606
3607                                         opp-540000000 {
3608                                                 opp-hz = /bits/ 64 <540000000>;
3609                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3610                                         };
3611
3612                                         opp-810000000 {
3613                                                 opp-hz = /bits/ 64 <810000000>;
3614                                                 required-opps = <&rpmhpd_opp_nom>;
3615                                         };
3616                                 };
3617                         };
3618
3619                         mdss1_dp3: displayport-controller@220a0000 {
3620                                 compatible = "qcom,sc8280xp-dp";
3621                                 reg = <0 0x220a0000 0 0x200>,
3622                                       <0 0x220a0200 0 0x200>,
3623                                       <0 0x220a0400 0 0x600>,
3624                                       <0 0x220a1000 0 0x400>;
3625
3626                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
3627                                          <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
3628                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
3629                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
3630                                          <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
3631                                 clock-names = "core_iface", "core_aux",
3632                                               "ctrl_link",
3633                                               "ctrl_link_iface", "stream_pixel";
3634                                 interrupt-parent = <&mdss1>;
3635                                 interrupts = <15>;
3636                                 phys = <&mdss1_dp3_phy>;
3637                                 phy-names = "dp";
3638                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3639
3640                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
3641                                                   <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
3642                                 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
3643                                 operating-points-v2 = <&mdss1_dp3_opp_table>;
3644
3645                                 #sound-dai-cells = <0>;
3646
3647                                 status = "disabled";
3648
3649                                 ports {
3650                                         #address-cells = <1>;
3651                                         #size-cells = <0>;
3652
3653                                         port@0 {
3654                                                 reg = <0>;
3655                                                 mdss1_dp3_in: endpoint {
3656                                                         remote-endpoint = <&mdss1_intf5_out>;
3657                                                 };
3658                                         };
3659
3660                                         port@1 {
3661                                                 reg = <1>;
3662                                         };
3663                                 };
3664
3665                                 mdss1_dp3_opp_table: opp-table {
3666                                         compatible = "operating-points-v2";
3667
3668                                         opp-160000000 {
3669                                                 opp-hz = /bits/ 64 <160000000>;
3670                                                 required-opps = <&rpmhpd_opp_low_svs>;
3671                                         };
3672
3673                                         opp-270000000 {
3674                                                 opp-hz = /bits/ 64 <270000000>;
3675                                                 required-opps = <&rpmhpd_opp_svs>;
3676                                         };
3677
3678                                         opp-540000000 {
3679                                                 opp-hz = /bits/ 64 <540000000>;
3680                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3681                                         };
3682
3683                                         opp-810000000 {
3684                                                 opp-hz = /bits/ 64 <810000000>;
3685                                                 required-opps = <&rpmhpd_opp_nom>;
3686                                         };
3687                                 };
3688                         };
3689                 };
3690
3691                 mdss1_dp2_phy: phy@220c2a00 {
3692                         compatible = "qcom,sc8280xp-dp-phy";
3693                         reg = <0 0x220c2a00 0 0x19c>,
3694                               <0 0x220c2200 0 0xec>,
3695                               <0 0x220c2600 0 0xec>,
3696                               <0 0x220c2000 0 0x1c8>;
3697
3698                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
3699                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3700                         clock-names = "aux", "cfg_ahb";
3701                         power-domains = <&rpmhpd SC8280XP_MX>;
3702
3703                         #clock-cells = <1>;
3704                         #phy-cells = <0>;
3705
3706                         status = "disabled";
3707                 };
3708
3709                 mdss1_dp3_phy: phy@220c5a00 {
3710                         compatible = "qcom,sc8280xp-dp-phy";
3711                         reg = <0 0x220c5a00 0 0x19c>,
3712                               <0 0x220c5200 0 0xec>,
3713                               <0 0x220c5600 0 0xec>,
3714                               <0 0x220c5000 0 0x1c8>;
3715
3716                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
3717                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3718                         clock-names = "aux", "cfg_ahb";
3719                         power-domains = <&rpmhpd SC8280XP_MX>;
3720
3721                         #clock-cells = <1>;
3722                         #phy-cells = <0>;
3723
3724                         status = "disabled";
3725                 };
3726
3727                 dispcc1: clock-controller@22100000 {
3728                         compatible = "qcom,sc8280xp-dispcc1";
3729                         reg = <0 0x22100000 0 0x20000>;
3730
3731                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3732                                  <&rpmhcc RPMH_CXO_CLK>,
3733                                  <0>,
3734                                  <&mdss1_dp0_phy 0>,
3735                                  <&mdss1_dp0_phy 1>,
3736                                  <&mdss1_dp1_phy 0>,
3737                                  <&mdss1_dp1_phy 1>,
3738                                  <&mdss1_dp2_phy 0>,
3739                                  <&mdss1_dp2_phy 1>,
3740                                  <&mdss1_dp3_phy 0>,
3741                                  <&mdss1_dp3_phy 1>,
3742                                  <0>,
3743                                  <0>,
3744                                  <0>,
3745                                  <0>;
3746                         power-domains = <&rpmhpd SC8280XP_MMCX>;
3747
3748                         #clock-cells = <1>;
3749                         #power-domain-cells = <1>;
3750                         #reset-cells = <1>;
3751
3752                         status = "disabled";
3753                 };
3754         };
3755
3756         sound: sound {
3757         };
3758
3759         thermal-zones {
3760                 cpu0-thermal {
3761                         polling-delay-passive = <250>;
3762                         polling-delay = <1000>;
3763
3764                         thermal-sensors = <&tsens0 1>;
3765
3766                         trips {
3767                                 cpu-crit {
3768                                         temperature = <110000>;
3769                                         hysteresis = <1000>;
3770                                         type = "critical";
3771                                 };
3772                         };
3773                 };
3774
3775                 cpu1-thermal {
3776                         polling-delay-passive = <250>;
3777                         polling-delay = <1000>;
3778
3779                         thermal-sensors = <&tsens0 2>;
3780
3781                         trips {
3782                                 cpu-crit {
3783                                         temperature = <110000>;
3784                                         hysteresis = <1000>;
3785                                         type = "critical";
3786                                 };
3787                         };
3788                 };
3789
3790                 cpu2-thermal {
3791                         polling-delay-passive = <250>;
3792                         polling-delay = <1000>;
3793
3794                         thermal-sensors = <&tsens0 3>;
3795
3796                         trips {
3797                                 cpu-crit {
3798                                         temperature = <110000>;
3799                                         hysteresis = <1000>;
3800                                         type = "critical";
3801                                 };
3802                         };
3803                 };
3804
3805                 cpu3-thermal {
3806                         polling-delay-passive = <250>;
3807                         polling-delay = <1000>;
3808
3809                         thermal-sensors = <&tsens0 4>;
3810
3811                         trips {
3812                                 cpu-crit {
3813                                         temperature = <110000>;
3814                                         hysteresis = <1000>;
3815                                         type = "critical";
3816                                 };
3817                         };
3818                 };
3819
3820                 cpu4-thermal {
3821                         polling-delay-passive = <250>;
3822                         polling-delay = <1000>;
3823
3824                         thermal-sensors = <&tsens0 5>;
3825
3826                         trips {
3827                                 cpu-crit {
3828                                         temperature = <110000>;
3829                                         hysteresis = <1000>;
3830                                         type = "critical";
3831                                 };
3832                         };
3833                 };
3834
3835                 cpu5-thermal {
3836                         polling-delay-passive = <250>;
3837                         polling-delay = <1000>;
3838
3839                         thermal-sensors = <&tsens0 6>;
3840
3841                         trips {
3842                                 cpu-crit {
3843                                         temperature = <110000>;
3844                                         hysteresis = <1000>;
3845                                         type = "critical";
3846                                 };
3847                         };
3848                 };
3849
3850                 cpu6-thermal {
3851                         polling-delay-passive = <250>;
3852                         polling-delay = <1000>;
3853
3854                         thermal-sensors = <&tsens0 7>;
3855
3856                         trips {
3857                                 cpu-crit {
3858                                         temperature = <110000>;
3859                                         hysteresis = <1000>;
3860                                         type = "critical";
3861                                 };
3862                         };
3863                 };
3864
3865                 cpu7-thermal {
3866                         polling-delay-passive = <250>;
3867                         polling-delay = <1000>;
3868
3869                         thermal-sensors = <&tsens0 8>;
3870
3871                         trips {
3872                                 cpu-crit {
3873                                         temperature = <110000>;
3874                                         hysteresis = <1000>;
3875                                         type = "critical";
3876                                 };
3877                         };
3878                 };
3879
3880                 cluster0-thermal {
3881                         polling-delay-passive = <250>;
3882                         polling-delay = <1000>;
3883
3884                         thermal-sensors = <&tsens0 9>;
3885
3886                         trips {
3887                                 cpu-crit {
3888                                         temperature = <110000>;
3889                                         hysteresis = <1000>;
3890                                         type = "critical";
3891                                 };
3892                         };
3893                 };
3894
3895                 mem-thermal {
3896                         polling-delay-passive = <250>;
3897                         polling-delay = <1000>;
3898
3899                         thermal-sensors = <&tsens1 15>;
3900
3901                         trips {
3902                                 trip-point0 {
3903                                         temperature = <90000>;
3904                                         hysteresis = <2000>;
3905                                         type = "hot";
3906                                 };
3907                         };
3908                 };
3909         };
3910
3911         timer {
3912                 compatible = "arm,armv8-timer";
3913                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3914                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3915                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3916                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3917         };
3918 };