1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
26 compatible = "fixed-clock";
27 clock-frequency = <76800000>;
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 clock-frequency = <32000>;
43 aop_mem: memory@80800000 {
44 reg = <0x0 0x80800000 0x0 0x60000>;
48 aop_cmd_db_mem: memory@80860000 {
49 reg = <0x0 0x80860000 0x0 0x20000>;
50 compatible = "qcom,cmd-db";
54 cpucp_mem: memory@80b00000 {
56 reg = <0x0 0x80b00000 0x0 0x100000>;
66 compatible = "arm,kryo";
68 enable-method = "psci";
69 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
72 next-level-cache = <&L2_0>;
75 next-level-cache = <&L3_0>;
84 compatible = "arm,kryo";
86 enable-method = "psci";
87 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
90 next-level-cache = <&L2_100>;
93 next-level-cache = <&L3_0>;
99 compatible = "arm,kryo";
101 enable-method = "psci";
102 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
105 next-level-cache = <&L2_200>;
107 compatible = "cache";
108 next-level-cache = <&L3_0>;
114 compatible = "arm,kryo";
116 enable-method = "psci";
117 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
120 next-level-cache = <&L2_300>;
122 compatible = "cache";
123 next-level-cache = <&L3_0>;
129 compatible = "arm,kryo";
131 enable-method = "psci";
132 cpu-idle-states = <&BIG_CPU_SLEEP_0
135 next-level-cache = <&L2_400>;
137 compatible = "cache";
138 next-level-cache = <&L3_0>;
144 compatible = "arm,kryo";
146 enable-method = "psci";
147 cpu-idle-states = <&BIG_CPU_SLEEP_0
150 next-level-cache = <&L2_500>;
152 compatible = "cache";
153 next-level-cache = <&L3_0>;
159 compatible = "arm,kryo";
161 enable-method = "psci";
162 cpu-idle-states = <&BIG_CPU_SLEEP_0
165 next-level-cache = <&L2_600>;
167 compatible = "cache";
168 next-level-cache = <&L3_0>;
174 compatible = "arm,kryo";
176 enable-method = "psci";
177 cpu-idle-states = <&BIG_CPU_SLEEP_0
180 next-level-cache = <&L2_700>;
182 compatible = "cache";
183 next-level-cache = <&L3_0>;
188 entry-method = "psci";
190 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
191 compatible = "arm,idle-state";
192 idle-state-name = "little-power-down";
193 arm,psci-suspend-param = <0x40000003>;
194 entry-latency-us = <549>;
195 exit-latency-us = <901>;
196 min-residency-us = <1774>;
200 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
201 compatible = "arm,idle-state";
202 idle-state-name = "little-rail-power-down";
203 arm,psci-suspend-param = <0x40000004>;
204 entry-latency-us = <702>;
205 exit-latency-us = <915>;
206 min-residency-us = <4001>;
210 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
211 compatible = "arm,idle-state";
212 idle-state-name = "big-power-down";
213 arm,psci-suspend-param = <0x40000003>;
214 entry-latency-us = <523>;
215 exit-latency-us = <1244>;
216 min-residency-us = <2207>;
220 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
221 compatible = "arm,idle-state";
222 idle-state-name = "big-rail-power-down";
223 arm,psci-suspend-param = <0x40000004>;
224 entry-latency-us = <526>;
225 exit-latency-us = <1854>;
226 min-residency-us = <5555>;
230 CLUSTER_SLEEP_0: cluster-sleep-0 {
231 compatible = "arm,idle-state";
232 idle-state-name = "cluster-power-down";
233 arm,psci-suspend-param = <0x40003444>;
234 entry-latency-us = <3263>;
235 exit-latency-us = <6562>;
236 min-residency-us = <9926>;
243 device_type = "memory";
244 /* We expect the bootloader to fill in the size */
245 reg = <0 0x80000000 0 0>;
250 compatible = "qcom,scm-sc7280", "qcom,scm";
255 compatible = "arm,armv8-pmuv3";
256 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
260 compatible = "arm,psci-1.0";
265 #address-cells = <2>;
267 ranges = <0 0 0 0 0x10 0>;
268 dma-ranges = <0 0 0 0 0x10 0>;
269 compatible = "simple-bus";
271 gcc: clock-controller@100000 {
272 compatible = "qcom,gcc-sc7280";
273 reg = <0 0x00100000 0 0x1f0000>;
274 clocks = <&rpmhcc RPMH_CXO_CLK>,
275 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
276 <0>, <0>, <0>, <0>, <0>, <0>;
277 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
278 "pcie_0_pipe_clk", "pcie_1_pipe-clk",
279 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
280 "ufs_phy_tx_symbol_0_clk",
281 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
284 #power-domain-cells = <1>;
287 ipcc: mailbox@408000 {
288 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
289 reg = <0 0x00408000 0 0x1000>;
290 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
291 interrupt-controller;
292 #interrupt-cells = <3>;
296 qupv3_id_0: geniqup@9c0000 {
297 compatible = "qcom,geni-se-qup";
298 reg = <0 0x009c0000 0 0x2000>;
299 clock-names = "m-ahb", "s-ahb";
300 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
301 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
302 #address-cells = <2>;
307 uart5: serial@994000 {
308 compatible = "qcom,geni-debug-uart";
309 reg = <0 0x00994000 0 0x4000>;
311 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&qup_uart5_default>;
314 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
320 compatible = "arm,coresight-stm", "arm,primecell";
321 reg = <0 0x06002000 0 0x1000>,
322 <0 0x16280000 0 0x180000>;
323 reg-names = "stm-base", "stm-stimulus-base";
325 clocks = <&aoss_qmp>;
326 clock-names = "apb_pclk";
331 remote-endpoint = <&funnel0_in7>;
338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
339 reg = <0 0x06041000 0 0x1000>;
341 clocks = <&aoss_qmp>;
342 clock-names = "apb_pclk";
346 funnel0_out: endpoint {
347 remote-endpoint = <&merge_funnel_in0>;
353 #address-cells = <1>;
358 funnel0_in7: endpoint {
359 remote-endpoint = <&stm_out>;
366 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
367 reg = <0 0x06042000 0 0x1000>;
369 clocks = <&aoss_qmp>;
370 clock-names = "apb_pclk";
374 funnel1_out: endpoint {
375 remote-endpoint = <&merge_funnel_in1>;
381 #address-cells = <1>;
386 funnel1_in4: endpoint {
387 remote-endpoint = <&apss_merge_funnel_out>;
394 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
395 reg = <0 0x06045000 0 0x1000>;
397 clocks = <&aoss_qmp>;
398 clock-names = "apb_pclk";
402 merge_funnel_out: endpoint {
403 remote-endpoint = <&swao_funnel_in>;
409 #address-cells = <1>;
414 merge_funnel_in0: endpoint {
415 remote-endpoint = <&funnel0_out>;
421 merge_funnel_in1: endpoint {
422 remote-endpoint = <&funnel1_out>;
429 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
430 reg = <0 0x06046000 0 0x1000>;
432 clocks = <&aoss_qmp>;
433 clock-names = "apb_pclk";
437 replicator_out: endpoint {
438 remote-endpoint = <&etr_in>;
445 replicator_in: endpoint {
446 remote-endpoint = <&swao_replicator_out>;
453 compatible = "arm,coresight-tmc", "arm,primecell";
454 reg = <0 0x06048000 0 0x1000>;
455 iommus = <&apps_smmu 0x04c0 0>;
457 clocks = <&aoss_qmp>;
458 clock-names = "apb_pclk";
464 remote-endpoint = <&replicator_out>;
471 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
472 reg = <0 0x06b04000 0 0x1000>;
474 clocks = <&aoss_qmp>;
475 clock-names = "apb_pclk";
479 swao_funnel_out: endpoint {
480 remote-endpoint = <&etf_in>;
486 #address-cells = <1>;
491 swao_funnel_in: endpoint {
492 remote-endpoint = <&merge_funnel_out>;
499 compatible = "arm,coresight-tmc", "arm,primecell";
500 reg = <0 0x06b05000 0 0x1000>;
502 clocks = <&aoss_qmp>;
503 clock-names = "apb_pclk";
508 remote-endpoint = <&swao_replicator_in>;
516 remote-endpoint = <&swao_funnel_out>;
523 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
524 reg = <0 0x06b06000 0 0x1000>;
526 clocks = <&aoss_qmp>;
527 clock-names = "apb_pclk";
528 qcom,replicator-loses-context;
532 swao_replicator_out: endpoint {
533 remote-endpoint = <&replicator_in>;
540 swao_replicator_in: endpoint {
541 remote-endpoint = <&etf_out>;
548 compatible = "arm,coresight-etm4x", "arm,primecell";
549 reg = <0 0x07040000 0 0x1000>;
553 clocks = <&aoss_qmp>;
554 clock-names = "apb_pclk";
555 arm,coresight-loses-context-with-cpu;
561 remote-endpoint = <&apss_funnel_in0>;
568 compatible = "arm,coresight-etm4x", "arm,primecell";
569 reg = <0 0x07140000 0 0x1000>;
573 clocks = <&aoss_qmp>;
574 clock-names = "apb_pclk";
575 arm,coresight-loses-context-with-cpu;
581 remote-endpoint = <&apss_funnel_in1>;
588 compatible = "arm,coresight-etm4x", "arm,primecell";
589 reg = <0 0x07240000 0 0x1000>;
593 clocks = <&aoss_qmp>;
594 clock-names = "apb_pclk";
595 arm,coresight-loses-context-with-cpu;
601 remote-endpoint = <&apss_funnel_in2>;
608 compatible = "arm,coresight-etm4x", "arm,primecell";
609 reg = <0 0x07340000 0 0x1000>;
613 clocks = <&aoss_qmp>;
614 clock-names = "apb_pclk";
615 arm,coresight-loses-context-with-cpu;
621 remote-endpoint = <&apss_funnel_in3>;
628 compatible = "arm,coresight-etm4x", "arm,primecell";
629 reg = <0 0x07440000 0 0x1000>;
633 clocks = <&aoss_qmp>;
634 clock-names = "apb_pclk";
635 arm,coresight-loses-context-with-cpu;
641 remote-endpoint = <&apss_funnel_in4>;
648 compatible = "arm,coresight-etm4x", "arm,primecell";
649 reg = <0 0x07540000 0 0x1000>;
653 clocks = <&aoss_qmp>;
654 clock-names = "apb_pclk";
655 arm,coresight-loses-context-with-cpu;
661 remote-endpoint = <&apss_funnel_in5>;
668 compatible = "arm,coresight-etm4x", "arm,primecell";
669 reg = <0 0x07640000 0 0x1000>;
673 clocks = <&aoss_qmp>;
674 clock-names = "apb_pclk";
675 arm,coresight-loses-context-with-cpu;
681 remote-endpoint = <&apss_funnel_in6>;
688 compatible = "arm,coresight-etm4x", "arm,primecell";
689 reg = <0 0x07740000 0 0x1000>;
693 clocks = <&aoss_qmp>;
694 clock-names = "apb_pclk";
695 arm,coresight-loses-context-with-cpu;
701 remote-endpoint = <&apss_funnel_in7>;
707 funnel@7800000 { /* APSS Funnel */
708 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
709 reg = <0 0x07800000 0 0x1000>;
711 clocks = <&aoss_qmp>;
712 clock-names = "apb_pclk";
716 apss_funnel_out: endpoint {
717 remote-endpoint = <&apss_merge_funnel_in>;
723 #address-cells = <1>;
728 apss_funnel_in0: endpoint {
729 remote-endpoint = <&etm0_out>;
735 apss_funnel_in1: endpoint {
736 remote-endpoint = <&etm1_out>;
742 apss_funnel_in2: endpoint {
743 remote-endpoint = <&etm2_out>;
749 apss_funnel_in3: endpoint {
750 remote-endpoint = <&etm3_out>;
756 apss_funnel_in4: endpoint {
757 remote-endpoint = <&etm4_out>;
763 apss_funnel_in5: endpoint {
764 remote-endpoint = <&etm5_out>;
770 apss_funnel_in6: endpoint {
771 remote-endpoint = <&etm6_out>;
777 apss_funnel_in7: endpoint {
778 remote-endpoint = <&etm7_out>;
785 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
786 reg = <0 0x07810000 0 0x1000>;
788 clocks = <&aoss_qmp>;
789 clock-names = "apb_pclk";
793 apss_merge_funnel_out: endpoint {
794 remote-endpoint = <&funnel1_in4>;
801 apss_merge_funnel_in: endpoint {
802 remote-endpoint = <&apss_funnel_out>;
808 system-cache-controller@9200000 {
809 compatible = "qcom,sc7280-llcc";
810 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
811 reg-names = "llcc_base", "llcc_broadcast_base";
812 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
815 pdc: interrupt-controller@b220000 {
816 compatible = "qcom,sc7280-pdc", "qcom,pdc";
817 reg = <0 0x0b220000 0 0x30000>;
818 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
819 <55 306 4>, <59 312 3>, <62 374 2>,
820 <64 434 2>, <66 438 3>, <69 86 1>,
821 <70 520 54>, <124 609 31>, <155 63 1>,
823 #interrupt-cells = <2>;
824 interrupt-parent = <&intc>;
825 interrupt-controller;
828 aoss_qmp: power-controller@c300000 {
829 compatible = "qcom,sc7280-aoss-qmp";
830 reg = <0 0x0c300000 0 0x100000>;
831 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
832 IPCC_MPROC_SIGNAL_GLINK_QMP
833 IRQ_TYPE_EDGE_RISING>;
834 mboxes = <&ipcc IPCC_CLIENT_AOP
835 IPCC_MPROC_SIGNAL_GLINK_QMP>;
838 #power-domain-cells = <1>;
841 spmi_bus: spmi@c440000 {
842 compatible = "qcom,spmi-pmic-arb";
843 reg = <0 0x0c440000 0 0x1100>,
844 <0 0x0c600000 0 0x2000000>,
845 <0 0x0e600000 0 0x100000>,
846 <0 0x0e700000 0 0xa0000>,
847 <0 0x0c40a000 0 0x26000>;
848 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
849 interrupt-names = "periph_irq";
850 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
853 #address-cells = <1>;
855 interrupt-controller;
856 #interrupt-cells = <4>;
859 tlmm: pinctrl@f100000 {
860 compatible = "qcom,sc7280-pinctrl";
861 reg = <0 0x0f100000 0 0x300000>;
862 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
865 interrupt-controller;
866 #interrupt-cells = <2>;
867 gpio-ranges = <&tlmm 0 0 175>;
868 wakeup-parent = <&pdc>;
870 qup_uart5_default: qup-uart5-default {
871 pins = "gpio46", "gpio47";
876 apps_smmu: iommu@15000000 {
877 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
878 reg = <0 0x15000000 0 0x100000>;
880 #global-interrupts = <1>;
882 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
904 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
965 intc: interrupt-controller@17a00000 {
966 compatible = "arm,gic-v3";
967 #address-cells = <2>;
970 #interrupt-cells = <3>;
971 interrupt-controller;
972 reg = <0 0x17a00000 0 0x10000>, /* GICD */
973 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
974 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
977 compatible = "arm,gic-v3-its";
980 reg = <0 0x17a40000 0 0x20000>;
986 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
987 reg = <0 0x17c10000 0 0x1000>;
988 clocks = <&sleep_clk>;
989 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
993 #address-cells = <2>;
996 compatible = "arm,armv7-timer-mem";
997 reg = <0 0x17c20000 0 0x1000>;
1001 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1003 reg = <0 0x17c21000 0 0x1000>,
1004 <0 0x17c22000 0 0x1000>;
1009 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1010 reg = <0 0x17c23000 0 0x1000>;
1011 status = "disabled";
1016 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1017 reg = <0 0x17c25000 0 0x1000>;
1018 status = "disabled";
1023 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1024 reg = <0 0x17c27000 0 0x1000>;
1025 status = "disabled";
1030 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1031 reg = <0 0x17c29000 0 0x1000>;
1032 status = "disabled";
1037 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1038 reg = <0 0x17c2b000 0 0x1000>;
1039 status = "disabled";
1044 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1045 reg = <0 0x17c2d000 0 0x1000>;
1046 status = "disabled";
1050 apps_rsc: rsc@18200000 {
1051 compatible = "qcom,rpmh-rsc";
1052 reg = <0 0x18200000 0 0x10000>,
1053 <0 0x18210000 0 0x10000>,
1054 <0 0x18220000 0 0x10000>;
1055 reg-names = "drv-0", "drv-1", "drv-2";
1056 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1059 qcom,tcs-offset = <0xd00>;
1061 qcom,tcs-config = <ACTIVE_TCS 2>,
1066 rpmhpd: power-controller {
1067 compatible = "qcom,sc7280-rpmhpd";
1068 #power-domain-cells = <1>;
1069 operating-points-v2 = <&rpmhpd_opp_table>;
1071 rpmhpd_opp_table: opp-table {
1072 compatible = "operating-points-v2";
1074 rpmhpd_opp_ret: opp1 {
1075 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1078 rpmhpd_opp_low_svs: opp2 {
1079 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1082 rpmhpd_opp_svs: opp3 {
1083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1086 rpmhpd_opp_svs_l1: opp4 {
1087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1090 rpmhpd_opp_svs_l2: opp5 {
1091 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1094 rpmhpd_opp_nom: opp6 {
1095 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1098 rpmhpd_opp_nom_l1: opp7 {
1099 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1102 rpmhpd_opp_turbo: opp8 {
1103 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1106 rpmhpd_opp_turbo_l1: opp9 {
1107 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1112 rpmhcc: clock-controller {
1113 compatible = "qcom,sc7280-rpmh-clk";
1114 clocks = <&xo_board>;
1122 compatible = "arm,armv8-timer";
1123 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1124 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1125 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1126 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;