1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
22 device_type = "memory";
23 /* We expect the bootloader to fill in the reg */
32 hyp_mem: memory@85800000 {
33 reg = <0x0 0x85800000 0x0 0x600000>;
37 xbl_mem: memory@85e00000 {
38 reg = <0x0 0x85e00000 0x0 0x100000>;
42 smem_mem: smem-mem@86000000 {
43 reg = <0x0 0x86000000 0x0 0x200000>;
47 tz_mem: memory@86200000 {
48 reg = <0x0 0x86200000 0x0 0x2d00000>;
52 rmtfs_mem: memory@88f00000 {
53 compatible = "qcom,rmtfs-mem";
54 reg = <0x0 0x88f00000 0x0 0x200000>;
61 spss_mem: memory@8ab00000 {
62 reg = <0x0 0x8ab00000 0x0 0x700000>;
66 adsp_mem: memory@8b200000 {
67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
71 mpss_mem: memory@8cc00000 {
72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
76 venus_mem: memory@93c00000 {
77 reg = <0x0 0x93c00000 0x0 0x500000>;
81 mba_mem: memory@94100000 {
82 reg = <0x0 0x94100000 0x0 0x200000>;
86 slpi_mem: memory@94300000 {
87 reg = <0x0 0x94300000 0x0 0xf00000>;
91 ipa_fw_mem: memory@95200000 {
92 reg = <0x0 0x95200000 0x0 0x10000>;
96 ipa_gsi_mem: memory@95210000 {
97 reg = <0x0 0x95210000 0x0 0x5000>;
101 gpu_mem: memory@95600000 {
102 reg = <0x0 0x95600000 0x0 0x100000>;
106 wlan_msa_mem: memory@95700000 {
107 reg = <0x0 0x95700000 0x0 0x100000>;
114 compatible = "fixed-clock";
116 clock-frequency = <19200000>;
117 clock-output-names = "xo_board";
121 compatible = "fixed-clock";
123 clock-frequency = <32764>;
128 #address-cells = <2>;
133 compatible = "qcom,kryo280";
135 enable-method = "psci";
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
138 next-level-cache = <&L2_0>;
140 compatible = "arm,arch-cache";
144 compatible = "arm,arch-cache";
147 compatible = "arm,arch-cache";
153 compatible = "qcom,kryo280";
155 enable-method = "psci";
156 capacity-dmips-mhz = <1024>;
157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
158 next-level-cache = <&L2_0>;
160 compatible = "arm,arch-cache";
163 compatible = "arm,arch-cache";
169 compatible = "qcom,kryo280";
171 enable-method = "psci";
172 capacity-dmips-mhz = <1024>;
173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
174 next-level-cache = <&L2_0>;
176 compatible = "arm,arch-cache";
179 compatible = "arm,arch-cache";
185 compatible = "qcom,kryo280";
187 enable-method = "psci";
188 capacity-dmips-mhz = <1024>;
189 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
190 next-level-cache = <&L2_0>;
192 compatible = "arm,arch-cache";
195 compatible = "arm,arch-cache";
201 compatible = "qcom,kryo280";
203 enable-method = "psci";
204 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L2_1>;
208 compatible = "arm,arch-cache";
211 L1_I_100: l1-icache {
212 compatible = "arm,arch-cache";
214 L1_D_100: l1-dcache {
215 compatible = "arm,arch-cache";
221 compatible = "qcom,kryo280";
223 enable-method = "psci";
224 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L2_1>;
227 L1_I_101: l1-icache {
228 compatible = "arm,arch-cache";
230 L1_D_101: l1-dcache {
231 compatible = "arm,arch-cache";
237 compatible = "qcom,kryo280";
239 enable-method = "psci";
240 capacity-dmips-mhz = <1536>;
241 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
242 next-level-cache = <&L2_1>;
243 L1_I_102: l1-icache {
244 compatible = "arm,arch-cache";
246 L1_D_102: l1-dcache {
247 compatible = "arm,arch-cache";
253 compatible = "qcom,kryo280";
255 enable-method = "psci";
256 capacity-dmips-mhz = <1536>;
257 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
258 next-level-cache = <&L2_1>;
259 L1_I_103: l1-icache {
260 compatible = "arm,arch-cache";
262 L1_D_103: l1-dcache {
263 compatible = "arm,arch-cache";
306 entry-method = "psci";
308 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
309 compatible = "arm,idle-state";
310 idle-state-name = "little-retention";
311 arm,psci-suspend-param = <0x00000002>;
312 entry-latency-us = <81>;
313 exit-latency-us = <86>;
314 min-residency-us = <200>;
317 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
318 compatible = "arm,idle-state";
319 idle-state-name = "little-power-collapse";
320 arm,psci-suspend-param = <0x40000003>;
321 entry-latency-us = <273>;
322 exit-latency-us = <612>;
323 min-residency-us = <1000>;
327 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
328 compatible = "arm,idle-state";
329 idle-state-name = "big-retention";
330 arm,psci-suspend-param = <0x00000002>;
331 entry-latency-us = <79>;
332 exit-latency-us = <82>;
333 min-residency-us = <200>;
336 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
337 compatible = "arm,idle-state";
338 idle-state-name = "big-power-collapse";
339 arm,psci-suspend-param = <0x40000003>;
340 entry-latency-us = <336>;
341 exit-latency-us = <525>;
342 min-residency-us = <1000>;
350 compatible = "qcom,scm-msm8998", "qcom,scm";
355 compatible = "qcom,tcsr-mutex";
356 syscon = <&tcsr_mutex_regs 0 0x1000>;
361 compatible = "arm,psci-1.0";
366 compatible = "qcom,glink-rpm";
368 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
369 qcom,rpm-msg-ram = <&rpm_msg_ram>;
370 mboxes = <&apcs_glb 0>;
372 rpm_requests: rpm-requests {
373 compatible = "qcom,rpm-msm8998";
374 qcom,glink-channels = "rpm_requests";
376 rpmcc: clock-controller {
377 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
381 rpmpd: power-controller {
382 compatible = "qcom,msm8998-rpmpd";
383 #power-domain-cells = <1>;
384 operating-points-v2 = <&rpmpd_opp_table>;
386 rpmpd_opp_table: opp-table {
387 compatible = "operating-points-v2";
389 rpmpd_opp_ret: opp1 {
390 opp-level = <RPM_SMD_LEVEL_RETENTION>;
393 rpmpd_opp_ret_plus: opp2 {
394 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
397 rpmpd_opp_min_svs: opp3 {
398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
401 rpmpd_opp_low_svs: opp4 {
402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
405 rpmpd_opp_svs: opp5 {
406 opp-level = <RPM_SMD_LEVEL_SVS>;
409 rpmpd_opp_svs_plus: opp6 {
410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
413 rpmpd_opp_nom: opp7 {
414 opp-level = <RPM_SMD_LEVEL_NOM>;
417 rpmpd_opp_nom_plus: opp8 {
418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
421 rpmpd_opp_turbo: opp9 {
422 opp-level = <RPM_SMD_LEVEL_TURBO>;
425 rpmpd_opp_turbo_plus: opp10 {
426 opp-level = <RPM_SMD_LEVEL_BINNING>;
434 compatible = "qcom,smem";
435 memory-region = <&smem_mem>;
436 hwlocks = <&tcsr_mutex 3>;
440 compatible = "qcom,smp2p";
441 qcom,smem = <443>, <429>;
443 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
445 mboxes = <&apcs_glb 10>;
447 qcom,local-pid = <0>;
448 qcom,remote-pid = <2>;
450 adsp_smp2p_out: master-kernel {
451 qcom,entry-name = "master-kernel";
452 #qcom,smem-state-cells = <1>;
455 adsp_smp2p_in: slave-kernel {
456 qcom,entry-name = "slave-kernel";
458 interrupt-controller;
459 #interrupt-cells = <2>;
464 compatible = "qcom,smp2p";
465 qcom,smem = <435>, <428>;
466 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
467 mboxes = <&apcs_glb 14>;
468 qcom,local-pid = <0>;
469 qcom,remote-pid = <1>;
471 modem_smp2p_out: master-kernel {
472 qcom,entry-name = "master-kernel";
473 #qcom,smem-state-cells = <1>;
476 modem_smp2p_in: slave-kernel {
477 qcom,entry-name = "slave-kernel";
478 interrupt-controller;
479 #interrupt-cells = <2>;
484 compatible = "qcom,smp2p";
485 qcom,smem = <481>, <430>;
486 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
487 mboxes = <&apcs_glb 26>;
488 qcom,local-pid = <0>;
489 qcom,remote-pid = <3>;
491 slpi_smp2p_out: master-kernel {
492 qcom,entry-name = "master-kernel";
493 #qcom,smem-state-cells = <1>;
496 slpi_smp2p_in: slave-kernel {
497 qcom,entry-name = "slave-kernel";
498 interrupt-controller;
499 #interrupt-cells = <2>;
505 polling-delay-passive = <250>;
506 polling-delay = <1000>;
508 thermal-sensors = <&tsens0 1>;
511 cpu0_alert0: trip-point0 {
512 temperature = <75000>;
517 cpu0_crit: cpu_crit {
518 temperature = <110000>;
526 polling-delay-passive = <250>;
527 polling-delay = <1000>;
529 thermal-sensors = <&tsens0 2>;
532 cpu1_alert0: trip-point0 {
533 temperature = <75000>;
538 cpu1_crit: cpu_crit {
539 temperature = <110000>;
547 polling-delay-passive = <250>;
548 polling-delay = <1000>;
550 thermal-sensors = <&tsens0 3>;
553 cpu2_alert0: trip-point0 {
554 temperature = <75000>;
559 cpu2_crit: cpu_crit {
560 temperature = <110000>;
568 polling-delay-passive = <250>;
569 polling-delay = <1000>;
571 thermal-sensors = <&tsens0 4>;
574 cpu3_alert0: trip-point0 {
575 temperature = <75000>;
580 cpu3_crit: cpu_crit {
581 temperature = <110000>;
589 polling-delay-passive = <250>;
590 polling-delay = <1000>;
592 thermal-sensors = <&tsens0 7>;
595 cpu4_alert0: trip-point0 {
596 temperature = <75000>;
601 cpu4_crit: cpu_crit {
602 temperature = <110000>;
610 polling-delay-passive = <250>;
611 polling-delay = <1000>;
613 thermal-sensors = <&tsens0 8>;
616 cpu5_alert0: trip-point0 {
617 temperature = <75000>;
622 cpu5_crit: cpu_crit {
623 temperature = <110000>;
631 polling-delay-passive = <250>;
632 polling-delay = <1000>;
634 thermal-sensors = <&tsens0 9>;
637 cpu6_alert0: trip-point0 {
638 temperature = <75000>;
643 cpu6_crit: cpu_crit {
644 temperature = <110000>;
652 polling-delay-passive = <250>;
653 polling-delay = <1000>;
655 thermal-sensors = <&tsens0 10>;
658 cpu7_alert0: trip-point0 {
659 temperature = <75000>;
664 cpu7_crit: cpu_crit {
665 temperature = <110000>;
673 polling-delay-passive = <250>;
674 polling-delay = <1000>;
676 thermal-sensors = <&tsens0 12>;
679 gpu1_alert0: trip-point0 {
680 temperature = <90000>;
688 polling-delay-passive = <250>;
689 polling-delay = <1000>;
691 thermal-sensors = <&tsens0 13>;
694 gpu2_alert0: trip-point0 {
695 temperature = <90000>;
703 polling-delay-passive = <250>;
704 polling-delay = <1000>;
706 thermal-sensors = <&tsens0 5>;
709 cluster0_mhm_alert0: trip-point0 {
710 temperature = <90000>;
718 polling-delay-passive = <250>;
719 polling-delay = <1000>;
721 thermal-sensors = <&tsens0 6>;
724 cluster1_mhm_alert0: trip-point0 {
725 temperature = <90000>;
732 cluster1-l2-thermal {
733 polling-delay-passive = <250>;
734 polling-delay = <1000>;
736 thermal-sensors = <&tsens0 11>;
739 cluster1_l2_alert0: trip-point0 {
740 temperature = <90000>;
748 polling-delay-passive = <250>;
749 polling-delay = <1000>;
751 thermal-sensors = <&tsens1 1>;
754 modem_alert0: trip-point0 {
755 temperature = <90000>;
763 polling-delay-passive = <250>;
764 polling-delay = <1000>;
766 thermal-sensors = <&tsens1 2>;
769 mem_alert0: trip-point0 {
770 temperature = <90000>;
778 polling-delay-passive = <250>;
779 polling-delay = <1000>;
781 thermal-sensors = <&tsens1 3>;
784 wlan_alert0: trip-point0 {
785 temperature = <90000>;
793 polling-delay-passive = <250>;
794 polling-delay = <1000>;
796 thermal-sensors = <&tsens1 4>;
799 q6_dsp_alert0: trip-point0 {
800 temperature = <90000>;
808 polling-delay-passive = <250>;
809 polling-delay = <1000>;
811 thermal-sensors = <&tsens1 5>;
814 camera_alert0: trip-point0 {
815 temperature = <90000>;
823 polling-delay-passive = <250>;
824 polling-delay = <1000>;
826 thermal-sensors = <&tsens1 6>;
829 multimedia_alert0: trip-point0 {
830 temperature = <90000>;
839 compatible = "arm,armv8-timer";
840 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
841 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
842 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
843 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
847 #address-cells = <1>;
849 ranges = <0 0 0 0xffffffff>;
850 compatible = "simple-bus";
852 gcc: clock-controller@100000 {
853 compatible = "qcom,gcc-msm8998";
856 #power-domain-cells = <1>;
857 reg = <0x00100000 0xb0000>;
860 rpm_msg_ram: memory@778000 {
861 compatible = "qcom,rpm-msg-ram";
862 reg = <0x00778000 0x7000>;
865 qfprom: qfprom@780000 {
866 compatible = "qcom,qfprom";
867 reg = <0x00780000 0x621c>;
868 #address-cells = <1>;
871 qusb2_hstx_trim: hstx-trim@423a {
877 tsens0: thermal@10ab000 {
878 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
879 reg = <0x010ab000 0x1000>, /* TM */
880 <0x010aa000 0x1000>; /* SROT */
881 #qcom,sensors = <14>;
882 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-names = "uplow", "critical";
885 #thermal-sensor-cells = <1>;
888 tsens1: thermal@10ae000 {
889 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
890 reg = <0x010ae000 0x1000>, /* TM */
891 <0x010ad000 0x1000>; /* SROT */
893 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
895 interrupt-names = "uplow", "critical";
896 #thermal-sensor-cells = <1>;
899 anoc1_smmu: iommu@1680000 {
900 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
901 reg = <0x01680000 0x10000>;
904 #global-interrupts = <0>;
906 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
907 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
908 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
909 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
910 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
911 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
914 anoc2_smmu: iommu@16c0000 {
915 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
916 reg = <0x016c0000 0x40000>;
919 #global-interrupts = <0>;
921 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
922 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
923 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
924 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
925 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
926 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
927 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
928 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
929 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
930 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
934 compatible = "qcom,pcie-msm8996";
935 reg = <0x01c00000 0x2000>,
938 <0x1b100000 0x100000>;
939 reg-names = "parf", "dbi", "elbi", "config";
941 linux,pci-domain = <0>;
942 bus-range = <0x00 0xff>;
943 #address-cells = <3>;
947 phy-names = "pciephy";
950 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
951 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
953 #interrupt-cells = <1>;
954 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
955 interrupt-names = "msi";
956 interrupt-map-mask = <0 0 0 0x7>;
957 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
958 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
959 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
960 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
963 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
964 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
965 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
966 <&gcc GCC_PCIE_0_AUX_CLK>;
967 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
969 power-domains = <&gcc PCIE_0_GDSC>;
970 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
971 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
974 pcie_phy: phy@1c06000 {
975 compatible = "qcom,msm8998-qmp-pcie-phy";
976 reg = <0x01c06000 0x18c>;
977 #address-cells = <1>;
982 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
983 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
984 <&gcc GCC_PCIE_CLKREF_CLK>;
985 clock-names = "aux", "cfg_ahb", "ref";
987 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988 reset-names = "phy", "common";
990 vdda-phy-supply = <&vreg_l1a_0p875>;
991 vdda-pll-supply = <&vreg_l2a_1p2>;
993 pciephy: lane@1c06800 {
994 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
997 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
998 clock-names = "pipe0";
999 clock-output-names = "pcie_0_pipe_clk_src";
1004 ufshc: ufshc@1da4000 {
1005 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1006 reg = <0x01da4000 0x2500>;
1007 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1008 phys = <&ufsphy_lanes>;
1009 phy-names = "ufsphy";
1010 lanes-per-direction = <2>;
1011 power-domains = <&gcc UFS_GDSC>;
1012 status = "disabled";
1021 "tx_lane0_sync_clk",
1022 "rx_lane0_sync_clk",
1023 "rx_lane1_sync_clk";
1025 <&gcc GCC_UFS_AXI_CLK>,
1026 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1027 <&gcc GCC_UFS_AHB_CLK>,
1028 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1029 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1030 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1031 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1032 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1034 <50000000 200000000>,
1037 <37500000 150000000>,
1043 resets = <&gcc GCC_UFS_BCR>;
1044 reset-names = "rst";
1047 ufsphy: phy@1da7000 {
1048 compatible = "qcom,msm8998-qmp-ufs-phy";
1049 reg = <0x01da7000 0x18c>;
1050 #address-cells = <1>;
1052 status = "disabled";
1059 <&gcc GCC_UFS_CLKREF_CLK>,
1060 <&gcc GCC_UFS_PHY_AUX_CLK>;
1062 reset-names = "ufsphy";
1063 resets = <&ufshc 0>;
1065 ufsphy_lanes: lanes@1da7400 {
1066 reg = <0x01da7400 0x128>,
1075 tcsr_mutex_regs: syscon@1f40000 {
1076 compatible = "syscon";
1077 reg = <0x01f40000 0x40000>;
1080 tlmm: pinctrl@3400000 {
1081 compatible = "qcom,msm8998-pinctrl";
1082 reg = <0x03400000 0xc00000>;
1083 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1085 #gpio-cells = <0x2>;
1086 interrupt-controller;
1087 #interrupt-cells = <0x2>;
1089 sdc2_clk_on: sdc2_clk_on {
1093 drive-strength = <16>;
1097 sdc2_clk_off: sdc2_clk_off {
1101 drive-strength = <2>;
1105 sdc2_cmd_on: sdc2_cmd_on {
1109 drive-strength = <10>;
1113 sdc2_cmd_off: sdc2_cmd_off {
1117 drive-strength = <2>;
1121 sdc2_data_on: sdc2_data_on {
1125 drive-strength = <10>;
1129 sdc2_data_off: sdc2_data_off {
1133 drive-strength = <2>;
1137 sdc2_cd_on: sdc2_cd_on {
1146 drive-strength = <2>;
1150 sdc2_cd_off: sdc2_cd_off {
1159 drive-strength = <2>;
1163 blsp1_uart3_on: blsp1_uart3_on {
1166 function = "blsp_uart3_a";
1167 drive-strength = <2>;
1173 function = "blsp_uart3_a";
1174 drive-strength = <2>;
1180 function = "blsp_uart3_a";
1181 drive-strength = <2>;
1187 function = "blsp_uart3_a";
1188 drive-strength = <2>;
1193 blsp1_i2c1_default: blsp1-i2c1-default {
1194 pins = "gpio2", "gpio3";
1195 function = "blsp_i2c1";
1196 drive-strength = <2>;
1200 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1201 pins = "gpio2", "gpio3";
1202 function = "blsp_i2c1";
1203 drive-strength = <2>;
1207 blsp1_i2c2_default: blsp1-i2c2-default {
1208 pins = "gpio32", "gpio33";
1209 function = "blsp_i2c2";
1210 drive-strength = <2>;
1214 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1215 pins = "gpio32", "gpio33";
1216 function = "blsp_i2c2";
1217 drive-strength = <2>;
1221 blsp1_i2c3_default: blsp1-i2c3-default {
1222 pins = "gpio47", "gpio48";
1223 function = "blsp_i2c3";
1224 drive-strength = <2>;
1228 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1229 pins = "gpio47", "gpio48";
1230 function = "blsp_i2c3";
1231 drive-strength = <2>;
1235 blsp1_i2c4_default: blsp1-i2c4-default {
1236 pins = "gpio10", "gpio11";
1237 function = "blsp_i2c4";
1238 drive-strength = <2>;
1242 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1243 pins = "gpio10", "gpio11";
1244 function = "blsp_i2c4";
1245 drive-strength = <2>;
1249 blsp1_i2c5_default: blsp1-i2c5-default {
1250 pins = "gpio87", "gpio88";
1251 function = "blsp_i2c5";
1252 drive-strength = <2>;
1256 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1257 pins = "gpio87", "gpio88";
1258 function = "blsp_i2c5";
1259 drive-strength = <2>;
1263 blsp1_i2c6_default: blsp1-i2c6-default {
1264 pins = "gpio43", "gpio44";
1265 function = "blsp_i2c6";
1266 drive-strength = <2>;
1270 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1271 pins = "gpio43", "gpio44";
1272 function = "blsp_i2c6";
1273 drive-strength = <2>;
1276 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1277 blsp2_i2c1_default: blsp2-i2c1-default {
1278 pins = "gpio55", "gpio56";
1279 function = "blsp_i2c7";
1280 drive-strength = <2>;
1284 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1285 pins = "gpio55", "gpio56";
1286 function = "blsp_i2c7";
1287 drive-strength = <2>;
1291 blsp2_i2c2_default: blsp2-i2c2-default {
1292 pins = "gpio6", "gpio7";
1293 function = "blsp_i2c8";
1294 drive-strength = <2>;
1298 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1299 pins = "gpio6", "gpio7";
1300 function = "blsp_i2c8";
1301 drive-strength = <2>;
1305 blsp2_i2c3_default: blsp2-i2c3-default {
1306 pins = "gpio51", "gpio52";
1307 function = "blsp_i2c9";
1308 drive-strength = <2>;
1312 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1313 pins = "gpio51", "gpio52";
1314 function = "blsp_i2c9";
1315 drive-strength = <2>;
1319 blsp2_i2c4_default: blsp2-i2c4-default {
1320 pins = "gpio67", "gpio68";
1321 function = "blsp_i2c10";
1322 drive-strength = <2>;
1326 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1327 pins = "gpio67", "gpio68";
1328 function = "blsp_i2c10";
1329 drive-strength = <2>;
1333 blsp2_i2c5_default: blsp2-i2c5-default {
1334 pins = "gpio60", "gpio61";
1335 function = "blsp_i2c11";
1336 drive-strength = <2>;
1340 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1341 pins = "gpio60", "gpio61";
1342 function = "blsp_i2c11";
1343 drive-strength = <2>;
1347 blsp2_i2c6_default: blsp2-i2c6-default {
1348 pins = "gpio83", "gpio84";
1349 function = "blsp_i2c12";
1350 drive-strength = <2>;
1354 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1355 pins = "gpio83", "gpio84";
1356 function = "blsp_i2c12";
1357 drive-strength = <2>;
1362 remoteproc_mss: remoteproc@4080000 {
1363 compatible = "qcom,msm8998-mss-pil";
1364 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1365 reg-names = "qdsp6", "rmb";
1367 interrupts-extended =
1368 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1369 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1370 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1371 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1372 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1373 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1374 interrupt-names = "wdog", "fatal", "ready",
1375 "handover", "stop-ack",
1378 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1379 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1380 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1381 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1382 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1383 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1384 <&rpmcc RPM_SMD_QDSS_CLK>,
1385 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1386 clock-names = "iface", "bus", "mem", "gpll0_mss",
1387 "snoc_axi", "mnoc_axi", "qdss", "xo";
1389 qcom,smem-states = <&modem_smp2p_out 0>;
1390 qcom,smem-state-names = "stop";
1392 resets = <&gcc GCC_MSS_RESTART>;
1393 reset-names = "mss_restart";
1395 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1397 power-domains = <&rpmpd MSM8998_VDDCX>,
1398 <&rpmpd MSM8998_VDDMX>;
1399 power-domain-names = "cx", "mx";
1401 status = "disabled";
1404 memory-region = <&mba_mem>;
1408 memory-region = <&mpss_mem>;
1412 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1414 qcom,remote-pid = <1>;
1415 mboxes = <&apcs_glb 15>;
1419 gpucc: clock-controller@5065000 {
1420 compatible = "qcom,msm8998-gpucc";
1423 #power-domain-cells = <1>;
1424 reg = <0x05065000 0x9000>;
1426 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1427 <&gcc GPLL0_OUT_MAIN>;
1432 remoteproc_slpi: remoteproc@5800000 {
1433 compatible = "qcom,msm8998-slpi-pas";
1434 reg = <0x05800000 0x4040>;
1436 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1437 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1438 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1439 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1440 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1441 interrupt-names = "wdog", "fatal", "ready",
1442 "handover", "stop-ack";
1444 px-supply = <&vreg_lvs2a_1p8>;
1446 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1447 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1448 clock-names = "xo", "aggre2";
1450 memory-region = <&slpi_mem>;
1452 qcom,smem-states = <&slpi_smp2p_out 0>;
1453 qcom,smem-state-names = "stop";
1455 power-domains = <&rpmpd MSM8998_SSCCX>;
1456 power-domain-names = "ssc_cx";
1458 status = "disabled";
1461 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1463 qcom,remote-pid = <3>;
1464 mboxes = <&apcs_glb 27>;
1469 compatible = "arm,coresight-stm", "arm,primecell";
1470 reg = <0x06002000 0x1000>,
1471 <0x16280000 0x180000>;
1472 reg-names = "stm-base", "stm-data-base";
1473 status = "disabled";
1475 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1476 clock-names = "apb_pclk", "atclk";
1481 remote-endpoint = <&funnel0_in7>;
1487 funnel1: funnel@6041000 {
1488 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1489 reg = <0x06041000 0x1000>;
1490 status = "disabled";
1492 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1493 clock-names = "apb_pclk", "atclk";
1497 funnel0_out: endpoint {
1499 <&merge_funnel_in0>;
1505 #address-cells = <1>;
1510 funnel0_in7: endpoint {
1511 remote-endpoint = <&stm_out>;
1517 funnel2: funnel@6042000 {
1518 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1519 reg = <0x06042000 0x1000>;
1520 status = "disabled";
1522 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1523 clock-names = "apb_pclk", "atclk";
1527 funnel1_out: endpoint {
1529 <&merge_funnel_in1>;
1535 #address-cells = <1>;
1540 funnel1_in6: endpoint {
1542 <&apss_merge_funnel_out>;
1548 funnel3: funnel@6045000 {
1549 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1550 reg = <0x06045000 0x1000>;
1551 status = "disabled";
1553 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1554 clock-names = "apb_pclk", "atclk";
1558 merge_funnel_out: endpoint {
1566 #address-cells = <1>;
1571 merge_funnel_in0: endpoint {
1579 merge_funnel_in1: endpoint {
1587 replicator1: replicator@6046000 {
1588 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1589 reg = <0x06046000 0x1000>;
1590 status = "disabled";
1592 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1593 clock-names = "apb_pclk", "atclk";
1597 replicator_out: endpoint {
1598 remote-endpoint = <&etr_in>;
1605 replicator_in: endpoint {
1606 remote-endpoint = <&etf_out>;
1613 compatible = "arm,coresight-tmc", "arm,primecell";
1614 reg = <0x06047000 0x1000>;
1615 status = "disabled";
1617 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1618 clock-names = "apb_pclk", "atclk";
1633 <&merge_funnel_out>;
1640 compatible = "arm,coresight-tmc", "arm,primecell";
1641 reg = <0x06048000 0x1000>;
1642 status = "disabled";
1644 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1645 clock-names = "apb_pclk", "atclk";
1659 compatible = "arm,coresight-etm4x", "arm,primecell";
1660 reg = <0x07840000 0x1000>;
1661 status = "disabled";
1663 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1664 clock-names = "apb_pclk", "atclk";
1670 etm0_out: endpoint {
1679 compatible = "arm,coresight-etm4x", "arm,primecell";
1680 reg = <0x07940000 0x1000>;
1681 status = "disabled";
1683 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1684 clock-names = "apb_pclk", "atclk";
1690 etm1_out: endpoint {
1699 compatible = "arm,coresight-etm4x", "arm,primecell";
1700 reg = <0x07a40000 0x1000>;
1701 status = "disabled";
1703 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1704 clock-names = "apb_pclk", "atclk";
1710 etm2_out: endpoint {
1719 compatible = "arm,coresight-etm4x", "arm,primecell";
1720 reg = <0x07b40000 0x1000>;
1721 status = "disabled";
1723 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1724 clock-names = "apb_pclk", "atclk";
1730 etm3_out: endpoint {
1738 funnel4: funnel@7b60000 { /* APSS Funnel */
1739 compatible = "arm,coresight-etm4x", "arm,primecell";
1740 reg = <0x07b60000 0x1000>;
1741 status = "disabled";
1743 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1744 clock-names = "apb_pclk", "atclk";
1748 apss_funnel_out: endpoint {
1750 <&apss_merge_funnel_in>;
1756 #address-cells = <1>;
1761 apss_funnel_in0: endpoint {
1769 apss_funnel_in1: endpoint {
1777 apss_funnel_in2: endpoint {
1785 apss_funnel_in3: endpoint {
1793 apss_funnel_in4: endpoint {
1801 apss_funnel_in5: endpoint {
1809 apss_funnel_in6: endpoint {
1817 apss_funnel_in7: endpoint {
1825 funnel5: funnel@7b70000 {
1826 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1827 reg = <0x07b70000 0x1000>;
1828 status = "disabled";
1830 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1831 clock-names = "apb_pclk", "atclk";
1835 apss_merge_funnel_out: endpoint {
1844 apss_merge_funnel_in: endpoint {
1853 compatible = "arm,coresight-etm4x", "arm,primecell";
1854 reg = <0x07c40000 0x1000>;
1855 status = "disabled";
1857 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1858 clock-names = "apb_pclk", "atclk";
1863 etm4_out: endpoint {
1864 remote-endpoint = <&apss_funnel_in4>;
1870 compatible = "arm,coresight-etm4x", "arm,primecell";
1871 reg = <0x07d40000 0x1000>;
1872 status = "disabled";
1874 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1875 clock-names = "apb_pclk", "atclk";
1880 etm5_out: endpoint {
1881 remote-endpoint = <&apss_funnel_in5>;
1887 compatible = "arm,coresight-etm4x", "arm,primecell";
1888 reg = <0x07e40000 0x1000>;
1889 status = "disabled";
1891 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1892 clock-names = "apb_pclk", "atclk";
1897 etm6_out: endpoint {
1898 remote-endpoint = <&apss_funnel_in6>;
1904 compatible = "arm,coresight-etm4x", "arm,primecell";
1905 reg = <0x07f40000 0x1000>;
1906 status = "disabled";
1908 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1909 clock-names = "apb_pclk", "atclk";
1914 etm7_out: endpoint {
1915 remote-endpoint = <&apss_funnel_in7>;
1920 spmi_bus: spmi@800f000 {
1921 compatible = "qcom,spmi-pmic-arb";
1922 reg = <0x0800f000 0x1000>,
1923 <0x08400000 0x1000000>,
1924 <0x09400000 0x1000000>,
1925 <0x0a400000 0x220000>,
1926 <0x0800a000 0x3000>;
1927 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1928 interrupt-names = "periph_irq";
1929 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1932 #address-cells = <2>;
1934 interrupt-controller;
1935 #interrupt-cells = <4>;
1940 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1941 reg = <0x0a8f8800 0x400>;
1942 status = "disabled";
1943 #address-cells = <1>;
1947 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1948 <&gcc GCC_USB30_MASTER_CLK>,
1949 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
1950 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1951 <&gcc GCC_USB30_SLEEP_CLK>;
1952 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1955 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1956 <&gcc GCC_USB30_MASTER_CLK>;
1957 assigned-clock-rates = <19200000>, <120000000>;
1959 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1961 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1963 power-domains = <&gcc USB_30_GDSC>;
1965 resets = <&gcc GCC_USB_30_BCR>;
1967 usb3_dwc3: dwc3@a800000 {
1968 compatible = "snps,dwc3";
1969 reg = <0x0a800000 0xcd00>;
1970 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1971 snps,dis_u2_susphy_quirk;
1972 snps,dis_enblslpm_quirk;
1973 phys = <&qusb2phy>, <&usb1_ssphy>;
1974 phy-names = "usb2-phy", "usb3-phy";
1975 snps,has-lpm-erratum;
1976 snps,hird-threshold = /bits/ 8 <0x10>;
1980 usb3phy: phy@c010000 {
1981 compatible = "qcom,msm8998-qmp-usb3-phy";
1982 reg = <0x0c010000 0x18c>;
1983 status = "disabled";
1985 #address-cells = <1>;
1989 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1990 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1991 <&gcc GCC_USB3_CLKREF_CLK>;
1992 clock-names = "aux", "cfg_ahb", "ref";
1994 resets = <&gcc GCC_USB3_PHY_BCR>,
1995 <&gcc GCC_USB3PHY_PHY_BCR>;
1996 reset-names = "phy", "common";
1998 usb1_ssphy: lane@c010200 {
1999 reg = <0xc010200 0x128>,
2005 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2006 clock-names = "pipe0";
2007 clock-output-names = "usb3_phy_pipe_clk_src";
2011 qusb2phy: phy@c012000 {
2012 compatible = "qcom,msm8998-qusb2-phy";
2013 reg = <0x0c012000 0x2a8>;
2014 status = "disabled";
2017 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2018 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2019 clock-names = "cfg_ahb", "ref";
2021 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2023 nvmem-cells = <&qusb2_hstx_trim>;
2026 sdhc2: sdhci@c0a4900 {
2027 compatible = "qcom,sdhci-msm-v4";
2028 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2029 reg-names = "hc_mem", "core_mem";
2031 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2032 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-names = "hc_irq", "pwr_irq";
2035 clock-names = "iface", "core", "xo";
2036 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2037 <&gcc GCC_SDCC2_APPS_CLK>,
2040 status = "disabled";
2043 blsp1_dma: dma-controller@c144000 {
2044 compatible = "qcom,bam-v1.7.0";
2045 reg = <0x0c144000 0x25000>;
2046 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2047 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2048 clock-names = "bam_clk";
2051 qcom,controlled-remotely;
2052 num-channels = <18>;
2056 blsp1_uart3: serial@c171000 {
2057 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2058 reg = <0x0c171000 0x1000>;
2059 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2060 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2061 <&gcc GCC_BLSP1_AHB_CLK>;
2062 clock-names = "core", "iface";
2063 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2064 dma-names = "tx", "rx";
2065 pinctrl-names = "default";
2066 pinctrl-0 = <&blsp1_uart3_on>;
2067 status = "disabled";
2070 blsp1_i2c1: i2c@c175000 {
2071 compatible = "qcom,i2c-qup-v2.2.1";
2072 reg = <0x0c175000 0x600>;
2073 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2075 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2076 <&gcc GCC_BLSP1_AHB_CLK>;
2077 clock-names = "core", "iface";
2078 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2079 dma-names = "tx", "rx";
2080 pinctrl-names = "default", "sleep";
2081 pinctrl-0 = <&blsp1_i2c1_default>;
2082 pinctrl-1 = <&blsp1_i2c1_sleep>;
2083 clock-frequency = <400000>;
2085 status = "disabled";
2086 #address-cells = <1>;
2090 blsp1_i2c2: i2c@c176000 {
2091 compatible = "qcom,i2c-qup-v2.2.1";
2092 reg = <0x0c176000 0x600>;
2093 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2095 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2096 <&gcc GCC_BLSP1_AHB_CLK>;
2097 clock-names = "core", "iface";
2098 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2099 dma-names = "tx", "rx";
2100 pinctrl-names = "default", "sleep";
2101 pinctrl-0 = <&blsp1_i2c2_default>;
2102 pinctrl-1 = <&blsp1_i2c2_sleep>;
2103 clock-frequency = <400000>;
2105 status = "disabled";
2106 #address-cells = <1>;
2110 blsp1_i2c3: i2c@c177000 {
2111 compatible = "qcom,i2c-qup-v2.2.1";
2112 reg = <0x0c177000 0x600>;
2113 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2115 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2116 <&gcc GCC_BLSP1_AHB_CLK>;
2117 clock-names = "core", "iface";
2118 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2119 dma-names = "tx", "rx";
2120 pinctrl-names = "default", "sleep";
2121 pinctrl-0 = <&blsp1_i2c3_default>;
2122 pinctrl-1 = <&blsp1_i2c3_sleep>;
2123 clock-frequency = <400000>;
2125 status = "disabled";
2126 #address-cells = <1>;
2130 blsp1_i2c4: i2c@c178000 {
2131 compatible = "qcom,i2c-qup-v2.2.1";
2132 reg = <0x0c178000 0x600>;
2133 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2135 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2136 <&gcc GCC_BLSP1_AHB_CLK>;
2137 clock-names = "core", "iface";
2138 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2139 dma-names = "tx", "rx";
2140 pinctrl-names = "default", "sleep";
2141 pinctrl-0 = <&blsp1_i2c4_default>;
2142 pinctrl-1 = <&blsp1_i2c4_sleep>;
2143 clock-frequency = <400000>;
2145 status = "disabled";
2146 #address-cells = <1>;
2150 blsp1_i2c5: i2c@c179000 {
2151 compatible = "qcom,i2c-qup-v2.2.1";
2152 reg = <0x0c179000 0x600>;
2153 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2155 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2156 <&gcc GCC_BLSP1_AHB_CLK>;
2157 clock-names = "core", "iface";
2158 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2159 dma-names = "tx", "rx";
2160 pinctrl-names = "default", "sleep";
2161 pinctrl-0 = <&blsp1_i2c5_default>;
2162 pinctrl-1 = <&blsp1_i2c5_sleep>;
2163 clock-frequency = <400000>;
2165 status = "disabled";
2166 #address-cells = <1>;
2170 blsp1_i2c6: i2c@c17a000 {
2171 compatible = "qcom,i2c-qup-v2.2.1";
2172 reg = <0x0c17a000 0x600>;
2173 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2175 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2176 <&gcc GCC_BLSP1_AHB_CLK>;
2177 clock-names = "core", "iface";
2178 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2179 dma-names = "tx", "rx";
2180 pinctrl-names = "default", "sleep";
2181 pinctrl-0 = <&blsp1_i2c6_default>;
2182 pinctrl-1 = <&blsp1_i2c6_sleep>;
2183 clock-frequency = <400000>;
2185 status = "disabled";
2186 #address-cells = <1>;
2190 blsp2_dma: dma@c184000 {
2191 compatible = "qcom,bam-v1.7.0";
2192 reg = <0x0c184000 0x25000>;
2193 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2194 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2195 clock-names = "bam_clk";
2198 qcom,controlled-remotely;
2199 num-channels = <18>;
2203 blsp2_uart1: serial@c1b0000 {
2204 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2205 reg = <0x0c1b0000 0x1000>;
2206 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2207 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2208 <&gcc GCC_BLSP2_AHB_CLK>;
2209 clock-names = "core", "iface";
2210 status = "disabled";
2213 blsp2_i2c1: i2c@c1b5000 {
2214 compatible = "qcom,i2c-qup-v2.2.1";
2215 reg = <0x0c1b5000 0x600>;
2216 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2218 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2219 <&gcc GCC_BLSP2_AHB_CLK>;
2220 clock-names = "core", "iface";
2221 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2222 dma-names = "tx", "rx";
2223 pinctrl-names = "default", "sleep";
2224 pinctrl-0 = <&blsp2_i2c1_default>;
2225 pinctrl-1 = <&blsp2_i2c1_sleep>;
2226 clock-frequency = <400000>;
2228 status = "disabled";
2229 #address-cells = <1>;
2233 blsp2_i2c2: i2c@c1b6000 {
2234 compatible = "qcom,i2c-qup-v2.2.1";
2235 reg = <0x0c1b6000 0x600>;
2236 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2238 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2239 <&gcc GCC_BLSP2_AHB_CLK>;
2240 clock-names = "core", "iface";
2241 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2242 dma-names = "tx", "rx";
2243 pinctrl-names = "default", "sleep";
2244 pinctrl-0 = <&blsp2_i2c2_default>;
2245 pinctrl-1 = <&blsp2_i2c2_sleep>;
2246 clock-frequency = <400000>;
2248 status = "disabled";
2249 #address-cells = <1>;
2253 blsp2_i2c3: i2c@c1b7000 {
2254 compatible = "qcom,i2c-qup-v2.2.1";
2255 reg = <0x0c1b7000 0x600>;
2256 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2258 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2259 <&gcc GCC_BLSP2_AHB_CLK>;
2260 clock-names = "core", "iface";
2261 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2262 dma-names = "tx", "rx";
2263 pinctrl-names = "default", "sleep";
2264 pinctrl-0 = <&blsp2_i2c3_default>;
2265 pinctrl-1 = <&blsp2_i2c3_sleep>;
2266 clock-frequency = <400000>;
2268 status = "disabled";
2269 #address-cells = <1>;
2273 blsp2_i2c4: i2c@c1b8000 {
2274 compatible = "qcom,i2c-qup-v2.2.1";
2275 reg = <0x0c1b8000 0x600>;
2276 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2278 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2279 <&gcc GCC_BLSP2_AHB_CLK>;
2280 clock-names = "core", "iface";
2281 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2282 dma-names = "tx", "rx";
2283 pinctrl-names = "default", "sleep";
2284 pinctrl-0 = <&blsp2_i2c4_default>;
2285 pinctrl-1 = <&blsp2_i2c4_sleep>;
2286 clock-frequency = <400000>;
2288 status = "disabled";
2289 #address-cells = <1>;
2293 blsp2_i2c5: i2c@c1b9000 {
2294 compatible = "qcom,i2c-qup-v2.2.1";
2295 reg = <0x0c1b9000 0x600>;
2296 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2298 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2299 <&gcc GCC_BLSP2_AHB_CLK>;
2300 clock-names = "core", "iface";
2301 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2302 dma-names = "tx", "rx";
2303 pinctrl-names = "default", "sleep";
2304 pinctrl-0 = <&blsp2_i2c5_default>;
2305 pinctrl-1 = <&blsp2_i2c5_sleep>;
2306 clock-frequency = <400000>;
2308 status = "disabled";
2309 #address-cells = <1>;
2313 blsp2_i2c6: i2c@c1ba000 {
2314 compatible = "qcom,i2c-qup-v2.2.1";
2315 reg = <0x0c1ba000 0x600>;
2316 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2318 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2319 <&gcc GCC_BLSP2_AHB_CLK>;
2320 clock-names = "core", "iface";
2321 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2322 dma-names = "tx", "rx";
2323 pinctrl-names = "default", "sleep";
2324 pinctrl-0 = <&blsp2_i2c6_default>;
2325 pinctrl-1 = <&blsp2_i2c6_sleep>;
2326 clock-frequency = <400000>;
2328 status = "disabled";
2329 #address-cells = <1>;
2333 remoteproc_adsp: remoteproc@17300000 {
2334 compatible = "qcom,msm8998-adsp-pas";
2335 reg = <0x17300000 0x4040>;
2337 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2338 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2339 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2340 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2341 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2342 interrupt-names = "wdog", "fatal", "ready",
2343 "handover", "stop-ack";
2345 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2348 memory-region = <&adsp_mem>;
2350 qcom,smem-states = <&adsp_smp2p_out 0>;
2351 qcom,smem-state-names = "stop";
2353 power-domains = <&rpmpd MSM8998_VDDCX>;
2354 power-domain-names = "cx";
2356 status = "disabled";
2359 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2361 qcom,remote-pid = <2>;
2362 mboxes = <&apcs_glb 9>;
2366 apcs_glb: mailbox@17911000 {
2367 compatible = "qcom,msm8998-apcs-hmss-global";
2368 reg = <0x17911000 0x1000>;
2374 #address-cells = <1>;
2377 compatible = "arm,armv7-timer-mem";
2378 reg = <0x17920000 0x1000>;
2382 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2384 reg = <0x17921000 0x1000>,
2385 <0x17922000 0x1000>;
2390 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2391 reg = <0x17923000 0x1000>;
2392 status = "disabled";
2397 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2398 reg = <0x17924000 0x1000>;
2399 status = "disabled";
2404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2405 reg = <0x17925000 0x1000>;
2406 status = "disabled";
2411 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2412 reg = <0x17926000 0x1000>;
2413 status = "disabled";
2418 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2419 reg = <0x17927000 0x1000>;
2420 status = "disabled";
2425 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2426 reg = <0x17928000 0x1000>;
2427 status = "disabled";
2431 intc: interrupt-controller@17a00000 {
2432 compatible = "arm,gic-v3";
2433 reg = <0x17a00000 0x10000>, /* GICD */
2434 <0x17b00000 0x100000>; /* GICR * 8 */
2435 #interrupt-cells = <3>;
2436 #address-cells = <1>;
2439 interrupt-controller;
2440 #redistributor-regions = <1>;
2441 redistributor-stride = <0x0 0x20000>;
2442 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2445 wifi: wifi@18800000 {
2446 compatible = "qcom,wcn3990-wifi";
2447 status = "disabled";
2448 reg = <0x18800000 0x800000>;
2449 reg-names = "membase";
2450 memory-region = <&wlan_msa_mem>;
2451 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
2452 clock-names = "cxo_ref_clk_pin";
2454 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2455 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2456 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2457 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2458 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2459 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2460 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2461 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2462 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2463 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2464 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2465 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2466 iommus = <&anoc2_smmu 0x1900>,
2467 <&anoc2_smmu 0x1901>;
2468 qcom,snoc-host-cap-8bit-quirk;