1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep_clk {
28 compatible = "fixed-clock";
30 clock-frequency = <32764>;
31 clock-output-names = "sleep_clk";
41 compatible = "qcom,kryo";
43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
55 compatible = "qcom,kryo";
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0>;
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
65 compatible = "qcom,kryo";
67 enable-method = "psci";
68 cpu-idle-states = <&CPU_SLEEP_0>;
69 capacity-dmips-mhz = <1024>;
70 next-level-cache = <&L2_1>;
79 compatible = "qcom,kryo";
81 enable-method = "psci";
82 cpu-idle-states = <&CPU_SLEEP_0>;
83 capacity-dmips-mhz = <1024>;
84 next-level-cache = <&L2_1>;
110 entry-method = "psci";
112 CPU_SLEEP_0: cpu-sleep-0 {
113 compatible = "arm,idle-state";
114 idle-state-name = "standalone-power-collapse";
115 arm,psci-suspend-param = <0x00000004>;
116 entry-latency-us = <130>;
117 exit-latency-us = <80>;
118 min-residency-us = <300>;
125 compatible = "qcom,scm-msm8996";
126 qcom,dload-mode = <&tcsr 0x13000>;
131 compatible = "qcom,tcsr-mutex";
132 syscon = <&tcsr_mutex_regs 0 0x1000>;
137 device_type = "memory";
138 /* We expect the bootloader to fill in the reg */
143 compatible = "arm,psci-1.0";
148 #address-cells = <2>;
152 mba_region: mba@91500000 {
153 reg = <0x0 0x91500000 0x0 0x200000>;
157 slpi_region: slpi@90b00000 {
158 reg = <0x0 0x90b00000 0x0 0xa00000>;
162 venus_region: venus@90400000 {
163 reg = <0x0 0x90400000 0x0 0x700000>;
167 adsp_region: adsp@8ea00000 {
168 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
172 mpss_region: mpss@88800000 {
173 reg = <0x0 0x88800000 0x0 0x6200000>;
177 smem_mem: smem-mem@86000000 {
178 reg = <0x0 0x86000000 0x0 0x200000>;
183 reg = <0x0 0x85800000 0x0 0x800000>;
188 reg = <0x0 0x86200000 0x0 0x2600000>;
193 compatible = "qcom,rmtfs-mem";
195 size = <0x0 0x200000>;
196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
199 qcom,client-id = <1>;
203 zap_shader_region: gpu@8f200000 {
204 compatible = "shared-dma-pool";
205 reg = <0x0 0x90b00000 0x0 0xa00000>;
211 compatible = "qcom,glink-rpm";
213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
215 qcom,rpm-msg-ram = <&rpm_msg_ram>;
217 mboxes = <&apcs_glb 0>;
219 rpm_requests: rpm-requests {
220 compatible = "qcom,rpm-msm8996";
221 qcom,glink-channels = "rpm_requests";
224 compatible = "qcom,rpmcc-msm8996";
228 rpmpd: power-controller {
229 compatible = "qcom,msm8996-rpmpd";
230 #power-domain-cells = <1>;
231 operating-points-v2 = <&rpmpd_opp_table>;
233 rpmpd_opp_table: opp-table {
234 compatible = "operating-points-v2";
265 compatible = "qcom,smem";
266 memory-region = <&smem_mem>;
267 hwlocks = <&tcsr_mutex 3>;
271 compatible = "qcom,smp2p";
272 qcom,smem = <443>, <429>;
274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
276 mboxes = <&apcs_glb 10>;
278 qcom,local-pid = <0>;
279 qcom,remote-pid = <2>;
281 smp2p_adsp_out: master-kernel {
282 qcom,entry-name = "master-kernel";
283 #qcom,smem-state-cells = <1>;
286 smp2p_adsp_in: slave-kernel {
287 qcom,entry-name = "slave-kernel";
289 interrupt-controller;
290 #interrupt-cells = <2>;
295 compatible = "qcom,smp2p";
296 qcom,smem = <435>, <428>;
298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
300 mboxes = <&apcs_glb 14>;
302 qcom,local-pid = <0>;
303 qcom,remote-pid = <1>;
305 modem_smp2p_out: master-kernel {
306 qcom,entry-name = "master-kernel";
307 #qcom,smem-state-cells = <1>;
310 modem_smp2p_in: slave-kernel {
311 qcom,entry-name = "slave-kernel";
313 interrupt-controller;
314 #interrupt-cells = <2>;
319 compatible = "qcom,smp2p";
320 qcom,smem = <481>, <430>;
322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
324 mboxes = <&apcs_glb 26>;
326 qcom,local-pid = <0>;
327 qcom,remote-pid = <3>;
329 smp2p_slpi_in: slave-kernel {
330 qcom,entry-name = "slave-kernel";
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 smp2p_slpi_out: master-kernel {
336 qcom,entry-name = "master-kernel";
337 #qcom,smem-state-cells = <1>;
342 #address-cells = <1>;
344 ranges = <0 0 0 0xffffffff>;
345 compatible = "simple-bus";
347 pcie_phy: phy@34000 {
348 compatible = "qcom,msm8996-qmp-pcie-phy";
349 reg = <0x00034000 0x488>;
351 #address-cells = <1>;
355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
357 <&gcc GCC_PCIE_CLKREF_CLK>;
358 clock-names = "aux", "cfg_ahb", "ref";
360 resets = <&gcc GCC_PCIE_PHY_BCR>,
361 <&gcc GCC_PCIE_PHY_COM_BCR>,
362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
363 reset-names = "phy", "common", "cfg";
366 pciephy_0: lane@35000 {
367 reg = <0x00035000 0x130>,
372 clock-output-names = "pcie_0_pipe_clk_src";
373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
374 clock-names = "pipe0";
375 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
376 reset-names = "lane0";
379 pciephy_1: lane@36000 {
380 reg = <0x00036000 0x130>,
385 clock-output-names = "pcie_1_pipe_clk_src";
386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
387 clock-names = "pipe1";
388 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
389 reset-names = "lane1";
392 pciephy_2: lane@37000 {
393 reg = <0x00037000 0x130>,
398 clock-output-names = "pcie_2_pipe_clk_src";
399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
400 clock-names = "pipe2";
401 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
402 reset-names = "lane2";
406 rpm_msg_ram: memory@68000 {
407 compatible = "qcom,rpm-msg-ram";
408 reg = <0x00068000 0x6000>;
412 compatible = "qcom,qfprom";
413 reg = <0x00074000 0x8ff>;
414 #address-cells = <1>;
417 qusb2p_hstx_trim: hstx_trim@24e {
422 qusb2s_hstx_trim: hstx_trim@24f {
427 gpu_speed_bin: gpu_speed_bin@133 {
434 compatible = "qcom,prng-ee";
435 reg = <0x00083000 0x1000>;
436 clocks = <&gcc GCC_PRNG_AHB_CLK>;
437 clock-names = "core";
440 gcc: clock-controller@300000 {
441 compatible = "qcom,gcc-msm8996";
444 #power-domain-cells = <1>;
445 reg = <0x00300000 0x90000>;
447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
448 clock-names = "cxo2";
451 tsens0: thermal-sensor@4a9000 {
452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
453 reg = <0x004a9000 0x1000>, /* TM */
454 <0x004a8000 0x1000>; /* SROT */
455 #qcom,sensors = <13>;
456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "uplow", "critical";
459 #thermal-sensor-cells = <1>;
462 tsens1: thermal-sensor@4ad000 {
463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
464 reg = <0x004ad000 0x1000>, /* TM */
465 <0x004ac000 0x1000>; /* SROT */
467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "uplow", "critical";
470 #thermal-sensor-cells = <1>;
473 tcsr_mutex_regs: syscon@740000 {
474 compatible = "syscon";
475 reg = <0x00740000 0x20000>;
478 tcsr: syscon@7a0000 {
479 compatible = "qcom,tcsr-msm8996", "syscon";
480 reg = <0x007a0000 0x18000>;
483 mmcc: clock-controller@8c0000 {
484 compatible = "qcom,mmcc-msm8996";
487 #power-domain-cells = <1>;
488 reg = <0x008c0000 0x40000>;
489 assigned-clocks = <&mmcc MMPLL9_PLL>,
494 assigned-clock-rates = <624000000>,
502 compatible = "qcom,mdss";
504 reg = <0x00900000 0x1000>,
507 reg-names = "mdss_phys",
511 power-domains = <&mmcc MDSS_GDSC>;
512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
514 interrupt-controller;
515 #interrupt-cells = <1>;
517 clocks = <&mmcc MDSS_AHB_CLK>;
518 clock-names = "iface";
520 #address-cells = <1>;
525 compatible = "qcom,mdp5";
526 reg = <0x00901000 0x90000>;
527 reg-names = "mdp_phys";
529 interrupt-parent = <&mdss>;
530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&mmcc MDSS_AHB_CLK>,
533 <&mmcc MDSS_AXI_CLK>,
534 <&mmcc MDSS_MDP_CLK>,
535 <&mmcc SMMU_MDP_AXI_CLK>,
536 <&mmcc MDSS_VSYNC_CLK>;
537 clock-names = "iface",
543 iommus = <&mdp_smmu 0>;
546 #address-cells = <1>;
551 mdp5_intf3_out: endpoint {
552 remote-endpoint = <&hdmi_in>;
558 hdmi: hdmi-tx@9a0000 {
559 compatible = "qcom,hdmi-tx-8996";
560 reg = <0x009a0000 0x50c>,
563 reg-names = "core_physical",
567 interrupt-parent = <&mdss>;
568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mmcc MDSS_MDP_CLK>,
571 <&mmcc MDSS_AHB_CLK>,
572 <&mmcc MDSS_HDMI_CLK>,
573 <&mmcc MDSS_HDMI_AHB_CLK>,
574 <&mmcc MDSS_EXTPCLK_CLK>;
583 phy-names = "hdmi_phy";
584 #sound-dai-cells = <1>;
587 #address-cells = <1>;
593 remote-endpoint = <&mdp5_intf3_out>;
599 hdmi_phy: hdmi-phy@9a0600 {
601 compatible = "qcom,hdmi-phy-8996";
602 reg = <0x009a0600 0x1c4>,
608 reg-names = "hdmi_pll",
615 clocks = <&mmcc MDSS_AHB_CLK>,
616 <&gcc GCC_HDMI_CLKREF_CLK>;
617 clock-names = "iface",
622 compatible = "qcom,adreno-530.2", "qcom,adreno";
623 #stream-id-cells = <16>;
625 reg = <0x00b00000 0x3f000>;
626 reg-names = "kgsl_3d0_reg_memory";
628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
632 <&mmcc GPU_GX_RBBMTIMER_CLK>,
633 <&gcc GCC_BIMC_GFX_CLK>,
634 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
636 clock-names = "core",
642 power-domains = <&mmcc GPU_GX_GDSC>;
643 iommus = <&adreno_smmu 0>;
645 nvmem-cells = <&gpu_speed_bin>;
646 nvmem-cell-names = "speed_bin";
648 qcom,gpu-quirk-two-pass-use-wfi;
649 qcom,gpu-quirk-fault-detect-mask;
651 operating-points-v2 = <&gpu_opp_table>;
653 gpu_opp_table: opp-table {
654 compatible ="operating-points-v2";
657 * 624Mhz and 560Mhz are only available on speed
658 * bin (1 << 0). All the rest are available on
659 * all bins of the hardware
662 opp-hz = /bits/ 64 <624000000>;
663 opp-supported-hw = <0x01>;
666 opp-hz = /bits/ 64 <560000000>;
667 opp-supported-hw = <0x01>;
670 opp-hz = /bits/ 64 <510000000>;
671 opp-supported-hw = <0xFF>;
674 opp-hz = /bits/ 64 <401800000>;
675 opp-supported-hw = <0xFF>;
678 opp-hz = /bits/ 64 <315000000>;
679 opp-supported-hw = <0xFF>;
682 opp-hz = /bits/ 64 <214000000>;
683 opp-supported-hw = <0xFF>;
686 opp-hz = /bits/ 64 <133000000>;
687 opp-supported-hw = <0xFF>;
692 memory-region = <&zap_shader_region>;
696 msmgpio: pinctrl@1010000 {
697 compatible = "qcom,msm8996-pinctrl";
698 reg = <0x01010000 0x300000>;
699 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
701 gpio-ranges = <&msmgpio 0 0 150>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
707 spmi_bus: qcom,spmi@400f000 {
708 compatible = "qcom,spmi-pmic-arb";
709 reg = <0x0400f000 0x1000>,
710 <0x04400000 0x800000>,
711 <0x04c00000 0x800000>,
712 <0x05800000 0x200000>,
713 <0x0400a000 0x002100>;
714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
715 interrupt-names = "periph_irq";
716 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <2>;
721 interrupt-controller;
722 #interrupt-cells = <4>;
726 power-domains = <&gcc AGGRE0_NOC_GDSC>;
727 compatible = "simple-pm-bus";
728 #address-cells = <1>;
733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
735 power-domains = <&gcc PCIE0_GDSC>;
736 bus-range = <0x00 0xff>;
739 reg = <0x00600000 0x2000>,
742 <0x0c100000 0x100000>;
743 reg-names = "parf", "dbi", "elbi","config";
746 phy-names = "pciephy";
748 #address-cells = <3>;
750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
753 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
754 interrupt-names = "msi";
755 #interrupt-cells = <1>;
756 interrupt-map-mask = <0 0 0 0x7>;
757 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
758 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
759 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
760 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
762 pinctrl-names = "default", "sleep";
763 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
764 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
766 linux,pci-domain = <0>;
768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
769 <&gcc GCC_PCIE_0_AUX_CLK>,
770 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
771 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
772 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
774 clock-names = "pipe",
783 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
784 power-domains = <&gcc PCIE1_GDSC>;
785 bus-range = <0x00 0xff>;
790 reg = <0x00608000 0x2000>,
793 <0x0d100000 0x100000>;
795 reg-names = "parf", "dbi", "elbi","config";
798 phy-names = "pciephy";
800 #address-cells = <3>;
802 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
803 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
805 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
806 interrupt-names = "msi";
807 #interrupt-cells = <1>;
808 interrupt-map-mask = <0 0 0 0x7>;
809 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
810 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
811 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
812 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
814 pinctrl-names = "default", "sleep";
815 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
816 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
818 linux,pci-domain = <1>;
820 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
821 <&gcc GCC_PCIE_1_AUX_CLK>,
822 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
823 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
824 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
826 clock-names = "pipe",
834 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
835 power-domains = <&gcc PCIE2_GDSC>;
836 bus-range = <0x00 0xff>;
839 reg = <0x00610000 0x2000>,
842 <0x0e100000 0x100000>;
844 reg-names = "parf", "dbi", "elbi","config";
847 phy-names = "pciephy";
849 #address-cells = <3>;
851 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
852 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
856 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
857 interrupt-names = "msi";
858 #interrupt-cells = <1>;
859 interrupt-map-mask = <0 0 0 0x7>;
860 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
861 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
862 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
863 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
865 pinctrl-names = "default", "sleep";
866 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
867 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
869 linux,pci-domain = <2>;
870 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
871 <&gcc GCC_PCIE_2_AUX_CLK>,
872 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
873 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
874 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
876 clock-names = "pipe",
884 ufshc: ufshc@624000 {
885 compatible = "qcom,ufshc";
886 reg = <0x00624000 0x2500>;
887 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
889 phys = <&ufsphy_lane>;
890 phy-names = "ufsphy";
892 power-domains = <&gcc UFS_GDSC>;
900 "core_clk_unipro_src",
907 <&gcc UFS_AXI_CLK_SRC>,
908 <&gcc GCC_UFS_AXI_CLK>,
909 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
910 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
911 <&gcc GCC_UFS_AHB_CLK>,
912 <&gcc UFS_ICE_CORE_CLK_SRC>,
913 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
914 <&gcc GCC_UFS_ICE_CORE_CLK>,
915 <&rpmcc RPM_SMD_LN_BB_CLK>,
916 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
917 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
919 <100000000 200000000>,
924 <150000000 300000000>,
931 lanes-per-direction = <1>;
936 compatible = "qcom,ufs_variant";
941 compatible = "qcom,msm8996-qmp-ufs-phy";
942 reg = <0x00627000 0x1c4>;
943 #address-cells = <1>;
947 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
951 reset-names = "ufsphy";
954 ufsphy_lane: lanes@627400 {
955 reg = <0x627400 0x12c>,
962 camss: camss@a00000 {
963 compatible = "qcom,msm8996-camss";
964 reg = <0x00a34000 0x1000>,
978 reg-names = "csiphy0",
992 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1002 interrupt-names = "csiphy0",
1012 power-domains = <&mmcc VFE0_GDSC>,
1014 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1015 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1016 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1017 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1018 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1019 <&mmcc CAMSS_CSI0_AHB_CLK>,
1020 <&mmcc CAMSS_CSI0_CLK>,
1021 <&mmcc CAMSS_CSI0PHY_CLK>,
1022 <&mmcc CAMSS_CSI0PIX_CLK>,
1023 <&mmcc CAMSS_CSI0RDI_CLK>,
1024 <&mmcc CAMSS_CSI1_AHB_CLK>,
1025 <&mmcc CAMSS_CSI1_CLK>,
1026 <&mmcc CAMSS_CSI1PHY_CLK>,
1027 <&mmcc CAMSS_CSI1PIX_CLK>,
1028 <&mmcc CAMSS_CSI1RDI_CLK>,
1029 <&mmcc CAMSS_CSI2_AHB_CLK>,
1030 <&mmcc CAMSS_CSI2_CLK>,
1031 <&mmcc CAMSS_CSI2PHY_CLK>,
1032 <&mmcc CAMSS_CSI2PIX_CLK>,
1033 <&mmcc CAMSS_CSI2RDI_CLK>,
1034 <&mmcc CAMSS_CSI3_AHB_CLK>,
1035 <&mmcc CAMSS_CSI3_CLK>,
1036 <&mmcc CAMSS_CSI3PHY_CLK>,
1037 <&mmcc CAMSS_CSI3PIX_CLK>,
1038 <&mmcc CAMSS_CSI3RDI_CLK>,
1039 <&mmcc CAMSS_AHB_CLK>,
1040 <&mmcc CAMSS_VFE0_CLK>,
1041 <&mmcc CAMSS_CSI_VFE0_CLK>,
1042 <&mmcc CAMSS_VFE0_AHB_CLK>,
1043 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1044 <&mmcc CAMSS_VFE1_CLK>,
1045 <&mmcc CAMSS_CSI_VFE1_CLK>,
1046 <&mmcc CAMSS_VFE1_AHB_CLK>,
1047 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1048 <&mmcc CAMSS_VFE_AHB_CLK>,
1049 <&mmcc CAMSS_VFE_AXI_CLK>;
1050 clock-names = "top_ahb",
1086 iommus = <&vfe_smmu 0>,
1090 status = "disabled";
1092 #address-cells = <1>;
1098 compatible = "qcom,msm8996-cci";
1099 #address-cells = <1>;
1101 reg = <0xa0c000 0x1000>;
1102 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1103 power-domains = <&mmcc CAMSS_GDSC>;
1104 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1105 <&mmcc CAMSS_CCI_AHB_CLK>,
1106 <&mmcc CAMSS_CCI_CLK>,
1107 <&mmcc CAMSS_AHB_CLK>;
1108 clock-names = "camss_top_ahb",
1112 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1113 <&mmcc CAMSS_CCI_CLK>;
1114 assigned-clock-rates = <80000000>, <37500000>;
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&cci0_default &cci1_default>;
1117 status = "disabled";
1119 cci_i2c0: i2c-bus@0 {
1121 clock-frequency = <400000>;
1122 #address-cells = <1>;
1126 cci_i2c1: i2c-bus@1 {
1128 clock-frequency = <400000>;
1129 #address-cells = <1>;
1134 adreno_smmu: iommu@b40000 {
1135 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1136 reg = <0x00b40000 0x10000>;
1138 #global-interrupts = <1>;
1139 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&mmcc GPU_AHB_CLK>,
1145 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1146 clock-names = "iface", "bus";
1148 power-domains = <&mmcc GPU_GDSC>;
1151 video-codec@c00000 {
1152 compatible = "qcom,msm8996-venus";
1153 reg = <0x00c00000 0xff000>;
1154 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1155 power-domains = <&mmcc VENUS_GDSC>;
1156 clocks = <&mmcc VIDEO_CORE_CLK>,
1157 <&mmcc VIDEO_AHB_CLK>,
1158 <&mmcc VIDEO_AXI_CLK>,
1159 <&mmcc VIDEO_MAXI_CLK>;
1160 clock-names = "core", "iface", "bus", "mbus";
1161 iommus = <&venus_smmu 0x00>,
1181 memory-region = <&venus_region>;
1185 compatible = "venus-decoder";
1186 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1187 clock-names = "core";
1188 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1192 compatible = "venus-encoder";
1193 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1194 clock-names = "core";
1195 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1199 mdp_smmu: iommu@d00000 {
1200 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1201 reg = <0x00d00000 0x10000>;
1203 #global-interrupts = <1>;
1204 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1209 <&mmcc SMMU_MDP_AXI_CLK>;
1210 clock-names = "iface", "bus";
1212 power-domains = <&mmcc MDSS_GDSC>;
1215 venus_smmu: iommu@d40000 {
1216 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1217 reg = <0x00d40000 0x20000>;
1218 #global-interrupts = <1>;
1219 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1227 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1228 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1229 <&mmcc SMMU_VIDEO_AXI_CLK>;
1230 clock-names = "iface", "bus";
1235 vfe_smmu: iommu@da0000 {
1236 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1237 reg = <0x00da0000 0x10000>;
1239 #global-interrupts = <1>;
1240 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1243 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1244 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1245 <&mmcc SMMU_VFE_AXI_CLK>;
1246 clock-names = "iface",
1251 lpass_q6_smmu: iommu@1600000 {
1252 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1253 reg = <0x01600000 0x20000>;
1255 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1257 #global-interrupts = <1>;
1258 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1272 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1273 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1274 clock-names = "iface", "bus";
1278 compatible = "arm,coresight-stm", "arm,primecell";
1279 reg = <0x3002000 0x1000>,
1280 <0x8280000 0x180000>;
1281 reg-names = "stm-base", "stm-stimulus-base";
1283 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1284 clock-names = "apb_pclk", "atclk";
1297 compatible = "arm,coresight-tpiu", "arm,primecell";
1298 reg = <0x3020000 0x1000>;
1300 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1301 clock-names = "apb_pclk", "atclk";
1314 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1315 reg = <0x3021000 0x1000>;
1317 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1318 clock-names = "apb_pclk", "atclk";
1321 #address-cells = <1>;
1326 funnel0_in: endpoint {
1335 funnel0_out: endpoint {
1337 <&merge_funnel_in0>;
1344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1345 reg = <0x3022000 0x1000>;
1347 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1348 clock-names = "apb_pclk", "atclk";
1351 #address-cells = <1>;
1356 funnel1_in: endpoint {
1358 <&apss_merge_funnel_out>;
1365 funnel1_out: endpoint {
1367 <&merge_funnel_in1>;
1374 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1375 reg = <0x3023000 0x1000>;
1377 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1378 clock-names = "apb_pclk", "atclk";
1383 funnel2_out: endpoint {
1385 <&merge_funnel_in2>;
1392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1393 reg = <0x3025000 0x1000>;
1395 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1396 clock-names = "apb_pclk", "atclk";
1399 #address-cells = <1>;
1404 merge_funnel_in0: endpoint {
1412 merge_funnel_in1: endpoint {
1420 merge_funnel_in2: endpoint {
1429 merge_funnel_out: endpoint {
1437 replicator@3026000 {
1438 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1439 reg = <0x3026000 0x1000>;
1441 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1442 clock-names = "apb_pclk", "atclk";
1446 replicator_in: endpoint {
1454 #address-cells = <1>;
1459 replicator_out0: endpoint {
1467 replicator_out1: endpoint {
1476 compatible = "arm,coresight-tmc", "arm,primecell";
1477 reg = <0x3027000 0x1000>;
1479 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1480 clock-names = "apb_pclk", "atclk";
1486 <&merge_funnel_out>;
1502 compatible = "arm,coresight-tmc", "arm,primecell";
1503 reg = <0x3028000 0x1000>;
1505 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1506 clock-names = "apb_pclk", "atclk";
1520 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1521 reg = <0x3810000 0x1000>;
1523 clocks = <&rpmcc RPM_QDSS_CLK>;
1524 clock-names = "apb_pclk";
1530 compatible = "arm,coresight-etm4x", "arm,primecell";
1531 reg = <0x3840000 0x1000>;
1533 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1534 clock-names = "apb_pclk", "atclk";
1540 etm0_out: endpoint {
1542 <&apss_funnel0_in0>;
1549 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1550 reg = <0x3910000 0x1000>;
1552 clocks = <&rpmcc RPM_QDSS_CLK>;
1553 clock-names = "apb_pclk";
1559 compatible = "arm,coresight-etm4x", "arm,primecell";
1560 reg = <0x3940000 0x1000>;
1562 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1563 clock-names = "apb_pclk", "atclk";
1569 etm1_out: endpoint {
1571 <&apss_funnel0_in1>;
1577 funnel@39b0000 { /* APSS Funnel 0 */
1578 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1579 reg = <0x39b0000 0x1000>;
1581 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1582 clock-names = "apb_pclk", "atclk";
1585 #address-cells = <1>;
1590 apss_funnel0_in0: endpoint {
1591 remote-endpoint = <&etm0_out>;
1597 apss_funnel0_in1: endpoint {
1598 remote-endpoint = <&etm1_out>;
1605 apss_funnel0_out: endpoint {
1607 <&apss_merge_funnel_in0>;
1614 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1615 reg = <0x3a10000 0x1000>;
1617 clocks = <&rpmcc RPM_QDSS_CLK>;
1618 clock-names = "apb_pclk";
1624 compatible = "arm,coresight-etm4x", "arm,primecell";
1625 reg = <0x3a40000 0x1000>;
1627 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1628 clock-names = "apb_pclk", "atclk";
1634 etm2_out: endpoint {
1636 <&apss_funnel1_in0>;
1643 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1644 reg = <0x3b10000 0x1000>;
1646 clocks = <&rpmcc RPM_QDSS_CLK>;
1647 clock-names = "apb_pclk";
1653 compatible = "arm,coresight-etm4x", "arm,primecell";
1654 reg = <0x3b40000 0x1000>;
1656 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1657 clock-names = "apb_pclk", "atclk";
1663 etm3_out: endpoint {
1665 <&apss_funnel1_in1>;
1671 funnel@3bb0000 { /* APSS Funnel 1 */
1672 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1673 reg = <0x3bb0000 0x1000>;
1675 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1676 clock-names = "apb_pclk", "atclk";
1679 #address-cells = <1>;
1684 apss_funnel1_in0: endpoint {
1685 remote-endpoint = <&etm2_out>;
1691 apss_funnel1_in1: endpoint {
1692 remote-endpoint = <&etm3_out>;
1699 apss_funnel1_out: endpoint {
1701 <&apss_merge_funnel_in1>;
1708 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1709 reg = <0x3bc0000 0x1000>;
1711 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1712 clock-names = "apb_pclk", "atclk";
1715 #address-cells = <1>;
1720 apss_merge_funnel_in0: endpoint {
1722 <&apss_funnel0_out>;
1728 apss_merge_funnel_in1: endpoint {
1730 <&apss_funnel1_out>;
1737 apss_merge_funnel_out: endpoint {
1744 kryocc: clock-controller@6400000 {
1745 compatible = "qcom,apcc-msm8996";
1746 reg = <0x06400000 0x90000>;
1751 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1752 reg = <0x06af8800 0x400>;
1753 #address-cells = <1>;
1757 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1758 <&gcc GCC_USB30_MASTER_CLK>,
1759 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1760 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1761 <&gcc GCC_USB30_SLEEP_CLK>,
1762 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1764 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1765 <&gcc GCC_USB30_MASTER_CLK>;
1766 assigned-clock-rates = <19200000>, <120000000>;
1768 power-domains = <&gcc USB30_GDSC>;
1769 status = "disabled";
1772 compatible = "snps,dwc3";
1773 reg = <0x06a00000 0xcc00>;
1774 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1775 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1776 phy-names = "usb2-phy", "usb3-phy";
1777 snps,dis_u2_susphy_quirk;
1778 snps,dis_enblslpm_quirk;
1782 usb3phy: phy@7410000 {
1783 compatible = "qcom,msm8996-qmp-usb3-phy";
1784 reg = <0x07410000 0x1c4>;
1786 #address-cells = <1>;
1790 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1791 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1792 <&gcc GCC_USB3_CLKREF_CLK>;
1793 clock-names = "aux", "cfg_ahb", "ref";
1795 resets = <&gcc GCC_USB3_PHY_BCR>,
1796 <&gcc GCC_USB3PHY_PHY_BCR>;
1797 reset-names = "phy", "common";
1798 status = "disabled";
1800 ssusb_phy_0: lane@7410200 {
1801 reg = <0x07410200 0x200>,
1806 clock-output-names = "usb3_phy_pipe_clk_src";
1807 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1808 clock-names = "pipe0";
1812 hsusb_phy1: phy@7411000 {
1813 compatible = "qcom,msm8996-qusb2-phy";
1814 reg = <0x07411000 0x180>;
1817 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1818 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1819 clock-names = "cfg_ahb", "ref";
1821 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1822 nvmem-cells = <&qusb2p_hstx_trim>;
1823 status = "disabled";
1826 hsusb_phy2: phy@7412000 {
1827 compatible = "qcom,msm8996-qusb2-phy";
1828 reg = <0x07412000 0x180>;
1831 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1832 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1833 clock-names = "cfg_ahb", "ref";
1835 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1836 nvmem-cells = <&qusb2s_hstx_trim>;
1837 status = "disabled";
1840 sdhc2: sdhci@74a4900 {
1841 status = "disabled";
1842 compatible = "qcom,sdhci-msm-v4";
1843 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
1844 reg-names = "hc_mem", "core_mem";
1846 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1847 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1848 interrupt-names = "hc_irq", "pwr_irq";
1850 clock-names = "iface", "core", "xo";
1851 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1852 <&gcc GCC_SDCC2_APPS_CLK>,
1857 blsp1_uart1: serial@7570000 {
1858 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1859 reg = <0x07570000 0x1000>;
1860 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1861 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1862 <&gcc GCC_BLSP1_AHB_CLK>;
1863 clock-names = "core", "iface";
1864 status = "disabled";
1867 blsp1_spi0: spi@7575000 {
1868 compatible = "qcom,spi-qup-v2.2.1";
1869 reg = <0x07575000 0x600>;
1870 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1871 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1872 <&gcc GCC_BLSP1_AHB_CLK>;
1873 clock-names = "core", "iface";
1874 pinctrl-names = "default", "sleep";
1875 pinctrl-0 = <&blsp1_spi0_default>;
1876 pinctrl-1 = <&blsp1_spi0_sleep>;
1877 #address-cells = <1>;
1879 status = "disabled";
1882 blsp1_i2c2: i2c@7577000 {
1883 compatible = "qcom,i2c-qup-v2.2.1";
1884 reg = <0x07577000 0x1000>;
1885 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1886 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1887 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1888 clock-names = "iface", "core";
1889 pinctrl-names = "default", "sleep";
1890 pinctrl-0 = <&blsp1_i2c2_default>;
1891 pinctrl-1 = <&blsp1_i2c2_sleep>;
1892 #address-cells = <1>;
1894 status = "disabled";
1897 blsp2_uart1: serial@75b0000 {
1898 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1899 reg = <0x075b0000 0x1000>;
1900 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1902 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", "iface";
1904 status = "disabled";
1907 blsp2_uart2: serial@75b1000 {
1908 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1909 reg = <0x075b1000 0x1000>;
1910 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1911 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1912 <&gcc GCC_BLSP2_AHB_CLK>;
1913 clock-names = "core", "iface";
1914 status = "disabled";
1917 blsp2_i2c0: i2c@75b5000 {
1918 compatible = "qcom,i2c-qup-v2.2.1";
1919 reg = <0x075b5000 0x1000>;
1920 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1921 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1922 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1923 clock-names = "iface", "core";
1924 pinctrl-names = "default", "sleep";
1925 pinctrl-0 = <&blsp2_i2c0_default>;
1926 pinctrl-1 = <&blsp2_i2c0_sleep>;
1927 #address-cells = <1>;
1929 status = "disabled";
1932 blsp2_i2c1: i2c@75b6000 {
1933 compatible = "qcom,i2c-qup-v2.2.1";
1934 reg = <0x075b6000 0x1000>;
1935 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1936 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1937 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1938 clock-names = "iface", "core";
1939 pinctrl-names = "default", "sleep";
1940 pinctrl-0 = <&blsp2_i2c1_default>;
1941 pinctrl-1 = <&blsp2_i2c1_sleep>;
1942 #address-cells = <1>;
1944 status = "disabled";
1947 blsp2_spi5: spi@75ba000{
1948 compatible = "qcom,spi-qup-v2.2.1";
1949 reg = <0x075ba000 0x600>;
1950 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1951 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1952 <&gcc GCC_BLSP2_AHB_CLK>;
1953 clock-names = "core", "iface";
1954 pinctrl-names = "default", "sleep";
1955 pinctrl-0 = <&blsp2_spi5_default>;
1956 pinctrl-1 = <&blsp2_spi5_sleep>;
1957 #address-cells = <1>;
1959 status = "disabled";
1963 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1964 reg = <0x076f8800 0x400>;
1965 #address-cells = <1>;
1969 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1970 <&gcc GCC_USB20_MASTER_CLK>,
1971 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1972 <&gcc GCC_USB20_SLEEP_CLK>,
1973 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1975 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1976 <&gcc GCC_USB20_MASTER_CLK>;
1977 assigned-clock-rates = <19200000>, <60000000>;
1979 power-domains = <&gcc USB30_GDSC>;
1980 status = "disabled";
1983 compatible = "snps,dwc3";
1984 reg = <0x07600000 0xcc00>;
1985 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1986 phys = <&hsusb_phy2>;
1987 phy-names = "usb2-phy";
1988 snps,dis_u2_susphy_quirk;
1989 snps,dis_enblslpm_quirk;
1993 slimbam: dma-controller@9184000 {
1994 compatible = "qcom,bam-v1.7.0";
1995 qcom,controlled-remotely;
1996 reg = <0x09184000 0x32000>;
1997 num-channels = <31>;
1998 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2004 slim_msm: slim@91c0000 {
2005 compatible = "qcom,slim-ngd-v1.5.0";
2006 reg = <0x091c0000 0x2C000>;
2008 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2009 dmas = <&slimbam 3>, <&slimbam 4>,
2010 <&slimbam 5>, <&slimbam 6>;
2011 dma-names = "rx", "tx", "tx2", "rx2";
2012 #address-cells = <1>;
2016 #address-cells = <1>;
2019 tasha_ifd: tas-ifd {
2020 compatible = "slim217,1a0";
2025 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2026 pinctrl-names = "default";
2028 compatible = "slim217,1a0";
2031 interrupt-parent = <&msmgpio>;
2032 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2033 <53 IRQ_TYPE_LEVEL_HIGH>;
2034 interrupt-names = "intr1", "intr2";
2035 interrupt-controller;
2036 #interrupt-cells = <1>;
2037 reset-gpios = <&msmgpio 64 0>;
2039 slim-ifc-dev = <&tasha_ifd>;
2041 #sound-dai-cells = <1>;
2046 adsp_pil: remoteproc@9300000 {
2047 compatible = "qcom,msm8996-adsp-pil";
2048 reg = <0x09300000 0x80000>;
2050 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2051 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2052 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2053 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2054 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2055 interrupt-names = "wdog", "fatal", "ready",
2056 "handover", "stop-ack";
2058 clocks = <&xo_board>;
2061 memory-region = <&adsp_region>;
2063 qcom,smem-states = <&smp2p_adsp_out 0>;
2064 qcom,smem-state-names = "stop";
2067 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2070 mboxes = <&apcs_glb 8>;
2071 qcom,smd-edge = <1>;
2072 qcom,remote-pid = <2>;
2073 #address-cells = <1>;
2076 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2077 compatible = "qcom,apr-v2";
2078 qcom,smd-channels = "apr_audio_svc";
2079 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2080 #address-cells = <1>;
2084 reg = <APR_SVC_ADSP_CORE>;
2085 compatible = "qcom,q6core";
2089 compatible = "qcom,q6afe";
2090 reg = <APR_SVC_AFE>;
2092 compatible = "qcom,q6afe-dais";
2093 #address-cells = <1>;
2095 #sound-dai-cells = <1>;
2103 compatible = "qcom,q6asm";
2104 reg = <APR_SVC_ASM>;
2106 compatible = "qcom,q6asm-dais";
2107 #address-cells = <1>;
2109 #sound-dai-cells = <1>;
2110 iommus = <&lpass_q6_smmu 1>;
2115 compatible = "qcom,q6adm";
2116 reg = <APR_SVC_ADM>;
2117 q6routing: routing {
2118 compatible = "qcom,q6adm-routing";
2119 #sound-dai-cells = <0>;
2127 apcs_glb: mailbox@9820000 {
2128 compatible = "qcom,msm8996-apcs-hmss-global";
2129 reg = <0x09820000 0x1000>;
2135 #address-cells = <1>;
2138 compatible = "arm,armv7-timer-mem";
2139 reg = <0x09840000 0x1000>;
2140 clock-frequency = <19200000>;
2144 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
2145 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2146 reg = <0x09850000 0x1000>,
2147 <0x09860000 0x1000>;
2152 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2153 reg = <0x09870000 0x1000>;
2154 status = "disabled";
2159 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2160 reg = <0x09880000 0x1000>;
2161 status = "disabled";
2166 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2167 reg = <0x09890000 0x1000>;
2168 status = "disabled";
2173 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2174 reg = <0x098a0000 0x1000>;
2175 status = "disabled";
2180 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2181 reg = <0x098b0000 0x1000>;
2182 status = "disabled";
2187 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2188 reg = <0x098c0000 0x1000>;
2189 status = "disabled";
2193 saw3: syscon@9a10000 {
2194 compatible = "syscon";
2195 reg = <0x09a10000 0x1000>;
2198 intc: interrupt-controller@9bc0000 {
2199 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
2200 #interrupt-cells = <3>;
2201 interrupt-controller;
2202 #redistributor-regions = <1>;
2203 redistributor-stride = <0x0 0x40000>;
2204 reg = <0x09bc0000 0x10000>,
2205 <0x09c00000 0x100000>;
2206 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2215 polling-delay-passive = <250>;
2216 polling-delay = <1000>;
2218 thermal-sensors = <&tsens0 3>;
2221 cpu0_alert0: trip-point0 {
2222 temperature = <75000>;
2223 hysteresis = <2000>;
2227 cpu0_crit: cpu_crit {
2228 temperature = <110000>;
2229 hysteresis = <2000>;
2236 polling-delay-passive = <250>;
2237 polling-delay = <1000>;
2239 thermal-sensors = <&tsens0 5>;
2242 cpu1_alert0: trip-point0 {
2243 temperature = <75000>;
2244 hysteresis = <2000>;
2248 cpu1_crit: cpu_crit {
2249 temperature = <110000>;
2250 hysteresis = <2000>;
2257 polling-delay-passive = <250>;
2258 polling-delay = <1000>;
2260 thermal-sensors = <&tsens0 8>;
2263 cpu2_alert0: trip-point0 {
2264 temperature = <75000>;
2265 hysteresis = <2000>;
2269 cpu2_crit: cpu_crit {
2270 temperature = <110000>;
2271 hysteresis = <2000>;
2278 polling-delay-passive = <250>;
2279 polling-delay = <1000>;
2281 thermal-sensors = <&tsens0 10>;
2284 cpu3_alert0: trip-point0 {
2285 temperature = <75000>;
2286 hysteresis = <2000>;
2290 cpu3_crit: cpu_crit {
2291 temperature = <110000>;
2292 hysteresis = <2000>;
2299 polling-delay-passive = <250>;
2300 polling-delay = <1000>;
2302 thermal-sensors = <&tsens1 6>;
2305 gpu1_alert0: trip-point0 {
2306 temperature = <90000>;
2307 hysteresis = <2000>;
2313 gpu-thermal-bottom {
2314 polling-delay-passive = <250>;
2315 polling-delay = <1000>;
2317 thermal-sensors = <&tsens1 7>;
2320 gpu2_alert0: trip-point0 {
2321 temperature = <90000>;
2322 hysteresis = <2000>;
2329 polling-delay-passive = <250>;
2330 polling-delay = <1000>;
2332 thermal-sensors = <&tsens0 1>;
2335 m4m_alert0: trip-point0 {
2336 temperature = <90000>;
2337 hysteresis = <2000>;
2343 l3-or-venus-thermal {
2344 polling-delay-passive = <250>;
2345 polling-delay = <1000>;
2347 thermal-sensors = <&tsens0 2>;
2350 l3_or_venus_alert0: trip-point0 {
2351 temperature = <90000>;
2352 hysteresis = <2000>;
2358 cluster0-l2-thermal {
2359 polling-delay-passive = <250>;
2360 polling-delay = <1000>;
2362 thermal-sensors = <&tsens0 7>;
2365 cluster0_l2_alert0: trip-point0 {
2366 temperature = <90000>;
2367 hysteresis = <2000>;
2373 cluster1-l2-thermal {
2374 polling-delay-passive = <250>;
2375 polling-delay = <1000>;
2377 thermal-sensors = <&tsens0 12>;
2380 cluster1_l2_alert0: trip-point0 {
2381 temperature = <90000>;
2382 hysteresis = <2000>;
2389 polling-delay-passive = <250>;
2390 polling-delay = <1000>;
2392 thermal-sensors = <&tsens1 1>;
2395 camera_alert0: trip-point0 {
2396 temperature = <90000>;
2397 hysteresis = <2000>;
2404 polling-delay-passive = <250>;
2405 polling-delay = <1000>;
2407 thermal-sensors = <&tsens1 2>;
2410 q6_dsp_alert0: trip-point0 {
2411 temperature = <90000>;
2412 hysteresis = <2000>;
2419 polling-delay-passive = <250>;
2420 polling-delay = <1000>;
2422 thermal-sensors = <&tsens1 3>;
2425 mem_alert0: trip-point0 {
2426 temperature = <90000>;
2427 hysteresis = <2000>;
2434 polling-delay-passive = <250>;
2435 polling-delay = <1000>;
2437 thermal-sensors = <&tsens1 4>;
2440 modemtx_alert0: trip-point0 {
2441 temperature = <90000>;
2442 hysteresis = <2000>;
2450 compatible = "arm,armv8-timer";
2451 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2452 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2453 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2454 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2457 #include "msm8996-pins.dtsi"