1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep_clk {
28 compatible = "fixed-clock";
30 clock-frequency = <32764>;
31 clock-output-names = "sleep_clk";
41 compatible = "qcom,kryo";
43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
55 compatible = "qcom,kryo";
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0>;
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
65 compatible = "qcom,kryo";
67 enable-method = "psci";
68 cpu-idle-states = <&CPU_SLEEP_0>;
69 capacity-dmips-mhz = <1024>;
70 next-level-cache = <&L2_1>;
79 compatible = "qcom,kryo";
81 enable-method = "psci";
82 cpu-idle-states = <&CPU_SLEEP_0>;
83 capacity-dmips-mhz = <1024>;
84 next-level-cache = <&L2_1>;
110 entry-method = "psci";
112 CPU_SLEEP_0: cpu-sleep-0 {
113 compatible = "arm,idle-state";
114 idle-state-name = "standalone-power-collapse";
115 arm,psci-suspend-param = <0x00000004>;
116 entry-latency-us = <130>;
117 exit-latency-us = <80>;
118 min-residency-us = <300>;
125 compatible = "qcom,scm-msm8996";
126 qcom,dload-mode = <&tcsr 0x13000>;
131 compatible = "qcom,tcsr-mutex";
132 syscon = <&tcsr_mutex_regs 0 0x1000>;
137 device_type = "memory";
138 /* We expect the bootloader to fill in the reg */
143 compatible = "arm,psci-1.0";
148 #address-cells = <2>;
152 mba_region: mba@91500000 {
153 reg = <0x0 0x91500000 0x0 0x200000>;
157 slpi_region: slpi@90b00000 {
158 reg = <0x0 0x90b00000 0x0 0xa00000>;
162 venus_region: venus@90400000 {
163 reg = <0x0 0x90400000 0x0 0x700000>;
167 adsp_region: adsp@8ea00000 {
168 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
172 mpss_region: mpss@88800000 {
173 reg = <0x0 0x88800000 0x0 0x6200000>;
177 smem_mem: smem-mem@86000000 {
178 reg = <0x0 0x86000000 0x0 0x200000>;
183 reg = <0x0 0x85800000 0x0 0x800000>;
188 reg = <0x0 0x86200000 0x0 0x2600000>;
193 compatible = "qcom,rmtfs-mem";
195 size = <0x0 0x200000>;
196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
199 qcom,client-id = <1>;
203 zap_shader_region: gpu@8f200000 {
204 compatible = "shared-dma-pool";
205 reg = <0x0 0x90b00000 0x0 0xa00000>;
211 compatible = "qcom,glink-rpm";
213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
215 qcom,rpm-msg-ram = <&rpm_msg_ram>;
217 mboxes = <&apcs_glb 0>;
219 rpm_requests: rpm-requests {
220 compatible = "qcom,rpm-msm8996";
221 qcom,glink-channels = "rpm_requests";
224 compatible = "qcom,rpmcc-msm8996";
228 rpmpd: power-controller {
229 compatible = "qcom,msm8996-rpmpd";
230 #power-domain-cells = <1>;
231 operating-points-v2 = <&rpmpd_opp_table>;
233 rpmpd_opp_table: opp-table {
234 compatible = "operating-points-v2";
265 compatible = "qcom,smem";
266 memory-region = <&smem_mem>;
267 hwlocks = <&tcsr_mutex 3>;
271 compatible = "qcom,smp2p";
272 qcom,smem = <443>, <429>;
274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
276 mboxes = <&apcs_glb 10>;
278 qcom,local-pid = <0>;
279 qcom,remote-pid = <2>;
281 smp2p_adsp_out: master-kernel {
282 qcom,entry-name = "master-kernel";
283 #qcom,smem-state-cells = <1>;
286 smp2p_adsp_in: slave-kernel {
287 qcom,entry-name = "slave-kernel";
289 interrupt-controller;
290 #interrupt-cells = <2>;
295 compatible = "qcom,smp2p";
296 qcom,smem = <435>, <428>;
298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
300 mboxes = <&apcs_glb 14>;
302 qcom,local-pid = <0>;
303 qcom,remote-pid = <1>;
305 modem_smp2p_out: master-kernel {
306 qcom,entry-name = "master-kernel";
307 #qcom,smem-state-cells = <1>;
310 modem_smp2p_in: slave-kernel {
311 qcom,entry-name = "slave-kernel";
313 interrupt-controller;
314 #interrupt-cells = <2>;
319 compatible = "qcom,smp2p";
320 qcom,smem = <481>, <430>;
322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
324 mboxes = <&apcs_glb 26>;
326 qcom,local-pid = <0>;
327 qcom,remote-pid = <3>;
329 smp2p_slpi_in: slave-kernel {
330 qcom,entry-name = "slave-kernel";
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 smp2p_slpi_out: master-kernel {
336 qcom,entry-name = "master-kernel";
337 #qcom,smem-state-cells = <1>;
342 #address-cells = <1>;
344 ranges = <0 0 0 0xffffffff>;
345 compatible = "simple-bus";
347 pcie_phy: phy@34000 {
348 compatible = "qcom,msm8996-qmp-pcie-phy";
349 reg = <0x00034000 0x488>;
351 #address-cells = <1>;
355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
357 <&gcc GCC_PCIE_CLKREF_CLK>;
358 clock-names = "aux", "cfg_ahb", "ref";
360 resets = <&gcc GCC_PCIE_PHY_BCR>,
361 <&gcc GCC_PCIE_PHY_COM_BCR>,
362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
363 reset-names = "phy", "common", "cfg";
366 pciephy_0: lane@35000 {
367 reg = <0x00035000 0x130>,
372 clock-output-names = "pcie_0_pipe_clk_src";
373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
374 clock-names = "pipe0";
375 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
376 reset-names = "lane0";
379 pciephy_1: lane@36000 {
380 reg = <0x00036000 0x130>,
385 clock-output-names = "pcie_1_pipe_clk_src";
386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
387 clock-names = "pipe1";
388 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
389 reset-names = "lane1";
392 pciephy_2: lane@37000 {
393 reg = <0x00037000 0x130>,
398 clock-output-names = "pcie_2_pipe_clk_src";
399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
400 clock-names = "pipe2";
401 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
402 reset-names = "lane2";
406 rpm_msg_ram: memory@68000 {
407 compatible = "qcom,rpm-msg-ram";
408 reg = <0x00068000 0x6000>;
412 compatible = "qcom,qfprom";
413 reg = <0x00074000 0x8ff>;
414 #address-cells = <1>;
417 qusb2p_hstx_trim: hstx_trim@24e {
422 qusb2s_hstx_trim: hstx_trim@24f {
427 gpu_speed_bin: gpu_speed_bin@133 {
434 compatible = "qcom,prng-ee";
435 reg = <0x00083000 0x1000>;
436 clocks = <&gcc GCC_PRNG_AHB_CLK>;
437 clock-names = "core";
440 gcc: clock-controller@300000 {
441 compatible = "qcom,gcc-msm8996";
444 #power-domain-cells = <1>;
445 reg = <0x00300000 0x90000>;
447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
448 clock-names = "cxo2";
451 tsens0: thermal-sensor@4a9000 {
452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
453 reg = <0x004a9000 0x1000>, /* TM */
454 <0x004a8000 0x1000>; /* SROT */
455 #qcom,sensors = <13>;
456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "uplow", "critical";
459 #thermal-sensor-cells = <1>;
462 tsens1: thermal-sensor@4ad000 {
463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
464 reg = <0x004ad000 0x1000>, /* TM */
465 <0x004ac000 0x1000>; /* SROT */
467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "uplow", "critical";
470 #thermal-sensor-cells = <1>;
473 tcsr_mutex_regs: syscon@740000 {
474 compatible = "syscon";
475 reg = <0x00740000 0x20000>;
478 tcsr: syscon@7a0000 {
479 compatible = "qcom,tcsr-msm8996", "syscon";
480 reg = <0x007a0000 0x18000>;
483 mmcc: clock-controller@8c0000 {
484 compatible = "qcom,mmcc-msm8996";
487 #power-domain-cells = <1>;
488 reg = <0x008c0000 0x40000>;
489 assigned-clocks = <&mmcc MMPLL9_PLL>,
494 assigned-clock-rates = <624000000>,
502 compatible = "qcom,mdss";
504 reg = <0x00900000 0x1000>,
507 reg-names = "mdss_phys",
511 power-domains = <&mmcc MDSS_GDSC>;
512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
514 interrupt-controller;
515 #interrupt-cells = <1>;
517 clocks = <&mmcc MDSS_AHB_CLK>;
518 clock-names = "iface";
520 #address-cells = <1>;
525 compatible = "qcom,mdp5";
526 reg = <0x00901000 0x90000>;
527 reg-names = "mdp_phys";
529 interrupt-parent = <&mdss>;
530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&mmcc MDSS_AHB_CLK>,
533 <&mmcc MDSS_AXI_CLK>,
534 <&mmcc MDSS_MDP_CLK>,
535 <&mmcc SMMU_MDP_AXI_CLK>,
536 <&mmcc MDSS_VSYNC_CLK>;
537 clock-names = "iface",
543 iommus = <&mdp_smmu 0>;
546 #address-cells = <1>;
551 mdp5_intf3_out: endpoint {
552 remote-endpoint = <&hdmi_in>;
558 hdmi: hdmi-tx@9a0000 {
559 compatible = "qcom,hdmi-tx-8996";
560 reg = <0x009a0000 0x50c>,
563 reg-names = "core_physical",
567 interrupt-parent = <&mdss>;
568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mmcc MDSS_MDP_CLK>,
571 <&mmcc MDSS_AHB_CLK>,
572 <&mmcc MDSS_HDMI_CLK>,
573 <&mmcc MDSS_HDMI_AHB_CLK>,
574 <&mmcc MDSS_EXTPCLK_CLK>;
583 phy-names = "hdmi_phy";
584 #sound-dai-cells = <1>;
587 #address-cells = <1>;
593 remote-endpoint = <&mdp5_intf3_out>;
599 hdmi_phy: hdmi-phy@9a0600 {
601 compatible = "qcom,hdmi-phy-8996";
602 reg = <0x009a0600 0x1c4>,
608 reg-names = "hdmi_pll",
615 clocks = <&mmcc MDSS_AHB_CLK>,
616 <&gcc GCC_HDMI_CLKREF_CLK>;
617 clock-names = "iface",
622 compatible = "qcom,adreno-530.2", "qcom,adreno";
623 #stream-id-cells = <16>;
625 reg = <0x00b00000 0x3f000>;
626 reg-names = "kgsl_3d0_reg_memory";
628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
632 <&mmcc GPU_GX_RBBMTIMER_CLK>,
633 <&gcc GCC_BIMC_GFX_CLK>,
634 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
636 clock-names = "core",
642 power-domains = <&mmcc GPU_GX_GDSC>;
643 iommus = <&adreno_smmu 0>;
645 nvmem-cells = <&gpu_speed_bin>;
646 nvmem-cell-names = "speed_bin";
648 qcom,gpu-quirk-two-pass-use-wfi;
649 qcom,gpu-quirk-fault-detect-mask;
651 operating-points-v2 = <&gpu_opp_table>;
653 gpu_opp_table: opp-table {
654 compatible ="operating-points-v2";
657 * 624Mhz and 560Mhz are only available on speed
658 * bin (1 << 0). All the rest are available on
659 * all bins of the hardware
662 opp-hz = /bits/ 64 <624000000>;
663 opp-supported-hw = <0x01>;
666 opp-hz = /bits/ 64 <560000000>;
667 opp-supported-hw = <0x01>;
670 opp-hz = /bits/ 64 <510000000>;
671 opp-supported-hw = <0xFF>;
674 opp-hz = /bits/ 64 <401800000>;
675 opp-supported-hw = <0xFF>;
678 opp-hz = /bits/ 64 <315000000>;
679 opp-supported-hw = <0xFF>;
682 opp-hz = /bits/ 64 <214000000>;
683 opp-supported-hw = <0xFF>;
686 opp-hz = /bits/ 64 <133000000>;
687 opp-supported-hw = <0xFF>;
692 memory-region = <&zap_shader_region>;
696 msmgpio: pinctrl@1010000 {
697 compatible = "qcom,msm8996-pinctrl";
698 reg = <0x01010000 0x300000>;
699 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
701 gpio-ranges = <&msmgpio 0 0 150>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
707 spmi_bus: qcom,spmi@400f000 {
708 compatible = "qcom,spmi-pmic-arb";
709 reg = <0x0400f000 0x1000>,
710 <0x04400000 0x800000>,
711 <0x04c00000 0x800000>,
712 <0x05800000 0x200000>,
713 <0x0400a000 0x002100>;
714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
715 interrupt-names = "periph_irq";
716 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <2>;
721 interrupt-controller;
722 #interrupt-cells = <4>;
726 power-domains = <&gcc AGGRE0_NOC_GDSC>;
727 compatible = "simple-pm-bus";
728 #address-cells = <1>;
733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
735 power-domains = <&gcc PCIE0_GDSC>;
736 bus-range = <0x00 0xff>;
739 reg = <0x00600000 0x2000>,
742 <0x0c100000 0x100000>;
743 reg-names = "parf", "dbi", "elbi","config";
746 phy-names = "pciephy";
748 #address-cells = <3>;
750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
755 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
756 interrupt-names = "msi";
757 #interrupt-cells = <1>;
758 interrupt-map-mask = <0 0 0 0x7>;
759 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
760 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
761 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
762 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
764 pinctrl-names = "default", "sleep";
765 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
766 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
768 linux,pci-domain = <0>;
770 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
771 <&gcc GCC_PCIE_0_AUX_CLK>,
772 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
773 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
774 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
776 clock-names = "pipe",
785 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
786 power-domains = <&gcc PCIE1_GDSC>;
787 bus-range = <0x00 0xff>;
792 reg = <0x00608000 0x2000>,
795 <0x0d100000 0x100000>;
797 reg-names = "parf", "dbi", "elbi","config";
800 phy-names = "pciephy";
802 #address-cells = <3>;
804 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
805 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
809 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "msi";
811 #interrupt-cells = <1>;
812 interrupt-map-mask = <0 0 0 0x7>;
813 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
814 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
815 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
816 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
818 pinctrl-names = "default", "sleep";
819 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
820 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
822 linux,pci-domain = <1>;
824 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
825 <&gcc GCC_PCIE_1_AUX_CLK>,
826 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
827 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
828 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
830 clock-names = "pipe",
838 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
839 power-domains = <&gcc PCIE2_GDSC>;
840 bus-range = <0x00 0xff>;
843 reg = <0x00610000 0x2000>,
846 <0x0e100000 0x100000>;
848 reg-names = "parf", "dbi", "elbi","config";
851 phy-names = "pciephy";
853 #address-cells = <3>;
855 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
856 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
860 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
861 interrupt-names = "msi";
862 #interrupt-cells = <1>;
863 interrupt-map-mask = <0 0 0 0x7>;
864 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
865 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
866 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
867 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
869 pinctrl-names = "default", "sleep";
870 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
871 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
873 linux,pci-domain = <2>;
874 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
875 <&gcc GCC_PCIE_2_AUX_CLK>,
876 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
877 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
878 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
880 clock-names = "pipe",
888 ufshc: ufshc@624000 {
889 compatible = "qcom,ufshc";
890 reg = <0x00624000 0x2500>;
891 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
893 phys = <&ufsphy_lane>;
894 phy-names = "ufsphy";
896 power-domains = <&gcc UFS_GDSC>;
904 "core_clk_unipro_src",
911 <&gcc UFS_AXI_CLK_SRC>,
912 <&gcc GCC_UFS_AXI_CLK>,
913 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
914 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
915 <&gcc GCC_UFS_AHB_CLK>,
916 <&gcc UFS_ICE_CORE_CLK_SRC>,
917 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
918 <&gcc GCC_UFS_ICE_CORE_CLK>,
919 <&rpmcc RPM_SMD_LN_BB_CLK>,
920 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
921 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
923 <100000000 200000000>,
928 <150000000 300000000>,
935 lanes-per-direction = <1>;
940 compatible = "qcom,ufs_variant";
945 compatible = "qcom,msm8996-qmp-ufs-phy";
946 reg = <0x00627000 0x1c4>;
947 #address-cells = <1>;
951 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
955 reset-names = "ufsphy";
958 ufsphy_lane: lanes@627400 {
959 reg = <0x627400 0x12c>,
966 camss: camss@a00000 {
967 compatible = "qcom,msm8996-camss";
968 reg = <0x00a34000 0x1000>,
982 reg-names = "csiphy0",
996 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1004 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1005 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1006 interrupt-names = "csiphy0",
1016 power-domains = <&mmcc VFE0_GDSC>,
1018 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1019 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1020 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1021 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1022 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1023 <&mmcc CAMSS_CSI0_AHB_CLK>,
1024 <&mmcc CAMSS_CSI0_CLK>,
1025 <&mmcc CAMSS_CSI0PHY_CLK>,
1026 <&mmcc CAMSS_CSI0PIX_CLK>,
1027 <&mmcc CAMSS_CSI0RDI_CLK>,
1028 <&mmcc CAMSS_CSI1_AHB_CLK>,
1029 <&mmcc CAMSS_CSI1_CLK>,
1030 <&mmcc CAMSS_CSI1PHY_CLK>,
1031 <&mmcc CAMSS_CSI1PIX_CLK>,
1032 <&mmcc CAMSS_CSI1RDI_CLK>,
1033 <&mmcc CAMSS_CSI2_AHB_CLK>,
1034 <&mmcc CAMSS_CSI2_CLK>,
1035 <&mmcc CAMSS_CSI2PHY_CLK>,
1036 <&mmcc CAMSS_CSI2PIX_CLK>,
1037 <&mmcc CAMSS_CSI2RDI_CLK>,
1038 <&mmcc CAMSS_CSI3_AHB_CLK>,
1039 <&mmcc CAMSS_CSI3_CLK>,
1040 <&mmcc CAMSS_CSI3PHY_CLK>,
1041 <&mmcc CAMSS_CSI3PIX_CLK>,
1042 <&mmcc CAMSS_CSI3RDI_CLK>,
1043 <&mmcc CAMSS_AHB_CLK>,
1044 <&mmcc CAMSS_VFE0_CLK>,
1045 <&mmcc CAMSS_CSI_VFE0_CLK>,
1046 <&mmcc CAMSS_VFE0_AHB_CLK>,
1047 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1048 <&mmcc CAMSS_VFE1_CLK>,
1049 <&mmcc CAMSS_CSI_VFE1_CLK>,
1050 <&mmcc CAMSS_VFE1_AHB_CLK>,
1051 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1052 <&mmcc CAMSS_VFE_AHB_CLK>,
1053 <&mmcc CAMSS_VFE_AXI_CLK>;
1054 clock-names = "top_ahb",
1090 iommus = <&vfe_smmu 0>,
1094 status = "disabled";
1096 #address-cells = <1>;
1102 compatible = "qcom,msm8996-cci";
1103 #address-cells = <1>;
1105 reg = <0xa0c000 0x1000>;
1106 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1107 power-domains = <&mmcc CAMSS_GDSC>;
1108 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1109 <&mmcc CAMSS_CCI_AHB_CLK>,
1110 <&mmcc CAMSS_CCI_CLK>,
1111 <&mmcc CAMSS_AHB_CLK>;
1112 clock-names = "camss_top_ahb",
1116 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1117 <&mmcc CAMSS_CCI_CLK>;
1118 assigned-clock-rates = <80000000>, <37500000>;
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&cci0_default &cci1_default>;
1121 status = "disabled";
1123 cci_i2c0: i2c-bus@0 {
1125 clock-frequency = <400000>;
1126 #address-cells = <1>;
1130 cci_i2c1: i2c-bus@1 {
1132 clock-frequency = <400000>;
1133 #address-cells = <1>;
1138 adreno_smmu: iommu@b40000 {
1139 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1140 reg = <0x00b40000 0x10000>;
1142 #global-interrupts = <1>;
1143 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&mmcc GPU_AHB_CLK>,
1149 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1150 clock-names = "iface", "bus";
1152 power-domains = <&mmcc GPU_GDSC>;
1155 video-codec@c00000 {
1156 compatible = "qcom,msm8996-venus";
1157 reg = <0x00c00000 0xff000>;
1158 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1159 power-domains = <&mmcc VENUS_GDSC>;
1160 clocks = <&mmcc VIDEO_CORE_CLK>,
1161 <&mmcc VIDEO_AHB_CLK>,
1162 <&mmcc VIDEO_AXI_CLK>,
1163 <&mmcc VIDEO_MAXI_CLK>;
1164 clock-names = "core", "iface", "bus", "mbus";
1165 iommus = <&venus_smmu 0x00>,
1185 memory-region = <&venus_region>;
1189 compatible = "venus-decoder";
1190 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1191 clock-names = "core";
1192 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1196 compatible = "venus-encoder";
1197 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1198 clock-names = "core";
1199 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1203 mdp_smmu: iommu@d00000 {
1204 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1205 reg = <0x00d00000 0x10000>;
1207 #global-interrupts = <1>;
1208 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1212 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1213 <&mmcc SMMU_MDP_AXI_CLK>;
1214 clock-names = "iface", "bus";
1216 power-domains = <&mmcc MDSS_GDSC>;
1219 venus_smmu: iommu@d40000 {
1220 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1221 reg = <0x00d40000 0x20000>;
1222 #global-interrupts = <1>;
1223 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1231 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1232 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1233 <&mmcc SMMU_VIDEO_AXI_CLK>;
1234 clock-names = "iface", "bus";
1239 vfe_smmu: iommu@da0000 {
1240 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1241 reg = <0x00da0000 0x10000>;
1243 #global-interrupts = <1>;
1244 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1247 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1248 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1249 <&mmcc SMMU_VFE_AXI_CLK>;
1250 clock-names = "iface",
1255 lpass_q6_smmu: iommu@1600000 {
1256 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1257 reg = <0x01600000 0x20000>;
1259 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1261 #global-interrupts = <1>;
1262 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1276 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1277 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1278 clock-names = "iface", "bus";
1282 compatible = "arm,coresight-stm", "arm,primecell";
1283 reg = <0x3002000 0x1000>,
1284 <0x8280000 0x180000>;
1285 reg-names = "stm-base", "stm-stimulus-base";
1287 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1288 clock-names = "apb_pclk", "atclk";
1301 compatible = "arm,coresight-tpiu", "arm,primecell";
1302 reg = <0x3020000 0x1000>;
1304 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1305 clock-names = "apb_pclk", "atclk";
1318 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1319 reg = <0x3021000 0x1000>;
1321 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1322 clock-names = "apb_pclk", "atclk";
1325 #address-cells = <1>;
1330 funnel0_in: endpoint {
1339 funnel0_out: endpoint {
1341 <&merge_funnel_in0>;
1348 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1349 reg = <0x3022000 0x1000>;
1351 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1352 clock-names = "apb_pclk", "atclk";
1355 #address-cells = <1>;
1360 funnel1_in: endpoint {
1362 <&apss_merge_funnel_out>;
1369 funnel1_out: endpoint {
1371 <&merge_funnel_in1>;
1378 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1379 reg = <0x3023000 0x1000>;
1381 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1382 clock-names = "apb_pclk", "atclk";
1387 funnel2_out: endpoint {
1389 <&merge_funnel_in2>;
1396 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1397 reg = <0x3025000 0x1000>;
1399 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1400 clock-names = "apb_pclk", "atclk";
1403 #address-cells = <1>;
1408 merge_funnel_in0: endpoint {
1416 merge_funnel_in1: endpoint {
1424 merge_funnel_in2: endpoint {
1433 merge_funnel_out: endpoint {
1441 replicator@3026000 {
1442 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1443 reg = <0x3026000 0x1000>;
1445 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1446 clock-names = "apb_pclk", "atclk";
1450 replicator_in: endpoint {
1458 #address-cells = <1>;
1463 replicator_out0: endpoint {
1471 replicator_out1: endpoint {
1480 compatible = "arm,coresight-tmc", "arm,primecell";
1481 reg = <0x3027000 0x1000>;
1483 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1484 clock-names = "apb_pclk", "atclk";
1490 <&merge_funnel_out>;
1506 compatible = "arm,coresight-tmc", "arm,primecell";
1507 reg = <0x3028000 0x1000>;
1509 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1510 clock-names = "apb_pclk", "atclk";
1524 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1525 reg = <0x3810000 0x1000>;
1527 clocks = <&rpmcc RPM_QDSS_CLK>;
1528 clock-names = "apb_pclk";
1534 compatible = "arm,coresight-etm4x", "arm,primecell";
1535 reg = <0x3840000 0x1000>;
1537 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1538 clock-names = "apb_pclk", "atclk";
1544 etm0_out: endpoint {
1546 <&apss_funnel0_in0>;
1553 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1554 reg = <0x3910000 0x1000>;
1556 clocks = <&rpmcc RPM_QDSS_CLK>;
1557 clock-names = "apb_pclk";
1563 compatible = "arm,coresight-etm4x", "arm,primecell";
1564 reg = <0x3940000 0x1000>;
1566 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1567 clock-names = "apb_pclk", "atclk";
1573 etm1_out: endpoint {
1575 <&apss_funnel0_in1>;
1581 funnel@39b0000 { /* APSS Funnel 0 */
1582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1583 reg = <0x39b0000 0x1000>;
1585 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1586 clock-names = "apb_pclk", "atclk";
1589 #address-cells = <1>;
1594 apss_funnel0_in0: endpoint {
1595 remote-endpoint = <&etm0_out>;
1601 apss_funnel0_in1: endpoint {
1602 remote-endpoint = <&etm1_out>;
1609 apss_funnel0_out: endpoint {
1611 <&apss_merge_funnel_in0>;
1618 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1619 reg = <0x3a10000 0x1000>;
1621 clocks = <&rpmcc RPM_QDSS_CLK>;
1622 clock-names = "apb_pclk";
1628 compatible = "arm,coresight-etm4x", "arm,primecell";
1629 reg = <0x3a40000 0x1000>;
1631 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1632 clock-names = "apb_pclk", "atclk";
1638 etm2_out: endpoint {
1640 <&apss_funnel1_in0>;
1647 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1648 reg = <0x3b10000 0x1000>;
1650 clocks = <&rpmcc RPM_QDSS_CLK>;
1651 clock-names = "apb_pclk";
1657 compatible = "arm,coresight-etm4x", "arm,primecell";
1658 reg = <0x3b40000 0x1000>;
1660 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1661 clock-names = "apb_pclk", "atclk";
1667 etm3_out: endpoint {
1669 <&apss_funnel1_in1>;
1675 funnel@3bb0000 { /* APSS Funnel 1 */
1676 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1677 reg = <0x3bb0000 0x1000>;
1679 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1680 clock-names = "apb_pclk", "atclk";
1683 #address-cells = <1>;
1688 apss_funnel1_in0: endpoint {
1689 remote-endpoint = <&etm2_out>;
1695 apss_funnel1_in1: endpoint {
1696 remote-endpoint = <&etm3_out>;
1703 apss_funnel1_out: endpoint {
1705 <&apss_merge_funnel_in1>;
1712 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1713 reg = <0x3bc0000 0x1000>;
1715 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1716 clock-names = "apb_pclk", "atclk";
1719 #address-cells = <1>;
1724 apss_merge_funnel_in0: endpoint {
1726 <&apss_funnel0_out>;
1732 apss_merge_funnel_in1: endpoint {
1734 <&apss_funnel1_out>;
1741 apss_merge_funnel_out: endpoint {
1748 kryocc: clock-controller@6400000 {
1749 compatible = "qcom,apcc-msm8996";
1750 reg = <0x06400000 0x90000>;
1755 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1756 reg = <0x06af8800 0x400>;
1757 #address-cells = <1>;
1761 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1762 <&gcc GCC_USB30_MASTER_CLK>,
1763 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1764 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1765 <&gcc GCC_USB30_SLEEP_CLK>,
1766 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1768 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1769 <&gcc GCC_USB30_MASTER_CLK>;
1770 assigned-clock-rates = <19200000>, <120000000>;
1772 power-domains = <&gcc USB30_GDSC>;
1773 status = "disabled";
1776 compatible = "snps,dwc3";
1777 reg = <0x06a00000 0xcc00>;
1778 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1779 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1780 phy-names = "usb2-phy", "usb3-phy";
1781 snps,dis_u2_susphy_quirk;
1782 snps,dis_enblslpm_quirk;
1786 usb3phy: phy@7410000 {
1787 compatible = "qcom,msm8996-qmp-usb3-phy";
1788 reg = <0x07410000 0x1c4>;
1790 #address-cells = <1>;
1794 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1795 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1796 <&gcc GCC_USB3_CLKREF_CLK>;
1797 clock-names = "aux", "cfg_ahb", "ref";
1799 resets = <&gcc GCC_USB3_PHY_BCR>,
1800 <&gcc GCC_USB3PHY_PHY_BCR>;
1801 reset-names = "phy", "common";
1802 status = "disabled";
1804 ssusb_phy_0: lane@7410200 {
1805 reg = <0x07410200 0x200>,
1810 clock-output-names = "usb3_phy_pipe_clk_src";
1811 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1812 clock-names = "pipe0";
1816 hsusb_phy1: phy@7411000 {
1817 compatible = "qcom,msm8996-qusb2-phy";
1818 reg = <0x07411000 0x180>;
1821 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1822 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1823 clock-names = "cfg_ahb", "ref";
1825 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1826 nvmem-cells = <&qusb2p_hstx_trim>;
1827 status = "disabled";
1830 hsusb_phy2: phy@7412000 {
1831 compatible = "qcom,msm8996-qusb2-phy";
1832 reg = <0x07412000 0x180>;
1835 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1836 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1837 clock-names = "cfg_ahb", "ref";
1839 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1840 nvmem-cells = <&qusb2s_hstx_trim>;
1841 status = "disabled";
1844 sdhc2: sdhci@74a4900 {
1845 status = "disabled";
1846 compatible = "qcom,sdhci-msm-v4";
1847 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
1848 reg-names = "hc_mem", "core_mem";
1850 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1851 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1852 interrupt-names = "hc_irq", "pwr_irq";
1854 clock-names = "iface", "core", "xo";
1855 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1856 <&gcc GCC_SDCC2_APPS_CLK>,
1861 blsp1_uart1: serial@7570000 {
1862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x07570000 0x1000>;
1864 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1866 <&gcc GCC_BLSP1_AHB_CLK>;
1867 clock-names = "core", "iface";
1868 status = "disabled";
1871 blsp1_spi0: spi@7575000 {
1872 compatible = "qcom,spi-qup-v2.2.1";
1873 reg = <0x07575000 0x600>;
1874 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1875 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1876 <&gcc GCC_BLSP1_AHB_CLK>;
1877 clock-names = "core", "iface";
1878 pinctrl-names = "default", "sleep";
1879 pinctrl-0 = <&blsp1_spi0_default>;
1880 pinctrl-1 = <&blsp1_spi0_sleep>;
1881 #address-cells = <1>;
1883 status = "disabled";
1886 blsp1_i2c2: i2c@7577000 {
1887 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x07577000 0x1000>;
1889 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1890 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1891 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1892 clock-names = "iface", "core";
1893 pinctrl-names = "default", "sleep";
1894 pinctrl-0 = <&blsp1_i2c2_default>;
1895 pinctrl-1 = <&blsp1_i2c2_sleep>;
1896 #address-cells = <1>;
1898 status = "disabled";
1901 blsp2_uart1: serial@75b0000 {
1902 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1903 reg = <0x075b0000 0x1000>;
1904 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1905 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1906 <&gcc GCC_BLSP2_AHB_CLK>;
1907 clock-names = "core", "iface";
1908 status = "disabled";
1911 blsp2_uart2: serial@75b1000 {
1912 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1913 reg = <0x075b1000 0x1000>;
1914 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1915 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1916 <&gcc GCC_BLSP2_AHB_CLK>;
1917 clock-names = "core", "iface";
1918 status = "disabled";
1921 blsp2_i2c0: i2c@75b5000 {
1922 compatible = "qcom,i2c-qup-v2.2.1";
1923 reg = <0x075b5000 0x1000>;
1924 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1925 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1926 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1927 clock-names = "iface", "core";
1928 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&blsp2_i2c0_default>;
1930 pinctrl-1 = <&blsp2_i2c0_sleep>;
1931 #address-cells = <1>;
1933 status = "disabled";
1936 blsp2_i2c1: i2c@75b6000 {
1937 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x075b6000 0x1000>;
1939 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1940 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1941 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1942 clock-names = "iface", "core";
1943 pinctrl-names = "default", "sleep";
1944 pinctrl-0 = <&blsp2_i2c1_default>;
1945 pinctrl-1 = <&blsp2_i2c1_sleep>;
1946 #address-cells = <1>;
1948 status = "disabled";
1951 blsp2_spi5: spi@75ba000{
1952 compatible = "qcom,spi-qup-v2.2.1";
1953 reg = <0x075ba000 0x600>;
1954 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1955 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1956 <&gcc GCC_BLSP2_AHB_CLK>;
1957 clock-names = "core", "iface";
1958 pinctrl-names = "default", "sleep";
1959 pinctrl-0 = <&blsp2_spi5_default>;
1960 pinctrl-1 = <&blsp2_spi5_sleep>;
1961 #address-cells = <1>;
1963 status = "disabled";
1967 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1968 reg = <0x076f8800 0x400>;
1969 #address-cells = <1>;
1973 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1974 <&gcc GCC_USB20_MASTER_CLK>,
1975 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1976 <&gcc GCC_USB20_SLEEP_CLK>,
1977 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1979 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1980 <&gcc GCC_USB20_MASTER_CLK>;
1981 assigned-clock-rates = <19200000>, <60000000>;
1983 power-domains = <&gcc USB30_GDSC>;
1984 status = "disabled";
1987 compatible = "snps,dwc3";
1988 reg = <0x07600000 0xcc00>;
1989 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1990 phys = <&hsusb_phy2>;
1991 phy-names = "usb2-phy";
1992 snps,dis_u2_susphy_quirk;
1993 snps,dis_enblslpm_quirk;
1997 slimbam: dma-controller@9184000 {
1998 compatible = "qcom,bam-v1.7.0";
1999 qcom,controlled-remotely;
2000 reg = <0x09184000 0x32000>;
2001 num-channels = <31>;
2002 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2008 slim_msm: slim@91c0000 {
2009 compatible = "qcom,slim-ngd-v1.5.0";
2010 reg = <0x091c0000 0x2C000>;
2012 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2013 dmas = <&slimbam 3>, <&slimbam 4>,
2014 <&slimbam 5>, <&slimbam 6>;
2015 dma-names = "rx", "tx", "tx2", "rx2";
2016 #address-cells = <1>;
2020 #address-cells = <1>;
2023 tasha_ifd: tas-ifd {
2024 compatible = "slim217,1a0";
2029 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2030 pinctrl-names = "default";
2032 compatible = "slim217,1a0";
2035 interrupt-parent = <&msmgpio>;
2036 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2037 <53 IRQ_TYPE_LEVEL_HIGH>;
2038 interrupt-names = "intr1", "intr2";
2039 interrupt-controller;
2040 #interrupt-cells = <1>;
2041 reset-gpios = <&msmgpio 64 0>;
2043 slim-ifc-dev = <&tasha_ifd>;
2045 #sound-dai-cells = <1>;
2050 adsp_pil: remoteproc@9300000 {
2051 compatible = "qcom,msm8996-adsp-pil";
2052 reg = <0x09300000 0x80000>;
2054 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2055 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2056 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2057 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2058 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2059 interrupt-names = "wdog", "fatal", "ready",
2060 "handover", "stop-ack";
2062 clocks = <&xo_board>;
2065 memory-region = <&adsp_region>;
2067 qcom,smem-states = <&smp2p_adsp_out 0>;
2068 qcom,smem-state-names = "stop";
2071 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2074 mboxes = <&apcs_glb 8>;
2075 qcom,smd-edge = <1>;
2076 qcom,remote-pid = <2>;
2077 #address-cells = <1>;
2080 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2081 compatible = "qcom,apr-v2";
2082 qcom,smd-channels = "apr_audio_svc";
2083 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2084 #address-cells = <1>;
2088 reg = <APR_SVC_ADSP_CORE>;
2089 compatible = "qcom,q6core";
2093 compatible = "qcom,q6afe";
2094 reg = <APR_SVC_AFE>;
2096 compatible = "qcom,q6afe-dais";
2097 #address-cells = <1>;
2099 #sound-dai-cells = <1>;
2107 compatible = "qcom,q6asm";
2108 reg = <APR_SVC_ASM>;
2110 compatible = "qcom,q6asm-dais";
2111 #address-cells = <1>;
2113 #sound-dai-cells = <1>;
2114 iommus = <&lpass_q6_smmu 1>;
2119 compatible = "qcom,q6adm";
2120 reg = <APR_SVC_ADM>;
2121 q6routing: routing {
2122 compatible = "qcom,q6adm-routing";
2123 #sound-dai-cells = <0>;
2131 apcs_glb: mailbox@9820000 {
2132 compatible = "qcom,msm8996-apcs-hmss-global";
2133 reg = <0x09820000 0x1000>;
2139 #address-cells = <1>;
2142 compatible = "arm,armv7-timer-mem";
2143 reg = <0x09840000 0x1000>;
2144 clock-frequency = <19200000>;
2148 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2150 reg = <0x09850000 0x1000>,
2151 <0x09860000 0x1000>;
2156 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2157 reg = <0x09870000 0x1000>;
2158 status = "disabled";
2163 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2164 reg = <0x09880000 0x1000>;
2165 status = "disabled";
2170 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2171 reg = <0x09890000 0x1000>;
2172 status = "disabled";
2177 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2178 reg = <0x098a0000 0x1000>;
2179 status = "disabled";
2184 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2185 reg = <0x098b0000 0x1000>;
2186 status = "disabled";
2191 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2192 reg = <0x098c0000 0x1000>;
2193 status = "disabled";
2197 saw3: syscon@9a10000 {
2198 compatible = "syscon";
2199 reg = <0x09a10000 0x1000>;
2202 intc: interrupt-controller@9bc0000 {
2203 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
2204 #interrupt-cells = <3>;
2205 interrupt-controller;
2206 #redistributor-regions = <1>;
2207 redistributor-stride = <0x0 0x40000>;
2208 reg = <0x09bc0000 0x10000>,
2209 <0x09c00000 0x100000>;
2210 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2219 polling-delay-passive = <250>;
2220 polling-delay = <1000>;
2222 thermal-sensors = <&tsens0 3>;
2225 cpu0_alert0: trip-point0 {
2226 temperature = <75000>;
2227 hysteresis = <2000>;
2231 cpu0_crit: cpu_crit {
2232 temperature = <110000>;
2233 hysteresis = <2000>;
2240 polling-delay-passive = <250>;
2241 polling-delay = <1000>;
2243 thermal-sensors = <&tsens0 5>;
2246 cpu1_alert0: trip-point0 {
2247 temperature = <75000>;
2248 hysteresis = <2000>;
2252 cpu1_crit: cpu_crit {
2253 temperature = <110000>;
2254 hysteresis = <2000>;
2261 polling-delay-passive = <250>;
2262 polling-delay = <1000>;
2264 thermal-sensors = <&tsens0 8>;
2267 cpu2_alert0: trip-point0 {
2268 temperature = <75000>;
2269 hysteresis = <2000>;
2273 cpu2_crit: cpu_crit {
2274 temperature = <110000>;
2275 hysteresis = <2000>;
2282 polling-delay-passive = <250>;
2283 polling-delay = <1000>;
2285 thermal-sensors = <&tsens0 10>;
2288 cpu3_alert0: trip-point0 {
2289 temperature = <75000>;
2290 hysteresis = <2000>;
2294 cpu3_crit: cpu_crit {
2295 temperature = <110000>;
2296 hysteresis = <2000>;
2303 polling-delay-passive = <250>;
2304 polling-delay = <1000>;
2306 thermal-sensors = <&tsens1 6>;
2309 gpu1_alert0: trip-point0 {
2310 temperature = <90000>;
2311 hysteresis = <2000>;
2317 gpu-thermal-bottom {
2318 polling-delay-passive = <250>;
2319 polling-delay = <1000>;
2321 thermal-sensors = <&tsens1 7>;
2324 gpu2_alert0: trip-point0 {
2325 temperature = <90000>;
2326 hysteresis = <2000>;
2333 polling-delay-passive = <250>;
2334 polling-delay = <1000>;
2336 thermal-sensors = <&tsens0 1>;
2339 m4m_alert0: trip-point0 {
2340 temperature = <90000>;
2341 hysteresis = <2000>;
2347 l3-or-venus-thermal {
2348 polling-delay-passive = <250>;
2349 polling-delay = <1000>;
2351 thermal-sensors = <&tsens0 2>;
2354 l3_or_venus_alert0: trip-point0 {
2355 temperature = <90000>;
2356 hysteresis = <2000>;
2362 cluster0-l2-thermal {
2363 polling-delay-passive = <250>;
2364 polling-delay = <1000>;
2366 thermal-sensors = <&tsens0 7>;
2369 cluster0_l2_alert0: trip-point0 {
2370 temperature = <90000>;
2371 hysteresis = <2000>;
2377 cluster1-l2-thermal {
2378 polling-delay-passive = <250>;
2379 polling-delay = <1000>;
2381 thermal-sensors = <&tsens0 12>;
2384 cluster1_l2_alert0: trip-point0 {
2385 temperature = <90000>;
2386 hysteresis = <2000>;
2393 polling-delay-passive = <250>;
2394 polling-delay = <1000>;
2396 thermal-sensors = <&tsens1 1>;
2399 camera_alert0: trip-point0 {
2400 temperature = <90000>;
2401 hysteresis = <2000>;
2408 polling-delay-passive = <250>;
2409 polling-delay = <1000>;
2411 thermal-sensors = <&tsens1 2>;
2414 q6_dsp_alert0: trip-point0 {
2415 temperature = <90000>;
2416 hysteresis = <2000>;
2423 polling-delay-passive = <250>;
2424 polling-delay = <1000>;
2426 thermal-sensors = <&tsens1 3>;
2429 mem_alert0: trip-point0 {
2430 temperature = <90000>;
2431 hysteresis = <2000>;
2438 polling-delay-passive = <250>;
2439 polling-delay = <1000>;
2441 thermal-sensors = <&tsens1 4>;
2444 modemtx_alert0: trip-point0 {
2445 temperature = <90000>;
2446 hysteresis = <2000>;
2454 compatible = "arm,armv8-timer";
2455 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2456 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2457 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2458 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2461 #include "msm8996-pins.dtsi"