arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,apr.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         chosen { };
  20
  21         clocks {
  22                 xo_board: xo-board {
  23                         compatible = "fixed-clock";
  24                         #clock-cells = <0>;
  25                         clock-frequency = <19200000>;
  26                         clock-output-names = "xo_board";
  27                 };
  28
  29                 sleep_clk: sleep-clk {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <32764>;
  33                         clock-output-names = "sleep_clk";
  34                 };
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "qcom,kryo";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         cpu-idle-states = <&CPU_SLEEP_0>;
  47                         capacity-dmips-mhz = <1024>;
  48                         clocks = <&kryocc 0>;
  49                         operating-points-v2 = <&cluster0_opp>;
  50                         #cooling-cells = <2>;
  51                         next-level-cache = <&L2_0>;
  52                         L2_0: l2-cache {
  53                               compatible = "cache";
  54                               cache-level = <2>;
  55                         };
  56                 };
  57
  58                 CPU1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "qcom,kryo";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                         capacity-dmips-mhz = <1024>;
  65                         clocks = <&kryocc 0>;
  66                         operating-points-v2 = <&cluster0_opp>;
  67                         #cooling-cells = <2>;
  68                         next-level-cache = <&L2_0>;
  69                 };
  70
  71                 CPU2: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "qcom,kryo";
  74                         reg = <0x0 0x100>;
  75                         enable-method = "psci";
  76                         cpu-idle-states = <&CPU_SLEEP_0>;
  77                         capacity-dmips-mhz = <1024>;
  78                         clocks = <&kryocc 1>;
  79                         operating-points-v2 = <&cluster1_opp>;
  80                         #cooling-cells = <2>;
  81                         next-level-cache = <&L2_1>;
  82                         L2_1: l2-cache {
  83                               compatible = "cache";
  84                               cache-level = <2>;
  85                         };
  86                 };
  87
  88                 CPU3: cpu@101 {
  89                         device_type = "cpu";
  90                         compatible = "qcom,kryo";
  91                         reg = <0x0 0x101>;
  92                         enable-method = "psci";
  93                         cpu-idle-states = <&CPU_SLEEP_0>;
  94                         capacity-dmips-mhz = <1024>;
  95                         clocks = <&kryocc 1>;
  96                         operating-points-v2 = <&cluster1_opp>;
  97                         #cooling-cells = <2>;
  98                         next-level-cache = <&L2_1>;
  99                 };
 100
 101                 cpu-map {
 102                         cluster0 {
 103                                 core0 {
 104                                         cpu = <&CPU0>;
 105                                 };
 106
 107                                 core1 {
 108                                         cpu = <&CPU1>;
 109                                 };
 110                         };
 111
 112                         cluster1 {
 113                                 core0 {
 114                                         cpu = <&CPU2>;
 115                                 };
 116
 117                                 core1 {
 118                                         cpu = <&CPU3>;
 119                                 };
 120                         };
 121                 };
 122
 123                 idle-states {
 124                         entry-method = "psci";
 125
 126                         CPU_SLEEP_0: cpu-sleep-0 {
 127                                 compatible = "arm,idle-state";
 128                                 idle-state-name = "standalone-power-collapse";
 129                                 arm,psci-suspend-param = <0x00000004>;
 130                                 entry-latency-us = <130>;
 131                                 exit-latency-us = <80>;
 132                                 min-residency-us = <300>;
 133                         };
 134                 };
 135         };
 136
 137         cluster0_opp: opp-table-cluster0 {
 138                 compatible = "operating-points-v2-kryo-cpu";
 139                 nvmem-cells = <&speedbin_efuse>;
 140                 opp-shared;
 141
 142                 /* Nominal fmax for now */
 143                 opp-307200000 {
 144                         opp-hz = /bits/ 64 <307200000>;
 145                         opp-supported-hw = <0x77>;
 146                         clock-latency-ns = <200000>;
 147                 };
 148                 opp-422400000 {
 149                         opp-hz = /bits/ 64 <422400000>;
 150                         opp-supported-hw = <0x77>;
 151                         clock-latency-ns = <200000>;
 152                 };
 153                 opp-480000000 {
 154                         opp-hz = /bits/ 64 <480000000>;
 155                         opp-supported-hw = <0x77>;
 156                         clock-latency-ns = <200000>;
 157                 };
 158                 opp-556800000 {
 159                         opp-hz = /bits/ 64 <556800000>;
 160                         opp-supported-hw = <0x77>;
 161                         clock-latency-ns = <200000>;
 162                 };
 163                 opp-652800000 {
 164                         opp-hz = /bits/ 64 <652800000>;
 165                         opp-supported-hw = <0x77>;
 166                         clock-latency-ns = <200000>;
 167                 };
 168                 opp-729600000 {
 169                         opp-hz = /bits/ 64 <729600000>;
 170                         opp-supported-hw = <0x77>;
 171                         clock-latency-ns = <200000>;
 172                 };
 173                 opp-844800000 {
 174                         opp-hz = /bits/ 64 <844800000>;
 175                         opp-supported-hw = <0x77>;
 176                         clock-latency-ns = <200000>;
 177                 };
 178                 opp-960000000 {
 179                         opp-hz = /bits/ 64 <960000000>;
 180                         opp-supported-hw = <0x77>;
 181                         clock-latency-ns = <200000>;
 182                 };
 183                 opp-1036800000 {
 184                         opp-hz = /bits/ 64 <1036800000>;
 185                         opp-supported-hw = <0x77>;
 186                         clock-latency-ns = <200000>;
 187                 };
 188                 opp-1113600000 {
 189                         opp-hz = /bits/ 64 <1113600000>;
 190                         opp-supported-hw = <0x77>;
 191                         clock-latency-ns = <200000>;
 192                 };
 193                 opp-1190400000 {
 194                         opp-hz = /bits/ 64 <1190400000>;
 195                         opp-supported-hw = <0x77>;
 196                         clock-latency-ns = <200000>;
 197                 };
 198                 opp-1228800000 {
 199                         opp-hz = /bits/ 64 <1228800000>;
 200                         opp-supported-hw = <0x77>;
 201                         clock-latency-ns = <200000>;
 202                 };
 203                 opp-1324800000 {
 204                         opp-hz = /bits/ 64 <1324800000>;
 205                         opp-supported-hw = <0x77>;
 206                         clock-latency-ns = <200000>;
 207                 };
 208                 opp-1401600000 {
 209                         opp-hz = /bits/ 64 <1401600000>;
 210                         opp-supported-hw = <0x77>;
 211                         clock-latency-ns = <200000>;
 212                 };
 213                 opp-1478400000 {
 214                         opp-hz = /bits/ 64 <1478400000>;
 215                         opp-supported-hw = <0x77>;
 216                         clock-latency-ns = <200000>;
 217                 };
 218                 opp-1593600000 {
 219                         opp-hz = /bits/ 64 <1593600000>;
 220                         opp-supported-hw = <0x77>;
 221                         clock-latency-ns = <200000>;
 222                 };
 223         };
 224
 225         cluster1_opp: opp-table-cluster1 {
 226                 compatible = "operating-points-v2-kryo-cpu";
 227                 nvmem-cells = <&speedbin_efuse>;
 228                 opp-shared;
 229
 230                 /* Nominal fmax for now */
 231                 opp-307200000 {
 232                         opp-hz = /bits/ 64 <307200000>;
 233                         opp-supported-hw = <0x77>;
 234                         clock-latency-ns = <200000>;
 235                 };
 236                 opp-403200000 {
 237                         opp-hz = /bits/ 64 <403200000>;
 238                         opp-supported-hw = <0x77>;
 239                         clock-latency-ns = <200000>;
 240                 };
 241                 opp-480000000 {
 242                         opp-hz = /bits/ 64 <480000000>;
 243                         opp-supported-hw = <0x77>;
 244                         clock-latency-ns = <200000>;
 245                 };
 246                 opp-556800000 {
 247                         opp-hz = /bits/ 64 <556800000>;
 248                         opp-supported-hw = <0x77>;
 249                         clock-latency-ns = <200000>;
 250                 };
 251                 opp-652800000 {
 252                         opp-hz = /bits/ 64 <652800000>;
 253                         opp-supported-hw = <0x77>;
 254                         clock-latency-ns = <200000>;
 255                 };
 256                 opp-729600000 {
 257                         opp-hz = /bits/ 64 <729600000>;
 258                         opp-supported-hw = <0x77>;
 259                         clock-latency-ns = <200000>;
 260                 };
 261                 opp-806400000 {
 262                         opp-hz = /bits/ 64 <806400000>;
 263                         opp-supported-hw = <0x77>;
 264                         clock-latency-ns = <200000>;
 265                 };
 266                 opp-883200000 {
 267                         opp-hz = /bits/ 64 <883200000>;
 268                         opp-supported-hw = <0x77>;
 269                         clock-latency-ns = <200000>;
 270                 };
 271                 opp-940800000 {
 272                         opp-hz = /bits/ 64 <940800000>;
 273                         opp-supported-hw = <0x77>;
 274                         clock-latency-ns = <200000>;
 275                 };
 276                 opp-1036800000 {
 277                         opp-hz = /bits/ 64 <1036800000>;
 278                         opp-supported-hw = <0x77>;
 279                         clock-latency-ns = <200000>;
 280                 };
 281                 opp-1113600000 {
 282                         opp-hz = /bits/ 64 <1113600000>;
 283                         opp-supported-hw = <0x77>;
 284                         clock-latency-ns = <200000>;
 285                 };
 286                 opp-1190400000 {
 287                         opp-hz = /bits/ 64 <1190400000>;
 288                         opp-supported-hw = <0x77>;
 289                         clock-latency-ns = <200000>;
 290                 };
 291                 opp-1248000000 {
 292                         opp-hz = /bits/ 64 <1248000000>;
 293                         opp-supported-hw = <0x77>;
 294                         clock-latency-ns = <200000>;
 295                 };
 296                 opp-1324800000 {
 297                         opp-hz = /bits/ 64 <1324800000>;
 298                         opp-supported-hw = <0x77>;
 299                         clock-latency-ns = <200000>;
 300                 };
 301                 opp-1401600000 {
 302                         opp-hz = /bits/ 64 <1401600000>;
 303                         opp-supported-hw = <0x77>;
 304                         clock-latency-ns = <200000>;
 305                 };
 306                 opp-1478400000 {
 307                         opp-hz = /bits/ 64 <1478400000>;
 308                         opp-supported-hw = <0x77>;
 309                         clock-latency-ns = <200000>;
 310                 };
 311                 opp-1555200000 {
 312                         opp-hz = /bits/ 64 <1555200000>;
 313                         opp-supported-hw = <0x77>;
 314                         clock-latency-ns = <200000>;
 315                 };
 316                 opp-1632000000 {
 317                         opp-hz = /bits/ 64 <1632000000>;
 318                         opp-supported-hw = <0x77>;
 319                         clock-latency-ns = <200000>;
 320                 };
 321                 opp-1708800000 {
 322                         opp-hz = /bits/ 64 <1708800000>;
 323                         opp-supported-hw = <0x77>;
 324                         clock-latency-ns = <200000>;
 325                 };
 326                 opp-1785600000 {
 327                         opp-hz = /bits/ 64 <1785600000>;
 328                         opp-supported-hw = <0x77>;
 329                         clock-latency-ns = <200000>;
 330                 };
 331                 opp-1824000000 {
 332                         opp-hz = /bits/ 64 <1824000000>;
 333                         opp-supported-hw = <0x77>;
 334                         clock-latency-ns = <200000>;
 335                 };
 336                 opp-1920000000 {
 337                         opp-hz = /bits/ 64 <1920000000>;
 338                         opp-supported-hw = <0x77>;
 339                         clock-latency-ns = <200000>;
 340                 };
 341                 opp-1996800000 {
 342                         opp-hz = /bits/ 64 <1996800000>;
 343                         opp-supported-hw = <0x77>;
 344                         clock-latency-ns = <200000>;
 345                 };
 346                 opp-2073600000 {
 347                         opp-hz = /bits/ 64 <2073600000>;
 348                         opp-supported-hw = <0x77>;
 349                         clock-latency-ns = <200000>;
 350                 };
 351                 opp-2150400000 {
 352                         opp-hz = /bits/ 64 <2150400000>;
 353                         opp-supported-hw = <0x77>;
 354                         clock-latency-ns = <200000>;
 355                 };
 356         };
 357
 358         firmware {
 359                 scm {
 360                         compatible = "qcom,scm-msm8996";
 361                         qcom,dload-mode = <&tcsr 0x13000>;
 362                 };
 363         };
 364
 365         tcsr_mutex: hwlock {
 366                 compatible = "qcom,tcsr-mutex";
 367                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 368                 #hwlock-cells = <1>;
 369         };
 370
 371         memory@80000000 {
 372                 device_type = "memory";
 373                 /* We expect the bootloader to fill in the reg */
 374                 reg = <0x0 0x80000000 0x0 0x0>;
 375         };
 376
 377         psci {
 378                 compatible = "arm,psci-1.0";
 379                 method = "smc";
 380         };
 381
 382         reserved-memory {
 383                 #address-cells = <2>;
 384                 #size-cells = <2>;
 385                 ranges;
 386
 387                 hyp_mem: memory@85800000 {
 388                         reg = <0x0 0x85800000 0x0 0x600000>;
 389                         no-map;
 390                 };
 391
 392                 xbl_mem: memory@85e00000 {
 393                         reg = <0x0 0x85e00000 0x0 0x200000>;
 394                         no-map;
 395                 };
 396
 397                 smem_mem: smem-mem@86000000 {
 398                         reg = <0x0 0x86000000 0x0 0x200000>;
 399                         no-map;
 400                 };
 401
 402                 tz_mem: memory@86200000 {
 403                         reg = <0x0 0x86200000 0x0 0x2600000>;
 404                         no-map;
 405                 };
 406
 407                 rmtfs_mem: rmtfs {
 408                         compatible = "qcom,rmtfs-mem";
 409
 410                         size = <0x0 0x200000>;
 411                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
 412                         no-map;
 413
 414                         qcom,client-id = <1>;
 415                         qcom,vmid = <15>;
 416                 };
 417
 418                 mpss_mem: mpss@88800000 {
 419                         reg = <0x0 0x88800000 0x0 0x6200000>;
 420                         no-map;
 421                 };
 422
 423                 adsp_mem: adsp@8ea00000 {
 424                         reg = <0x0 0x8ea00000 0x0 0x1b00000>;
 425                         no-map;
 426                 };
 427
 428                 slpi_mem: slpi@90500000 {
 429                         reg = <0x0 0x90500000 0x0 0xa00000>;
 430                         no-map;
 431                 };
 432
 433                 gpu_mem: gpu@90f00000 {
 434                         compatible = "shared-dma-pool";
 435                         reg = <0x0 0x90f00000 0x0 0x100000>;
 436                         no-map;
 437                 };
 438
 439                 venus_mem: venus@91000000 {
 440                         reg = <0x0 0x91000000 0x0 0x500000>;
 441                         no-map;
 442                 };
 443
 444                 mba_mem: mba@91500000 {
 445                         reg = <0x0 0x91500000 0x0 0x200000>;
 446                         no-map;
 447                 };
 448         };
 449
 450         rpm-glink {
 451                 compatible = "qcom,glink-rpm";
 452
 453                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 454
 455                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 456
 457                 mboxes = <&apcs_glb 0>;
 458
 459                 rpm_requests: rpm-requests {
 460                         compatible = "qcom,rpm-msm8996";
 461                         qcom,glink-channels = "rpm_requests";
 462
 463                         rpmcc: qcom,rpmcc {
 464                                 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
 465                                 #clock-cells = <1>;
 466                         };
 467
 468                         rpmpd: power-controller {
 469                                 compatible = "qcom,msm8996-rpmpd";
 470                                 #power-domain-cells = <1>;
 471                                 operating-points-v2 = <&rpmpd_opp_table>;
 472
 473                                 rpmpd_opp_table: opp-table {
 474                                         compatible = "operating-points-v2";
 475
 476                                         rpmpd_opp1: opp1 {
 477                                                 opp-level = <1>;
 478                                         };
 479
 480                                         rpmpd_opp2: opp2 {
 481                                                 opp-level = <2>;
 482                                         };
 483
 484                                         rpmpd_opp3: opp3 {
 485                                                 opp-level = <3>;
 486                                         };
 487
 488                                         rpmpd_opp4: opp4 {
 489                                                 opp-level = <4>;
 490                                         };
 491
 492                                         rpmpd_opp5: opp5 {
 493                                                 opp-level = <5>;
 494                                         };
 495
 496                                         rpmpd_opp6: opp6 {
 497                                                 opp-level = <6>;
 498                                         };
 499                                 };
 500                         };
 501                 };
 502         };
 503
 504         smem {
 505                 compatible = "qcom,smem";
 506                 memory-region = <&smem_mem>;
 507                 hwlocks = <&tcsr_mutex 3>;
 508         };
 509
 510         smp2p-adsp {
 511                 compatible = "qcom,smp2p";
 512                 qcom,smem = <443>, <429>;
 513
 514                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 515
 516                 mboxes = <&apcs_glb 10>;
 517
 518                 qcom,local-pid = <0>;
 519                 qcom,remote-pid = <2>;
 520
 521                 adsp_smp2p_out: master-kernel {
 522                         qcom,entry-name = "master-kernel";
 523                         #qcom,smem-state-cells = <1>;
 524                 };
 525
 526                 adsp_smp2p_in: slave-kernel {
 527                         qcom,entry-name = "slave-kernel";
 528
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532         };
 533
 534         smp2p-mpss {
 535                 compatible = "qcom,smp2p";
 536                 qcom,smem = <435>, <428>;
 537
 538                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 539
 540                 mboxes = <&apcs_glb 14>;
 541
 542                 qcom,local-pid = <0>;
 543                 qcom,remote-pid = <1>;
 544
 545                 mpss_smp2p_out: master-kernel {
 546                         qcom,entry-name = "master-kernel";
 547                         #qcom,smem-state-cells = <1>;
 548                 };
 549
 550                 mpss_smp2p_in: slave-kernel {
 551                         qcom,entry-name = "slave-kernel";
 552
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                 };
 556         };
 557
 558         smp2p-slpi {
 559                 compatible = "qcom,smp2p";
 560                 qcom,smem = <481>, <430>;
 561
 562                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 563
 564                 mboxes = <&apcs_glb 26>;
 565
 566                 qcom,local-pid = <0>;
 567                 qcom,remote-pid = <3>;
 568
 569                 slpi_smp2p_out: master-kernel {
 570                         qcom,entry-name = "master-kernel";
 571                         #qcom,smem-state-cells = <1>;
 572                 };
 573
 574                 slpi_smp2p_in: slave-kernel {
 575                         qcom,entry-name = "slave-kernel";
 576
 577                         interrupt-controller;
 578                         #interrupt-cells = <2>;
 579                 };
 580         };
 581
 582         soc: soc {
 583                 #address-cells = <1>;
 584                 #size-cells = <1>;
 585                 ranges = <0 0 0 0xffffffff>;
 586                 compatible = "simple-bus";
 587
 588                 pcie_phy: phy@34000 {
 589                         compatible = "qcom,msm8996-qmp-pcie-phy";
 590                         reg = <0x00034000 0x488>;
 591                         #address-cells = <1>;
 592                         #size-cells = <1>;
 593                         ranges;
 594
 595                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 596                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 597                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 598                         clock-names = "aux", "cfg_ahb", "ref";
 599
 600                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 601                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 602                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 603                         reset-names = "phy", "common", "cfg";
 604                         status = "disabled";
 605
 606                         pciephy_0: phy@35000 {
 607                                 reg = <0x00035000 0x130>,
 608                                       <0x00035200 0x200>,
 609                                       <0x00035400 0x1dc>;
 610                                 #phy-cells = <0>;
 611
 612                                 #clock-cells = <1>;
 613                                 clock-output-names = "pcie_0_pipe_clk_src";
 614                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 615                                 clock-names = "pipe0";
 616                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 617                                 reset-names = "lane0";
 618                         };
 619
 620                         pciephy_1: phy@36000 {
 621                                 reg = <0x00036000 0x130>,
 622                                       <0x00036200 0x200>,
 623                                       <0x00036400 0x1dc>;
 624                                 #phy-cells = <0>;
 625
 626                                 clock-output-names = "pcie_1_pipe_clk_src";
 627                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 628                                 clock-names = "pipe1";
 629                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 630                                 reset-names = "lane1";
 631                         };
 632
 633                         pciephy_2: phy@37000 {
 634                                 reg = <0x00037000 0x130>,
 635                                       <0x00037200 0x200>,
 636                                       <0x00037400 0x1dc>;
 637                                 #phy-cells = <0>;
 638
 639                                 clock-output-names = "pcie_2_pipe_clk_src";
 640                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 641                                 clock-names = "pipe2";
 642                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 643                                 reset-names = "lane2";
 644                         };
 645                 };
 646
 647                 rpm_msg_ram: sram@68000 {
 648                         compatible = "qcom,rpm-msg-ram";
 649                         reg = <0x00068000 0x6000>;
 650                 };
 651
 652                 qfprom@74000 {
 653                         compatible = "qcom,qfprom";
 654                         reg = <0x00074000 0x8ff>;
 655                         #address-cells = <1>;
 656                         #size-cells = <1>;
 657
 658                         qusb2p_hstx_trim: hstx_trim@24e {
 659                                 reg = <0x24e 0x2>;
 660                                 bits = <5 4>;
 661                         };
 662
 663                         qusb2s_hstx_trim: hstx_trim@24f {
 664                                 reg = <0x24f 0x1>;
 665                                 bits = <1 4>;
 666                         };
 667
 668                         speedbin_efuse: speedbin@133 {
 669                                 reg = <0x133 0x1>;
 670                                 bits = <5 3>;
 671                         };
 672                 };
 673
 674                 rng: rng@83000 {
 675                         compatible = "qcom,prng-ee";
 676                         reg = <0x00083000 0x1000>;
 677                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 678                         clock-names = "core";
 679                 };
 680
 681                 gcc: clock-controller@300000 {
 682                         compatible = "qcom,gcc-msm8996";
 683                         #clock-cells = <1>;
 684                         #reset-cells = <1>;
 685                         #power-domain-cells = <1>;
 686                         reg = <0x00300000 0x90000>;
 687
 688                         clocks = <&rpmcc RPM_SMD_BB_CLK1>,
 689                                  <&rpmcc RPM_SMD_LN_BB_CLK>,
 690                                  <&sleep_clk>;
 691                         clock-names = "cxo", "cxo2", "sleep_clk";
 692                 };
 693
 694                 tsens0: thermal-sensor@4a9000 {
 695                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 696                         reg = <0x004a9000 0x1000>, /* TM */
 697                               <0x004a8000 0x1000>; /* SROT */
 698                         #qcom,sensors = <13>;
 699                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 701                         interrupt-names = "uplow", "critical";
 702                         #thermal-sensor-cells = <1>;
 703                 };
 704
 705                 tsens1: thermal-sensor@4ad000 {
 706                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 707                         reg = <0x004ad000 0x1000>, /* TM */
 708                               <0x004ac000 0x1000>; /* SROT */
 709                         #qcom,sensors = <8>;
 710                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 712                         interrupt-names = "uplow", "critical";
 713                         #thermal-sensor-cells = <1>;
 714                 };
 715
 716                 cryptobam: dma-controller@644000 {
 717                         compatible = "qcom,bam-v1.7.0";
 718                         reg = <0x00644000 0x24000>;
 719                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 720                         clocks = <&gcc GCC_CE1_CLK>;
 721                         clock-names = "bam_clk";
 722                         #dma-cells = <1>;
 723                         qcom,ee = <0>;
 724                         qcom,controlled-remotely;
 725                 };
 726
 727                 crypto: crypto@67a000 {
 728                         compatible = "qcom,crypto-v5.4";
 729                         reg = <0x0067a000 0x6000>;
 730                         clocks = <&gcc GCC_CE1_AHB_CLK>,
 731                                  <&gcc GCC_CE1_AXI_CLK>,
 732                                  <&gcc GCC_CE1_CLK>;
 733                         clock-names = "iface", "bus", "core";
 734                         dmas = <&cryptobam 6>, <&cryptobam 7>;
 735                         dma-names = "rx", "tx";
 736                 };
 737
 738                 tcsr_mutex_regs: syscon@740000 {
 739                         compatible = "syscon";
 740                         reg = <0x00740000 0x40000>;
 741                 };
 742
 743                 tcsr: syscon@7a0000 {
 744                         compatible = "qcom,tcsr-msm8996", "syscon";
 745                         reg = <0x007a0000 0x18000>;
 746                 };
 747
 748                 mmcc: clock-controller@8c0000 {
 749                         compatible = "qcom,mmcc-msm8996";
 750                         #clock-cells = <1>;
 751                         #reset-cells = <1>;
 752                         #power-domain-cells = <1>;
 753                         reg = <0x008c0000 0x40000>;
 754                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 755                                           <&mmcc MMPLL1_PLL>,
 756                                           <&mmcc MMPLL3_PLL>,
 757                                           <&mmcc MMPLL4_PLL>,
 758                                           <&mmcc MMPLL5_PLL>;
 759                         assigned-clock-rates = <624000000>,
 760                                                <810000000>,
 761                                                <980000000>,
 762                                                <960000000>,
 763                                                <825000000>;
 764                 };
 765
 766                 mdss: mdss@900000 {
 767                         compatible = "qcom,mdss";
 768
 769                         reg = <0x00900000 0x1000>,
 770                               <0x009b0000 0x1040>,
 771                               <0x009b8000 0x1040>;
 772                         reg-names = "mdss_phys",
 773                                     "vbif_phys",
 774                                     "vbif_nrt_phys";
 775
 776                         power-domains = <&mmcc MDSS_GDSC>;
 777                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 778
 779                         interrupt-controller;
 780                         #interrupt-cells = <1>;
 781
 782                         clocks = <&mmcc MDSS_AHB_CLK>;
 783                         clock-names = "iface";
 784
 785                         #address-cells = <1>;
 786                         #size-cells = <1>;
 787                         ranges;
 788
 789                         status = "disabled";
 790
 791                         mdp: mdp@901000 {
 792                                 compatible = "qcom,mdp5";
 793                                 reg = <0x00901000 0x90000>;
 794                                 reg-names = "mdp_phys";
 795
 796                                 interrupt-parent = <&mdss>;
 797                                 interrupts = <0>;
 798
 799                                 clocks = <&mmcc MDSS_AHB_CLK>,
 800                                          <&mmcc MDSS_AXI_CLK>,
 801                                          <&mmcc MDSS_MDP_CLK>,
 802                                          <&mmcc SMMU_MDP_AXI_CLK>,
 803                                          <&mmcc MDSS_VSYNC_CLK>;
 804                                 clock-names = "iface",
 805                                               "bus",
 806                                               "core",
 807                                               "iommu",
 808                                               "vsync";
 809
 810                                 iommus = <&mdp_smmu 0>;
 811
 812                                 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
 813                                          <&mmcc MDSS_VSYNC_CLK>;
 814                                 assigned-clock-rates = <300000000>,
 815                                          <19200000>;
 816
 817                                 ports {
 818                                         #address-cells = <1>;
 819                                         #size-cells = <0>;
 820
 821                                         port@0 {
 822                                                 reg = <0>;
 823                                                 mdp5_intf3_out: endpoint {
 824                                                         remote-endpoint = <&hdmi_in>;
 825                                                 };
 826                                         };
 827
 828                                         port@1 {
 829                                                 reg = <1>;
 830                                                 mdp5_intf1_out: endpoint {
 831                                                         remote-endpoint = <&dsi0_in>;
 832                                                 };
 833                                         };
 834                                 };
 835                         };
 836
 837                         dsi0: dsi@994000 {
 838                                 compatible = "qcom,mdss-dsi-ctrl";
 839                                 reg = <0x00994000 0x400>;
 840                                 reg-names = "dsi_ctrl";
 841
 842                                 interrupt-parent = <&mdss>;
 843                                 interrupts = <4>;
 844
 845                                 clocks = <&mmcc MDSS_MDP_CLK>,
 846                                          <&mmcc MDSS_BYTE0_CLK>,
 847                                          <&mmcc MDSS_AHB_CLK>,
 848                                          <&mmcc MDSS_AXI_CLK>,
 849                                          <&mmcc MMSS_MISC_AHB_CLK>,
 850                                          <&mmcc MDSS_PCLK0_CLK>,
 851                                          <&mmcc MDSS_ESC0_CLK>;
 852                                 clock-names = "mdp_core",
 853                                               "byte",
 854                                               "iface",
 855                                               "bus",
 856                                               "core_mmss",
 857                                               "pixel",
 858                                               "core";
 859
 860                                 phys = <&dsi0_phy>;
 861                                 phy-names = "dsi";
 862                                 status = "disabled";
 863
 864                                 #address-cells = <1>;
 865                                 #size-cells = <0>;
 866
 867                                 ports {
 868                                         #address-cells = <1>;
 869                                         #size-cells = <0>;
 870
 871                                         port@0 {
 872                                                 reg = <0>;
 873                                                 dsi0_in: endpoint {
 874                                                         remote-endpoint = <&mdp5_intf1_out>;
 875                                                 };
 876                                         };
 877
 878                                         port@1 {
 879                                                 reg = <1>;
 880                                                 dsi0_out: endpoint {
 881                                                 };
 882                                         };
 883                                 };
 884                         };
 885
 886                         dsi0_phy: dsi-phy@994400 {
 887                                 compatible = "qcom,dsi-phy-14nm";
 888                                 reg = <0x00994400 0x100>,
 889                                       <0x00994500 0x300>,
 890                                       <0x00994800 0x188>;
 891                                 reg-names = "dsi_phy",
 892                                             "dsi_phy_lane",
 893                                             "dsi_pll";
 894
 895                                 #clock-cells = <1>;
 896                                 #phy-cells = <0>;
 897
 898                                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
 899                                 clock-names = "iface", "ref";
 900                                 status = "disabled";
 901                         };
 902
 903                         hdmi: hdmi-tx@9a0000 {
 904                                 compatible = "qcom,hdmi-tx-8996";
 905                                 reg =   <0x009a0000 0x50c>,
 906                                         <0x00070000 0x6158>,
 907                                         <0x009e0000 0xfff>;
 908                                 reg-names = "core_physical",
 909                                             "qfprom_physical",
 910                                             "hdcp_physical";
 911
 912                                 interrupt-parent = <&mdss>;
 913                                 interrupts = <8>;
 914
 915                                 clocks = <&mmcc MDSS_MDP_CLK>,
 916                                          <&mmcc MDSS_AHB_CLK>,
 917                                          <&mmcc MDSS_HDMI_CLK>,
 918                                          <&mmcc MDSS_HDMI_AHB_CLK>,
 919                                          <&mmcc MDSS_EXTPCLK_CLK>;
 920                                 clock-names =
 921                                         "mdp_core",
 922                                         "iface",
 923                                         "core",
 924                                         "alt_iface",
 925                                         "extp";
 926
 927                                 phys = <&hdmi_phy>;
 928                                 phy-names = "hdmi_phy";
 929                                 #sound-dai-cells = <1>;
 930
 931                                 status = "disabled";
 932
 933                                 ports {
 934                                         #address-cells = <1>;
 935                                         #size-cells = <0>;
 936
 937                                         port@0 {
 938                                                 reg = <0>;
 939                                                 hdmi_in: endpoint {
 940                                                         remote-endpoint = <&mdp5_intf3_out>;
 941                                                 };
 942                                         };
 943                                 };
 944                         };
 945
 946                         hdmi_phy: hdmi-phy@9a0600 {
 947                                 #phy-cells = <0>;
 948                                 compatible = "qcom,hdmi-phy-8996";
 949                                 reg = <0x009a0600 0x1c4>,
 950                                       <0x009a0a00 0x124>,
 951                                       <0x009a0c00 0x124>,
 952                                       <0x009a0e00 0x124>,
 953                                       <0x009a1000 0x124>,
 954                                       <0x009a1200 0x0c8>;
 955                                 reg-names = "hdmi_pll",
 956                                             "hdmi_tx_l0",
 957                                             "hdmi_tx_l1",
 958                                             "hdmi_tx_l2",
 959                                             "hdmi_tx_l3",
 960                                             "hdmi_phy";
 961
 962                                 clocks = <&mmcc MDSS_AHB_CLK>,
 963                                          <&gcc GCC_HDMI_CLKREF_CLK>;
 964                                 clock-names = "iface",
 965                                               "ref";
 966
 967                                 status = "disabled";
 968                         };
 969                 };
 970
 971                 gpu: gpu@b00000 {
 972                         compatible = "qcom,adreno-530.2", "qcom,adreno";
 973
 974                         reg = <0x00b00000 0x3f000>;
 975                         reg-names = "kgsl_3d0_reg_memory";
 976
 977                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 978
 979                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
 980                                 <&mmcc GPU_AHB_CLK>,
 981                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
 982                                 <&gcc GCC_BIMC_GFX_CLK>,
 983                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
 984
 985                         clock-names = "core",
 986                                 "iface",
 987                                 "rbbmtimer",
 988                                 "mem",
 989                                 "mem_iface";
 990
 991                         power-domains = <&mmcc GPU_GX_GDSC>;
 992                         iommus = <&adreno_smmu 0>;
 993
 994                         nvmem-cells = <&speedbin_efuse>;
 995                         nvmem-cell-names = "speed_bin";
 996
 997                         operating-points-v2 = <&gpu_opp_table>;
 998
 999                         status = "disabled";
1000
1001                         #cooling-cells = <2>;
1002
1003                         gpu_opp_table: opp-table {
1004                                 compatible  ="operating-points-v2";
1005
1006                                 /*
1007                                  * 624Mhz and 560Mhz are only available on speed
1008                                  * bin (1 << 0). All the rest are available on
1009                                  * all bins of the hardware
1010                                  */
1011                                 opp-624000000 {
1012                                         opp-hz = /bits/ 64 <624000000>;
1013                                         opp-supported-hw = <0x01>;
1014                                 };
1015                                 opp-560000000 {
1016                                         opp-hz = /bits/ 64 <560000000>;
1017                                         opp-supported-hw = <0x01>;
1018                                 };
1019                                 opp-510000000 {
1020                                         opp-hz = /bits/ 64 <510000000>;
1021                                         opp-supported-hw = <0xFF>;
1022                                 };
1023                                 opp-401800000 {
1024                                         opp-hz = /bits/ 64 <401800000>;
1025                                         opp-supported-hw = <0xFF>;
1026                                 };
1027                                 opp-315000000 {
1028                                         opp-hz = /bits/ 64 <315000000>;
1029                                         opp-supported-hw = <0xFF>;
1030                                 };
1031                                 opp-214000000 {
1032                                         opp-hz = /bits/ 64 <214000000>;
1033                                         opp-supported-hw = <0xFF>;
1034                                 };
1035                                 opp-133000000 {
1036                                         opp-hz = /bits/ 64 <133000000>;
1037                                         opp-supported-hw = <0xFF>;
1038                                 };
1039                         };
1040
1041                         zap-shader {
1042                                 memory-region = <&gpu_mem>;
1043                         };
1044                 };
1045
1046                 tlmm: pinctrl@1010000 {
1047                         compatible = "qcom,msm8996-pinctrl";
1048                         reg = <0x01010000 0x300000>;
1049                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1050                         gpio-controller;
1051                         gpio-ranges = <&tlmm 0 0 150>;
1052                         #gpio-cells = <2>;
1053                         interrupt-controller;
1054                         #interrupt-cells = <2>;
1055
1056                         blsp1_spi1_default: blsp1-spi1-default {
1057                                 spi {
1058                                         pins = "gpio0", "gpio1", "gpio3";
1059                                         function = "blsp_spi1";
1060                                         drive-strength = <12>;
1061                                         bias-disable;
1062                                 };
1063
1064                                 cs {
1065                                         pins = "gpio2";
1066                                         function = "gpio";
1067                                         drive-strength = <16>;
1068                                         bias-disable;
1069                                         output-high;
1070                                 };
1071                         };
1072
1073                         blsp1_spi1_sleep: blsp1-spi1-sleep {
1074                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1075                                 function = "gpio";
1076                                 drive-strength = <2>;
1077                                 bias-pull-down;
1078                         };
1079
1080                         blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1081                                 pins = "gpio4", "gpio5";
1082                                 function = "blsp_uart8";
1083                                 drive-strength = <16>;
1084                                 bias-disable;
1085                         };
1086
1087                         blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1088                                 pins = "gpio4", "gpio5";
1089                                 function = "gpio";
1090                                 drive-strength = <2>;
1091                                 bias-disable;
1092                         };
1093
1094                         blsp2_i2c2_default: blsp2-i2c2 {
1095                                 pins = "gpio6", "gpio7";
1096                                 function = "blsp_i2c8";
1097                                 drive-strength = <16>;
1098                                 bias-disable;
1099                         };
1100
1101                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1102                                 pins = "gpio6", "gpio7";
1103                                 function = "gpio";
1104                                 drive-strength = <2>;
1105                                 bias-disable;
1106                         };
1107
1108                         cci0_default: cci0-default {
1109                                 pins = "gpio17", "gpio18";
1110                                 function = "cci_i2c";
1111                                 drive-strength = <16>;
1112                                 bias-disable;
1113                         };
1114
1115                         camera0_state_on:
1116                         camera_rear_default: camera-rear-default {
1117                                 camera0_mclk: mclk0 {
1118                                         pins = "gpio13";
1119                                         function = "cam_mclk";
1120                                         drive-strength = <16>;
1121                                         bias-disable;
1122                                 };
1123
1124                                 camera0_rst: rst {
1125                                         pins = "gpio25";
1126                                         function = "gpio";
1127                                         drive-strength = <16>;
1128                                         bias-disable;
1129                                 };
1130
1131                                 camera0_pwdn: pwdn {
1132                                         pins = "gpio26";
1133                                         function = "gpio";
1134                                         drive-strength = <16>;
1135                                         bias-disable;
1136                                 };
1137                         };
1138
1139                         cci1_default: cci1-default {
1140                                 pins = "gpio19", "gpio20";
1141                                 function = "cci_i2c";
1142                                 drive-strength = <16>;
1143                                 bias-disable;
1144                         };
1145
1146                         camera1_state_on:
1147                         camera_board_default: camera-board-default {
1148                                 mclk1 {
1149                                         pins = "gpio14";
1150                                         function = "cam_mclk";
1151                                         drive-strength = <16>;
1152                                         bias-disable;
1153                                 };
1154
1155                                 pwdn {
1156                                         pins = "gpio98";
1157                                         function = "gpio";
1158                                         drive-strength = <16>;
1159                                         bias-disable;
1160                                 };
1161
1162                                 rst {
1163                                         pins = "gpio104";
1164                                         function = "gpio";
1165                                         drive-strength = <16>;
1166                                         bias-disable;
1167                                 };
1168                         };
1169
1170                         camera2_state_on:
1171                         camera_front_default: camera-front-default {
1172                                 camera2_mclk: mclk2 {
1173                                         pins = "gpio15";
1174                                         function = "cam_mclk";
1175                                         drive-strength = <16>;
1176                                         bias-disable;
1177                                 };
1178
1179                                 camera2_rst: rst {
1180                                         pins = "gpio23";
1181                                         function = "gpio";
1182                                         drive-strength = <16>;
1183                                         bias-disable;
1184                                 };
1185
1186                                 pwdn {
1187                                         pins = "gpio133";
1188                                         function = "gpio";
1189                                         drive-strength = <16>;
1190                                         bias-disable;
1191                                 };
1192                         };
1193
1194                         pcie0_state_on: pcie0-state-on {
1195                                 perst {
1196                                         pins = "gpio35";
1197                                         function = "gpio";
1198                                         drive-strength = <2>;
1199                                         bias-pull-down;
1200                                 };
1201
1202                                 clkreq {
1203                                         pins = "gpio36";
1204                                         function = "pci_e0";
1205                                         drive-strength = <2>;
1206                                         bias-pull-up;
1207                                 };
1208
1209                                 wake {
1210                                         pins = "gpio37";
1211                                         function = "gpio";
1212                                         drive-strength = <2>;
1213                                         bias-pull-up;
1214                                 };
1215                         };
1216
1217                         pcie0_state_off: pcie0-state-off {
1218                                 perst {
1219                                         pins = "gpio35";
1220                                         function = "gpio";
1221                                         drive-strength = <2>;
1222                                         bias-pull-down;
1223                                 };
1224
1225                                 clkreq {
1226                                         pins = "gpio36";
1227                                         function = "gpio";
1228                                         drive-strength = <2>;
1229                                         bias-disable;
1230                                 };
1231
1232                                 wake {
1233                                         pins = "gpio37";
1234                                         function = "gpio";
1235                                         drive-strength = <2>;
1236                                         bias-disable;
1237                                 };
1238                         };
1239
1240                         blsp1_uart2_default: blsp1-uart2-default {
1241                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1242                                 function = "blsp_uart2";
1243                                 drive-strength = <16>;
1244                                 bias-disable;
1245                         };
1246
1247                         blsp1_uart2_sleep: blsp1-uart2-sleep {
1248                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1249                                 function = "gpio";
1250                                 drive-strength = <2>;
1251                                 bias-disable;
1252                         };
1253
1254                         blsp1_i2c3_default: blsp1-i2c2-default {
1255                                 pins = "gpio47", "gpio48";
1256                                 function = "blsp_i2c3";
1257                                 drive-strength = <16>;
1258                                 bias-disable;
1259                         };
1260
1261                         blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1262                                 pins = "gpio47", "gpio48";
1263                                 function = "gpio";
1264                                 drive-strength = <2>;
1265                                 bias-disable;
1266                         };
1267
1268                         blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1269                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1270                                 function = "blsp_uart9";
1271                                 drive-strength = <16>;
1272                                 bias-disable;
1273                         };
1274
1275                         blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1276                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1277                                 function = "blsp_uart9";
1278                                 drive-strength = <2>;
1279                                 bias-disable;
1280                         };
1281
1282                         blsp2_i2c3_default: blsp2-i2c3 {
1283                                 pins = "gpio51", "gpio52";
1284                                 function = "blsp_i2c9";
1285                                 drive-strength = <16>;
1286                                 bias-disable;
1287                         };
1288
1289                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1290                                 pins = "gpio51", "gpio52";
1291                                 function = "gpio";
1292                                 drive-strength = <2>;
1293                                 bias-disable;
1294                         };
1295
1296                         wcd_intr_default: wcd-intr-default{
1297                                 pins = "gpio54";
1298                                 function = "gpio";
1299                                 drive-strength = <2>;
1300                                 bias-pull-down;
1301                                 input-enable;
1302                         };
1303
1304                         blsp2_i2c1_default: blsp2-i2c1 {
1305                                 pins = "gpio55", "gpio56";
1306                                 function = "blsp_i2c7";
1307                                 drive-strength = <16>;
1308                                 bias-disable;
1309                         };
1310
1311                         blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1312                                 pins = "gpio55", "gpio56";
1313                                 function = "gpio";
1314                                 drive-strength = <2>;
1315                                 bias-disable;
1316                         };
1317
1318                         blsp2_i2c5_default: blsp2-i2c5 {
1319                                 pins = "gpio60", "gpio61";
1320                                 function = "blsp_i2c11";
1321                                 drive-strength = <2>;
1322                                 bias-disable;
1323                         };
1324
1325                         /* Sleep state for BLSP2_I2C5 is missing.. */
1326
1327                         cdc_reset_active: cdc-reset-active {
1328                                 pins = "gpio64";
1329                                 function = "gpio";
1330                                 drive-strength = <16>;
1331                                 bias-pull-down;
1332                                 output-high;
1333                         };
1334
1335                         cdc_reset_sleep: cdc-reset-sleep {
1336                                 pins = "gpio64";
1337                                 function = "gpio";
1338                                 drive-strength = <16>;
1339                                 bias-disable;
1340                                 output-low;
1341                         };
1342
1343                         blsp2_spi6_default: blsp2-spi5-default {
1344                                 spi {
1345                                         pins = "gpio85", "gpio86", "gpio88";
1346                                         function = "blsp_spi12";
1347                                         drive-strength = <12>;
1348                                         bias-disable;
1349                                 };
1350
1351                                 cs {
1352                                         pins = "gpio87";
1353                                         function = "gpio";
1354                                         drive-strength = <16>;
1355                                         bias-disable;
1356                                         output-high;
1357                                 };
1358                         };
1359
1360                         blsp2_spi6_sleep: blsp2-spi5-sleep {
1361                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1362                                 function = "gpio";
1363                                 drive-strength = <2>;
1364                                 bias-pull-down;
1365                         };
1366
1367                         blsp2_i2c6_default: blsp2-i2c6 {
1368                                 pins = "gpio87", "gpio88";
1369                                 function = "blsp_i2c12";
1370                                 drive-strength = <16>;
1371                                 bias-disable;
1372                         };
1373
1374                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1375                                 pins = "gpio87", "gpio88";
1376                                 function = "gpio";
1377                                 drive-strength = <2>;
1378                                 bias-disable;
1379                         };
1380
1381                         pcie1_state_on: pcie1-state-on {
1382                                 perst {
1383                                         pins = "gpio130";
1384                                         function = "gpio";
1385                                         drive-strength = <2>;
1386                                         bias-pull-down;
1387                                 };
1388
1389                                 clkreq {
1390                                         pins = "gpio131";
1391                                         function = "pci_e1";
1392                                         drive-strength = <2>;
1393                                         bias-pull-up;
1394                                 };
1395
1396                                 wake {
1397                                         pins = "gpio132";
1398                                         function = "gpio";
1399                                         drive-strength = <2>;
1400                                         bias-pull-down;
1401                                 };
1402                         };
1403
1404                         pcie1_state_off: pcie1-state-off {
1405                                 /* Perst is missing? */
1406                                 clkreq {
1407                                         pins = "gpio131";
1408                                         function = "gpio";
1409                                         drive-strength = <2>;
1410                                         bias-disable;
1411                                 };
1412
1413                                 wake {
1414                                         pins = "gpio132";
1415                                         function = "gpio";
1416                                         drive-strength = <2>;
1417                                         bias-disable;
1418                                 };
1419                         };
1420
1421                         pcie2_state_on: pcie2-state-on {
1422                                 perst {
1423                                         pins = "gpio114";
1424                                         function = "gpio";
1425                                         drive-strength = <2>;
1426                                         bias-pull-down;
1427                                 };
1428
1429                                 clkreq {
1430                                         pins = "gpio115";
1431                                         function = "pci_e2";
1432                                         drive-strength = <2>;
1433                                         bias-pull-up;
1434                                 };
1435
1436                                 wake {
1437                                         pins = "gpio116";
1438                                         function = "gpio";
1439                                         drive-strength = <2>;
1440                                         bias-pull-down;
1441                                 };
1442                         };
1443
1444                         pcie2_state_off: pcie2-state-off {
1445                                 /* Perst is missing? */
1446                                 clkreq {
1447                                         pins = "gpio115";
1448                                         function = "gpio";
1449                                         drive-strength = <2>;
1450                                         bias-disable;
1451                                 };
1452
1453                                 wake {
1454                                         pins = "gpio116";
1455                                         function = "gpio";
1456                                         drive-strength = <2>;
1457                                         bias-disable;
1458                                 };
1459                         };
1460
1461                         sdc1_state_on: sdc1-state-on {
1462                                 clk {
1463                                         pins = "sdc1_clk";
1464                                         bias-disable;
1465                                         drive-strength = <16>;
1466                                 };
1467
1468                                 cmd {
1469                                         pins = "sdc1_cmd";
1470                                         bias-pull-up;
1471                                         drive-strength = <10>;
1472                                 };
1473
1474                                 data {
1475                                         pins = "sdc1_data";
1476                                         bias-pull-up;
1477                                         drive-strength = <10>;
1478                                 };
1479
1480                                 rclk {
1481                                         pins = "sdc1_rclk";
1482                                         bias-pull-down;
1483                                 };
1484                         };
1485
1486                         sdc1_state_off: sdc1-state-off {
1487                                 clk {
1488                                         pins = "sdc1_clk";
1489                                         bias-disable;
1490                                         drive-strength = <2>;
1491                                 };
1492
1493                                 cmd {
1494                                         pins = "sdc1_cmd";
1495                                         bias-pull-up;
1496                                         drive-strength = <2>;
1497                                 };
1498
1499                                 data {
1500                                         pins = "sdc1_data";
1501                                         bias-pull-up;
1502                                         drive-strength = <2>;
1503                                 };
1504
1505                                 rclk {
1506                                         pins = "sdc1_rclk";
1507                                         bias-pull-down;
1508                                 };
1509                         };
1510
1511                         sdc2_state_on: sdc2-clk-on {
1512                                 clk {
1513                                         pins = "sdc2_clk";
1514                                         bias-disable;
1515                                         drive-strength = <16>;
1516                                 };
1517
1518                                 cmd {
1519                                         pins = "sdc2_cmd";
1520                                         bias-pull-up;
1521                                         drive-strength = <10>;
1522                                 };
1523
1524                                 data {
1525                                         pins = "sdc2_data";
1526                                         bias-pull-up;
1527                                         drive-strength = <10>;
1528                                 };
1529                         };
1530
1531                         sdc2_state_off: sdc2-clk-off {
1532                                 clk {
1533                                         pins = "sdc2_clk";
1534                                         bias-disable;
1535                                         drive-strength = <2>;
1536                                 };
1537
1538                                 cmd {
1539                                         pins = "sdc2_cmd";
1540                                         bias-pull-up;
1541                                         drive-strength = <2>;
1542                                 };
1543
1544                                 data {
1545                                         pins = "sdc2_data";
1546                                         bias-pull-up;
1547                                         drive-strength = <2>;
1548                                 };
1549                         };
1550                 };
1551
1552                 sram@290000 {
1553                         compatible = "qcom,rpm-stats";
1554                         reg = <0x00290000 0x10000>;
1555                 };
1556
1557                 spmi_bus: spmi@400f000 {
1558                         compatible = "qcom,spmi-pmic-arb";
1559                         reg = <0x0400f000 0x1000>,
1560                               <0x04400000 0x800000>,
1561                               <0x04c00000 0x800000>,
1562                               <0x05800000 0x200000>,
1563                               <0x0400a000 0x002100>;
1564                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1565                         interrupt-names = "periph_irq";
1566                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1567                         qcom,ee = <0>;
1568                         qcom,channel = <0>;
1569                         #address-cells = <2>;
1570                         #size-cells = <0>;
1571                         interrupt-controller;
1572                         #interrupt-cells = <4>;
1573                 };
1574
1575                 agnoc@0 {
1576                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1577                         compatible = "simple-pm-bus";
1578                         #address-cells = <1>;
1579                         #size-cells = <1>;
1580                         ranges;
1581
1582                         pcie0: pcie@600000 {
1583                                 compatible = "qcom,pcie-msm8996";
1584                                 status = "disabled";
1585                                 power-domains = <&gcc PCIE0_GDSC>;
1586                                 bus-range = <0x00 0xff>;
1587                                 num-lanes = <1>;
1588
1589                                 reg = <0x00600000 0x2000>,
1590                                       <0x0c000000 0xf1d>,
1591                                       <0x0c000f20 0xa8>,
1592                                       <0x0c100000 0x100000>;
1593                                 reg-names = "parf", "dbi", "elbi","config";
1594
1595                                 phys = <&pciephy_0>;
1596                                 phy-names = "pciephy";
1597
1598                                 #address-cells = <3>;
1599                                 #size-cells = <2>;
1600                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1601                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1602
1603                                 device_type = "pci";
1604
1605                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1606                                 interrupt-names = "msi";
1607                                 #interrupt-cells = <1>;
1608                                 interrupt-map-mask = <0 0 0 0x7>;
1609                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1610                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1611                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1612                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1613
1614                                 pinctrl-names = "default", "sleep";
1615                                 pinctrl-0 = <&pcie0_state_on>;
1616                                 pinctrl-1 = <&pcie0_state_off>;
1617
1618                                 linux,pci-domain = <0>;
1619
1620                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1621                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1622                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1623                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1624                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1625
1626                                 clock-names =  "pipe",
1627                                                 "aux",
1628                                                 "cfg",
1629                                                 "bus_master",
1630                                                 "bus_slave";
1631
1632                         };
1633
1634                         pcie1: pcie@608000 {
1635                                 compatible = "qcom,pcie-msm8996";
1636                                 power-domains = <&gcc PCIE1_GDSC>;
1637                                 bus-range = <0x00 0xff>;
1638                                 num-lanes = <1>;
1639
1640                                 status  = "disabled";
1641
1642                                 reg = <0x00608000 0x2000>,
1643                                       <0x0d000000 0xf1d>,
1644                                       <0x0d000f20 0xa8>,
1645                                       <0x0d100000 0x100000>;
1646
1647                                 reg-names = "parf", "dbi", "elbi","config";
1648
1649                                 phys = <&pciephy_1>;
1650                                 phy-names = "pciephy";
1651
1652                                 #address-cells = <3>;
1653                                 #size-cells = <2>;
1654                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1655                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1656
1657                                 device_type = "pci";
1658
1659                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1660                                 interrupt-names = "msi";
1661                                 #interrupt-cells = <1>;
1662                                 interrupt-map-mask = <0 0 0 0x7>;
1663                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1664                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1665                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1666                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1667
1668                                 pinctrl-names = "default", "sleep";
1669                                 pinctrl-0 = <&pcie1_state_on>;
1670                                 pinctrl-1 = <&pcie1_state_off>;
1671
1672                                 linux,pci-domain = <1>;
1673
1674                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1675                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1676                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1677                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1678                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1679
1680                                 clock-names =  "pipe",
1681                                                 "aux",
1682                                                 "cfg",
1683                                                 "bus_master",
1684                                                 "bus_slave";
1685                         };
1686
1687                         pcie2: pcie@610000 {
1688                                 compatible = "qcom,pcie-msm8996";
1689                                 power-domains = <&gcc PCIE2_GDSC>;
1690                                 bus-range = <0x00 0xff>;
1691                                 num-lanes = <1>;
1692                                 status = "disabled";
1693                                 reg = <0x00610000 0x2000>,
1694                                       <0x0e000000 0xf1d>,
1695                                       <0x0e000f20 0xa8>,
1696                                       <0x0e100000 0x100000>;
1697
1698                                 reg-names = "parf", "dbi", "elbi","config";
1699
1700                                 phys = <&pciephy_2>;
1701                                 phy-names = "pciephy";
1702
1703                                 #address-cells = <3>;
1704                                 #size-cells = <2>;
1705                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1706                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1707
1708                                 device_type = "pci";
1709
1710                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1711                                 interrupt-names = "msi";
1712                                 #interrupt-cells = <1>;
1713                                 interrupt-map-mask = <0 0 0 0x7>;
1714                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1715                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1716                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1717                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1718
1719                                 pinctrl-names = "default", "sleep";
1720                                 pinctrl-0 = <&pcie2_state_on>;
1721                                 pinctrl-1 = <&pcie2_state_off>;
1722
1723                                 linux,pci-domain = <2>;
1724                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1725                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1726                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1727                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1728                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1729
1730                                 clock-names =  "pipe",
1731                                                 "aux",
1732                                                 "cfg",
1733                                                 "bus_master",
1734                                                 "bus_slave";
1735                         };
1736                 };
1737
1738                 ufshc: ufshc@624000 {
1739                         compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
1740                                      "jedec,ufs-2.0";
1741                         reg = <0x00624000 0x2500>;
1742                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1743
1744                         phys = <&ufsphy_lane>;
1745                         phy-names = "ufsphy";
1746
1747                         power-domains = <&gcc UFS_GDSC>;
1748
1749                         clock-names =
1750                                 "core_clk_src",
1751                                 "core_clk",
1752                                 "bus_clk",
1753                                 "bus_aggr_clk",
1754                                 "iface_clk",
1755                                 "core_clk_unipro_src",
1756                                 "core_clk_unipro",
1757                                 "core_clk_ice",
1758                                 "ref_clk",
1759                                 "tx_lane0_sync_clk",
1760                                 "rx_lane0_sync_clk";
1761                         clocks =
1762                                 <&gcc UFS_AXI_CLK_SRC>,
1763                                 <&gcc GCC_UFS_AXI_CLK>,
1764                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1765                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1766                                 <&gcc GCC_UFS_AHB_CLK>,
1767                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
1768                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1769                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
1770                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
1771                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1772                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1773                         freq-table-hz =
1774                                 <100000000 200000000>,
1775                                 <0 0>,
1776                                 <0 0>,
1777                                 <0 0>,
1778                                 <0 0>,
1779                                 <150000000 300000000>,
1780                                 <0 0>,
1781                                 <0 0>,
1782                                 <0 0>,
1783                                 <0 0>,
1784                                 <0 0>;
1785
1786                         lanes-per-direction = <1>;
1787                         #reset-cells = <1>;
1788                         status = "disabled";
1789
1790                         ufs_variant {
1791                                 compatible = "qcom,ufs_variant";
1792                         };
1793                 };
1794
1795                 ufsphy: phy@627000 {
1796                         compatible = "qcom,msm8996-qmp-ufs-phy";
1797                         reg = <0x00627000 0x1c4>;
1798                         #address-cells = <1>;
1799                         #size-cells = <1>;
1800                         ranges;
1801
1802                         clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1803                         clock-names = "ref";
1804
1805                         resets = <&ufshc 0>;
1806                         reset-names = "ufsphy";
1807                         status = "disabled";
1808
1809                         ufsphy_lane: phy@627400 {
1810                                 reg = <0x627400 0x12c>,
1811                                       <0x627600 0x200>,
1812                                       <0x627c00 0x1b4>;
1813                                 #phy-cells = <0>;
1814                         };
1815                 };
1816
1817                 camss: camss@a00000 {
1818                         compatible = "qcom,msm8996-camss";
1819                         reg = <0x00a34000 0x1000>,
1820                               <0x00a00030 0x4>,
1821                               <0x00a35000 0x1000>,
1822                               <0x00a00038 0x4>,
1823                               <0x00a36000 0x1000>,
1824                               <0x00a00040 0x4>,
1825                               <0x00a30000 0x100>,
1826                               <0x00a30400 0x100>,
1827                               <0x00a30800 0x100>,
1828                               <0x00a30c00 0x100>,
1829                               <0x00a31000 0x500>,
1830                               <0x00a00020 0x10>,
1831                               <0x00a10000 0x1000>,
1832                               <0x00a14000 0x1000>;
1833                         reg-names = "csiphy0",
1834                                 "csiphy0_clk_mux",
1835                                 "csiphy1",
1836                                 "csiphy1_clk_mux",
1837                                 "csiphy2",
1838                                 "csiphy2_clk_mux",
1839                                 "csid0",
1840                                 "csid1",
1841                                 "csid2",
1842                                 "csid3",
1843                                 "ispif",
1844                                 "csi_clk_mux",
1845                                 "vfe0",
1846                                 "vfe1";
1847                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1848                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1849                                 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1850                                 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1851                                 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1852                                 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1853                                 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1854                                 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1855                                 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1856                                 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1857                         interrupt-names = "csiphy0",
1858                                 "csiphy1",
1859                                 "csiphy2",
1860                                 "csid0",
1861                                 "csid1",
1862                                 "csid2",
1863                                 "csid3",
1864                                 "ispif",
1865                                 "vfe0",
1866                                 "vfe1";
1867                         power-domains = <&mmcc VFE0_GDSC>,
1868                                         <&mmcc VFE1_GDSC>;
1869                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1870                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1871                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1872                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1873                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1874                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1875                                 <&mmcc CAMSS_CSI0_CLK>,
1876                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1877                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1878                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1879                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1880                                 <&mmcc CAMSS_CSI1_CLK>,
1881                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1882                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1883                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1884                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1885                                 <&mmcc CAMSS_CSI2_CLK>,
1886                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1887                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1888                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1889                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1890                                 <&mmcc CAMSS_CSI3_CLK>,
1891                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1892                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1893                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1894                                 <&mmcc CAMSS_AHB_CLK>,
1895                                 <&mmcc CAMSS_VFE0_CLK>,
1896                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1897                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1898                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1899                                 <&mmcc CAMSS_VFE1_CLK>,
1900                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1901                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1902                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1903                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1904                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1905                         clock-names = "top_ahb",
1906                                 "ispif_ahb",
1907                                 "csiphy0_timer",
1908                                 "csiphy1_timer",
1909                                 "csiphy2_timer",
1910                                 "csi0_ahb",
1911                                 "csi0",
1912                                 "csi0_phy",
1913                                 "csi0_pix",
1914                                 "csi0_rdi",
1915                                 "csi1_ahb",
1916                                 "csi1",
1917                                 "csi1_phy",
1918                                 "csi1_pix",
1919                                 "csi1_rdi",
1920                                 "csi2_ahb",
1921                                 "csi2",
1922                                 "csi2_phy",
1923                                 "csi2_pix",
1924                                 "csi2_rdi",
1925                                 "csi3_ahb",
1926                                 "csi3",
1927                                 "csi3_phy",
1928                                 "csi3_pix",
1929                                 "csi3_rdi",
1930                                 "ahb",
1931                                 "vfe0",
1932                                 "csi_vfe0",
1933                                 "vfe0_ahb",
1934                                 "vfe0_stream",
1935                                 "vfe1",
1936                                 "csi_vfe1",
1937                                 "vfe1_ahb",
1938                                 "vfe1_stream",
1939                                 "vfe_ahb",
1940                                 "vfe_axi";
1941                         iommus = <&vfe_smmu 0>,
1942                                  <&vfe_smmu 1>,
1943                                  <&vfe_smmu 2>,
1944                                  <&vfe_smmu 3>;
1945                         status = "disabled";
1946                         ports {
1947                                 #address-cells = <1>;
1948                                 #size-cells = <0>;
1949                         };
1950                 };
1951
1952                 cci: cci@a0c000 {
1953                         compatible = "qcom,msm8996-cci";
1954                         #address-cells = <1>;
1955                         #size-cells = <0>;
1956                         reg = <0xa0c000 0x1000>;
1957                         interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1958                         power-domains = <&mmcc CAMSS_GDSC>;
1959                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1960                                  <&mmcc CAMSS_CCI_AHB_CLK>,
1961                                  <&mmcc CAMSS_CCI_CLK>,
1962                                  <&mmcc CAMSS_AHB_CLK>;
1963                         clock-names = "camss_top_ahb",
1964                                       "cci_ahb",
1965                                       "cci",
1966                                       "camss_ahb";
1967                         assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1968                                           <&mmcc CAMSS_CCI_CLK>;
1969                         assigned-clock-rates = <80000000>, <37500000>;
1970                         pinctrl-names = "default";
1971                         pinctrl-0 = <&cci0_default &cci1_default>;
1972                         status = "disabled";
1973
1974                         cci_i2c0: i2c-bus@0 {
1975                                 reg = <0>;
1976                                 clock-frequency = <400000>;
1977                                 #address-cells = <1>;
1978                                 #size-cells = <0>;
1979                         };
1980
1981                         cci_i2c1: i2c-bus@1 {
1982                                 reg = <1>;
1983                                 clock-frequency = <400000>;
1984                                 #address-cells = <1>;
1985                                 #size-cells = <0>;
1986                         };
1987                 };
1988
1989                 adreno_smmu: iommu@b40000 {
1990                         compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1991                         reg = <0x00b40000 0x10000>;
1992
1993                         #global-interrupts = <1>;
1994                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1995                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1996                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1997                         #iommu-cells = <1>;
1998
1999                         clocks = <&mmcc GPU_AHB_CLK>,
2000                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2001                         clock-names = "iface", "bus";
2002
2003                         power-domains = <&mmcc GPU_GDSC>;
2004                 };
2005
2006                 venus: video-codec@c00000 {
2007                         compatible = "qcom,msm8996-venus";
2008                         reg = <0x00c00000 0xff000>;
2009                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2010                         power-domains = <&mmcc VENUS_GDSC>;
2011                         clocks = <&mmcc VIDEO_CORE_CLK>,
2012                                  <&mmcc VIDEO_AHB_CLK>,
2013                                  <&mmcc VIDEO_AXI_CLK>,
2014                                  <&mmcc VIDEO_MAXI_CLK>;
2015                         clock-names = "core", "iface", "bus", "mbus";
2016                         iommus = <&venus_smmu 0x00>,
2017                                  <&venus_smmu 0x01>,
2018                                  <&venus_smmu 0x0a>,
2019                                  <&venus_smmu 0x07>,
2020                                  <&venus_smmu 0x0e>,
2021                                  <&venus_smmu 0x0f>,
2022                                  <&venus_smmu 0x08>,
2023                                  <&venus_smmu 0x09>,
2024                                  <&venus_smmu 0x0b>,
2025                                  <&venus_smmu 0x0c>,
2026                                  <&venus_smmu 0x0d>,
2027                                  <&venus_smmu 0x10>,
2028                                  <&venus_smmu 0x11>,
2029                                  <&venus_smmu 0x21>,
2030                                  <&venus_smmu 0x28>,
2031                                  <&venus_smmu 0x29>,
2032                                  <&venus_smmu 0x2b>,
2033                                  <&venus_smmu 0x2c>,
2034                                  <&venus_smmu 0x2d>,
2035                                  <&venus_smmu 0x31>;
2036                         memory-region = <&venus_mem>;
2037                         status = "disabled";
2038
2039                         video-decoder {
2040                                 compatible = "venus-decoder";
2041                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2042                                 clock-names = "core";
2043                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2044                         };
2045
2046                         video-encoder {
2047                                 compatible = "venus-encoder";
2048                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2049                                 clock-names = "core";
2050                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2051                         };
2052                 };
2053
2054                 mdp_smmu: iommu@d00000 {
2055                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2056                         reg = <0x00d00000 0x10000>;
2057
2058                         #global-interrupts = <1>;
2059                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2060                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2061                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2062                         #iommu-cells = <1>;
2063                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2064                                  <&mmcc SMMU_MDP_AXI_CLK>;
2065                         clock-names = "iface", "bus";
2066
2067                         power-domains = <&mmcc MDSS_GDSC>;
2068                 };
2069
2070                 venus_smmu: iommu@d40000 {
2071                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2072                         reg = <0x00d40000 0x20000>;
2073                         #global-interrupts = <1>;
2074                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2075                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2076                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2077                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2078                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2079                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2080                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2081                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2082                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2083                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2084                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
2085                         clock-names = "iface", "bus";
2086                         #iommu-cells = <1>;
2087                         status = "okay";
2088                 };
2089
2090                 vfe_smmu: iommu@da0000 {
2091                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2092                         reg = <0x00da0000 0x10000>;
2093
2094                         #global-interrupts = <1>;
2095                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2096                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2097                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2098                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2099                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2100                                  <&mmcc SMMU_VFE_AXI_CLK>;
2101                         clock-names = "iface",
2102                                       "bus";
2103                         #iommu-cells = <1>;
2104                 };
2105
2106                 lpass_q6_smmu: iommu@1600000 {
2107                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2108                         reg = <0x01600000 0x20000>;
2109                         #iommu-cells = <1>;
2110                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2111
2112                         #global-interrupts = <1>;
2113                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2114                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2115                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2116                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2117                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2118                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2119                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2120                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2121                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2122                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2123                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2124                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2125                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2126
2127                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2128                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2129                         clock-names = "iface", "bus";
2130                 };
2131
2132                 slpi_pil: remoteproc@1c00000 {
2133                         compatible = "qcom,msm8996-slpi-pil";
2134                         reg = <0x01c00000 0x4000>;
2135
2136                         interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2137                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2138                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2139                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2140                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2141                         interrupt-names = "wdog",
2142                                           "fatal",
2143                                           "ready",
2144                                           "handover",
2145                                           "stop-ack";
2146
2147                         clocks = <&xo_board>,
2148                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
2149                         clock-names = "xo", "aggre2";
2150
2151                         memory-region = <&slpi_mem>;
2152
2153                         qcom,smem-states = <&slpi_smp2p_out 0>;
2154                         qcom,smem-state-names = "stop";
2155
2156                         power-domains = <&rpmpd MSM8996_VDDSSCX>;
2157                         power-domain-names = "ssc_cx";
2158
2159                         status = "disabled";
2160
2161                         smd-edge {
2162                                 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2163
2164                                 label = "dsps";
2165                                 mboxes = <&apcs_glb 25>;
2166                                 qcom,smd-edge = <3>;
2167                                 qcom,remote-pid = <3>;
2168                         };
2169                 };
2170
2171                 mss_pil: remoteproc@2080000 {
2172                         compatible = "qcom,msm8996-mss-pil";
2173                         reg = <0x2080000 0x100>,
2174                               <0x2180000 0x020>;
2175                         reg-names = "qdsp6", "rmb";
2176
2177                         interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2178                                               <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2179                                               <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2180                                               <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2181                                               <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2182                                               <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2183                         interrupt-names = "wdog", "fatal", "ready",
2184                                           "handover", "stop-ack",
2185                                           "shutdown-ack";
2186
2187                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2188                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2189                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2190                                  <&xo_board>,
2191                                  <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2192                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2193                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2194                                  <&rpmcc RPM_SMD_PCNOC_CLK>,
2195                                  <&rpmcc RPM_SMD_QDSS_CLK>;
2196                         clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2197                                       "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2198
2199                         resets = <&gcc GCC_MSS_RESTART>;
2200                         reset-names = "mss_restart";
2201
2202                         power-domains = <&rpmpd MSM8996_VDDCX>,
2203                                         <&rpmpd MSM8996_VDDMX>;
2204                         power-domain-names = "cx", "mx";
2205
2206                         qcom,smem-states = <&mpss_smp2p_out 0>;
2207                         qcom,smem-state-names = "stop";
2208
2209                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2210
2211                         status = "disabled";
2212
2213                         mba {
2214                                 memory-region = <&mba_mem>;
2215                         };
2216
2217                         mpss {
2218                                 memory-region = <&mpss_mem>;
2219                         };
2220
2221                         smd-edge {
2222                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2223
2224                                 label = "mpss";
2225                                 mboxes = <&apcs_glb 12>;
2226                                 qcom,smd-edge = <0>;
2227                                 qcom,remote-pid = <1>;
2228                         };
2229                 };
2230
2231                 stm@3002000 {
2232                         compatible = "arm,coresight-stm", "arm,primecell";
2233                         reg = <0x3002000 0x1000>,
2234                               <0x8280000 0x180000>;
2235                         reg-names = "stm-base", "stm-stimulus-base";
2236
2237                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2238                         clock-names = "apb_pclk", "atclk";
2239
2240                         out-ports {
2241                                 port {
2242                                         stm_out: endpoint {
2243                                                 remote-endpoint =
2244                                                   <&funnel0_in>;
2245                                         };
2246                                 };
2247                         };
2248                 };
2249
2250                 tpiu@3020000 {
2251                         compatible = "arm,coresight-tpiu", "arm,primecell";
2252                         reg = <0x3020000 0x1000>;
2253
2254                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2255                         clock-names = "apb_pclk", "atclk";
2256
2257                         in-ports {
2258                                 port {
2259                                         tpiu_in: endpoint {
2260                                                 remote-endpoint =
2261                                                   <&replicator_out1>;
2262                                         };
2263                                 };
2264                         };
2265                 };
2266
2267                 funnel@3021000 {
2268                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2269                         reg = <0x3021000 0x1000>;
2270
2271                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2272                         clock-names = "apb_pclk", "atclk";
2273
2274                         in-ports {
2275                                 #address-cells = <1>;
2276                                 #size-cells = <0>;
2277
2278                                 port@7 {
2279                                         reg = <7>;
2280                                         funnel0_in: endpoint {
2281                                                 remote-endpoint =
2282                                                   <&stm_out>;
2283                                         };
2284                                 };
2285                         };
2286
2287                         out-ports {
2288                                 port {
2289                                         funnel0_out: endpoint {
2290                                                 remote-endpoint =
2291                                                   <&merge_funnel_in0>;
2292                                         };
2293                                 };
2294                         };
2295                 };
2296
2297                 funnel@3022000 {
2298                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2299                         reg = <0x3022000 0x1000>;
2300
2301                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2302                         clock-names = "apb_pclk", "atclk";
2303
2304                         in-ports {
2305                                 #address-cells = <1>;
2306                                 #size-cells = <0>;
2307
2308                                 port@6 {
2309                                         reg = <6>;
2310                                         funnel1_in: endpoint {
2311                                                 remote-endpoint =
2312                                                   <&apss_merge_funnel_out>;
2313                                         };
2314                                 };
2315                         };
2316
2317                         out-ports {
2318                                 port {
2319                                         funnel1_out: endpoint {
2320                                                 remote-endpoint =
2321                                                   <&merge_funnel_in1>;
2322                                         };
2323                                 };
2324                         };
2325                 };
2326
2327                 funnel@3023000 {
2328                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2329                         reg = <0x3023000 0x1000>;
2330
2331                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2332                         clock-names = "apb_pclk", "atclk";
2333
2334
2335                         out-ports {
2336                                 port {
2337                                         funnel2_out: endpoint {
2338                                                 remote-endpoint =
2339                                                   <&merge_funnel_in2>;
2340                                         };
2341                                 };
2342                         };
2343                 };
2344
2345                 funnel@3025000 {
2346                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2347                         reg = <0x3025000 0x1000>;
2348
2349                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2350                         clock-names = "apb_pclk", "atclk";
2351
2352                         in-ports {
2353                                 #address-cells = <1>;
2354                                 #size-cells = <0>;
2355
2356                                 port@0 {
2357                                         reg = <0>;
2358                                         merge_funnel_in0: endpoint {
2359                                                 remote-endpoint =
2360                                                   <&funnel0_out>;
2361                                         };
2362                                 };
2363
2364                                 port@1 {
2365                                         reg = <1>;
2366                                         merge_funnel_in1: endpoint {
2367                                                 remote-endpoint =
2368                                                   <&funnel1_out>;
2369                                         };
2370                                 };
2371
2372                                 port@2 {
2373                                         reg = <2>;
2374                                         merge_funnel_in2: endpoint {
2375                                                 remote-endpoint =
2376                                                   <&funnel2_out>;
2377                                         };
2378                                 };
2379                         };
2380
2381                         out-ports {
2382                                 port {
2383                                         merge_funnel_out: endpoint {
2384                                                 remote-endpoint =
2385                                                   <&etf_in>;
2386                                         };
2387                                 };
2388                         };
2389                 };
2390
2391                 replicator@3026000 {
2392                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2393                         reg = <0x3026000 0x1000>;
2394
2395                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2396                         clock-names = "apb_pclk", "atclk";
2397
2398                         in-ports {
2399                                 port {
2400                                         replicator_in: endpoint {
2401                                                 remote-endpoint =
2402                                                   <&etf_out>;
2403                                         };
2404                                 };
2405                         };
2406
2407                         out-ports {
2408                                 #address-cells = <1>;
2409                                 #size-cells = <0>;
2410
2411                                 port@0 {
2412                                         reg = <0>;
2413                                         replicator_out0: endpoint {
2414                                                 remote-endpoint =
2415                                                   <&etr_in>;
2416                                         };
2417                                 };
2418
2419                                 port@1 {
2420                                         reg = <1>;
2421                                         replicator_out1: endpoint {
2422                                                 remote-endpoint =
2423                                                   <&tpiu_in>;
2424                                         };
2425                                 };
2426                         };
2427                 };
2428
2429                 etf@3027000 {
2430                         compatible = "arm,coresight-tmc", "arm,primecell";
2431                         reg = <0x3027000 0x1000>;
2432
2433                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2434                         clock-names = "apb_pclk", "atclk";
2435
2436                         in-ports {
2437                                 port {
2438                                         etf_in: endpoint {
2439                                                 remote-endpoint =
2440                                                   <&merge_funnel_out>;
2441                                         };
2442                                 };
2443                         };
2444
2445                         out-ports {
2446                                 port {
2447                                         etf_out: endpoint {
2448                                                 remote-endpoint =
2449                                                   <&replicator_in>;
2450                                         };
2451                                 };
2452                         };
2453                 };
2454
2455                 etr@3028000 {
2456                         compatible = "arm,coresight-tmc", "arm,primecell";
2457                         reg = <0x3028000 0x1000>;
2458
2459                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2460                         clock-names = "apb_pclk", "atclk";
2461                         arm,scatter-gather;
2462
2463                         in-ports {
2464                                 port {
2465                                         etr_in: endpoint {
2466                                                 remote-endpoint =
2467                                                   <&replicator_out0>;
2468                                         };
2469                                 };
2470                         };
2471                 };
2472
2473                 debug@3810000 {
2474                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2475                         reg = <0x3810000 0x1000>;
2476
2477                         clocks = <&rpmcc RPM_QDSS_CLK>;
2478                         clock-names = "apb_pclk";
2479
2480                         cpu = <&CPU0>;
2481                 };
2482
2483                 etm@3840000 {
2484                         compatible = "arm,coresight-etm4x", "arm,primecell";
2485                         reg = <0x3840000 0x1000>;
2486
2487                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2488                         clock-names = "apb_pclk", "atclk";
2489
2490                         cpu = <&CPU0>;
2491
2492                         out-ports {
2493                                 port {
2494                                         etm0_out: endpoint {
2495                                                 remote-endpoint =
2496                                                   <&apss_funnel0_in0>;
2497                                         };
2498                                 };
2499                         };
2500                 };
2501
2502                 debug@3910000 {
2503                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2504                         reg = <0x3910000 0x1000>;
2505
2506                         clocks = <&rpmcc RPM_QDSS_CLK>;
2507                         clock-names = "apb_pclk";
2508
2509                         cpu = <&CPU1>;
2510                 };
2511
2512                 etm@3940000 {
2513                         compatible = "arm,coresight-etm4x", "arm,primecell";
2514                         reg = <0x3940000 0x1000>;
2515
2516                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2517                         clock-names = "apb_pclk", "atclk";
2518
2519                         cpu = <&CPU1>;
2520
2521                         out-ports {
2522                                 port {
2523                                         etm1_out: endpoint {
2524                                                 remote-endpoint =
2525                                                   <&apss_funnel0_in1>;
2526                                         };
2527                                 };
2528                         };
2529                 };
2530
2531                 funnel@39b0000 { /* APSS Funnel 0 */
2532                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2533                         reg = <0x39b0000 0x1000>;
2534
2535                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2536                         clock-names = "apb_pclk", "atclk";
2537
2538                         in-ports {
2539                                 #address-cells = <1>;
2540                                 #size-cells = <0>;
2541
2542                                 port@0 {
2543                                         reg = <0>;
2544                                         apss_funnel0_in0: endpoint {
2545                                                 remote-endpoint = <&etm0_out>;
2546                                         };
2547                                 };
2548
2549                                 port@1 {
2550                                         reg = <1>;
2551                                         apss_funnel0_in1: endpoint {
2552                                                 remote-endpoint = <&etm1_out>;
2553                                         };
2554                                 };
2555                         };
2556
2557                         out-ports {
2558                                 port {
2559                                         apss_funnel0_out: endpoint {
2560                                                 remote-endpoint =
2561                                                   <&apss_merge_funnel_in0>;
2562                                         };
2563                                 };
2564                         };
2565                 };
2566
2567                 debug@3a10000 {
2568                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2569                         reg = <0x3a10000 0x1000>;
2570
2571                         clocks = <&rpmcc RPM_QDSS_CLK>;
2572                         clock-names = "apb_pclk";
2573
2574                         cpu = <&CPU2>;
2575                 };
2576
2577                 etm@3a40000 {
2578                         compatible = "arm,coresight-etm4x", "arm,primecell";
2579                         reg = <0x3a40000 0x1000>;
2580
2581                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582                         clock-names = "apb_pclk", "atclk";
2583
2584                         cpu = <&CPU2>;
2585
2586                         out-ports {
2587                                 port {
2588                                         etm2_out: endpoint {
2589                                                 remote-endpoint =
2590                                                   <&apss_funnel1_in0>;
2591                                         };
2592                                 };
2593                         };
2594                 };
2595
2596                 debug@3b10000 {
2597                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2598                         reg = <0x3b10000 0x1000>;
2599
2600                         clocks = <&rpmcc RPM_QDSS_CLK>;
2601                         clock-names = "apb_pclk";
2602
2603                         cpu = <&CPU3>;
2604                 };
2605
2606                 etm@3b40000 {
2607                         compatible = "arm,coresight-etm4x", "arm,primecell";
2608                         reg = <0x3b40000 0x1000>;
2609
2610                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2611                         clock-names = "apb_pclk", "atclk";
2612
2613                         cpu = <&CPU3>;
2614
2615                         out-ports {
2616                                 port {
2617                                         etm3_out: endpoint {
2618                                                 remote-endpoint =
2619                                                   <&apss_funnel1_in1>;
2620                                         };
2621                                 };
2622                         };
2623                 };
2624
2625                 funnel@3bb0000 { /* APSS Funnel 1 */
2626                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2627                         reg = <0x3bb0000 0x1000>;
2628
2629                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2630                         clock-names = "apb_pclk", "atclk";
2631
2632                         in-ports {
2633                                 #address-cells = <1>;
2634                                 #size-cells = <0>;
2635
2636                                 port@0 {
2637                                         reg = <0>;
2638                                         apss_funnel1_in0: endpoint {
2639                                                 remote-endpoint = <&etm2_out>;
2640                                         };
2641                                 };
2642
2643                                 port@1 {
2644                                         reg = <1>;
2645                                         apss_funnel1_in1: endpoint {
2646                                                 remote-endpoint = <&etm3_out>;
2647                                         };
2648                                 };
2649                         };
2650
2651                         out-ports {
2652                                 port {
2653                                         apss_funnel1_out: endpoint {
2654                                                 remote-endpoint =
2655                                                   <&apss_merge_funnel_in1>;
2656                                         };
2657                                 };
2658                         };
2659                 };
2660
2661                 funnel@3bc0000 {
2662                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2663                         reg = <0x3bc0000 0x1000>;
2664
2665                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2666                         clock-names = "apb_pclk", "atclk";
2667
2668                         in-ports {
2669                                 #address-cells = <1>;
2670                                 #size-cells = <0>;
2671
2672                                 port@0 {
2673                                         reg = <0>;
2674                                         apss_merge_funnel_in0: endpoint {
2675                                                 remote-endpoint =
2676                                                   <&apss_funnel0_out>;
2677                                         };
2678                                 };
2679
2680                                 port@1 {
2681                                         reg = <1>;
2682                                         apss_merge_funnel_in1: endpoint {
2683                                                 remote-endpoint =
2684                                                   <&apss_funnel1_out>;
2685                                         };
2686                                 };
2687                         };
2688
2689                         out-ports {
2690                                 port {
2691                                         apss_merge_funnel_out: endpoint {
2692                                                 remote-endpoint =
2693                                                   <&funnel1_in>;
2694                                         };
2695                                 };
2696                         };
2697                 };
2698
2699                 kryocc: clock-controller@6400000 {
2700                         compatible = "qcom,msm8996-apcc";
2701                         reg = <0x06400000 0x90000>;
2702
2703                         clock-names = "xo";
2704                         clocks = <&rpmcc RPM_SMD_BB_CLK1>;
2705
2706                         #clock-cells = <1>;
2707                 };
2708
2709                 usb3: usb@6af8800 {
2710                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2711                         reg = <0x06af8800 0x400>;
2712                         #address-cells = <1>;
2713                         #size-cells = <1>;
2714                         ranges;
2715
2716                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2717                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2718                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2719
2720                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2721                                  <&gcc GCC_USB30_MASTER_CLK>,
2722                                  <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2723                                  <&gcc GCC_USB30_SLEEP_CLK>,
2724                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2725                         clock-names = "cfg_noc",
2726                                       "core",
2727                                       "iface",
2728                                       "sleep",
2729                                       "mock_utmi";
2730
2731                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2732                                           <&gcc GCC_USB30_MASTER_CLK>;
2733                         assigned-clock-rates = <19200000>, <120000000>;
2734
2735                         power-domains = <&gcc USB30_GDSC>;
2736                         status = "disabled";
2737
2738                         usb3_dwc3: usb@6a00000 {
2739                                 compatible = "snps,dwc3";
2740                                 reg = <0x06a00000 0xcc00>;
2741                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
2742                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
2743                                 phy-names = "usb2-phy", "usb3-phy";
2744                                 snps,dis_u2_susphy_quirk;
2745                                 snps,dis_enblslpm_quirk;
2746                         };
2747                 };
2748
2749                 usb3phy: phy@7410000 {
2750                         compatible = "qcom,msm8996-qmp-usb3-phy";
2751                         reg = <0x07410000 0x1c4>;
2752                         #address-cells = <1>;
2753                         #size-cells = <1>;
2754                         ranges;
2755
2756                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2757                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2758                                 <&gcc GCC_USB3_CLKREF_CLK>;
2759                         clock-names = "aux", "cfg_ahb", "ref";
2760
2761                         resets = <&gcc GCC_USB3_PHY_BCR>,
2762                                 <&gcc GCC_USB3PHY_PHY_BCR>;
2763                         reset-names = "phy", "common";
2764                         status = "disabled";
2765
2766                         ssusb_phy_0: phy@7410200 {
2767                                 reg = <0x07410200 0x200>,
2768                                       <0x07410400 0x130>,
2769                                       <0x07410600 0x1a8>;
2770                                 #phy-cells = <0>;
2771
2772                                 #clock-cells = <1>;
2773                                 clock-output-names = "usb3_phy_pipe_clk_src";
2774                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2775                                 clock-names = "pipe0";
2776                         };
2777                 };
2778
2779                 hsusb_phy1: phy@7411000 {
2780                         compatible = "qcom,msm8996-qusb2-phy";
2781                         reg = <0x07411000 0x180>;
2782                         #phy-cells = <0>;
2783
2784                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2785                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2786                         clock-names = "cfg_ahb", "ref";
2787
2788                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2789                         nvmem-cells = <&qusb2p_hstx_trim>;
2790                         status = "disabled";
2791                 };
2792
2793                 hsusb_phy2: phy@7412000 {
2794                         compatible = "qcom,msm8996-qusb2-phy";
2795                         reg = <0x07412000 0x180>;
2796                         #phy-cells = <0>;
2797
2798                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2799                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
2800                         clock-names = "cfg_ahb", "ref";
2801
2802                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2803                         nvmem-cells = <&qusb2s_hstx_trim>;
2804                         status = "disabled";
2805                 };
2806
2807                 sdhc1: sdhci@7464900 {
2808                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
2809                         reg = <0x07464900 0x11c>, <0x07464000 0x800>;
2810                         reg-names = "hc_mem", "core_mem";
2811
2812                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2813                                         <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2814                         interrupt-names = "hc_irq", "pwr_irq";
2815
2816                         clock-names = "iface", "core", "xo";
2817                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2818                                 <&gcc GCC_SDCC1_APPS_CLK>,
2819                                 <&rpmcc RPM_SMD_BB_CLK1>;
2820
2821                         pinctrl-names = "default", "sleep";
2822                         pinctrl-0 = <&sdc1_state_on>;
2823                         pinctrl-1 = <&sdc1_state_off>;
2824
2825                         bus-width = <8>;
2826                         non-removable;
2827                         status = "disabled";
2828                 };
2829
2830                 sdhc2: sdhci@74a4900 {
2831                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
2832                         reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
2833                         reg-names = "hc_mem", "core_mem";
2834
2835                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2836                                       <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2837                         interrupt-names = "hc_irq", "pwr_irq";
2838
2839                         clock-names = "iface", "core", "xo";
2840                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2841                                 <&gcc GCC_SDCC2_APPS_CLK>,
2842                                 <&rpmcc RPM_SMD_BB_CLK1>;
2843
2844                         pinctrl-names = "default", "sleep";
2845                         pinctrl-0 = <&sdc2_state_on>;
2846                         pinctrl-1 = <&sdc2_state_off>;
2847
2848                         bus-width = <4>;
2849                         status = "disabled";
2850                  };
2851
2852                 blsp1_dma: dma-controller@7544000 {
2853                         compatible = "qcom,bam-v1.7.0";
2854                         reg = <0x07544000 0x2b000>;
2855                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2856                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2857                         clock-names = "bam_clk";
2858                         qcom,controlled-remotely;
2859                         #dma-cells = <1>;
2860                         qcom,ee = <0>;
2861                 };
2862
2863                 blsp1_uart2: serial@7570000 {
2864                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2865                         reg = <0x07570000 0x1000>;
2866                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2867                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2868                                  <&gcc GCC_BLSP1_AHB_CLK>;
2869                         clock-names = "core", "iface";
2870                         pinctrl-names = "default", "sleep";
2871                         pinctrl-0 = <&blsp1_uart2_default>;
2872                         pinctrl-1 = <&blsp1_uart2_sleep>;
2873                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
2874                         dma-names = "tx", "rx";
2875                         status = "disabled";
2876                 };
2877
2878                 blsp1_spi1: spi@7575000 {
2879                         compatible = "qcom,spi-qup-v2.2.1";
2880                         reg = <0x07575000 0x600>;
2881                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2882                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2883                                  <&gcc GCC_BLSP1_AHB_CLK>;
2884                         clock-names = "core", "iface";
2885                         pinctrl-names = "default", "sleep";
2886                         pinctrl-0 = <&blsp1_spi1_default>;
2887                         pinctrl-1 = <&blsp1_spi1_sleep>;
2888                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2889                         dma-names = "tx", "rx";
2890                         #address-cells = <1>;
2891                         #size-cells = <0>;
2892                         status = "disabled";
2893                 };
2894
2895                 blsp1_i2c3: i2c@7577000 {
2896                         compatible = "qcom,i2c-qup-v2.2.1";
2897                         reg = <0x07577000 0x1000>;
2898                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2899                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2900                                  <&gcc GCC_BLSP1_AHB_CLK>;
2901                         clock-names = "core", "iface";
2902                         pinctrl-names = "default", "sleep";
2903                         pinctrl-0 = <&blsp1_i2c3_default>;
2904                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2905                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2906                         dma-names = "tx", "rx";
2907                         #address-cells = <1>;
2908                         #size-cells = <0>;
2909                         status = "disabled";
2910                 };
2911
2912                 blsp2_dma: dma-controller@7584000 {
2913                         compatible = "qcom,bam-v1.7.0";
2914                         reg = <0x07584000 0x2b000>;
2915                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2916                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2917                         clock-names = "bam_clk";
2918                         qcom,controlled-remotely;
2919                         #dma-cells = <1>;
2920                         qcom,ee = <0>;
2921                 };
2922
2923                 blsp2_uart2: serial@75b0000 {
2924                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2925                         reg = <0x075b0000 0x1000>;
2926                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2927                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2928                                  <&gcc GCC_BLSP2_AHB_CLK>;
2929                         clock-names = "core", "iface";
2930                         status = "disabled";
2931                 };
2932
2933                 blsp2_uart3: serial@75b1000 {
2934                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2935                         reg = <0x075b1000 0x1000>;
2936                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2937                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2938                                  <&gcc GCC_BLSP2_AHB_CLK>;
2939                         clock-names = "core", "iface";
2940                         status = "disabled";
2941                 };
2942
2943                 blsp2_i2c1: i2c@75b5000 {
2944                         compatible = "qcom,i2c-qup-v2.2.1";
2945                         reg = <0x075b5000 0x1000>;
2946                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2947                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2948                                  <&gcc GCC_BLSP2_AHB_CLK>;
2949                         clock-names = "core", "iface";
2950                         pinctrl-names = "default", "sleep";
2951                         pinctrl-0 = <&blsp2_i2c1_default>;
2952                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2953                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2954                         dma-names = "tx", "rx";
2955                         #address-cells = <1>;
2956                         #size-cells = <0>;
2957                         status = "disabled";
2958                 };
2959
2960                 blsp2_i2c2: i2c@75b6000 {
2961                         compatible = "qcom,i2c-qup-v2.2.1";
2962                         reg = <0x075b6000 0x1000>;
2963                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2964                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2965                                  <&gcc GCC_BLSP2_AHB_CLK>;
2966                         clock-names = "core", "iface";
2967                         pinctrl-names = "default", "sleep";
2968                         pinctrl-0 = <&blsp2_i2c2_default>;
2969                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2970                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2971                         dma-names = "tx", "rx";
2972                         #address-cells = <1>;
2973                         #size-cells = <0>;
2974                         status = "disabled";
2975                 };
2976
2977                 blsp2_i2c3: i2c@75b7000 {
2978                         compatible = "qcom,i2c-qup-v2.2.1";
2979                         reg = <0x075b7000 0x1000>;
2980                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2981                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2982                                  <&gcc GCC_BLSP2_AHB_CLK>;
2983                         clock-names = "core", "iface";
2984                         clock-frequency = <400000>;
2985                         pinctrl-names = "default", "sleep";
2986                         pinctrl-0 = <&blsp2_i2c3_default>;
2987                         pinctrl-1 = <&blsp2_i2c3_sleep>;
2988                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2989                         dma-names = "tx", "rx";
2990                         #address-cells = <1>;
2991                         #size-cells = <0>;
2992                         status = "disabled";
2993                 };
2994
2995                 blsp2_i2c5: i2c@75b9000 {
2996                         compatible = "qcom,i2c-qup-v2.2.1";
2997                         reg = <0x75b9000 0x1000>;
2998                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2999                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3000                                  <&gcc GCC_BLSP2_AHB_CLK>;
3001                         clock-names = "core", "iface";
3002                         pinctrl-names = "default";
3003                         pinctrl-0 = <&blsp2_i2c5_default>;
3004                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3005                         dma-names = "tx", "rx";
3006                         #address-cells = <1>;
3007                         #size-cells = <0>;
3008                         status = "disabled";
3009                 };
3010
3011                 blsp2_i2c6: i2c@75ba000 {
3012                         compatible = "qcom,i2c-qup-v2.2.1";
3013                         reg = <0x75ba000 0x1000>;
3014                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3015                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3016                                  <&gcc GCC_BLSP2_AHB_CLK>;
3017                         clock-names = "core", "iface";
3018                         pinctrl-names = "default", "sleep";
3019                         pinctrl-0 = <&blsp2_i2c6_default>;
3020                         pinctrl-1 = <&blsp2_i2c6_sleep>;
3021                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3022                         dma-names = "tx", "rx";
3023                         #address-cells = <1>;
3024                         #size-cells = <0>;
3025                         status = "disabled";
3026                 };
3027
3028                 blsp2_spi6: spi@75ba000{
3029                         compatible = "qcom,spi-qup-v2.2.1";
3030                         reg = <0x075ba000 0x600>;
3031                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3032                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3033                                  <&gcc GCC_BLSP2_AHB_CLK>;
3034                         clock-names = "core", "iface";
3035                         pinctrl-names = "default", "sleep";
3036                         pinctrl-0 = <&blsp2_spi6_default>;
3037                         pinctrl-1 = <&blsp2_spi6_sleep>;
3038                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3039                         dma-names = "tx", "rx";
3040                         #address-cells = <1>;
3041                         #size-cells = <0>;
3042                         status = "disabled";
3043                 };
3044
3045                 usb2: usb@76f8800 {
3046                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3047                         reg = <0x076f8800 0x400>;
3048                         #address-cells = <1>;
3049                         #size-cells = <1>;
3050                         ranges;
3051
3052                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3053                                 <&gcc GCC_USB20_MASTER_CLK>,
3054                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3055                                 <&gcc GCC_USB20_SLEEP_CLK>,
3056                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3057                         clock-names = "cfg_noc",
3058                                       "core",
3059                                       "iface",
3060                                       "sleep",
3061                                       "mock_utmi";
3062
3063                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3064                                           <&gcc GCC_USB20_MASTER_CLK>;
3065                         assigned-clock-rates = <19200000>, <60000000>;
3066
3067                         power-domains = <&gcc USB30_GDSC>;
3068                         qcom,select-utmi-as-pipe-clk;
3069                         status = "disabled";
3070
3071                         usb2_dwc3: usb@7600000 {
3072                                 compatible = "snps,dwc3";
3073                                 reg = <0x07600000 0xcc00>;
3074                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3075                                 phys = <&hsusb_phy2>;
3076                                 phy-names = "usb2-phy";
3077                                 maximum-speed = "high-speed";
3078                                 snps,dis_u2_susphy_quirk;
3079                                 snps,dis_enblslpm_quirk;
3080                         };
3081                 };
3082
3083                 slimbam: dma-controller@9184000 {
3084                         compatible = "qcom,bam-v1.7.0";
3085                         qcom,controlled-remotely;
3086                         reg = <0x09184000 0x32000>;
3087                         num-channels  = <31>;
3088                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3089                         #dma-cells = <1>;
3090                         qcom,ee = <1>;
3091                         qcom,num-ees = <2>;
3092                 };
3093
3094                 slim_msm: slim@91c0000 {
3095                         compatible = "qcom,slim-ngd-v1.5.0";
3096                         reg = <0x091c0000 0x2C000>;
3097                         reg-names = "ctrl";
3098                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3099                         dmas =  <&slimbam 3>, <&slimbam 4>,
3100                                 <&slimbam 5>, <&slimbam 6>;
3101                         dma-names = "rx", "tx", "tx2", "rx2";
3102                         #address-cells = <1>;
3103                         #size-cells = <0>;
3104                         ngd@1 {
3105                                 reg = <1>;
3106                                 #address-cells = <1>;
3107                                 #size-cells = <1>;
3108
3109                                 tasha_ifd: tas-ifd {
3110                                         compatible = "slim217,1a0";
3111                                         reg  = <0 0>;
3112                                 };
3113
3114                                 wcd9335: codec@1{
3115                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3116                                         pinctrl-names = "default";
3117
3118                                         compatible = "slim217,1a0";
3119                                         reg  = <1 0>;
3120
3121                                         interrupt-parent = <&tlmm>;
3122                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
3123                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
3124                                         interrupt-names  = "intr1", "intr2";
3125                                         interrupt-controller;
3126                                         #interrupt-cells = <1>;
3127                                         reset-gpios = <&tlmm 64 0>;
3128
3129                                         slim-ifc-dev  = <&tasha_ifd>;
3130
3131                                         #sound-dai-cells = <1>;
3132                                 };
3133                         };
3134                 };
3135
3136                 adsp_pil: remoteproc@9300000 {
3137                         compatible = "qcom,msm8996-adsp-pil";
3138                         reg = <0x09300000 0x80000>;
3139
3140                         interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3141                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3142                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3143                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3144                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3145                         interrupt-names = "wdog", "fatal", "ready",
3146                                           "handover", "stop-ack";
3147
3148                         clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3149                         clock-names = "xo";
3150
3151                         memory-region = <&adsp_mem>;
3152
3153                         qcom,smem-states = <&adsp_smp2p_out 0>;
3154                         qcom,smem-state-names = "stop";
3155
3156                         power-domains = <&rpmpd MSM8996_VDDCX>;
3157                         power-domain-names = "cx";
3158
3159                         status = "disabled";
3160
3161                         smd-edge {
3162                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3163
3164                                 label = "lpass";
3165                                 mboxes = <&apcs_glb 8>;
3166                                 qcom,smd-edge = <1>;
3167                                 qcom,remote-pid = <2>;
3168                                 #address-cells = <1>;
3169                                 #size-cells = <0>;
3170                                 apr {
3171                                         power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3172                                         compatible = "qcom,apr-v2";
3173                                         qcom,smd-channels = "apr_audio_svc";
3174                                         qcom,domain = <APR_DOMAIN_ADSP>;
3175                                         #address-cells = <1>;
3176                                         #size-cells = <0>;
3177
3178                                         q6core {
3179                                                 reg = <APR_SVC_ADSP_CORE>;
3180                                                 compatible = "qcom,q6core";
3181                                         };
3182
3183                                         q6afe: q6afe {
3184                                                 compatible = "qcom,q6afe";
3185                                                 reg = <APR_SVC_AFE>;
3186                                                 q6afedai: dais {
3187                                                         compatible = "qcom,q6afe-dais";
3188                                                         #address-cells = <1>;
3189                                                         #size-cells = <0>;
3190                                                         #sound-dai-cells = <1>;
3191                                                         hdmi@1 {
3192                                                                 reg = <1>;
3193                                                         };
3194                                                 };
3195                                         };
3196
3197                                         q6asm: q6asm {
3198                                                 compatible = "qcom,q6asm";
3199                                                 reg = <APR_SVC_ASM>;
3200                                                 q6asmdai: dais {
3201                                                         compatible = "qcom,q6asm-dais";
3202                                                         #address-cells = <1>;
3203                                                         #size-cells = <0>;
3204                                                         #sound-dai-cells = <1>;
3205                                                         iommus = <&lpass_q6_smmu 1>;
3206                                                 };
3207                                         };
3208
3209                                         q6adm: q6adm {
3210                                                 compatible = "qcom,q6adm";
3211                                                 reg = <APR_SVC_ADM>;
3212                                                 q6routing: routing {
3213                                                         compatible = "qcom,q6adm-routing";
3214                                                         #sound-dai-cells = <0>;
3215                                                 };
3216                                         };
3217                                 };
3218
3219                         };
3220                 };
3221
3222                 apcs_glb: mailbox@9820000 {
3223                         compatible = "qcom,msm8996-apcs-hmss-global";
3224                         reg = <0x09820000 0x1000>;
3225
3226                         #mbox-cells = <1>;
3227                 };
3228
3229                 timer@9840000 {
3230                         #address-cells = <1>;
3231                         #size-cells = <1>;
3232                         ranges;
3233                         compatible = "arm,armv7-timer-mem";
3234                         reg = <0x09840000 0x1000>;
3235                         clock-frequency = <19200000>;
3236
3237                         frame@9850000 {
3238                                 frame-number = <0>;
3239                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3240                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3241                                 reg = <0x09850000 0x1000>,
3242                                       <0x09860000 0x1000>;
3243                         };
3244
3245                         frame@9870000 {
3246                                 frame-number = <1>;
3247                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3248                                 reg = <0x09870000 0x1000>;
3249                                 status = "disabled";
3250                         };
3251
3252                         frame@9880000 {
3253                                 frame-number = <2>;
3254                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3255                                 reg = <0x09880000 0x1000>;
3256                                 status = "disabled";
3257                         };
3258
3259                         frame@9890000 {
3260                                 frame-number = <3>;
3261                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3262                                 reg = <0x09890000 0x1000>;
3263                                 status = "disabled";
3264                         };
3265
3266                         frame@98a0000 {
3267                                 frame-number = <4>;
3268                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3269                                 reg = <0x098a0000 0x1000>;
3270                                 status = "disabled";
3271                         };
3272
3273                         frame@98b0000 {
3274                                 frame-number = <5>;
3275                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3276                                 reg = <0x098b0000 0x1000>;
3277                                 status = "disabled";
3278                         };
3279
3280                         frame@98c0000 {
3281                                 frame-number = <6>;
3282                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3283                                 reg = <0x098c0000 0x1000>;
3284                                 status = "disabled";
3285                         };
3286                 };
3287
3288                 saw3: syscon@9a10000 {
3289                         compatible = "syscon";
3290                         reg = <0x09a10000 0x1000>;
3291                 };
3292
3293                 intc: interrupt-controller@9bc0000 {
3294                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3295                         #interrupt-cells = <3>;
3296                         interrupt-controller;
3297                         #redistributor-regions = <1>;
3298                         redistributor-stride = <0x0 0x40000>;
3299                         reg = <0x09bc0000 0x10000>,
3300                               <0x09c00000 0x100000>;
3301                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3302                 };
3303         };
3304
3305         sound: sound {
3306         };
3307
3308         thermal-zones {
3309                 cpu0-thermal {
3310                         polling-delay-passive = <250>;
3311                         polling-delay = <1000>;
3312
3313                         thermal-sensors = <&tsens0 3>;
3314
3315                         trips {
3316                                 cpu0_alert0: trip-point0 {
3317                                         temperature = <75000>;
3318                                         hysteresis = <2000>;
3319                                         type = "passive";
3320                                 };
3321
3322                                 cpu0_crit: cpu_crit {
3323                                         temperature = <110000>;
3324                                         hysteresis = <2000>;
3325                                         type = "critical";
3326                                 };
3327                         };
3328                 };
3329
3330                 cpu1-thermal {
3331                         polling-delay-passive = <250>;
3332                         polling-delay = <1000>;
3333
3334                         thermal-sensors = <&tsens0 5>;
3335
3336                         trips {
3337                                 cpu1_alert0: trip-point0 {
3338                                         temperature = <75000>;
3339                                         hysteresis = <2000>;
3340                                         type = "passive";
3341                                 };
3342
3343                                 cpu1_crit: cpu_crit {
3344                                         temperature = <110000>;
3345                                         hysteresis = <2000>;
3346                                         type = "critical";
3347                                 };
3348                         };
3349                 };
3350
3351                 cpu2-thermal {
3352                         polling-delay-passive = <250>;
3353                         polling-delay = <1000>;
3354
3355                         thermal-sensors = <&tsens0 8>;
3356
3357                         trips {
3358                                 cpu2_alert0: trip-point0 {
3359                                         temperature = <75000>;
3360                                         hysteresis = <2000>;
3361                                         type = "passive";
3362                                 };
3363
3364                                 cpu2_crit: cpu_crit {
3365                                         temperature = <110000>;
3366                                         hysteresis = <2000>;
3367                                         type = "critical";
3368                                 };
3369                         };
3370                 };
3371
3372                 cpu3-thermal {
3373                         polling-delay-passive = <250>;
3374                         polling-delay = <1000>;
3375
3376                         thermal-sensors = <&tsens0 10>;
3377
3378                         trips {
3379                                 cpu3_alert0: trip-point0 {
3380                                         temperature = <75000>;
3381                                         hysteresis = <2000>;
3382                                         type = "passive";
3383                                 };
3384
3385                                 cpu3_crit: cpu_crit {
3386                                         temperature = <110000>;
3387                                         hysteresis = <2000>;
3388                                         type = "critical";
3389                                 };
3390                         };
3391                 };
3392
3393                 gpu-top-thermal {
3394                         polling-delay-passive = <250>;
3395                         polling-delay = <1000>;
3396
3397                         thermal-sensors = <&tsens1 6>;
3398
3399                         trips {
3400                                 gpu1_alert0: trip-point0 {
3401                                         temperature = <90000>;
3402                                         hysteresis = <2000>;
3403                                         type = "passive";
3404                                 };
3405                         };
3406
3407                         cooling-maps {
3408                                 map0 {
3409                                         trip = <&gpu1_alert0>;
3410                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3411                                 };
3412                         };
3413                 };
3414
3415                 gpu-bottom-thermal {
3416                         polling-delay-passive = <250>;
3417                         polling-delay = <1000>;
3418
3419                         thermal-sensors = <&tsens1 7>;
3420
3421                         trips {
3422                                 gpu2_alert0: trip-point0 {
3423                                         temperature = <90000>;
3424                                         hysteresis = <2000>;
3425                                         type = "passive";
3426                                 };
3427                         };
3428
3429                         cooling-maps {
3430                                 map0 {
3431                                         trip = <&gpu2_alert0>;
3432                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3433                                 };
3434                         };
3435                 };
3436
3437                 m4m-thermal {
3438                         polling-delay-passive = <250>;
3439                         polling-delay = <1000>;
3440
3441                         thermal-sensors = <&tsens0 1>;
3442
3443                         trips {
3444                                 m4m_alert0: trip-point0 {
3445                                         temperature = <90000>;
3446                                         hysteresis = <2000>;
3447                                         type = "hot";
3448                                 };
3449                         };
3450                 };
3451
3452                 l3-or-venus-thermal {
3453                         polling-delay-passive = <250>;
3454                         polling-delay = <1000>;
3455
3456                         thermal-sensors = <&tsens0 2>;
3457
3458                         trips {
3459                                 l3_or_venus_alert0: trip-point0 {
3460                                         temperature = <90000>;
3461                                         hysteresis = <2000>;
3462                                         type = "hot";
3463                                 };
3464                         };
3465                 };
3466
3467                 cluster0-l2-thermal {
3468                         polling-delay-passive = <250>;
3469                         polling-delay = <1000>;
3470
3471                         thermal-sensors = <&tsens0 7>;
3472
3473                         trips {
3474                                 cluster0_l2_alert0: trip-point0 {
3475                                         temperature = <90000>;
3476                                         hysteresis = <2000>;
3477                                         type = "hot";
3478                                 };
3479                         };
3480                 };
3481
3482                 cluster1-l2-thermal {
3483                         polling-delay-passive = <250>;
3484                         polling-delay = <1000>;
3485
3486                         thermal-sensors = <&tsens0 12>;
3487
3488                         trips {
3489                                 cluster1_l2_alert0: trip-point0 {
3490                                         temperature = <90000>;
3491                                         hysteresis = <2000>;
3492                                         type = "hot";
3493                                 };
3494                         };
3495                 };
3496
3497                 camera-thermal {
3498                         polling-delay-passive = <250>;
3499                         polling-delay = <1000>;
3500
3501                         thermal-sensors = <&tsens1 1>;
3502
3503                         trips {
3504                                 camera_alert0: trip-point0 {
3505                                         temperature = <90000>;
3506                                         hysteresis = <2000>;
3507                                         type = "hot";
3508                                 };
3509                         };
3510                 };
3511
3512                 q6-dsp-thermal {
3513                         polling-delay-passive = <250>;
3514                         polling-delay = <1000>;
3515
3516                         thermal-sensors = <&tsens1 2>;
3517
3518                         trips {
3519                                 q6_dsp_alert0: trip-point0 {
3520                                         temperature = <90000>;
3521                                         hysteresis = <2000>;
3522                                         type = "hot";
3523                                 };
3524                         };
3525                 };
3526
3527                 mem-thermal {
3528                         polling-delay-passive = <250>;
3529                         polling-delay = <1000>;
3530
3531                         thermal-sensors = <&tsens1 3>;
3532
3533                         trips {
3534                                 mem_alert0: trip-point0 {
3535                                         temperature = <90000>;
3536                                         hysteresis = <2000>;
3537                                         type = "hot";
3538                                 };
3539                         };
3540                 };
3541
3542                 modemtx-thermal {
3543                         polling-delay-passive = <250>;
3544                         polling-delay = <1000>;
3545
3546                         thermal-sensors = <&tsens1 4>;
3547
3548                         trips {
3549                                 modemtx_alert0: trip-point0 {
3550                                         temperature = <90000>;
3551                                         hysteresis = <2000>;
3552                                         type = "hot";
3553                                 };
3554                         };
3555                 };
3556         };
3557
3558         timer {
3559                 compatible = "arm,armv8-timer";
3560                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3561                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3562                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3563                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3564         };
3565 };