1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
28 compatible = "fixed-clock";
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
37 clock-frequency = <32768>;
38 clock-output-names = "sleep_clk";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 next-level-cache = <&L2_0>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 next-level-cache = <&L2_0>;
77 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
85 compatible = "arm,cortex-a57";
87 enable-method = "psci";
88 next-level-cache = <&L2_1>;
98 compatible = "arm,cortex-a57";
100 enable-method = "psci";
101 next-level-cache = <&L2_1>;
106 compatible = "arm,cortex-a57";
108 enable-method = "psci";
109 next-level-cache = <&L2_1>;
114 compatible = "arm,cortex-a57";
116 enable-method = "psci";
117 next-level-cache = <&L2_1>;
161 compatible = "qcom,scm-msm8994", "qcom,scm";
166 device_type = "memory";
167 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>;
172 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
177 compatible = "arm,psci-0.2";
182 compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";
185 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
187 qcom,smd-edge = <15>;
188 qcom,remote-pid = <6>;
190 rpm_requests: rpm-requests {
191 compatible = "qcom,rpm-msm8994", "qcom,smd-rpm";
192 qcom,smd-channels = "rpm_requests";
194 rpmcc: clock-controller {
195 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
199 rpmpd: power-controller {
200 compatible = "qcom,msm8994-rpmpd";
201 #power-domain-cells = <1>;
202 operating-points-v2 = <&rpmpd_opp_table>;
204 rpmpd_opp_table: opp-table {
205 compatible = "operating-points-v2";
207 rpmpd_opp_ret: opp1 {
210 rpmpd_opp_svs_krait: opp2 {
213 rpmpd_opp_svs_soc: opp3 {
216 rpmpd_opp_nom: opp4 {
219 rpmpd_opp_turbo: opp5 {
222 rpmpd_opp_super_turbo: opp6 {
232 #address-cells = <2>;
236 dfps_data_mem: dfps-data@3400000 {
237 reg = <0 0x03400000 0 0x1000>;
241 cont_splash_mem: memory@3401000 {
242 reg = <0 0x03401000 0 0x2200000>;
246 smem_mem: smem@6a00000 {
247 reg = <0 0x06a00000 0 0x200000>;
251 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0 0x5a00000>;
256 peripheral_region: memory@ca00000 {
257 reg = <0 0x0ca00000 0 0x1f00000>;
261 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmtfs-mem";
263 reg = <0 0xc6400000 0 0x180000>;
266 qcom,client-id = <1>;
269 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0 0x100000>;
274 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0 0x800000>;
279 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0 0x3f00000>;
284 res_hyp_mem: reserved@6c00000 {
285 reg = <0 0x06c00000 0 0x400000>;
291 compatible = "qcom,smem";
292 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>;
298 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>;
301 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
305 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>;
308 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells = <1>;
313 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "slave-kernel";
316 interrupt-controller;
317 #interrupt-cells = <2>;
322 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>;
325 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
330 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>;
333 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells = <1>;
338 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "slave-kernel";
341 interrupt-controller;
342 #interrupt-cells = <2>;
347 #address-cells = <1>;
349 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus";
352 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm-qgic2";
354 interrupt-controller;
355 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x1000>,
360 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x2000>;
367 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
368 reg = <0xf9017000 0x1000>;
369 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
370 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
371 clocks = <&sleep_clk>;
376 #address-cells = <1>;
379 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x1000>;
384 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021000 0x1000>,
392 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023000 0x1000>;
399 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024000 0x1000>;
406 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025000 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026000 0x1000>;
420 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027000 0x1000>;
427 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028000 0x1000>;
434 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>;
440 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core",
449 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = <19200000>, <120000000>;
453 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pipe-clk;
457 compatible = "snps,dwc3";
458 reg = <0xf9200000 0xcc00>;
459 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_susphy_quirk;
461 snps,dis_enblslpm_quirk;
462 maximum-speed = "high-speed";
463 dr_mode = "peripheral";
467 sdhc1: mmc@f9824900 {
468 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "core";
472 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_irq", "pwr_irq";
476 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
477 <&gcc GCC_SDCC1_APPS_CLK>,
479 clock-names = "iface", "core", "xo";
481 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
490 sdhc2: mmc@f98a4900 {
491 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "core";
495 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_irq", "pwr_irq";
499 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
500 <&gcc GCC_SDCC2_APPS_CLK>,
502 clock-names = "iface", "core", "xo";
504 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
508 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
513 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk";
521 qcom,controlled-remotely;
526 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_uart2_sleep>;
539 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
544 <&gcc GCC_BLSP1_AHB_CLK>;
545 clock-names = "core", "iface";
546 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
548 dma-names = "tx", "rx";
549 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>;
557 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", "iface";
564 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx";
566 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>;
574 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
579 <&gcc GCC_BLSP1_AHB_CLK>;
580 clock-names = "core", "iface";
581 clock-frequency = <400000>;
582 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx";
584 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>;
592 /* I2C3 doesn't exist */
594 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
599 <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", "iface";
601 clock-frequency = <400000>;
602 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
603 dma-names = "tx", "rx";
604 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>;
612 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c-qup-v2.2.1";
614 reg = <0xf9927000 0x500>;
615 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
617 <&gcc GCC_BLSP1_AHB_CLK>;
618 clock-names = "core", "iface";
619 clock-frequency = <400000>;
620 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
621 dma-names = "tx", "rx";
622 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>;
630 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
635 <&gcc GCC_BLSP1_AHB_CLK>;
636 clock-names = "core", "iface";
637 clock-frequency = <400000>;
638 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx";
640 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>;
648 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam-v1.7.0";
650 reg = <0xf9944000 0x19000>;
651 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
653 clock-names = "bam_clk";
656 qcom,controlled-remotely;
661 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
665 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx";
670 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_uart2_sleep>;
676 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c-qup-v2.2.1";
678 reg = <0xf9963000 0x500>;
679 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
681 <&gcc GCC_BLSP2_AHB_CLK>;
682 clock-names = "core", "iface";
683 clock-frequency = <400000>;
684 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
685 dma-names = "tx", "rx";
686 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>;
694 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi-qup-v2.2.1";
696 reg = <0xf9966000 0x500>;
697 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
699 <&gcc GCC_BLSP2_AHB_CLK>;
700 clock-names = "core", "iface";
701 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
702 dma-names = "tx", "rx";
703 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>;
711 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
716 <&gcc GCC_BLSP2_AHB_CLK>;
717 clock-names = "core", "iface";
718 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx";
721 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>;
729 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc-msm8994";
733 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x2000>;
736 clock-names = "xo", "sleep";
737 clocks = <&xo_board>, <&sleep_clk>;
740 rpm_msg_ram: sram@fc428000 {
741 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x4000>;
746 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4>;
750 spmi_bus: spmi@fc4cf000 {
751 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x1000>,
755 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
760 #address-cells = <2>;
762 interrupt-controller;
763 #interrupt-cells = <4>;
766 tcsr_mutex: hwlock@fd484000 {
767 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
768 reg = <0xfd484000 0x1000>;
772 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
777 gpio-ranges = <&tlmm 0 0 146>;
779 interrupt-controller;
780 #interrupt-cells = <2>;
782 blsp1_uart2_default: blsp1-uart2-default-state {
783 pins = "gpio4", "gpio5";
784 function = "blsp_uart2";
785 drive-strength = <16>;
789 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
790 pins = "gpio4", "gpio5";
792 drive-strength = <2>;
796 blsp2_uart2_default: blsp2-uart2-default-state {
797 pins = "gpio45", "gpio46", "gpio47", "gpio48";
798 function = "blsp_uart8";
799 drive-strength = <16>;
803 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
804 pins = "gpio45", "gpio46", "gpio47", "gpio48";
806 drive-strength = <2>;
810 i2c1_default: i2c1-default-state {
811 pins = "gpio2", "gpio3";
812 function = "blsp_i2c1";
813 drive-strength = <2>;
817 i2c1_sleep: i2c1-sleep-state {
818 pins = "gpio2", "gpio3";
820 drive-strength = <2>;
824 i2c2_default: i2c2-default-state {
825 pins = "gpio6", "gpio7";
826 function = "blsp_i2c2";
827 drive-strength = <2>;
831 i2c2_sleep: i2c2-sleep-state {
832 pins = "gpio6", "gpio7";
834 drive-strength = <2>;
838 i2c4_default: i2c4-default-state {
839 pins = "gpio19", "gpio20";
840 function = "blsp_i2c4";
841 drive-strength = <2>;
845 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio19", "gpio20";
848 drive-strength = <2>;
852 i2c5_default: i2c5-default-state {
853 pins = "gpio23", "gpio24";
854 function = "blsp_i2c5";
855 drive-strength = <2>;
859 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio23", "gpio24";
862 drive-strength = <2>;
866 i2c6_default: i2c6-default-state {
867 pins = "gpio28", "gpio27";
868 function = "blsp_i2c6";
869 drive-strength = <2>;
873 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio28", "gpio27";
876 drive-strength = <2>;
880 i2c7_default: i2c7-default-state {
881 pins = "gpio44", "gpio43";
882 function = "blsp_i2c7";
883 drive-strength = <2>;
887 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio44", "gpio43";
890 drive-strength = <2>;
894 blsp2_spi10_default: blsp2-spi10-default-state {
896 pins = "gpio53", "gpio54", "gpio55";
897 function = "blsp_spi10";
898 drive-strength = <10>;
905 drive-strength = <2>;
910 blsp2_spi10_sleep: blsp2-spi10-sleep-state {
911 pins = "gpio53", "gpio54", "gpio55";
913 drive-strength = <2>;
917 i2c11_default: i2c11-default-state {
918 pins = "gpio83", "gpio84";
919 function = "blsp_i2c11";
920 drive-strength = <2>;
924 i2c11_sleep: i2c11-sleep-state {
925 pins = "gpio83", "gpio84";
927 drive-strength = <2>;
931 blsp1_spi1_default: blsp1-spi1-default-state {
933 pins = "gpio0", "gpio1", "gpio3";
934 function = "blsp_spi1";
935 drive-strength = <10>;
942 drive-strength = <2>;
947 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
948 pins = "gpio0", "gpio1", "gpio3";
950 drive-strength = <2>;
954 sdc1_clk_on: clk-on-state {
957 drive-strength = <16>;
960 sdc1_clk_off: clk-off-state {
963 drive-strength = <2>;
966 sdc1_cmd_on: cmd-on-state {
969 drive-strength = <8>;
972 sdc1_cmd_off: cmd-off-state {
975 drive-strength = <2>;
978 sdc1_data_on: data-on-state {
981 drive-strength = <8>;
984 sdc1_data_off: data-off-state {
987 drive-strength = <2>;
990 sdc1_rclk_on: rclk-on-state {
995 sdc1_rclk_off: rclk-off-state {
1000 sdc2_clk_on: sdc2-clk-on-state {
1003 drive-strength = <10>;
1006 sdc2_clk_off: sdc2-clk-off-state {
1009 drive-strength = <2>;
1012 sdc2_cmd_on: sdc2-cmd-on-state {
1015 drive-strength = <10>;
1018 sdc2_cmd_off: sdc2-cmd-off-state {
1021 drive-strength = <2>;
1024 sdc2_data_on: sdc2-data-on-state {
1027 drive-strength = <10>;
1030 sdc2_data_off: sdc2-data-off-state {
1033 drive-strength = <2>;
1037 mmcc: clock-controller@fd8c0000 {
1038 compatible = "qcom,mmcc-msm8994";
1039 reg = <0xfd8c0000 0x5200>;
1042 #power-domain-cells = <1>;
1047 "oxili_gfx3d_clk_src",
1053 clocks = <&xo_board>,
1054 <&gcc GPLL0_OUT_MMSSCC>,
1055 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1056 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1063 assigned-clocks = <&mmcc MMPLL0_PLL>,
1068 assigned-clock-rates = <800000000>,
1075 ocmem: sram@fdd00000 {
1076 compatible = "qcom,msm8974-ocmem";
1077 reg = <0xfdd00000 0x2000>,
1078 <0xfec00000 0x200000>;
1079 reg-names = "ctrl", "mem";
1080 ranges = <0 0xfec00000 0x200000>;
1081 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1082 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1083 clock-names = "core", "iface";
1085 #address-cells = <1>;
1088 gmu_sram: gmu-sram@0 {
1089 reg = <0x0 0x180000>;
1095 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1097 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1098 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1099 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1102 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr";
1106 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <3600000>;
1109 regulator-always-on;