arch/arm64/boot/dts/qcom/msm8994.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
   7
   8 / {
   9         interrupt-parent = <&intc>;
  10
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         chosen { };
  15
  16         clocks {
  17                 xo_board: xo_board {
  18                         compatible = "fixed-clock";
  19                         #clock-cells = <0>;
  20                         clock-frequency = <19200000>;
  21                 };
  22
  23                 sleep_clk: sleep_clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                         clock-frequency = <32768>;
  27                 };
  28         };
  29
  30         cpus {
  31                 #address-cells = <2>;
  32                 #size-cells = <0>;
  33
  34                 CPU0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&L2_0>;
  40                         L2_0: l2-cache {
  41                                 compatible = "cache";
  42                                 cache-level = <2>;
  43                         };
  44                 };
  45
  46                 CPU1: cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x0 0x1>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&L2_0>;
  52                 };
  53
  54                 CPU2: cpu@2 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a53";
  57                         reg = <0x0 0x2>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&L2_0>;
  60                 };
  61
  62                 CPU3: cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53";
  65                         reg = <0x0 0x3>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&L2_0>;
  68                 };
  69
  70                 CPU4: cpu@100 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a57";
  73                         reg = <0x0 0x100>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&L2_1>;
  76                         L2_1: l2-cache {
  77                                 compatible = "cache";
  78                                 cache-level = <2>;
  79                         };
  80                 };
  81
  82                 CPU5: cpu@101 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a57";
  85                         reg = <0x0 0x101>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&L2_1>;
  88                 };
  89
  90                 CPU6: cpu@102 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a57";
  93                         reg = <0x0 0x101>;
  94                         enable-method = "psci";
  95                         next-level-cache = <&L2_1>;
  96                 };
  97
  98                 CPU7: cpu@103 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a57";
 101                         reg = <0x0 0x101>;
 102                         enable-method = "psci";
 103                         next-level-cache = <&L2_1>;
 104                 };
 105
 106                 cpu-map {
 107                         cluster0 {
 108                                 core0 {
 109                                         cpu = <&CPU0>;
 110                                 };
 111
 112                                 core1 {
 113                                         cpu = <&CPU1>;
 114                                 };
 115
 116                                 core2 {
 117                                         cpu = <&CPU2>;
 118                                 };
 119
 120                                 core3 {
 121                                         cpu = <&CPU3>;
 122                                 };
 123                         };
 124
 125                         cluster1 {
 126                                 core0 {
 127                                         cpu = <&CPU4>;
 128                                 };
 129
 130                                 core1 {
 131                                         cpu = <&CPU5>;
 132                                 };
 133
 134                                 core2 {
 135                                         cpu = <&CPU6>;
 136                                 };
 137
 138                                 core3 {
 139                                         cpu = <&CPU7>;
 140                                 };
 141                         };
 142                 };
 143         };
 144
 145         firmware {
 146                 scm {
 147                         compatible = "qcom,scm-msm8994", "qcom,scm";
 148                 };
 149         };
 150
 151         memory {
 152                 device_type = "memory";
 153                 /* We expect the bootloader to fill in the reg */
 154                 reg = <0 0 0 0>;
 155         };
 156
 157         pmu {
 158                 compatible = "arm,cortex-a53-pmu";
 159                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
 160         };
 161
 162         psci {
 163                 compatible = "arm,psci-0.2";
 164                 method = "hvc";
 165         };
 166
 167         reserved-memory {
 168                 #address-cells = <2>;
 169                 #size-cells = <2>;
 170                 ranges;
 171
 172                 smem_mem: smem_region@6a00000 {
 173                         reg = <0x0 0x6a00000 0x0 0x200000>;
 174                         no-map;
 175                 };
 176         };
 177
 178         smd {
 179                 compatible = "qcom,smd";
 180                 rpm {
 181                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 182                         qcom,ipc = <&apcs 8 0>;
 183                         qcom,smd-edge = <15>;
 184                         qcom,local-pid = <0>;
 185                         qcom,remote-pid = <6>;
 186
 187                         rpm_requests: rpm-requests {
 188                                 compatible = "qcom,rpm-msm8994";
 189                                 qcom,smd-channels = "rpm_requests";
 190
 191                                 rpmcc: rpmcc {
 192                                         compatible = "qcom,rpmcc-msm8994";
 193                                         #clock-cells = <1>;
 194                                 };
 195                         };
 196                 };
 197         };
 198
 199         smem {
 200                 compatible = "qcom,smem";
 201                 memory-region = <&smem_mem>;
 202                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 203                 hwlocks = <&tcsr_mutex 3>;
 204         };
 205
 206         soc: soc {
 207
 208                 #address-cells = <1>;
 209                 #size-cells = <1>;
 210                 ranges = <0 0 0 0xffffffff>;
 211                 compatible = "simple-bus";
 212
 213                 intc: interrupt-controller@f9000000 {
 214                         compatible = "qcom,msm-qgic2";
 215                         interrupt-controller;
 216                         #interrupt-cells = <3>;
 217                         reg = <0xf9000000 0x1000>,
 218                               <0xf9002000 0x1000>;
 219                 };
 220
 221                 apcs: mailbox@f900d000 {
 222                         compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
 223                         reg = <0xf900d000 0x2000>;
 224                         #mbox-cells = <1>;
 225                 };
 226
 227                 timer@f9020000 {
 228                         #address-cells = <1>;
 229                         #size-cells = <1>;
 230                         ranges;
 231                         compatible = "arm,armv7-timer-mem";
 232                         reg = <0xf9020000 0x1000>;
 233
 234                         frame@f9021000 {
 235                                 frame-number = <0>;
 236                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 237                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 238                                 reg = <0xf9021000 0x1000>,
 239                                       <0xf9022000 0x1000>;
 240                         };
 241
 242                         frame@f9023000 {
 243                                 frame-number = <1>;
 244                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 245                                 reg = <0xf9023000 0x1000>;
 246                                 status = "disabled";
 247                         };
 248
 249                         frame@f9024000 {
 250                                 frame-number = <2>;
 251                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 252                                 reg = <0xf9024000 0x1000>;
 253                                 status = "disabled";
 254                         };
 255
 256                         frame@f9025000 {
 257                                 frame-number = <3>;
 258                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 259                                 reg = <0xf9025000 0x1000>;
 260                                 status = "disabled";
 261                         };
 262
 263                         frame@f9026000 {
 264                                 frame-number = <4>;
 265                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 266                                 reg = <0xf9026000 0x1000>;
 267                                 status = "disabled";
 268                         };
 269
 270                         frame@f9027000 {
 271                                 frame-number = <5>;
 272                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 273                                 reg = <0xf9027000 0x1000>;
 274                                 status = "disabled";
 275                         };
 276
 277                         frame@f9028000 {
 278                                 frame-number = <6>;
 279                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 280                                 reg = <0xf9028000 0x1000>;
 281                                 status = "disabled";
 282                         };
 283                 };
 284
 285                 sdhc1: sdhci@f9824900 {
 286                         compatible = "qcom,sdhci-msm-v4";
 287                         reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
 288                         reg-names = "hc_mem", "core_mem";
 289
 290                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 292                         interrupt-names = "hc_irq", "pwr_irq";
 293
 294                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 295                                  <&gcc GCC_SDCC1_AHB_CLK>,
 296                                  <&xo_board>;
 297                         clock-names = "core", "iface", "xo";
 298
 299                         pinctrl-names = "default", "sleep";
 300                         pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
 301                         pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
 302
 303                         bus-width = <8>;
 304                         non-removable;
 305                         status = "disabled";
 306                 };
 307
 308                 blsp1_dma: dma@f9904000 {
 309                         compatible = "qcom,bam-v1.7.0";
 310                         reg = <0xf9904000 0x19000>;
 311                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 313                         clock-names = "bam_clk";
 314                         #dma-cells = <1>;
 315                         qcom,ee = <0>;
 316                         qcom,controlled-remotely;
 317                         num-channels = <18>;
 318                         qcom,num-ees = <4>;
 319                 };
 320
 321                 blsp1_uart2: serial@f991e000 {
 322                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 323                         reg = <0xf991e000 0x1000>;
 324                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 325                         clock-names = "core", "iface";
 326                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 327                                  <&gcc GCC_BLSP1_AHB_CLK>;
 328                         pinctrl-names = "default", "sleep";
 329                         pinctrl-0 = <&blsp1_uart2_default>;
 330                         pinctrl-1 = <&blsp1_uart2_sleep>;
 331                         status = "disabled";
 332                 };
 333
 334                 blsp_i2c1: i2c@f9923000 {
 335                         compatible = "qcom,i2c-qup-v2.2.1";
 336                         reg = <0xf9923000 0x500>;
 337                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 339                                                 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 340                         clock-names = "iface", "core";
 341                         clock-frequency = <400000>;
 342                         pinctrl-names = "default", "sleep";
 343                         pinctrl-0 = <&i2c1_default>;
 344                         pinctrl-1 = <&i2c1_sleep>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         status = "disabled";
 348                 };
 349
 350                 blsp_spi0: spi@f9923000 {
 351                         compatible = "qcom,spi-qup-v2.2.1";
 352                         reg = <0xf9923000 0x500>;
 353                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 355                                  <&gcc GCC_BLSP1_AHB_CLK>;
 356                         clock-names = "core", "iface";
 357                         spi-max-frequency = <19200000>;
 358                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 359                         dma-names = "tx", "rx";
 360                         pinctrl-names = "default", "sleep";
 361                         pinctrl-0 = <&blsp1_spi0_default>;
 362                         pinctrl-1 = <&blsp1_spi0_sleep>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         status = "disabled";
 366                 };
 367
 368                 blsp_i2c2: i2c@f9924000 {
 369                         compatible = "qcom,i2c-qup-v2.2.1";
 370                         reg = <0xf9924000 0x500>;
 371                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 373                                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 374                         clock-names = "iface", "core";
 375                         clock-frequency = <355000>;
 376                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
 377                         dma-names = "tx", "rx";
 378                         pinctrl-names = "default", "sleep";
 379                         pinctrl-0 = <&i2c2_default>;
 380                         pinctrl-1 = <&i2c2_sleep>;
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         status = "disabled";
 384                 };
 385
 386                 /* I2C3 doesn't exist */
 387
 388                 blsp_i2c4: i2c@f9926000 {
 389                         compatible = "qcom,i2c-qup-v2.2.1";
 390                         reg = <0xf9926000 0x500>;
 391                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 393                                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 394                         clock-names = "iface", "core";
 395                         clock-frequency = <355000>;
 396                         pinctrl-names = "default", "sleep";
 397                         pinctrl-0 = <&i2c4_default>;
 398                         pinctrl-1 = <&i2c4_sleep>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         status = "disabled";
 402                 };
 403
 404                 blsp2_dma: dma@f9944000 {
 405                         compatible = "qcom,bam-v1.7.0";
 406                         reg = <0xf9944000 0x19000>;
 407                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 409                         clock-names = "bam_clk";
 410                         #dma-cells = <1>;
 411                         qcom,ee = <0>;
 412                         qcom,controlled-remotely;
 413                         num-channels = <18>;
 414                         qcom,num-ees = <4>;
 415                 };
 416
 417                 /* According to downstream kernels, i2c6
 418                  * comes before i2c5 address-wise...
 419                  */
 420
 421                 blsp_i2c6: i2c@f9928000 {
 422                         compatible = "qcom,i2c-qup-v2.2.1";
 423                         reg = <0xf9928000 0x500>;
 424                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 425                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 426                                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 427                         clock-names = "iface", "core";
 428                         clock-frequency = <355000>;
 429                         dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
 430                         dma-names = "tx", "rx";
 431                         pinctrl-names = "default", "sleep";
 432                         pinctrl-0 = <&i2c6_default>;
 433                         pinctrl-1 = <&i2c6_sleep>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         status = "disabled";
 437                 };
 438
 439                 blsp2_uart2: serial@f995e000 {
 440                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 441                         reg = <0xf995e000 0x1000>;
 442                         interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
 443                         clock-names = "core", "iface";
 444                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 445                                         <&gcc GCC_BLSP2_AHB_CLK>;
 446                         dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
 447                         dma-names = "tx", "rx";
 448                         pinctrl-names = "default", "sleep";
 449                         pinctrl-0 = <&blsp2_uart2_default>;
 450                         pinctrl-1 = <&blsp2_uart2_sleep>;
 451                         status = "disabled";
 452                 };
 453
 454                 blsp_i2c5: i2c@f9967000 {
 455                         compatible = "qcom,i2c-qup-v2.2.1";
 456                         reg = <0xf9967000 0x500>;
 457                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 458                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 459                                                 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
 460                         clock-names = "iface", "core";
 461                         clock-frequency = <355000>;
 462                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 463                         dma-names = "tx", "rx";
 464                         pinctrl-names = "default", "sleep";
 465                         pinctrl-0 = <&i2c5_default>;
 466                         pinctrl-1 = <&i2c5_sleep>;
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         status = "disabled";
 470                 };
 471
 472                 gcc: clock-controller@fc400000 {
 473                         compatible = "qcom,gcc-msm8994";
 474                         #clock-cells = <1>;
 475                         #reset-cells = <1>;
 476                         #power-domain-cells = <1>;
 477                         reg = <0xfc400000 0x2000>;
 478                 };
 479
 480                 rpm_msg_ram: memory@fc428000 {
 481                         compatible = "qcom,rpm-msg-ram";
 482                         reg = <0xfc428000 0x4000>;
 483                 };
 484
 485                 restart@fc4ab000 {
 486                         compatible = "qcom,pshold";
 487                         reg = <0xfc4ab000 0x4>;
 488                 };
 489
 490                 spmi_bus: spmi@fc4c0000 {
 491                         compatible = "qcom,spmi-pmic-arb";
 492                         reg = <0xfc4cf000 0x1000>,
 493                               <0xfc4cb000 0x1000>,
 494                               <0xfc4ca000 0x1000>;
 495                         reg-names = "core", "intr", "cnfg";
 496                         interrupt-names = "periph_irq";
 497                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 498                         qcom,ee = <0>;
 499                         qcom,channel = <0>;
 500                         #address-cells = <2>;
 501                         #size-cells = <0>;
 502                         interrupt-controller;
 503                         #interrupt-cells = <4>;
 504                 };
 505
 506                 tcsr_mutex_regs: syscon@fd484000 {
 507                         compatible = "syscon";
 508                         reg = <0xfd484000 0x2000>;
 509                 };
 510
 511                 tlmm: pinctrl@fd510000 {
 512                         compatible = "qcom,msm8994-pinctrl";
 513                         reg = <0xfd510000 0x4000>;
 514                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 515                         gpio-controller;
 516                         gpio-ranges = <&tlmm 0 0 146>;
 517                         #gpio-cells = <2>;
 518                         interrupt-controller;
 519                         #interrupt-cells = <2>;
 520
 521                         blsp1_uart2_default: blsp1-uart2-default {
 522                                 function = "blsp_uart2";
 523                                 pins = "gpio4", "gpio5";
 524                                 drive-strength = <16>;
 525                                 bias-disable;
 526                         };
 527
 528                         blsp1_uart2_sleep: blsp1-uart2-sleep {
 529                                 function = "gpio";
 530                                 pins = "gpio4", "gpio5";
 531                                 drive-strength = <2>;
 532                                 bias-pull-down;
 533                         };
 534
 535                         blsp2_uart2_default: blsp2-uart2-default {
 536                                 function = "blsp_uart8";
 537                                 pins = "gpio45", "gpio46";
 538                                 drive-strength = <2>;
 539                                 bias-disable;
 540                         };
 541
 542                         blsp2_uart2_sleep: blsp2-uart2-sleep {
 543                                 function = "gpio";
 544                                 pins = "gpio45", "gpio46";
 545                                 drive-strength = <2>;
 546                                 bias-pull-down;
 547                         };
 548
 549                         i2c1_default: i2c1-default {
 550                                 function = "blsp_i2c1";
 551                                 pins = "gpio2", "gpio3";
 552                                 drive-strength = <2>;
 553                                 bias-disable;
 554                         };
 555
 556                         i2c1_sleep: i2c1-sleep {
 557                                 function = "gpio";
 558                                 pins = "gpio2", "gpio3";
 559                                 drive-strength = <2>;
 560                                 bias-disable;
 561                         };
 562
 563                         i2c2_default: i2c2-default {
 564                                 function = "blsp_i2c2";
 565                                 pins = "gpio6", "gpio7";
 566                                 drive-strength = <2>;
 567                                 bias-disable;
 568                         };
 569
 570                         i2c2_sleep: i2c2-sleep {
 571                                 function = "gpio";
 572                                 pins = "gpio6", "gpio7";
 573                                 drive-strength = <2>;
 574                                 bias-disable;
 575                         };
 576
 577                         i2c4_default: i2c4-default {
 578                                 function = "blsp_i2c4";
 579                                 pins = "gpio19", "gpio20";
 580                                 drive-strength = <2>;
 581                                 bias-disable;
 582                         };
 583
 584                         i2c4_sleep: i2c4-sleep {
 585                                 function = "gpio";
 586                                 pins = "gpio19", "gpio20";
 587                                 drive-strength = <2>;
 588                                 bias-pull-down;
 589                                 input-enable;
 590                         };
 591
 592                         i2c5_default: i2c5-default {
 593                                 function = "blsp_i2c5";
 594                                 pins = "gpio23", "gpio24";
 595                                 drive-strength = <2>;
 596                                 bias-disable;
 597                         };
 598
 599                         i2c5_sleep: i2c5-sleep {
 600                                 function = "gpio";
 601                                 pins = "gpio23", "gpio24";
 602                                 drive-strength = <2>;
 603                                 bias-disable;
 604                         };
 605
 606                         i2c6_default: i2c6-default {
 607                                 function = "blsp_i2c6";
 608                                 pins = "gpio28", "gpio27";
 609                                 drive-strength = <2>;
 610                                 bias-disable;
 611                         };
 612
 613                         i2c6_sleep: i2c6-sleep {
 614                                 function = "gpio";
 615                                 pins = "gpio28", "gpio27";
 616                                 drive-strength = <2>;
 617                                 bias-disable;
 618                         };
 619
 620                         blsp1_spi0_default: blsp1-spi0-default {
 621                                 default {
 622                                         function = "blsp_spi1";
 623                                         pins = "gpio0", "gpio1", "gpio3";
 624                                         drive-strength = <10>;
 625                                         bias-pull-down;
 626                                 };
 627                                 cs {
 628                                         function = "gpio";
 629                                         pins = "gpio8";
 630                                         drive-strength = <2>;
 631                                         bias-disable;
 632                                 };
 633                         };
 634
 635                         blsp1_spi0_sleep: blsp1-spi0-sleep {
 636                                 pins = "gpio0", "gpio1", "gpio3";
 637                                 drive-strength = <2>;
 638                                 bias-disable;
 639                         };
 640
 641                         sdc1_clk_on: clk-on {
 642                                 pins = "sdc1_clk";
 643                                 bias-disable;
 644                                 drive-strength = <16>;
 645                         };
 646
 647                         sdc1_clk_off: clk-off {
 648                                 pins = "sdc1_clk";
 649                                 bias-disable;
 650                                 drive-strength = <2>;
 651                         };
 652
 653                         sdc1_cmd_on: cmd-on {
 654                                 pins = "sdc1_cmd";
 655                                 bias-pull-up;
 656                                 drive-strength = <8>;
 657                         };
 658
 659                         sdc1_cmd_off: cmd-off {
 660                                 pins = "sdc1_cmd";
 661                                 bias-pull-up;
 662                                 drive-strength = <2>;
 663                         };
 664
 665                         sdc1_data_on: data-on {
 666                                 pins = "sdc1_data";
 667                                 bias-pull-up;
 668                                 drive-strength = <8>;
 669                         };
 670
 671                         sdc1_data_off: data-off {
 672                                 pins = "sdc1_data";
 673                                 bias-pull-up;
 674                                 drive-strength = <2>;
 675                         };
 676
 677                         sdc1_rclk_on: rclk-on {
 678                                 pins = "sdc1_rclk";
 679                                 bias-pull-down;
 680                         };
 681
 682                         sdc1_rclk_off: rclk-off {
 683                                 pins = "sdc1_rclk";
 684                                 bias-pull-down;
 685                         };
 686                 };
 687         };
 688
 689         tcsr_mutex: hwlock {
 690                 compatible = "qcom,tcsr-mutex";
 691                 syscon = <&tcsr_mutex_regs 0 0x80>;
 692                 #hwlock-cells = <1>;
 693         };
 694
 695         timer {
 696                 compatible = "arm,armv8-timer";
 697                 interrupts = <GIC_PPI 2 0xff08>,
 698                              <GIC_PPI 3 0xff08>,
 699                              <GIC_PPI 4 0xff08>,
 700                              <GIC_PPI 1 0xff08>;
 701         };
 702
 703         vreg_vph_pwr: vreg-vph-pwr {
 704                 compatible = "regulator-fixed";
 705                 regulator-name = "vph-pwr";
 706
 707                 regulator-min-microvolt = <3600000>;
 708                 regulator-max-microvolt = <3600000>;
 709
 710                 regulator-always-on;
 711         };
 712 };
 713