1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
10 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
21 clock-frequency = <19200000>;
24 sleep_clk: sleep_clk {
25 compatible = "fixed-clock";
27 clock-frequency = <32768>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
52 next-level-cache = <&L2_0>;
57 compatible = "arm,cortex-a53";
59 enable-method = "psci";
60 next-level-cache = <&L2_0>;
65 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 next-level-cache = <&L2_0>;
73 compatible = "arm,cortex-a57";
75 enable-method = "psci";
76 next-level-cache = <&L2_1>;
85 compatible = "arm,cortex-a57";
87 enable-method = "psci";
88 next-level-cache = <&L2_1>;
93 compatible = "arm,cortex-a57";
95 enable-method = "psci";
96 next-level-cache = <&L2_1>;
101 compatible = "arm,cortex-a57";
103 enable-method = "psci";
104 next-level-cache = <&L2_1>;
148 compatible = "qcom,scm-msm8994", "qcom,scm";
153 device_type = "memory";
154 /* We expect the bootloader to fill in the reg */
155 reg = <0 0x80000000 0 0>;
159 compatible = "qcom,tcsr-mutex";
160 syscon = <&tcsr_mutex_regs 0 0x80>;
165 compatible = "arm,cortex-a53-pmu";
166 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
170 compatible = "arm,psci-0.2";
175 #address-cells = <2>;
179 dfps_data_mem: dfps_data_mem@3400000 {
180 reg = <0 0x03400000 0 0x1000>;
184 cont_splash_mem: memory@3800000 {
185 reg = <0 0x03800000 0 0x2400000>;
189 smem_mem: smem_region@6a00000 {
190 reg = <0 0x06a00000 0 0x200000>;
194 mpss_mem: memory@7000000 {
195 reg = <0 0x07000000 0 0x5a00000>;
199 peripheral_region: memory@ca00000 {
200 reg = <0 0x0ca00000 0 0x1f00000>;
204 rmtfs_mem: memory@c6400000 {
205 compatible = "qcom,rmtfs-mem";
206 reg = <0 0xc6400000 0 0x180000>;
209 qcom,client-id = <1>;
212 mba_mem: memory@c6700000 {
213 reg = <0 0xc6700000 0 0x100000>;
217 audio_mem: memory@c7000000 {
218 reg = <0 0xc7000000 0 0x800000>;
222 adsp_mem: memory@c9400000 {
223 reg = <0 0xc9400000 0 0x3f00000>;
229 compatible = "qcom,smd";
231 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
232 qcom,ipc = <&apcs 8 0>;
233 qcom,smd-edge = <15>;
234 qcom,local-pid = <0>;
235 qcom,remote-pid = <6>;
237 rpm_requests: rpm-requests {
238 compatible = "qcom,rpm-msm8994";
239 qcom,smd-channels = "rpm_requests";
242 compatible = "qcom,rpmcc-msm8994";
246 rpmpd: power-controller {
247 compatible = "qcom,msm8994-rpmpd";
248 #power-domain-cells = <1>;
249 operating-points-v2 = <&rpmpd_opp_table>;
251 rpmpd_opp_table: opp-table {
252 compatible = "operating-points-v2";
254 rpmpd_opp_ret: opp1 {
257 rpmpd_opp_svs_krait: opp2 {
260 rpmpd_opp_svs_soc: opp3 {
263 rpmpd_opp_nom: opp4 {
266 rpmpd_opp_turbo: opp5 {
269 rpmpd_opp_super_turbo: opp6 {
279 compatible = "qcom,smem";
280 memory-region = <&smem_mem>;
281 qcom,rpm-msg-ram = <&rpm_msg_ram>;
282 hwlocks = <&tcsr_mutex 3>;
286 compatible = "qcom,smp2p";
287 qcom,smem = <443>, <429>;
289 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
291 qcom,ipc = <&apcs 8 10>;
293 qcom,local-pid = <0>;
294 qcom,remote-pid = <2>;
296 adsp_smp2p_out: master-kernel {
297 qcom,entry-name = "master-kernel";
298 #qcom,smem-state-cells = <1>;
301 adsp_smp2p_in: slave-kernel {
302 qcom,entry-name = "slave-kernel";
304 interrupt-controller;
305 #interrupt-cells = <2>;
310 compatible = "qcom,smp2p";
311 qcom,smem = <435>, <428>;
313 interrupt-parent = <&intc>;
314 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
316 qcom,ipc = <&apcs 8 14>;
318 qcom,local-pid = <0>;
319 qcom,remote-pid = <1>;
321 modem_smp2p_out: master-kernel {
322 qcom,entry-name = "master-kernel";
323 #qcom,smem-state-cells = <1>;
326 modem_smp2p_in: slave-kernel {
327 qcom,entry-name = "slave-kernel";
329 interrupt-controller;
330 #interrupt-cells = <2>;
336 #address-cells = <1>;
338 ranges = <0 0 0 0xffffffff>;
339 compatible = "simple-bus";
341 intc: interrupt-controller@f9000000 {
342 compatible = "qcom,msm-qgic2";
343 interrupt-controller;
344 #interrupt-cells = <3>;
345 reg = <0xf9000000 0x1000>,
349 apcs: mailbox@f900d000 {
350 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
351 reg = <0xf900d000 0x2000>;
356 #address-cells = <1>;
359 compatible = "arm,armv7-timer-mem";
360 reg = <0xf9020000 0x1000>;
364 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
366 reg = <0xf9021000 0x1000>,
372 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
373 reg = <0xf9023000 0x1000>;
379 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
380 reg = <0xf9024000 0x1000>;
386 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
387 reg = <0xf9025000 0x1000>;
393 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
394 reg = <0xf9026000 0x1000>;
400 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
401 reg = <0xf9027000 0x1000>;
407 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
408 reg = <0xf9028000 0x1000>;
414 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
415 reg = <0xf92f8800 0x400>;
416 #address-cells = <1>;
420 clocks = <&gcc GCC_USB30_MASTER_CLK>,
421 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
422 <&gcc GCC_USB30_SLEEP_CLK>,
423 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
424 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
426 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
427 <&gcc GCC_USB30_MASTER_CLK>;
428 assigned-clock-rates = <19200000>, <120000000>;
430 power-domains = <&gcc USB30_GDSC>;
431 qcom,select-utmi-as-pipe-clk;
434 compatible = "snps,dwc3";
435 reg = <0xf9200000 0xcc00>;
436 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
437 snps,dis_u2_susphy_quirk;
438 snps,dis_enblslpm_quirk;
439 maximum-speed = "high-speed";
440 dr_mode = "peripheral";
444 sdhc1: sdhci@f9824900 {
445 compatible = "qcom,sdhci-msm-v4";
446 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
447 reg-names = "hc_mem", "core_mem";
449 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-names = "hc_irq", "pwr_irq";
453 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
454 <&gcc GCC_SDCC1_AHB_CLK>,
456 clock-names = "core", "iface", "xo";
458 pinctrl-names = "default", "sleep";
459 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
460 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
467 sdhc2: sdhci@f98a4900 {
468 compatible = "qcom,sdhci-msm-v4";
469 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
470 reg-names = "hc_mem", "core_mem";
472 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_irq", "pwr_irq";
476 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
477 <&gcc GCC_SDCC2_AHB_CLK>,
479 clock-names = "core", "iface", "xo";
481 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
483 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
485 cd-gpios = <&tlmm 100 0>;
490 blsp1_dma: dma-controller@f9904000 {
491 compatible = "qcom,bam-v1.7.0";
492 reg = <0xf9904000 0x19000>;
493 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
495 clock-names = "bam_clk";
498 qcom,controlled-remotely;
503 blsp1_uart2: serial@f991e000 {
504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
505 reg = <0xf991e000 0x1000>;
506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
507 clock-names = "core", "iface";
508 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
509 <&gcc GCC_BLSP1_AHB_CLK>;
510 pinctrl-names = "default", "sleep";
511 pinctrl-0 = <&blsp1_uart2_default>;
512 pinctrl-1 = <&blsp1_uart2_sleep>;
516 blsp1_i2c1: i2c@f9923000 {
517 compatible = "qcom,i2c-qup-v2.2.1";
518 reg = <0xf9923000 0x500>;
519 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
521 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
522 clock-names = "iface", "core";
523 clock-frequency = <400000>;
524 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
525 dma-names = "tx", "rx";
526 pinctrl-names = "default", "sleep";
527 pinctrl-0 = <&i2c1_default>;
528 pinctrl-1 = <&i2c1_sleep>;
529 #address-cells = <1>;
534 blsp1_spi1: spi@f9923000 {
535 compatible = "qcom,spi-qup-v2.2.1";
536 reg = <0xf9923000 0x500>;
537 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
539 <&gcc GCC_BLSP1_AHB_CLK>;
540 clock-names = "core", "iface";
541 spi-max-frequency = <19200000>;
542 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
543 dma-names = "tx", "rx";
544 pinctrl-names = "default", "sleep";
545 pinctrl-0 = <&blsp1_spi1_default>;
546 pinctrl-1 = <&blsp1_spi1_sleep>;
547 #address-cells = <1>;
552 blsp1_i2c2: i2c@f9924000 {
553 compatible = "qcom,i2c-qup-v2.2.1";
554 reg = <0xf9924000 0x500>;
555 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
557 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
558 clock-names = "iface", "core";
559 clock-frequency = <400000>;
560 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
561 dma-names = "tx", "rx";
562 pinctrl-names = "default", "sleep";
563 pinctrl-0 = <&i2c2_default>;
564 pinctrl-1 = <&i2c2_sleep>;
565 #address-cells = <1>;
570 /* I2C3 doesn't exist */
572 blsp1_i2c4: i2c@f9926000 {
573 compatible = "qcom,i2c-qup-v2.2.1";
574 reg = <0xf9926000 0x500>;
575 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
577 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
578 clock-names = "iface", "core";
579 clock-frequency = <400000>;
580 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
581 dma-names = "tx", "rx";
582 pinctrl-names = "default", "sleep";
583 pinctrl-0 = <&i2c4_default>;
584 pinctrl-1 = <&i2c4_sleep>;
585 #address-cells = <1>;
590 blsp1_i2c5: i2c@f9927000 {
591 compatible = "qcom,i2c-qup-v2.2.1";
592 reg = <0xf9927000 0x500>;
593 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
595 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
596 clock-names = "iface", "core";
597 clock-frequency = <400000>;
598 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
599 dma-names = "tx", "rx";
600 pinctrl-names = "default", "sleep";
601 pinctrl-0 = <&i2c5_default>;
602 pinctrl-1 = <&i2c5_sleep>;
603 #address-cells = <1>;
608 blsp1_i2c6: i2c@f9928000 {
609 compatible = "qcom,i2c-qup-v2.2.1";
610 reg = <0xf9928000 0x500>;
611 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
613 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
614 clock-names = "iface", "core";
615 clock-frequency = <400000>;
616 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
617 dma-names = "tx", "rx";
618 pinctrl-names = "default", "sleep";
619 pinctrl-0 = <&i2c6_default>;
620 pinctrl-1 = <&i2c6_sleep>;
621 #address-cells = <1>;
626 blsp2_dma: dma-controller@f9944000 {
627 compatible = "qcom,bam-v1.7.0";
628 reg = <0xf9944000 0x19000>;
629 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
631 clock-names = "bam_clk";
634 qcom,controlled-remotely;
639 blsp2_uart2: serial@f995e000 {
640 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
641 reg = <0xf995e000 0x1000>;
642 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
643 clock-names = "core", "iface";
644 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
645 <&gcc GCC_BLSP2_AHB_CLK>;
646 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
647 dma-names = "tx", "rx";
648 pinctrl-names = "default", "sleep";
649 pinctrl-0 = <&blsp2_uart2_default>;
650 pinctrl-1 = <&blsp2_uart2_sleep>;
654 blsp2_i2c1: i2c@f9963000 {
655 compatible = "qcom,i2c-qup-v2.2.1";
656 reg = <0xf9963000 0x500>;
657 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
659 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
660 clock-names = "iface", "core";
661 clock-frequency = <400000>;
662 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
663 dma-names = "tx", "rx";
664 pinctrl-names = "default", "sleep";
665 pinctrl-0 = <&i2c7_default>;
666 pinctrl-1 = <&i2c7_sleep>;
667 #address-cells = <1>;
672 blsp2_spi4: spi@f9966000 {
673 compatible = "qcom,spi-qup-v2.2.1";
674 reg = <0xf9966000 0x500>;
675 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
677 <&gcc GCC_BLSP2_AHB_CLK>;
678 clock-names = "core", "iface";
679 spi-max-frequency = <19200000>;
680 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
681 dma-names = "tx", "rx";
682 pinctrl-names = "default", "sleep";
683 pinctrl-0 = <&blsp2_spi10_default>;
684 pinctrl-1 = <&blsp2_spi10_sleep>;
685 #address-cells = <1>;
690 blsp2_i2c5: i2c@f9967000 {
691 compatible = "qcom,i2c-qup-v2.2.1";
692 reg = <0xf9967000 0x500>;
693 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
695 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
696 clock-names = "iface", "core";
697 clock-frequency = <355000>;
698 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
699 dma-names = "tx", "rx";
700 pinctrl-names = "default", "sleep";
701 pinctrl-0 = <&i2c11_default>;
702 pinctrl-1 = <&i2c11_sleep>;
703 #address-cells = <1>;
708 gcc: clock-controller@fc400000 {
709 compatible = "qcom,gcc-msm8994";
712 #power-domain-cells = <1>;
713 reg = <0xfc400000 0x2000>;
716 rpm_msg_ram: memory@fc428000 {
717 compatible = "qcom,rpm-msg-ram";
718 reg = <0xfc428000 0x4000>;
722 compatible = "qcom,pshold";
723 reg = <0xfc4ab000 0x4>;
726 spmi_bus: spmi@fc4c0000 {
727 compatible = "qcom,spmi-pmic-arb";
728 reg = <0xfc4cf000 0x1000>,
731 reg-names = "core", "intr", "cnfg";
732 interrupt-names = "periph_irq";
733 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
736 #address-cells = <2>;
738 interrupt-controller;
739 #interrupt-cells = <4>;
742 tcsr_mutex_regs: syscon@fd484000 {
743 compatible = "syscon";
744 reg = <0xfd484000 0x2000>;
747 tlmm: pinctrl@fd510000 {
748 compatible = "qcom,msm8994-pinctrl";
749 reg = <0xfd510000 0x4000>;
750 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
752 gpio-ranges = <&tlmm 0 0 146>;
754 interrupt-controller;
755 #interrupt-cells = <2>;
757 blsp1_uart2_default: blsp1-uart2-default {
758 function = "blsp_uart2";
759 pins = "gpio4", "gpio5";
760 drive-strength = <16>;
764 blsp1_uart2_sleep: blsp1-uart2-sleep {
766 pins = "gpio4", "gpio5";
767 drive-strength = <2>;
771 blsp2_uart2_default: blsp2-uart2-default {
772 function = "blsp_uart8";
773 pins = "gpio45", "gpio46",
775 drive-strength = <16>;
779 blsp2_uart2_sleep: blsp2-uart2-sleep {
781 pins = "gpio45", "gpio46",
783 drive-strength = <2>;
787 i2c1_default: i2c1-default {
788 function = "blsp_i2c1";
789 pins = "gpio2", "gpio3";
790 drive-strength = <2>;
794 i2c1_sleep: i2c1-sleep {
796 pins = "gpio2", "gpio3";
797 drive-strength = <2>;
801 i2c2_default: i2c2-default {
802 function = "blsp_i2c2";
803 pins = "gpio6", "gpio7";
804 drive-strength = <2>;
808 i2c2_sleep: i2c2-sleep {
810 pins = "gpio6", "gpio7";
811 drive-strength = <2>;
815 i2c4_default: i2c4-default {
816 function = "blsp_i2c4";
817 pins = "gpio19", "gpio20";
818 drive-strength = <2>;
822 i2c4_sleep: i2c4-sleep {
824 pins = "gpio19", "gpio20";
825 drive-strength = <2>;
830 i2c5_default: i2c5-default {
831 function = "blsp_i2c5";
832 pins = "gpio23", "gpio24";
833 drive-strength = <2>;
837 i2c5_sleep: i2c5-sleep {
839 pins = "gpio23", "gpio24";
840 drive-strength = <2>;
844 i2c6_default: i2c6-default {
845 function = "blsp_i2c6";
846 pins = "gpio28", "gpio27";
847 drive-strength = <2>;
851 i2c6_sleep: i2c6-sleep {
853 pins = "gpio28", "gpio27";
854 drive-strength = <2>;
858 i2c7_default: i2c7-default {
859 function = "blsp_i2c7";
860 pins = "gpio44", "gpio43";
861 drive-strength = <2>;
865 i2c7_sleep: i2c7-sleep {
867 pins = "gpio44", "gpio43";
868 drive-strength = <2>;
872 blsp2_spi10_default: blsp2-spi10-default {
874 function = "blsp_spi10";
875 pins = "gpio53", "gpio54", "gpio55";
876 drive-strength = <10>;
882 drive-strength = <2>;
887 blsp2_spi10_sleep: blsp2-spi10-sleep {
888 pins = "gpio53", "gpio54", "gpio55";
889 drive-strength = <2>;
893 i2c11_default: i2c11-default {
894 function = "blsp_i2c11";
895 pins = "gpio83", "gpio84";
896 drive-strength = <2>;
900 i2c11_sleep: i2c11-sleep {
902 pins = "gpio83", "gpio84";
903 drive-strength = <2>;
907 blsp1_spi1_default: blsp1-spi1-default {
909 function = "blsp_spi1";
910 pins = "gpio0", "gpio1", "gpio3";
911 drive-strength = <10>;
917 drive-strength = <2>;
922 blsp1_spi1_sleep: blsp1-spi1-sleep {
923 pins = "gpio0", "gpio1", "gpio3";
924 drive-strength = <2>;
928 sdc1_clk_on: clk-on {
931 drive-strength = <16>;
934 sdc1_clk_off: clk-off {
937 drive-strength = <2>;
940 sdc1_cmd_on: cmd-on {
943 drive-strength = <8>;
946 sdc1_cmd_off: cmd-off {
949 drive-strength = <2>;
952 sdc1_data_on: data-on {
955 drive-strength = <8>;
958 sdc1_data_off: data-off {
961 drive-strength = <2>;
964 sdc1_rclk_on: rclk-on {
969 sdc1_rclk_off: rclk-off {
974 sdc2_clk_on: sdc2-clk-on {
977 drive-strength = <10>;
980 sdc2_clk_off: sdc2-clk-off {
983 drive-strength = <2>;
986 sdc2_cmd_on: sdc2-cmd-on {
989 drive-strength = <10>;
992 sdc2_cmd_off: sdc2-cmd-off {
995 drive-strength = <2>;
998 sdc2_data_on: sdc2-data-on {
1001 drive-strength = <10>;
1004 sdc2_data_off: sdc2-data-off {
1007 drive-strength = <2>;
1013 compatible = "arm,armv8-timer";
1014 interrupts = <GIC_PPI 2 0xff08>,
1020 vph_pwr: vph-pwr-regulator {
1021 compatible = "regulator-fixed";
1022 regulator-name = "vph_pwr";
1024 regulator-min-microvolt = <3600000>;
1025 regulator-max-microvolt = <3600000>;
1027 regulator-always-on;