1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
9 interrupt-parent = <&intc>;
18 compatible = "fixed-clock";
20 clock-frequency = <19200000>;
23 sleep_clk: sleep_clk {
24 compatible = "fixed-clock";
26 clock-frequency = <32768>;
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 next-level-cache = <&L2_0>;
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
64 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
72 compatible = "arm,cortex-a57";
74 enable-method = "psci";
75 next-level-cache = <&L2_1>;
84 compatible = "arm,cortex-a57";
86 enable-method = "psci";
87 next-level-cache = <&L2_1>;
92 compatible = "arm,cortex-a57";
94 enable-method = "psci";
95 next-level-cache = <&L2_1>;
100 compatible = "arm,cortex-a57";
102 enable-method = "psci";
103 next-level-cache = <&L2_1>;
147 compatible = "qcom,scm-msm8994", "qcom,scm";
152 device_type = "memory";
153 /* We expect the bootloader to fill in the reg */
158 compatible = "arm,cortex-a53-pmu";
159 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
163 compatible = "arm,psci-0.2";
168 #address-cells = <2>;
172 smem_mem: smem_region@6a00000 {
173 reg = <0x0 0x6a00000 0x0 0x200000>;
179 compatible = "qcom,smd";
181 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
182 qcom,ipc = <&apcs 8 0>;
183 qcom,smd-edge = <15>;
184 qcom,local-pid = <0>;
185 qcom,remote-pid = <6>;
187 rpm_requests: rpm-requests {
188 compatible = "qcom,rpm-msm8994";
189 qcom,smd-channels = "rpm_requests";
192 compatible = "qcom,rpmcc-msm8994";
200 compatible = "qcom,smem";
201 memory-region = <&smem_mem>;
202 qcom,rpm-msg-ram = <&rpm_msg_ram>;
203 hwlocks = <&tcsr_mutex 3>;
208 #address-cells = <1>;
210 ranges = <0 0 0 0xffffffff>;
211 compatible = "simple-bus";
213 intc: interrupt-controller@f9000000 {
214 compatible = "qcom,msm-qgic2";
215 interrupt-controller;
216 #interrupt-cells = <3>;
217 reg = <0xf9000000 0x1000>,
221 apcs: mailbox@f900d000 {
222 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
223 reg = <0xf900d000 0x2000>;
228 #address-cells = <1>;
231 compatible = "arm,armv7-timer-mem";
232 reg = <0xf9020000 0x1000>;
236 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0xf9021000 0x1000>,
244 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
245 reg = <0xf9023000 0x1000>;
251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
252 reg = <0xf9024000 0x1000>;
258 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
259 reg = <0xf9025000 0x1000>;
265 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
266 reg = <0xf9026000 0x1000>;
272 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
273 reg = <0xf9027000 0x1000>;
279 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
280 reg = <0xf9028000 0x1000>;
286 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
287 reg = <0xf92f8800 0x400>;
288 #address-cells = <1>;
292 clocks = <&gcc GCC_USB30_MASTER_CLK>,
293 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
294 <&gcc GCC_USB30_SLEEP_CLK>,
295 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
296 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
298 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
299 <&gcc GCC_USB30_MASTER_CLK>;
300 assigned-clock-rates = <19200000>, <120000000>;
302 power-domains = <&gcc USB30_GDSC>;
303 qcom,select-utmi-as-pipe-clk;
306 compatible = "snps,dwc3";
307 reg = <0xf9200000 0xcc00>;
308 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
309 snps,dis_u2_susphy_quirk;
310 snps,dis_enblslpm_quirk;
311 maximum-speed = "high-speed";
312 dr_mode = "peripheral";
316 sdhc1: sdhci@f9824900 {
317 compatible = "qcom,sdhci-msm-v4";
318 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
319 reg-names = "hc_mem", "core_mem";
321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
323 interrupt-names = "hc_irq", "pwr_irq";
325 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
326 <&gcc GCC_SDCC1_AHB_CLK>,
328 clock-names = "core", "iface", "xo";
330 pinctrl-names = "default", "sleep";
331 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
332 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
339 sdhc2: sdhci@f98a4900 {
340 compatible = "qcom,sdhci-msm-v4";
341 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
342 reg-names = "hc_mem", "core_mem";
344 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "hc_irq", "pwr_irq";
348 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
349 <&gcc GCC_SDCC2_AHB_CLK>,
351 clock-names = "core", "iface", "xo";
353 pinctrl-names = "default", "sleep";
354 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
355 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
357 cd-gpios = <&tlmm 100 0>;
362 blsp1_dma: dma-controller@f9904000 {
363 compatible = "qcom,bam-v1.7.0";
364 reg = <0xf9904000 0x19000>;
365 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
367 clock-names = "bam_clk";
370 qcom,controlled-remotely;
375 blsp1_uart2: serial@f991e000 {
376 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
377 reg = <0xf991e000 0x1000>;
378 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
379 clock-names = "core", "iface";
380 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
381 <&gcc GCC_BLSP1_AHB_CLK>;
382 pinctrl-names = "default", "sleep";
383 pinctrl-0 = <&blsp1_uart2_default>;
384 pinctrl-1 = <&blsp1_uart2_sleep>;
388 blsp_i2c1: i2c@f9923000 {
389 compatible = "qcom,i2c-qup-v2.2.1";
390 reg = <0xf9923000 0x500>;
391 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
393 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
394 clock-names = "iface", "core";
395 clock-frequency = <400000>;
396 pinctrl-names = "default", "sleep";
397 pinctrl-0 = <&i2c1_default>;
398 pinctrl-1 = <&i2c1_sleep>;
399 #address-cells = <1>;
404 blsp_spi0: spi@f9923000 {
405 compatible = "qcom,spi-qup-v2.2.1";
406 reg = <0xf9923000 0x500>;
407 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
409 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", "iface";
411 spi-max-frequency = <19200000>;
412 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
413 dma-names = "tx", "rx";
414 pinctrl-names = "default", "sleep";
415 pinctrl-0 = <&blsp1_spi0_default>;
416 pinctrl-1 = <&blsp1_spi0_sleep>;
417 #address-cells = <1>;
422 blsp_i2c2: i2c@f9924000 {
423 compatible = "qcom,i2c-qup-v2.2.1";
424 reg = <0xf9924000 0x500>;
425 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
427 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
428 clock-names = "iface", "core";
429 clock-frequency = <355000>;
430 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
431 dma-names = "tx", "rx";
432 pinctrl-names = "default", "sleep";
433 pinctrl-0 = <&i2c2_default>;
434 pinctrl-1 = <&i2c2_sleep>;
435 #address-cells = <1>;
440 /* I2C3 doesn't exist */
442 blsp_i2c4: i2c@f9926000 {
443 compatible = "qcom,i2c-qup-v2.2.1";
444 reg = <0xf9926000 0x500>;
445 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
447 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
448 clock-names = "iface", "core";
449 clock-frequency = <355000>;
450 pinctrl-names = "default", "sleep";
451 pinctrl-0 = <&i2c4_default>;
452 pinctrl-1 = <&i2c4_sleep>;
453 #address-cells = <1>;
458 blsp2_dma: dma-controller@f9944000 {
459 compatible = "qcom,bam-v1.7.0";
460 reg = <0xf9944000 0x19000>;
461 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
463 clock-names = "bam_clk";
466 qcom,controlled-remotely;
471 /* According to downstream kernels, i2c6
472 * comes before i2c5 address-wise...
475 blsp_i2c6: i2c@f9928000 {
476 compatible = "qcom,i2c-qup-v2.2.1";
477 reg = <0xf9928000 0x500>;
478 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
480 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
481 clock-names = "iface", "core";
482 clock-frequency = <355000>;
483 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
484 dma-names = "tx", "rx";
485 pinctrl-names = "default", "sleep";
486 pinctrl-0 = <&i2c6_default>;
487 pinctrl-1 = <&i2c6_sleep>;
488 #address-cells = <1>;
493 blsp2_uart2: serial@f995e000 {
494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
495 reg = <0xf995e000 0x1000>;
496 interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
497 clock-names = "core", "iface";
498 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
499 <&gcc GCC_BLSP2_AHB_CLK>;
500 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
501 dma-names = "tx", "rx";
502 pinctrl-names = "default", "sleep";
503 pinctrl-0 = <&blsp2_uart2_default>;
504 pinctrl-1 = <&blsp2_uart2_sleep>;
508 blsp_i2c5: i2c@f9967000 {
509 compatible = "qcom,i2c-qup-v2.2.1";
510 reg = <0xf9967000 0x500>;
511 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
513 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
514 clock-names = "iface", "core";
515 clock-frequency = <355000>;
516 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
517 dma-names = "tx", "rx";
518 pinctrl-names = "default", "sleep";
519 pinctrl-0 = <&i2c5_default>;
520 pinctrl-1 = <&i2c5_sleep>;
521 #address-cells = <1>;
526 gcc: clock-controller@fc400000 {
527 compatible = "qcom,gcc-msm8994";
530 #power-domain-cells = <1>;
531 reg = <0xfc400000 0x2000>;
534 rpm_msg_ram: memory@fc428000 {
535 compatible = "qcom,rpm-msg-ram";
536 reg = <0xfc428000 0x4000>;
540 compatible = "qcom,pshold";
541 reg = <0xfc4ab000 0x4>;
544 spmi_bus: spmi@fc4c0000 {
545 compatible = "qcom,spmi-pmic-arb";
546 reg = <0xfc4cf000 0x1000>,
549 reg-names = "core", "intr", "cnfg";
550 interrupt-names = "periph_irq";
551 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <2>;
556 interrupt-controller;
557 #interrupt-cells = <4>;
560 tcsr_mutex_regs: syscon@fd484000 {
561 compatible = "syscon";
562 reg = <0xfd484000 0x2000>;
565 tlmm: pinctrl@fd510000 {
566 compatible = "qcom,msm8994-pinctrl";
567 reg = <0xfd510000 0x4000>;
568 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
570 gpio-ranges = <&tlmm 0 0 146>;
572 interrupt-controller;
573 #interrupt-cells = <2>;
575 blsp1_uart2_default: blsp1-uart2-default {
576 function = "blsp_uart2";
577 pins = "gpio4", "gpio5";
578 drive-strength = <16>;
582 blsp1_uart2_sleep: blsp1-uart2-sleep {
584 pins = "gpio4", "gpio5";
585 drive-strength = <2>;
589 blsp2_uart2_default: blsp2-uart2-default {
590 function = "blsp_uart8";
591 pins = "gpio45", "gpio46";
592 drive-strength = <2>;
596 blsp2_uart2_sleep: blsp2-uart2-sleep {
598 pins = "gpio45", "gpio46";
599 drive-strength = <2>;
603 i2c1_default: i2c1-default {
604 function = "blsp_i2c1";
605 pins = "gpio2", "gpio3";
606 drive-strength = <2>;
610 i2c1_sleep: i2c1-sleep {
612 pins = "gpio2", "gpio3";
613 drive-strength = <2>;
617 i2c2_default: i2c2-default {
618 function = "blsp_i2c2";
619 pins = "gpio6", "gpio7";
620 drive-strength = <2>;
624 i2c2_sleep: i2c2-sleep {
626 pins = "gpio6", "gpio7";
627 drive-strength = <2>;
631 i2c4_default: i2c4-default {
632 function = "blsp_i2c4";
633 pins = "gpio19", "gpio20";
634 drive-strength = <2>;
638 i2c4_sleep: i2c4-sleep {
640 pins = "gpio19", "gpio20";
641 drive-strength = <2>;
646 i2c5_default: i2c5-default {
647 function = "blsp_i2c5";
648 pins = "gpio23", "gpio24";
649 drive-strength = <2>;
653 i2c5_sleep: i2c5-sleep {
655 pins = "gpio23", "gpio24";
656 drive-strength = <2>;
660 i2c6_default: i2c6-default {
661 function = "blsp_i2c6";
662 pins = "gpio28", "gpio27";
663 drive-strength = <2>;
667 i2c6_sleep: i2c6-sleep {
669 pins = "gpio28", "gpio27";
670 drive-strength = <2>;
674 blsp1_spi0_default: blsp1-spi0-default {
676 function = "blsp_spi1";
677 pins = "gpio0", "gpio1", "gpio3";
678 drive-strength = <10>;
684 drive-strength = <2>;
689 blsp1_spi0_sleep: blsp1-spi0-sleep {
690 pins = "gpio0", "gpio1", "gpio3";
691 drive-strength = <2>;
695 sdc1_clk_on: clk-on {
698 drive-strength = <16>;
701 sdc1_clk_off: clk-off {
704 drive-strength = <2>;
707 sdc1_cmd_on: cmd-on {
710 drive-strength = <8>;
713 sdc1_cmd_off: cmd-off {
716 drive-strength = <2>;
719 sdc1_data_on: data-on {
722 drive-strength = <8>;
725 sdc1_data_off: data-off {
728 drive-strength = <2>;
731 sdc1_rclk_on: rclk-on {
736 sdc1_rclk_off: rclk-off {
741 sdc2_clk_on: sdc2-clk-on {
744 drive-strength = <10>;
747 sdc2_clk_off: sdc2-clk-off {
750 drive-strength = <2>;
753 sdc2_cmd_on: sdc2-cmd-on {
756 drive-strength = <10>;
759 sdc2_cmd_off: sdc2-cmd-off {
762 drive-strength = <2>;
765 sdc2_data_on: sdc2-data-on {
768 drive-strength = <10>;
771 sdc2_data_off: sdc2-data-off {
774 drive-strength = <2>;
780 compatible = "qcom,tcsr-mutex";
781 syscon = <&tcsr_mutex_regs 0 0x80>;
786 compatible = "arm,armv8-timer";
787 interrupts = <GIC_PPI 2 0xff08>,
793 vreg_vph_pwr: vreg-vph-pwr {
794 compatible = "regulator-fixed";
795 regulator-name = "vph-pwr";
797 regulator-min-microvolt = <3600000>;
798 regulator-max-microvolt = <3600000>;