1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
21 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
22 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
28 device_type = "memory";
29 /* We expect the bootloader to fill in the reg */
39 reg = <0x0 0x86000000 0x0 0x300000>;
43 smem_mem: smem_region@86300000 {
44 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
64 compatible = "qcom,rmtfs-mem";
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
76 mpss_mem: mpss@86800000 {
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
81 wcnss_mem: wcnss@89300000 {
82 reg = <0x0 0x89300000 0x0 0x600000>;
86 venus_mem: venus@89900000 {
87 reg = <0x0 0x89900000 0x0 0x600000>;
91 mba_mem: mba@8ea00000 {
93 reg = <0 0x8ea00000 0 0x100000>;
99 compatible = "fixed-clock";
101 clock-frequency = <19200000>;
104 sleep_clk: sleep-clk {
105 compatible = "fixed-clock";
107 clock-frequency = <32768>;
112 #address-cells = <1>;
117 compatible = "arm,cortex-a53";
119 next-level-cache = <&L2_0>;
120 enable-method = "psci";
122 operating-points-v2 = <&cpu_opp_table>;
123 #cooling-cells = <2>;
124 power-domains = <&CPU_PD0>;
125 power-domain-names = "psci";
130 compatible = "arm,cortex-a53";
132 next-level-cache = <&L2_0>;
133 enable-method = "psci";
135 operating-points-v2 = <&cpu_opp_table>;
136 #cooling-cells = <2>;
137 power-domains = <&CPU_PD1>;
138 power-domain-names = "psci";
143 compatible = "arm,cortex-a53";
145 next-level-cache = <&L2_0>;
146 enable-method = "psci";
148 operating-points-v2 = <&cpu_opp_table>;
149 #cooling-cells = <2>;
150 power-domains = <&CPU_PD2>;
151 power-domain-names = "psci";
156 compatible = "arm,cortex-a53";
158 next-level-cache = <&L2_0>;
159 enable-method = "psci";
161 operating-points-v2 = <&cpu_opp_table>;
162 #cooling-cells = <2>;
163 power-domains = <&CPU_PD3>;
164 power-domain-names = "psci";
168 compatible = "cache";
173 entry-method = "psci";
175 CPU_SLEEP_0: cpu-sleep-0 {
176 compatible = "arm,idle-state";
177 idle-state-name = "standalone-power-collapse";
178 arm,psci-suspend-param = <0x40000002>;
179 entry-latency-us = <130>;
180 exit-latency-us = <150>;
181 min-residency-us = <2000>;
188 CLUSTER_RET: cluster-retention {
189 compatible = "domain-idle-state";
190 arm,psci-suspend-param = <0x41000012>;
191 entry-latency-us = <500>;
192 exit-latency-us = <500>;
193 min-residency-us = <2000>;
196 CLUSTER_PWRDN: cluster-gdhs {
197 compatible = "domain-idle-state";
198 arm,psci-suspend-param = <0x41000032>;
199 entry-latency-us = <2000>;
200 exit-latency-us = <2000>;
201 min-residency-us = <6000>;
206 cpu_opp_table: cpu-opp-table {
207 compatible = "operating-points-v2";
211 opp-hz = /bits/ 64 <200000000>;
214 opp-hz = /bits/ 64 <400000000>;
217 opp-hz = /bits/ 64 <800000000>;
220 opp-hz = /bits/ 64 <998400000>;
226 compatible = "qcom,scm-msm8916", "qcom,scm";
227 clocks = <&gcc GCC_CRYPTO_CLK>,
228 <&gcc GCC_CRYPTO_AXI_CLK>,
229 <&gcc GCC_CRYPTO_AHB_CLK>;
230 clock-names = "core", "bus", "iface";
233 qcom,dload-mode = <&tcsr 0x6100>;
238 compatible = "arm,cortex-a53-pmu";
239 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
243 compatible = "arm,psci-1.0";
246 CPU_PD0: power-domain-cpu0 {
247 #power-domain-cells = <0>;
248 power-domains = <&CLUSTER_PD>;
249 domain-idle-states = <&CPU_SLEEP_0>;
252 CPU_PD1: power-domain-cpu1 {
253 #power-domain-cells = <0>;
254 power-domains = <&CLUSTER_PD>;
255 domain-idle-states = <&CPU_SLEEP_0>;
258 CPU_PD2: power-domain-cpu2 {
259 #power-domain-cells = <0>;
260 power-domains = <&CLUSTER_PD>;
261 domain-idle-states = <&CPU_SLEEP_0>;
264 CPU_PD3: power-domain-cpu3 {
265 #power-domain-cells = <0>;
266 power-domains = <&CLUSTER_PD>;
267 domain-idle-states = <&CPU_SLEEP_0>;
270 CLUSTER_PD: power-domain-cluster {
271 #power-domain-cells = <0>;
272 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
277 compatible = "qcom,smd";
280 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
281 qcom,ipc = <&apcs 8 0>;
282 qcom,smd-edge = <15>;
284 rpm_requests: rpm-requests {
285 compatible = "qcom,rpm-msm8916";
286 qcom,smd-channels = "rpm_requests";
288 rpmcc: clock-controller {
289 compatible = "qcom,rpmcc-msm8916";
297 compatible = "qcom,smem";
299 memory-region = <&smem_mem>;
300 qcom,rpm-msg-ram = <&rpm_msg_ram>;
302 hwlocks = <&tcsr_mutex 3>;
306 compatible = "qcom,smp2p";
307 qcom,smem = <435>, <428>;
309 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
311 qcom,ipc = <&apcs 8 14>;
313 qcom,local-pid = <0>;
314 qcom,remote-pid = <1>;
316 hexagon_smp2p_out: master-kernel {
317 qcom,entry-name = "master-kernel";
319 #qcom,smem-state-cells = <1>;
322 hexagon_smp2p_in: slave-kernel {
323 qcom,entry-name = "slave-kernel";
325 interrupt-controller;
326 #interrupt-cells = <2>;
331 compatible = "qcom,smp2p";
332 qcom,smem = <451>, <431>;
334 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
336 qcom,ipc = <&apcs 8 18>;
338 qcom,local-pid = <0>;
339 qcom,remote-pid = <4>;
341 wcnss_smp2p_out: master-kernel {
342 qcom,entry-name = "master-kernel";
344 #qcom,smem-state-cells = <1>;
347 wcnss_smp2p_in: slave-kernel {
348 qcom,entry-name = "slave-kernel";
350 interrupt-controller;
351 #interrupt-cells = <2>;
356 compatible = "qcom,smsm";
358 #address-cells = <1>;
361 qcom,ipc-1 = <&apcs 8 13>;
362 qcom,ipc-3 = <&apcs 8 19>;
367 #qcom,smem-state-cells = <1>;
370 hexagon_smsm: hexagon@1 {
372 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
378 wcnss_smsm: wcnss@6 {
380 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
388 #address-cells = <1>;
390 ranges = <0 0 0 0xffffffff>;
391 compatible = "simple-bus";
394 compatible = "qcom,prng";
395 reg = <0x00022000 0x200>;
396 clocks = <&gcc GCC_PRNG_AHB_CLK>;
397 clock-names = "core";
401 compatible = "qcom,pshold";
402 reg = <0x004ab000 0x4>;
405 qfprom: qfprom@5c000 {
406 compatible = "qcom,qfprom";
407 reg = <0x0005c000 0x1000>;
408 #address-cells = <1>;
410 tsens_caldata: caldata@d0 {
413 tsens_calsel: calsel@ec {
418 rpm_msg_ram: memory@60000 {
419 compatible = "qcom,rpm-msg-ram";
420 reg = <0x00060000 0x8000>;
423 bimc: interconnect@400000 {
424 compatible = "qcom,msm8916-bimc";
425 reg = <0x00400000 0x62000>;
426 #interconnect-cells = <1>;
427 clock-names = "bus", "bus_a";
428 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
429 <&rpmcc RPM_SMD_BIMC_A_CLK>;
432 tsens: thermal-sensor@4a9000 {
433 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
434 reg = <0x004a9000 0x1000>, /* TM */
435 <0x004a8000 0x1000>; /* SROT */
436 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
437 nvmem-cell-names = "calib", "calib_sel";
439 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "uplow";
441 #thermal-sensor-cells = <1>;
444 pcnoc: interconnect@500000 {
445 compatible = "qcom,msm8916-pcnoc";
446 reg = <0x00500000 0x11000>;
447 #interconnect-cells = <1>;
448 clock-names = "bus", "bus_a";
449 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
450 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
453 snoc: interconnect@580000 {
454 compatible = "qcom,msm8916-snoc";
455 reg = <0x00580000 0x14000>;
456 #interconnect-cells = <1>;
457 clock-names = "bus", "bus_a";
458 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
459 <&rpmcc RPM_SMD_SNOC_A_CLK>;
463 /* CTI 0 - TMC connections */
465 compatible = "arm,coresight-cti", "arm,primecell";
466 reg = <0x00810000 0x1000>;
468 clocks = <&rpmcc RPM_QDSS_CLK>;
469 clock-names = "apb_pclk";
474 /* CTI 1 - TPIU connections */
476 compatible = "arm,coresight-cti", "arm,primecell";
477 reg = <0x00811000 0x1000>;
479 clocks = <&rpmcc RPM_QDSS_CLK>;
480 clock-names = "apb_pclk";
485 /* CTIs 2-11 - no information - not instantiated */
488 compatible = "arm,coresight-tpiu", "arm,primecell";
489 reg = <0x00820000 0x1000>;
491 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
492 clock-names = "apb_pclk", "atclk";
499 remote-endpoint = <&replicator_out1>;
505 funnel0: funnel@821000 {
506 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
507 reg = <0x00821000 0x1000>;
509 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
510 clock-names = "apb_pclk", "atclk";
515 #address-cells = <1>;
519 * Not described input ports:
520 * 0 - connected to Resource and Power Manger CPU ETM
522 * 2 - connected to Modem CPU ETM
525 * 6 - connected trought funnel to Wireless CPU ETM
526 * 7 - connected to STM component
531 funnel0_in4: endpoint {
532 remote-endpoint = <&funnel1_out>;
539 funnel0_out: endpoint {
540 remote-endpoint = <&etf_in>;
546 replicator: replicator@824000 {
547 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
548 reg = <0x00824000 0x1000>;
550 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
551 clock-names = "apb_pclk", "atclk";
556 #address-cells = <1>;
561 replicator_out0: endpoint {
562 remote-endpoint = <&etr_in>;
567 replicator_out1: endpoint {
568 remote-endpoint = <&tpiu_in>;
575 replicator_in: endpoint {
576 remote-endpoint = <&etf_out>;
583 compatible = "arm,coresight-tmc", "arm,primecell";
584 reg = <0x00825000 0x1000>;
586 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
587 clock-names = "apb_pclk", "atclk";
594 remote-endpoint = <&funnel0_out>;
602 remote-endpoint = <&replicator_in>;
609 compatible = "arm,coresight-tmc", "arm,primecell";
610 reg = <0x00826000 0x1000>;
612 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
613 clock-names = "apb_pclk", "atclk";
620 remote-endpoint = <&replicator_out0>;
626 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
627 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
628 reg = <0x00841000 0x1000>;
630 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
631 clock-names = "apb_pclk", "atclk";
636 #address-cells = <1>;
641 funnel1_in0: endpoint {
642 remote-endpoint = <&etm0_out>;
647 funnel1_in1: endpoint {
648 remote-endpoint = <&etm1_out>;
653 funnel1_in2: endpoint {
654 remote-endpoint = <&etm2_out>;
659 funnel1_in3: endpoint {
660 remote-endpoint = <&etm3_out>;
667 funnel1_out: endpoint {
668 remote-endpoint = <&funnel0_in4>;
674 debug0: debug@850000 {
675 compatible = "arm,coresight-cpu-debug", "arm,primecell";
676 reg = <0x00850000 0x1000>;
677 clocks = <&rpmcc RPM_QDSS_CLK>;
678 clock-names = "apb_pclk";
683 debug1: debug@852000 {
684 compatible = "arm,coresight-cpu-debug", "arm,primecell";
685 reg = <0x00852000 0x1000>;
686 clocks = <&rpmcc RPM_QDSS_CLK>;
687 clock-names = "apb_pclk";
692 debug2: debug@854000 {
693 compatible = "arm,coresight-cpu-debug", "arm,primecell";
694 reg = <0x00854000 0x1000>;
695 clocks = <&rpmcc RPM_QDSS_CLK>;
696 clock-names = "apb_pclk";
701 debug3: debug@856000 {
702 compatible = "arm,coresight-cpu-debug", "arm,primecell";
703 reg = <0x00856000 0x1000>;
704 clocks = <&rpmcc RPM_QDSS_CLK>;
705 clock-names = "apb_pclk";
710 /* Core CTIs; CTIs 12-15 */
713 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
715 reg = <0x00858000 0x1000>;
717 clocks = <&rpmcc RPM_QDSS_CLK>;
718 clock-names = "apb_pclk";
721 arm,cs-dev-assoc = <&etm0>;
728 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
730 reg = <0x00859000 0x1000>;
732 clocks = <&rpmcc RPM_QDSS_CLK>;
733 clock-names = "apb_pclk";
736 arm,cs-dev-assoc = <&etm1>;
743 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
745 reg = <0x0085a000 0x1000>;
747 clocks = <&rpmcc RPM_QDSS_CLK>;
748 clock-names = "apb_pclk";
751 arm,cs-dev-assoc = <&etm2>;
758 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
760 reg = <0x0085b000 0x1000>;
762 clocks = <&rpmcc RPM_QDSS_CLK>;
763 clock-names = "apb_pclk";
766 arm,cs-dev-assoc = <&etm3>;
772 compatible = "arm,coresight-etm4x", "arm,primecell";
773 reg = <0x0085c000 0x1000>;
775 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
776 clock-names = "apb_pclk", "atclk";
777 arm,coresight-loses-context-with-cpu;
786 remote-endpoint = <&funnel1_in0>;
793 compatible = "arm,coresight-etm4x", "arm,primecell";
794 reg = <0x0085d000 0x1000>;
796 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
797 clock-names = "apb_pclk", "atclk";
798 arm,coresight-loses-context-with-cpu;
807 remote-endpoint = <&funnel1_in1>;
814 compatible = "arm,coresight-etm4x", "arm,primecell";
815 reg = <0x0085e000 0x1000>;
817 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
818 clock-names = "apb_pclk", "atclk";
819 arm,coresight-loses-context-with-cpu;
828 remote-endpoint = <&funnel1_in2>;
835 compatible = "arm,coresight-etm4x", "arm,primecell";
836 reg = <0x0085f000 0x1000>;
838 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
839 clock-names = "apb_pclk", "atclk";
840 arm,coresight-loses-context-with-cpu;
849 remote-endpoint = <&funnel1_in3>;
855 msmgpio: pinctrl@1000000 {
856 compatible = "qcom,msm8916-pinctrl";
857 reg = <0x01000000 0x300000>;
858 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
860 gpio-ranges = <&msmgpio 0 0 122>;
862 interrupt-controller;
863 #interrupt-cells = <2>;
866 gcc: clock-controller@1800000 {
867 compatible = "qcom,gcc-msm8916";
870 #power-domain-cells = <1>;
871 reg = <0x01800000 0x80000>;
874 tcsr_mutex: hwlock@1905000 {
875 compatible = "qcom,tcsr-mutex";
876 reg = <0x01905000 0x20000>;
880 tcsr: syscon@1937000 {
881 compatible = "qcom,tcsr-msm8916", "syscon";
882 reg = <0x01937000 0x30000>;
886 compatible = "qcom,mdss";
887 reg = <0x01a00000 0x1000>,
889 reg-names = "mdss_phys", "vbif_phys";
891 power-domains = <&gcc MDSS_GDSC>;
893 clocks = <&gcc GCC_MDSS_AHB_CLK>,
894 <&gcc GCC_MDSS_AXI_CLK>,
895 <&gcc GCC_MDSS_VSYNC_CLK>;
896 clock-names = "iface",
900 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
902 interrupt-controller;
903 #interrupt-cells = <1>;
905 #address-cells = <1>;
910 compatible = "qcom,mdp5";
911 reg = <0x01a01000 0x89000>;
912 reg-names = "mdp_phys";
914 interrupt-parent = <&mdss>;
917 clocks = <&gcc GCC_MDSS_AHB_CLK>,
918 <&gcc GCC_MDSS_AXI_CLK>,
919 <&gcc GCC_MDSS_MDP_CLK>,
920 <&gcc GCC_MDSS_VSYNC_CLK>;
921 clock-names = "iface",
926 iommus = <&apps_iommu 4>;
929 #address-cells = <1>;
934 mdp5_intf1_out: endpoint {
935 remote-endpoint = <&dsi0_in>;
942 compatible = "qcom,mdss-dsi-ctrl";
943 reg = <0x01a98000 0x25c>;
944 reg-names = "dsi_ctrl";
946 interrupt-parent = <&mdss>;
949 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
950 <&gcc PCLK0_CLK_SRC>;
951 assigned-clock-parents = <&dsi_phy0 0>,
954 clocks = <&gcc GCC_MDSS_MDP_CLK>,
955 <&gcc GCC_MDSS_AHB_CLK>,
956 <&gcc GCC_MDSS_AXI_CLK>,
957 <&gcc GCC_MDSS_BYTE0_CLK>,
958 <&gcc GCC_MDSS_PCLK0_CLK>,
959 <&gcc GCC_MDSS_ESC0_CLK>;
960 clock-names = "mdp_core",
967 phy-names = "dsi-phy";
969 #address-cells = <1>;
973 #address-cells = <1>;
979 remote-endpoint = <&mdp5_intf1_out>;
991 dsi_phy0: dsi-phy@1a98300 {
992 compatible = "qcom,dsi-phy-28nm-lp";
993 reg = <0x01a98300 0xd4>,
996 reg-names = "dsi_pll",
1003 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1005 clock-names = "iface", "ref";
1009 camss: camss@1b00000 {
1010 compatible = "qcom,msm8916-camss";
1011 reg = <0x01b0ac00 0x200>,
1019 <0x01b10000 0x1000>;
1020 reg-names = "csiphy0",
1029 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1030 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1031 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1032 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1033 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1034 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1035 interrupt-names = "csiphy0",
1041 power-domains = <&gcc VFE_GDSC>;
1042 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1043 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1044 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1045 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1046 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1047 <&gcc GCC_CAMSS_CSI0_CLK>,
1048 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1049 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1050 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1051 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1052 <&gcc GCC_CAMSS_CSI1_CLK>,
1053 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1054 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1055 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1056 <&gcc GCC_CAMSS_AHB_CLK>,
1057 <&gcc GCC_CAMSS_VFE0_CLK>,
1058 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1059 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1060 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1061 clock-names = "top_ahb",
1080 iommus = <&apps_iommu 3>;
1081 status = "disabled";
1083 #address-cells = <1>;
1089 compatible = "qcom,msm8916-cci";
1090 #address-cells = <1>;
1092 reg = <0x01b0c000 0x1000>;
1093 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1094 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1095 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1096 <&gcc GCC_CAMSS_CCI_CLK>,
1097 <&gcc GCC_CAMSS_AHB_CLK>;
1098 clock-names = "camss_top_ahb", "cci_ahb",
1100 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1101 <&gcc GCC_CAMSS_CCI_CLK>;
1102 assigned-clock-rates = <80000000>, <19200000>;
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&cci0_default>;
1105 status = "disabled";
1107 cci_i2c0: i2c-bus@0 {
1109 clock-frequency = <400000>;
1110 #address-cells = <1>;
1116 compatible = "qcom,adreno-306.0", "qcom,adreno";
1117 reg = <0x01c00000 0x20000>;
1118 reg-names = "kgsl_3d0_reg_memory";
1119 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1120 interrupt-names = "kgsl_3d0_irq";
1129 <&gcc GCC_OXILI_GFX3D_CLK>,
1130 <&gcc GCC_OXILI_AHB_CLK>,
1131 <&gcc GCC_OXILI_GMEM_CLK>,
1132 <&gcc GCC_BIMC_GFX_CLK>,
1133 <&gcc GCC_BIMC_GPU_CLK>,
1134 <&gcc GFX3D_CLK_SRC>;
1135 power-domains = <&gcc OXILI_GDSC>;
1136 operating-points-v2 = <&gpu_opp_table>;
1137 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1139 gpu_opp_table: opp-table {
1140 compatible = "operating-points-v2";
1143 opp-hz = /bits/ 64 <400000000>;
1146 opp-hz = /bits/ 64 <19200000>;
1151 venus: video-codec@1d00000 {
1152 compatible = "qcom,msm8916-venus";
1153 reg = <0x01d00000 0xff000>;
1154 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1155 power-domains = <&gcc VENUS_GDSC>;
1156 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1157 <&gcc GCC_VENUS0_AHB_CLK>,
1158 <&gcc GCC_VENUS0_AXI_CLK>;
1159 clock-names = "core", "iface", "bus";
1160 iommus = <&apps_iommu 5>;
1161 memory-region = <&venus_mem>;
1165 compatible = "venus-decoder";
1169 compatible = "venus-encoder";
1173 apps_iommu: iommu@1ef0000 {
1174 #address-cells = <1>;
1177 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1178 ranges = <0 0x01e20000 0x40000>;
1179 reg = <0x01ef0000 0x3000>;
1180 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1181 <&gcc GCC_APSS_TCU_CLK>;
1182 clock-names = "iface", "bus";
1183 qcom,iommu-secure-id = <17>;
1187 compatible = "qcom,msm-iommu-v1-sec";
1188 reg = <0x3000 0x1000>;
1189 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1194 compatible = "qcom,msm-iommu-v1-ns";
1195 reg = <0x4000 0x1000>;
1196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1201 compatible = "qcom,msm-iommu-v1-sec";
1202 reg = <0x5000 0x1000>;
1203 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1207 gpu_iommu: iommu@1f08000 {
1208 #address-cells = <1>;
1211 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1212 ranges = <0 0x01f08000 0x10000>;
1213 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1214 <&gcc GCC_GFX_TCU_CLK>;
1215 clock-names = "iface", "bus";
1216 qcom,iommu-secure-id = <18>;
1220 compatible = "qcom,msm-iommu-v1-ns";
1221 reg = <0x1000 0x1000>;
1222 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1227 compatible = "qcom,msm-iommu-v1-ns";
1228 reg = <0x2000 0x1000>;
1229 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1233 spmi_bus: spmi@200f000 {
1234 compatible = "qcom,spmi-pmic-arb";
1235 reg = <0x0200f000 0x001000>,
1236 <0x02400000 0x400000>,
1237 <0x02c00000 0x400000>,
1238 <0x03800000 0x200000>,
1239 <0x0200a000 0x002100>;
1240 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1241 interrupt-names = "periph_irq";
1242 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1245 #address-cells = <2>;
1247 interrupt-controller;
1248 #interrupt-cells = <4>;
1251 mpss: remoteproc@4080000 {
1252 compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1253 reg = <0x04080000 0x100>,
1256 reg-names = "qdsp6", "rmb";
1258 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1259 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1260 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1261 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1262 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1263 interrupt-names = "wdog", "fatal", "ready",
1264 "handover", "stop-ack";
1266 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1267 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1268 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1270 clock-names = "iface", "bus", "mem", "xo";
1272 qcom,smem-states = <&hexagon_smp2p_out 0>;
1273 qcom,smem-state-names = "stop";
1276 reset-names = "mss_restart";
1278 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1280 status = "disabled";
1283 memory-region = <&mba_mem>;
1287 memory-region = <&mpss_mem>;
1291 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1293 qcom,smd-edge = <0>;
1294 qcom,ipc = <&apcs 8 12>;
1295 qcom,remote-pid = <1>;
1300 compatible = "qcom,fastrpc";
1301 qcom,smd-channels = "fastrpcsmd-apps-dsp";
1304 #address-cells = <1>;
1308 compatible = "qcom,fastrpc-compute-cb";
1315 sound: sound@7702000 {
1316 status = "disabled";
1317 compatible = "qcom,apq8016-sbc-sndcard";
1318 reg = <0x07702000 0x4>, <0x07702004 0x4>;
1319 reg-names = "mic-iomux", "spkr-iomux";
1322 lpass: audio-controller@7708000 {
1323 status = "disabled";
1324 compatible = "qcom,lpass-cpu-apq8016";
1325 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1326 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1327 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1328 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1329 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1330 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1331 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1333 clock-names = "ahbix-clk",
1340 #sound-dai-cells = <1>;
1342 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1343 interrupt-names = "lpass-irq-lpaif";
1344 reg = <0x07708000 0x10000>;
1345 reg-names = "lpass-lpaif";
1347 #address-cells = <1>;
1351 lpass_codec: audio-codec@771c000 {
1352 compatible = "qcom,msm8916-wcd-digital-codec";
1353 reg = <0x0771c000 0x400>;
1354 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1355 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1356 clock-names = "ahbix-clk", "mclk";
1357 #sound-dai-cells = <1>;
1360 sdhc_1: sdhci@7824000 {
1361 compatible = "qcom,sdhci-msm-v4";
1362 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1363 reg-names = "hc_mem", "core_mem";
1365 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1367 interrupt-names = "hc_irq", "pwr_irq";
1368 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1369 <&gcc GCC_SDCC1_AHB_CLK>,
1371 clock-names = "core", "iface", "xo";
1375 status = "disabled";
1378 sdhc_2: sdhci@7864000 {
1379 compatible = "qcom,sdhci-msm-v4";
1380 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1381 reg-names = "hc_mem", "core_mem";
1383 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "hc_irq", "pwr_irq";
1386 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1387 <&gcc GCC_SDCC2_AHB_CLK>,
1389 clock-names = "core", "iface", "xo";
1391 status = "disabled";
1394 blsp_dma: dma@7884000 {
1395 compatible = "qcom,bam-v1.7.0";
1396 reg = <0x07884000 0x23000>;
1397 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1398 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1399 clock-names = "bam_clk";
1402 status = "disabled";
1405 blsp1_uart1: serial@78af000 {
1406 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1407 reg = <0x078af000 0x200>;
1408 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1410 clock-names = "core", "iface";
1411 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
1412 dma-names = "rx", "tx";
1413 pinctrl-names = "default", "sleep";
1414 pinctrl-0 = <&blsp1_uart1_default>;
1415 pinctrl-1 = <&blsp1_uart1_sleep>;
1416 status = "disabled";
1419 blsp1_uart2: serial@78b0000 {
1420 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1421 reg = <0x078b0000 0x200>;
1422 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1423 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1424 clock-names = "core", "iface";
1425 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
1426 dma-names = "rx", "tx";
1427 pinctrl-names = "default", "sleep";
1428 pinctrl-0 = <&blsp1_uart2_default>;
1429 pinctrl-1 = <&blsp1_uart2_sleep>;
1430 status = "disabled";
1433 blsp_i2c1: i2c@78b5000 {
1434 compatible = "qcom,i2c-qup-v2.2.1";
1435 reg = <0x078b5000 0x500>;
1436 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1437 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1438 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
1439 clock-names = "iface", "core";
1440 pinctrl-names = "default", "sleep";
1441 pinctrl-0 = <&i2c1_default>;
1442 pinctrl-1 = <&i2c1_sleep>;
1443 #address-cells = <1>;
1445 status = "disabled";
1448 blsp_spi1: spi@78b5000 {
1449 compatible = "qcom,spi-qup-v2.2.1";
1450 reg = <0x078b5000 0x500>;
1451 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1452 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1453 <&gcc GCC_BLSP1_AHB_CLK>;
1454 clock-names = "core", "iface";
1455 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
1456 dma-names = "rx", "tx";
1457 pinctrl-names = "default", "sleep";
1458 pinctrl-0 = <&spi1_default>;
1459 pinctrl-1 = <&spi1_sleep>;
1460 #address-cells = <1>;
1462 status = "disabled";
1465 blsp_i2c2: i2c@78b6000 {
1466 compatible = "qcom,i2c-qup-v2.2.1";
1467 reg = <0x078b6000 0x500>;
1468 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1470 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
1471 clock-names = "iface", "core";
1472 pinctrl-names = "default", "sleep";
1473 pinctrl-0 = <&i2c2_default>;
1474 pinctrl-1 = <&i2c2_sleep>;
1475 #address-cells = <1>;
1477 status = "disabled";
1480 blsp_spi2: spi@78b6000 {
1481 compatible = "qcom,spi-qup-v2.2.1";
1482 reg = <0x078b6000 0x500>;
1483 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1485 <&gcc GCC_BLSP1_AHB_CLK>;
1486 clock-names = "core", "iface";
1487 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
1488 dma-names = "rx", "tx";
1489 pinctrl-names = "default", "sleep";
1490 pinctrl-0 = <&spi2_default>;
1491 pinctrl-1 = <&spi2_sleep>;
1492 #address-cells = <1>;
1494 status = "disabled";
1497 blsp_spi3: spi@78b7000 {
1498 compatible = "qcom,spi-qup-v2.2.1";
1499 reg = <0x078b7000 0x500>;
1500 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1501 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1502 <&gcc GCC_BLSP1_AHB_CLK>;
1503 clock-names = "core", "iface";
1504 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
1505 dma-names = "rx", "tx";
1506 pinctrl-names = "default", "sleep";
1507 pinctrl-0 = <&spi3_default>;
1508 pinctrl-1 = <&spi3_sleep>;
1509 #address-cells = <1>;
1511 status = "disabled";
1514 blsp_i2c4: i2c@78b8000 {
1515 compatible = "qcom,i2c-qup-v2.2.1";
1516 reg = <0x078b8000 0x500>;
1517 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1518 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1519 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1520 clock-names = "iface", "core";
1521 pinctrl-names = "default", "sleep";
1522 pinctrl-0 = <&i2c4_default>;
1523 pinctrl-1 = <&i2c4_sleep>;
1524 #address-cells = <1>;
1526 status = "disabled";
1529 blsp_spi4: spi@78b8000 {
1530 compatible = "qcom,spi-qup-v2.2.1";
1531 reg = <0x078b8000 0x500>;
1532 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1534 <&gcc GCC_BLSP1_AHB_CLK>;
1535 clock-names = "core", "iface";
1536 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
1537 dma-names = "rx", "tx";
1538 pinctrl-names = "default", "sleep";
1539 pinctrl-0 = <&spi4_default>;
1540 pinctrl-1 = <&spi4_sleep>;
1541 #address-cells = <1>;
1543 status = "disabled";
1546 blsp_i2c5: i2c@78b9000 {
1547 compatible = "qcom,i2c-qup-v2.2.1";
1548 reg = <0x078b9000 0x500>;
1549 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1550 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1551 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
1552 clock-names = "iface", "core";
1553 pinctrl-names = "default", "sleep";
1554 pinctrl-0 = <&i2c5_default>;
1555 pinctrl-1 = <&i2c5_sleep>;
1556 #address-cells = <1>;
1558 status = "disabled";
1561 blsp_spi5: spi@78b9000 {
1562 compatible = "qcom,spi-qup-v2.2.1";
1563 reg = <0x078b9000 0x500>;
1564 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1565 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1566 <&gcc GCC_BLSP1_AHB_CLK>;
1567 clock-names = "core", "iface";
1568 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
1569 dma-names = "rx", "tx";
1570 pinctrl-names = "default", "sleep";
1571 pinctrl-0 = <&spi5_default>;
1572 pinctrl-1 = <&spi5_sleep>;
1573 #address-cells = <1>;
1575 status = "disabled";
1578 blsp_i2c6: i2c@78ba000 {
1579 compatible = "qcom,i2c-qup-v2.2.1";
1580 reg = <0x078ba000 0x500>;
1581 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1582 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1583 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
1584 clock-names = "iface", "core";
1585 pinctrl-names = "default", "sleep";
1586 pinctrl-0 = <&i2c6_default>;
1587 pinctrl-1 = <&i2c6_sleep>;
1588 #address-cells = <1>;
1590 status = "disabled";
1593 blsp_spi6: spi@78ba000 {
1594 compatible = "qcom,spi-qup-v2.2.1";
1595 reg = <0x078ba000 0x500>;
1596 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1598 <&gcc GCC_BLSP1_AHB_CLK>;
1599 clock-names = "core", "iface";
1600 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
1601 dma-names = "rx", "tx";
1602 pinctrl-names = "default", "sleep";
1603 pinctrl-0 = <&spi6_default>;
1604 pinctrl-1 = <&spi6_sleep>;
1605 #address-cells = <1>;
1607 status = "disabled";
1611 compatible = "qcom,ci-hdrc";
1612 reg = <0x078d9000 0x200>,
1614 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1615 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1616 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1617 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1618 clock-names = "iface", "core";
1619 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1620 assigned-clock-rates = <80000000>;
1621 resets = <&gcc GCC_USB_HS_BCR>;
1622 reset-names = "core";
1628 ahb-burst-config = <0>;
1629 phy-names = "usb-phy";
1630 phys = <&usb_hs_phy>;
1631 status = "disabled";
1636 compatible = "qcom,usb-hs-phy-msm8916",
1639 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1640 clock-names = "ref", "sleep";
1641 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1642 reset-names = "phy", "por";
1643 qcom,init-seq = /bits/ 8 <0x0 0x44
1644 0x1 0x6b 0x2 0x24 0x3 0x13>;
1649 pronto: remoteproc@a21b000 {
1650 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1651 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1652 reg-names = "ccu", "dxe", "pmu";
1654 memory-region = <&wcnss_mem>;
1656 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1657 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1658 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1659 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1660 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1661 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1663 qcom,state = <&wcnss_smp2p_out 0>;
1664 qcom,state-names = "stop";
1666 pinctrl-names = "default";
1667 pinctrl-0 = <&wcnss_pin_a>;
1669 status = "disabled";
1672 compatible = "qcom,wcn3620";
1674 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1679 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1681 qcom,ipc = <&apcs 8 17>;
1682 qcom,smd-edge = <6>;
1683 qcom,remote-pid = <4>;
1688 compatible = "qcom,wcnss";
1689 qcom,smd-channels = "WCNSS_CTRL";
1691 qcom,mmio = <&pronto>;
1694 compatible = "qcom,wcnss-bt";
1698 compatible = "qcom,wcnss-wlan";
1700 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1702 interrupt-names = "tx", "rx";
1704 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1705 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1711 intc: interrupt-controller@b000000 {
1712 compatible = "qcom,msm-qgic2";
1713 interrupt-controller;
1714 #interrupt-cells = <3>;
1715 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1718 apcs: mailbox@b011000 {
1719 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1720 reg = <0x0b011000 0x1000>;
1722 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1723 clock-names = "pll", "aux";
1727 a53pll: clock@b016000 {
1728 compatible = "qcom,msm8916-a53pll";
1729 reg = <0x0b016000 0x40>;
1734 #address-cells = <1>;
1737 compatible = "arm,armv7-timer-mem";
1738 reg = <0x0b020000 0x1000>;
1739 clock-frequency = <19200000>;
1743 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1745 reg = <0x0b021000 0x1000>,
1746 <0x0b022000 0x1000>;
1751 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1752 reg = <0x0b023000 0x1000>;
1753 status = "disabled";
1758 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1759 reg = <0x0b024000 0x1000>;
1760 status = "disabled";
1765 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1766 reg = <0x0b025000 0x1000>;
1767 status = "disabled";
1772 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1773 reg = <0x0b026000 0x1000>;
1774 status = "disabled";
1779 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1780 reg = <0x0b027000 0x1000>;
1781 status = "disabled";
1786 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1787 reg = <0x0b028000 0x1000>;
1788 status = "disabled";
1795 polling-delay-passive = <250>;
1796 polling-delay = <1000>;
1798 thermal-sensors = <&tsens 5>;
1801 cpu0_1_alert0: trip-point0 {
1802 temperature = <75000>;
1803 hysteresis = <2000>;
1806 cpu0_1_crit: cpu_crit {
1807 temperature = <110000>;
1808 hysteresis = <2000>;
1815 trip = <&cpu0_1_alert0>;
1816 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1817 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1818 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1819 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1825 polling-delay-passive = <250>;
1826 polling-delay = <1000>;
1828 thermal-sensors = <&tsens 4>;
1831 cpu2_3_alert0: trip-point0 {
1832 temperature = <75000>;
1833 hysteresis = <2000>;
1836 cpu2_3_crit: cpu_crit {
1837 temperature = <110000>;
1838 hysteresis = <2000>;
1845 trip = <&cpu2_3_alert0>;
1846 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1847 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1848 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1849 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1855 polling-delay-passive = <250>;
1856 polling-delay = <1000>;
1858 thermal-sensors = <&tsens 2>;
1861 gpu_alert0: trip-point0 {
1862 temperature = <75000>;
1863 hysteresis = <2000>;
1866 gpu_crit: gpu_crit {
1867 temperature = <95000>;
1868 hysteresis = <2000>;
1875 polling-delay-passive = <250>;
1876 polling-delay = <1000>;
1878 thermal-sensors = <&tsens 1>;
1881 cam_alert0: trip-point0 {
1882 temperature = <75000>;
1883 hysteresis = <2000>;
1890 polling-delay-passive = <250>;
1891 polling-delay = <1000>;
1893 thermal-sensors = <&tsens 0>;
1896 modem_alert0: trip-point0 {
1897 temperature = <85000>;
1898 hysteresis = <2000>;
1907 compatible = "arm,armv8-timer";
1908 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1909 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1910 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1911 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1915 #include "msm8916-pins.dtsi"