1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/interconnect/qcom,msm8916.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
21 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
22 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
28 device_type = "memory";
29 /* We expect the bootloader to fill in the reg */
39 reg = <0x0 0x86000000 0x0 0x300000>;
43 smem_mem: smem_region@86300000 {
44 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
64 compatible = "qcom,rmtfs-mem";
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
76 mpss_mem: mpss@86800000 {
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
81 wcnss_mem: wcnss@89300000 {
82 reg = <0x0 0x89300000 0x0 0x600000>;
86 venus_mem: venus@89900000 {
87 reg = <0x0 0x89900000 0x0 0x600000>;
91 mba_mem: mba@8ea00000 {
93 reg = <0 0x8ea00000 0 0x100000>;
103 compatible = "arm,cortex-a53";
105 next-level-cache = <&L2_0>;
106 enable-method = "psci";
108 operating-points-v2 = <&cpu_opp_table>;
109 #cooling-cells = <2>;
110 power-domains = <&CPU_PD0>;
111 power-domain-names = "psci";
116 compatible = "arm,cortex-a53";
118 next-level-cache = <&L2_0>;
119 enable-method = "psci";
121 operating-points-v2 = <&cpu_opp_table>;
122 #cooling-cells = <2>;
123 power-domains = <&CPU_PD1>;
124 power-domain-names = "psci";
129 compatible = "arm,cortex-a53";
131 next-level-cache = <&L2_0>;
132 enable-method = "psci";
134 operating-points-v2 = <&cpu_opp_table>;
135 #cooling-cells = <2>;
136 power-domains = <&CPU_PD2>;
137 power-domain-names = "psci";
142 compatible = "arm,cortex-a53";
144 next-level-cache = <&L2_0>;
145 enable-method = "psci";
147 operating-points-v2 = <&cpu_opp_table>;
148 #cooling-cells = <2>;
149 power-domains = <&CPU_PD3>;
150 power-domain-names = "psci";
154 compatible = "cache";
159 entry-method = "psci";
161 CPU_SLEEP_0: cpu-sleep-0 {
162 compatible = "arm,idle-state";
163 idle-state-name = "standalone-power-collapse";
164 arm,psci-suspend-param = <0x40000002>;
165 entry-latency-us = <130>;
166 exit-latency-us = <150>;
167 min-residency-us = <2000>;
174 CLUSTER_RET: cluster-retention {
175 compatible = "domain-idle-state";
176 arm,psci-suspend-param = <0x41000012>;
177 entry-latency-us = <500>;
178 exit-latency-us = <500>;
179 min-residency-us = <2000>;
182 CLUSTER_PWRDN: cluster-gdhs {
183 compatible = "domain-idle-state";
184 arm,psci-suspend-param = <0x41000032>;
185 entry-latency-us = <2000>;
186 exit-latency-us = <2000>;
187 min-residency-us = <6000>;
193 compatible = "arm,psci-1.0";
196 CPU_PD0: power-domain-cpu0 {
197 #power-domain-cells = <0>;
198 power-domains = <&CLUSTER_PD>;
199 domain-idle-states = <&CPU_SLEEP_0>;
202 CPU_PD1: power-domain-cpu1 {
203 #power-domain-cells = <0>;
204 power-domains = <&CLUSTER_PD>;
205 domain-idle-states = <&CPU_SLEEP_0>;
208 CPU_PD2: power-domain-cpu2 {
209 #power-domain-cells = <0>;
210 power-domains = <&CLUSTER_PD>;
211 domain-idle-states = <&CPU_SLEEP_0>;
214 CPU_PD3: power-domain-cpu3 {
215 #power-domain-cells = <0>;
216 power-domains = <&CLUSTER_PD>;
217 domain-idle-states = <&CPU_SLEEP_0>;
220 CLUSTER_PD: power-domain-cluster {
221 #power-domain-cells = <0>;
222 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
227 compatible = "arm,cortex-a53-pmu";
228 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
233 polling-delay-passive = <250>;
234 polling-delay = <1000>;
236 thermal-sensors = <&tsens 5>;
239 cpu0_1_alert0: trip-point@0 {
240 temperature = <75000>;
244 cpu0_1_crit: cpu_crit {
245 temperature = <110000>;
253 trip = <&cpu0_1_alert0>;
254 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
257 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
263 polling-delay-passive = <250>;
264 polling-delay = <1000>;
266 thermal-sensors = <&tsens 4>;
269 cpu2_3_alert0: trip-point0 {
270 temperature = <75000>;
274 cpu2_3_crit: cpu_crit {
275 temperature = <110000>;
283 trip = <&cpu2_3_alert0>;
284 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
285 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
286 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
287 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
293 polling-delay-passive = <250>;
294 polling-delay = <1000>;
296 thermal-sensors = <&tsens 2>;
299 gpu_alert0: trip-point0 {
300 temperature = <75000>;
305 temperature = <95000>;
313 polling-delay-passive = <250>;
314 polling-delay = <1000>;
316 thermal-sensors = <&tsens 1>;
319 cam_alert0: trip-point0 {
320 temperature = <75000>;
328 polling-delay-passive = <250>;
329 polling-delay = <1000>;
331 thermal-sensors = <&tsens 0>;
334 modem_alert0: trip-point0 {
335 temperature = <85000>;
344 cpu_opp_table: cpu-opp-table {
345 compatible = "operating-points-v2";
349 opp-hz = /bits/ 64 <200000000>;
352 opp-hz = /bits/ 64 <400000000>;
355 opp-hz = /bits/ 64 <800000000>;
358 opp-hz = /bits/ 64 <998400000>;
363 compatible = "arm,armv8-timer";
364 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
365 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
366 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
367 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
372 compatible = "fixed-clock";
374 clock-frequency = <19200000>;
377 sleep_clk: sleep-clk {
378 compatible = "fixed-clock";
380 clock-frequency = <32768>;
385 compatible = "qcom,smem";
387 memory-region = <&smem_mem>;
388 qcom,rpm-msg-ram = <&rpm_msg_ram>;
390 hwlocks = <&tcsr_mutex 3>;
395 compatible = "qcom,scm";
396 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
397 clock-names = "core", "bus", "iface";
400 qcom,dload-mode = <&tcsr 0x6100>;
405 #address-cells = <1>;
407 ranges = <0 0 0 0xffffffff>;
408 compatible = "simple-bus";
410 bimc: interconnect@400000 {
411 compatible = "qcom,msm8916-bimc";
412 reg = <0x00400000 0x62000>;
413 #interconnect-cells = <1>;
414 clock-names = "bus", "bus_a";
415 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
416 <&rpmcc RPM_SMD_BIMC_A_CLK>;
420 compatible = "qcom,pshold";
421 reg = <0x4ab000 0x4>;
424 pcnoc: interconnect@500000 {
425 compatible = "qcom,msm8916-pcnoc";
426 reg = <0x00500000 0x11000>;
427 #interconnect-cells = <1>;
428 clock-names = "bus", "bus_a";
429 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
430 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
433 snoc: interconnect@580000 {
434 compatible = "qcom,msm8916-snoc";
435 reg = <0x00580000 0x14000>;
436 #interconnect-cells = <1>;
437 clock-names = "bus", "bus_a";
438 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
439 <&rpmcc RPM_SMD_SNOC_A_CLK>;
442 msmgpio: pinctrl@1000000 {
443 compatible = "qcom,msm8916-pinctrl";
444 reg = <0x1000000 0x300000>;
445 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
447 gpio-ranges = <&msmgpio 0 0 122>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
453 gcc: clock-controller@1800000 {
454 compatible = "qcom,gcc-msm8916";
457 #power-domain-cells = <1>;
458 reg = <0x1800000 0x80000>;
461 tcsr_mutex_regs: syscon@1905000 {
462 compatible = "syscon";
463 reg = <0x1905000 0x20000>;
466 tcsr: syscon@1937000 {
467 compatible = "qcom,tcsr-msm8916", "syscon";
468 reg = <0x1937000 0x30000>;
472 compatible = "qcom,tcsr-mutex";
473 syscon = <&tcsr_mutex_regs 0 0x1000>;
477 rpm_msg_ram: memory@60000 {
478 compatible = "qcom,rpm-msg-ram";
479 reg = <0x60000 0x8000>;
482 blsp1_uart1: serial@78af000 {
483 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
484 reg = <0x78af000 0x200>;
485 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
487 clock-names = "core", "iface";
488 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
489 dma-names = "rx", "tx";
493 a53pll: clock@b016000 {
494 compatible = "qcom,msm8916-a53pll";
495 reg = <0xb016000 0x40>;
499 apcs: mailbox@b011000 {
500 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
501 reg = <0xb011000 0x1000>;
503 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
504 clock-names = "pll", "aux";
508 blsp1_uart2: serial@78b0000 {
509 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
510 reg = <0x78b0000 0x200>;
511 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
513 clock-names = "core", "iface";
514 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
515 dma-names = "rx", "tx";
519 blsp_dma: dma@7884000 {
520 compatible = "qcom,bam-v1.7.0";
521 reg = <0x07884000 0x23000>;
522 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
524 clock-names = "bam_clk";
530 blsp_spi1: spi@78b5000 {
531 compatible = "qcom,spi-qup-v2.2.1";
532 reg = <0x078b5000 0x500>;
533 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
535 <&gcc GCC_BLSP1_AHB_CLK>;
536 clock-names = "core", "iface";
537 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
538 dma-names = "rx", "tx";
539 pinctrl-names = "default", "sleep";
540 pinctrl-0 = <&spi1_default>;
541 pinctrl-1 = <&spi1_sleep>;
542 #address-cells = <1>;
547 blsp_spi2: spi@78b6000 {
548 compatible = "qcom,spi-qup-v2.2.1";
549 reg = <0x078b6000 0x500>;
550 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
552 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", "iface";
554 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
555 dma-names = "rx", "tx";
556 pinctrl-names = "default", "sleep";
557 pinctrl-0 = <&spi2_default>;
558 pinctrl-1 = <&spi2_sleep>;
559 #address-cells = <1>;
564 blsp_spi3: spi@78b7000 {
565 compatible = "qcom,spi-qup-v2.2.1";
566 reg = <0x078b7000 0x500>;
567 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
569 <&gcc GCC_BLSP1_AHB_CLK>;
570 clock-names = "core", "iface";
571 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
572 dma-names = "rx", "tx";
573 pinctrl-names = "default", "sleep";
574 pinctrl-0 = <&spi3_default>;
575 pinctrl-1 = <&spi3_sleep>;
576 #address-cells = <1>;
581 blsp_spi4: spi@78b8000 {
582 compatible = "qcom,spi-qup-v2.2.1";
583 reg = <0x078b8000 0x500>;
584 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
586 <&gcc GCC_BLSP1_AHB_CLK>;
587 clock-names = "core", "iface";
588 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
589 dma-names = "rx", "tx";
590 pinctrl-names = "default", "sleep";
591 pinctrl-0 = <&spi4_default>;
592 pinctrl-1 = <&spi4_sleep>;
593 #address-cells = <1>;
598 blsp_spi5: spi@78b9000 {
599 compatible = "qcom,spi-qup-v2.2.1";
600 reg = <0x078b9000 0x500>;
601 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
603 <&gcc GCC_BLSP1_AHB_CLK>;
604 clock-names = "core", "iface";
605 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
606 dma-names = "rx", "tx";
607 pinctrl-names = "default", "sleep";
608 pinctrl-0 = <&spi5_default>;
609 pinctrl-1 = <&spi5_sleep>;
610 #address-cells = <1>;
615 blsp_spi6: spi@78ba000 {
616 compatible = "qcom,spi-qup-v2.2.1";
617 reg = <0x078ba000 0x500>;
618 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
620 <&gcc GCC_BLSP1_AHB_CLK>;
621 clock-names = "core", "iface";
622 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
623 dma-names = "rx", "tx";
624 pinctrl-names = "default", "sleep";
625 pinctrl-0 = <&spi6_default>;
626 pinctrl-1 = <&spi6_sleep>;
627 #address-cells = <1>;
632 blsp_i2c1: i2c@78b5000 {
633 compatible = "qcom,i2c-qup-v2.2.1";
634 reg = <0x078b5000 0x500>;
635 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
637 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
638 clock-names = "iface", "core";
639 pinctrl-names = "default", "sleep";
640 pinctrl-0 = <&i2c1_default>;
641 pinctrl-1 = <&i2c1_sleep>;
642 #address-cells = <1>;
647 blsp_i2c2: i2c@78b6000 {
648 compatible = "qcom,i2c-qup-v2.2.1";
649 reg = <0x078b6000 0x500>;
650 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
652 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
653 clock-names = "iface", "core";
654 pinctrl-names = "default", "sleep";
655 pinctrl-0 = <&i2c2_default>;
656 pinctrl-1 = <&i2c2_sleep>;
657 #address-cells = <1>;
662 blsp_i2c4: i2c@78b8000 {
663 compatible = "qcom,i2c-qup-v2.2.1";
664 reg = <0x078b8000 0x500>;
665 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
667 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
668 clock-names = "iface", "core";
669 pinctrl-names = "default", "sleep";
670 pinctrl-0 = <&i2c4_default>;
671 pinctrl-1 = <&i2c4_sleep>;
672 #address-cells = <1>;
677 blsp_i2c5: i2c@78b9000 {
678 compatible = "qcom,i2c-qup-v2.2.1";
679 reg = <0x078b9000 0x500>;
680 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
682 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
683 clock-names = "iface", "core";
684 pinctrl-names = "default", "sleep";
685 pinctrl-0 = <&i2c5_default>;
686 pinctrl-1 = <&i2c5_sleep>;
687 #address-cells = <1>;
692 blsp_i2c6: i2c@78ba000 {
693 compatible = "qcom,i2c-qup-v2.2.1";
694 reg = <0x078ba000 0x500>;
695 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
697 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
698 clock-names = "iface", "core";
699 pinctrl-names = "default", "sleep";
700 pinctrl-0 = <&i2c6_default>;
701 pinctrl-1 = <&i2c6_sleep>;
702 #address-cells = <1>;
707 lpass: lpass@7708000 {
709 compatible = "qcom,lpass-cpu-apq8016";
710 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
711 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
712 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
713 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
714 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
715 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
716 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
718 clock-names = "ahbix-clk",
725 #sound-dai-cells = <1>;
727 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
728 interrupt-names = "lpass-irq-lpaif";
729 reg = <0x07708000 0x10000>;
730 reg-names = "lpass-lpaif";
732 #address-cells = <1>;
737 compatible = "qcom,msm8916-wcd-digital-codec";
738 reg = <0x0771c000 0x400>;
739 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
740 <&gcc GCC_CODEC_DIGCODEC_CLK>;
741 clock-names = "ahbix-clk", "mclk";
742 #sound-dai-cells = <1>;
745 sdhc_1: sdhci@7824000 {
746 compatible = "qcom,sdhci-msm-v4";
747 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
748 reg-names = "hc_mem", "core_mem";
750 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "hc_irq", "pwr_irq";
752 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
753 <&gcc GCC_SDCC1_AHB_CLK>,
755 clock-names = "core", "iface", "xo";
762 sdhc_2: sdhci@7864000 {
763 compatible = "qcom,sdhci-msm-v4";
764 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
765 reg-names = "hc_mem", "core_mem";
767 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-names = "hc_irq", "pwr_irq";
769 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
770 <&gcc GCC_SDCC2_AHB_CLK>,
772 clock-names = "core", "iface", "xo";
778 compatible = "qcom,ci-hdrc";
779 reg = <0x78d9000 0x200>,
781 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
784 <&gcc GCC_USB_HS_SYSTEM_CLK>;
785 clock-names = "iface", "core";
786 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
787 assigned-clock-rates = <80000000>;
788 resets = <&gcc GCC_USB_HS_BCR>;
789 reset-names = "core";
792 ahb-burst-config = <0>;
793 phy-names = "usb-phy";
794 phys = <&usb_hs_phy>;
800 compatible = "qcom,usb-hs-phy-msm8916",
803 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
804 clock-names = "ref", "sleep";
805 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
806 reset-names = "phy", "por";
807 qcom,init-seq = /bits/ 8 <0x0 0x44
808 0x1 0x6b 0x2 0x24 0x3 0x13>;
813 intc: interrupt-controller@b000000 {
814 compatible = "qcom,msm-qgic2";
815 interrupt-controller;
816 #interrupt-cells = <3>;
817 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
821 #address-cells = <1>;
824 compatible = "arm,armv7-timer-mem";
825 reg = <0xb020000 0x1000>;
826 clock-frequency = <19200000>;
830 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
832 reg = <0xb021000 0x1000>,
838 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
839 reg = <0xb023000 0x1000>;
845 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
846 reg = <0xb024000 0x1000>;
852 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
853 reg = <0xb025000 0x1000>;
859 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
860 reg = <0xb026000 0x1000>;
866 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
867 reg = <0xb027000 0x1000>;
873 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
874 reg = <0xb028000 0x1000>;
879 spmi_bus: spmi@200f000 {
880 compatible = "qcom,spmi-pmic-arb";
881 reg = <0x200f000 0x001000>,
882 <0x2400000 0x400000>,
883 <0x2c00000 0x400000>,
884 <0x3800000 0x200000>,
885 <0x200a000 0x002100>;
886 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
887 interrupt-names = "periph_irq";
888 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
891 #address-cells = <2>;
893 interrupt-controller;
894 #interrupt-cells = <4>;
898 compatible = "qcom,prng";
899 reg = <0x00022000 0x200>;
900 clocks = <&gcc GCC_PRNG_AHB_CLK>;
901 clock-names = "core";
904 qfprom: qfprom@5c000 {
905 compatible = "qcom,qfprom";
906 reg = <0x5c000 0x1000>;
907 #address-cells = <1>;
909 tsens_caldata: caldata@d0 {
912 tsens_calsel: calsel@ec {
917 tsens: thermal-sensor@4a9000 {
918 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
919 reg = <0x4a9000 0x1000>, /* TM */
920 <0x4a8000 0x1000>; /* SROT */
921 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
922 nvmem-cell-names = "calib", "calib_sel";
924 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
925 interrupt-names = "uplow";
926 #thermal-sensor-cells = <1>;
929 apps_iommu: iommu@1ef0000 {
930 #address-cells = <1>;
933 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
934 ranges = <0 0x1e20000 0x40000>;
935 reg = <0x1ef0000 0x3000>;
936 clocks = <&gcc GCC_SMMU_CFG_CLK>,
937 <&gcc GCC_APSS_TCU_CLK>;
938 clock-names = "iface", "bus";
939 qcom,iommu-secure-id = <17>;
943 compatible = "qcom,msm-iommu-v1-sec";
944 reg = <0x3000 0x1000>;
945 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
950 compatible = "qcom,msm-iommu-v1-ns";
951 reg = <0x4000 0x1000>;
952 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
957 compatible = "qcom,msm-iommu-v1-sec";
958 reg = <0x5000 0x1000>;
959 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
963 gpu_iommu: iommu@1f08000 {
964 #address-cells = <1>;
967 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
968 ranges = <0 0x1f08000 0x10000>;
969 clocks = <&gcc GCC_SMMU_CFG_CLK>,
970 <&gcc GCC_GFX_TCU_CLK>;
971 clock-names = "iface", "bus";
972 qcom,iommu-secure-id = <18>;
976 compatible = "qcom,msm-iommu-v1-ns";
977 reg = <0x1000 0x1000>;
978 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
983 compatible = "qcom,msm-iommu-v1-ns";
984 reg = <0x2000 0x1000>;
985 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
990 compatible = "qcom,adreno-306.0", "qcom,adreno";
991 reg = <0x01c00000 0x20000>;
992 reg-names = "kgsl_3d0_reg_memory";
993 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
994 interrupt-names = "kgsl_3d0_irq";
1003 <&gcc GCC_OXILI_GFX3D_CLK>,
1004 <&gcc GCC_OXILI_AHB_CLK>,
1005 <&gcc GCC_OXILI_GMEM_CLK>,
1006 <&gcc GCC_BIMC_GFX_CLK>,
1007 <&gcc GCC_BIMC_GPU_CLK>,
1008 <&gcc GFX3D_CLK_SRC>;
1009 power-domains = <&gcc OXILI_GDSC>;
1010 operating-points-v2 = <&gpu_opp_table>;
1011 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1013 gpu_opp_table: opp-table {
1014 compatible = "operating-points-v2";
1017 opp-hz = /bits/ 64 <400000000>;
1020 opp-hz = /bits/ 64 <19200000>;
1025 mdss: mdss@1a00000 {
1026 compatible = "qcom,mdss";
1027 reg = <0x1a00000 0x1000>,
1029 reg-names = "mdss_phys", "vbif_phys";
1031 power-domains = <&gcc MDSS_GDSC>;
1033 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1034 <&gcc GCC_MDSS_AXI_CLK>,
1035 <&gcc GCC_MDSS_VSYNC_CLK>;
1036 clock-names = "iface",
1040 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
1042 interrupt-controller;
1043 #interrupt-cells = <1>;
1045 #address-cells = <1>;
1050 compatible = "qcom,mdp5";
1051 reg = <0x1a01000 0x89000>;
1052 reg-names = "mdp_phys";
1054 interrupt-parent = <&mdss>;
1057 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1058 <&gcc GCC_MDSS_AXI_CLK>,
1059 <&gcc GCC_MDSS_MDP_CLK>,
1060 <&gcc GCC_MDSS_VSYNC_CLK>;
1061 clock-names = "iface",
1066 iommus = <&apps_iommu 4>;
1069 #address-cells = <1>;
1074 mdp5_intf1_out: endpoint {
1075 remote-endpoint = <&dsi0_in>;
1082 compatible = "qcom,mdss-dsi-ctrl";
1083 reg = <0x1a98000 0x25c>;
1084 reg-names = "dsi_ctrl";
1086 interrupt-parent = <&mdss>;
1089 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1090 <&gcc PCLK0_CLK_SRC>;
1091 assigned-clock-parents = <&dsi_phy0 0>,
1094 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1095 <&gcc GCC_MDSS_AHB_CLK>,
1096 <&gcc GCC_MDSS_AXI_CLK>,
1097 <&gcc GCC_MDSS_BYTE0_CLK>,
1098 <&gcc GCC_MDSS_PCLK0_CLK>,
1099 <&gcc GCC_MDSS_ESC0_CLK>;
1100 clock-names = "mdp_core",
1107 phy-names = "dsi-phy";
1110 #address-cells = <1>;
1116 remote-endpoint = <&mdp5_intf1_out>;
1122 dsi0_out: endpoint {
1128 dsi_phy0: dsi-phy@1a98300 {
1129 compatible = "qcom,dsi-phy-28nm-lp";
1130 reg = <0x1a98300 0xd4>,
1133 reg-names = "dsi_pll",
1135 "dsi_phy_regulator";
1140 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1142 clock-names = "iface", "ref";
1148 compatible = "qcom,q6v5-pil";
1149 reg = <0x04080000 0x100>,
1152 reg-names = "qdsp6", "rmb";
1154 interrupts-extended = <&intc 0 24 1>,
1155 <&hexagon_smp2p_in 0 0>,
1156 <&hexagon_smp2p_in 1 0>,
1157 <&hexagon_smp2p_in 2 0>,
1158 <&hexagon_smp2p_in 3 0>;
1159 interrupt-names = "wdog", "fatal", "ready",
1160 "handover", "stop-ack";
1162 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1163 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1164 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1166 clock-names = "iface", "bus", "mem", "xo";
1168 qcom,smem-states = <&hexagon_smp2p_out 0>;
1169 qcom,smem-state-names = "stop";
1172 reset-names = "mss_restart";
1174 cx-supply = <&pm8916_s1>;
1175 mx-supply = <&pm8916_l3>;
1176 pll-supply = <&pm8916_l7>;
1178 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1180 status = "disabled";
1183 memory-region = <&mba_mem>;
1187 memory-region = <&mpss_mem>;
1191 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1193 qcom,smd-edge = <0>;
1194 qcom,ipc = <&apcs 8 12>;
1195 qcom,remote-pid = <1>;
1200 compatible = "qcom,fastrpc";
1201 qcom,smd-channels = "fastrpcsmd-apps-dsp";
1204 #address-cells = <1>;
1208 compatible = "qcom,fastrpc-compute-cb";
1215 pronto: wcnss@a21b000 {
1216 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1217 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1218 reg-names = "ccu", "dxe", "pmu";
1220 memory-region = <&wcnss_mem>;
1222 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1223 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1224 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1225 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1226 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1227 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1229 vddmx-supply = <&pm8916_l3>;
1230 vddpx-supply = <&pm8916_l7>;
1232 qcom,state = <&wcnss_smp2p_out 0>;
1233 qcom,state-names = "stop";
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&wcnss_pin_a>;
1238 status = "disabled";
1241 compatible = "qcom,wcn3620";
1243 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1246 vddxo-supply = <&pm8916_l7>;
1247 vddrfa-supply = <&pm8916_s3>;
1248 vddpa-supply = <&pm8916_l9>;
1249 vdddig-supply = <&pm8916_l5>;
1253 interrupts = <0 142 1>;
1255 qcom,ipc = <&apcs 8 17>;
1256 qcom,smd-edge = <6>;
1257 qcom,remote-pid = <4>;
1262 compatible = "qcom,wcnss";
1263 qcom,smd-channels = "WCNSS_CTRL";
1265 qcom,mmio = <&pronto>;
1268 compatible = "qcom,wcnss-bt";
1272 compatible = "qcom,wcnss-wlan";
1274 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1275 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1276 interrupt-names = "tx", "rx";
1278 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1279 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1286 compatible = "arm,coresight-tpiu", "arm,primecell";
1287 reg = <0x820000 0x1000>;
1289 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1290 clock-names = "apb_pclk", "atclk";
1292 status = "disabled";
1297 remote-endpoint = <&replicator_out1>;
1304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1305 reg = <0x821000 0x1000>;
1307 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1308 clock-names = "apb_pclk", "atclk";
1310 status = "disabled";
1313 #address-cells = <1>;
1317 * Not described input ports:
1318 * 0 - connected to Resource and Power Manger CPU ETM
1320 * 2 - connected to Modem CPU ETM
1323 * 6 - connected trought funnel to Wireless CPU ETM
1324 * 7 - connected to STM component
1329 funnel0_in4: endpoint {
1330 remote-endpoint = <&funnel1_out>;
1337 funnel0_out: endpoint {
1338 remote-endpoint = <&etf_in>;
1345 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1346 reg = <0x824000 0x1000>;
1348 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1349 clock-names = "apb_pclk", "atclk";
1351 status = "disabled";
1354 #address-cells = <1>;
1359 replicator_out0: endpoint {
1360 remote-endpoint = <&etr_in>;
1365 replicator_out1: endpoint {
1366 remote-endpoint = <&tpiu_in>;
1373 replicator_in: endpoint {
1374 remote-endpoint = <&etf_out>;
1381 compatible = "arm,coresight-tmc", "arm,primecell";
1382 reg = <0x825000 0x1000>;
1384 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1385 clock-names = "apb_pclk", "atclk";
1387 status = "disabled";
1392 remote-endpoint = <&funnel0_out>;
1400 remote-endpoint = <&replicator_in>;
1407 compatible = "arm,coresight-tmc", "arm,primecell";
1408 reg = <0x826000 0x1000>;
1410 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1411 clock-names = "apb_pclk", "atclk";
1413 status = "disabled";
1418 remote-endpoint = <&replicator_out0>;
1424 funnel@841000 { /* APSS funnel only 4 inputs are used */
1425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1426 reg = <0x841000 0x1000>;
1428 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1429 clock-names = "apb_pclk", "atclk";
1431 status = "disabled";
1434 #address-cells = <1>;
1439 funnel1_in0: endpoint {
1440 remote-endpoint = <&etm0_out>;
1445 funnel1_in1: endpoint {
1446 remote-endpoint = <&etm1_out>;
1451 funnel1_in2: endpoint {
1452 remote-endpoint = <&etm2_out>;
1457 funnel1_in3: endpoint {
1458 remote-endpoint = <&etm3_out>;
1465 funnel1_out: endpoint {
1466 remote-endpoint = <&funnel0_in4>;
1473 compatible = "arm,coresight-cpu-debug","arm,primecell";
1474 reg = <0x850000 0x1000>;
1475 clocks = <&rpmcc RPM_QDSS_CLK>;
1476 clock-names = "apb_pclk";
1478 status = "disabled";
1482 compatible = "arm,coresight-cpu-debug","arm,primecell";
1483 reg = <0x852000 0x1000>;
1484 clocks = <&rpmcc RPM_QDSS_CLK>;
1485 clock-names = "apb_pclk";
1487 status = "disabled";
1491 compatible = "arm,coresight-cpu-debug","arm,primecell";
1492 reg = <0x854000 0x1000>;
1493 clocks = <&rpmcc RPM_QDSS_CLK>;
1494 clock-names = "apb_pclk";
1496 status = "disabled";
1500 compatible = "arm,coresight-cpu-debug","arm,primecell";
1501 reg = <0x856000 0x1000>;
1502 clocks = <&rpmcc RPM_QDSS_CLK>;
1503 clock-names = "apb_pclk";
1505 status = "disabled";
1509 compatible = "arm,coresight-etm4x", "arm,primecell";
1510 reg = <0x85c000 0x1000>;
1512 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1513 clock-names = "apb_pclk", "atclk";
1514 arm,coresight-loses-context-with-cpu;
1518 status = "disabled";
1522 etm0_out: endpoint {
1523 remote-endpoint = <&funnel1_in0>;
1530 compatible = "arm,coresight-etm4x", "arm,primecell";
1531 reg = <0x85d000 0x1000>;
1533 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1534 clock-names = "apb_pclk", "atclk";
1535 arm,coresight-loses-context-with-cpu;
1539 status = "disabled";
1543 etm1_out: endpoint {
1544 remote-endpoint = <&funnel1_in1>;
1551 compatible = "arm,coresight-etm4x", "arm,primecell";
1552 reg = <0x85e000 0x1000>;
1554 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1555 clock-names = "apb_pclk", "atclk";
1556 arm,coresight-loses-context-with-cpu;
1560 status = "disabled";
1564 etm2_out: endpoint {
1565 remote-endpoint = <&funnel1_in2>;
1572 compatible = "arm,coresight-etm4x", "arm,primecell";
1573 reg = <0x85f000 0x1000>;
1575 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1576 clock-names = "apb_pclk", "atclk";
1577 arm,coresight-loses-context-with-cpu;
1581 status = "disabled";
1585 etm3_out: endpoint {
1586 remote-endpoint = <&funnel1_in3>;
1593 /* CTI 0 - TMC connections */
1595 compatible = "arm,coresight-cti", "arm,primecell";
1596 reg = <0x810000 0x1000>;
1598 clocks = <&rpmcc RPM_QDSS_CLK>;
1599 clock-names = "apb_pclk";
1601 status = "disabled";
1604 /* CTI 1 - TPIU connections */
1606 compatible = "arm,coresight-cti", "arm,primecell";
1607 reg = <0x811000 0x1000>;
1609 clocks = <&rpmcc RPM_QDSS_CLK>;
1610 clock-names = "apb_pclk";
1612 status = "disabled";
1615 /* CTIs 2-11 - no information - not instantiated */
1617 /* Core CTIs; CTIs 12-15 */
1620 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1622 reg = <0x858000 0x1000>;
1624 clocks = <&rpmcc RPM_QDSS_CLK>;
1625 clock-names = "apb_pclk";
1628 arm,cs-dev-assoc = <&etm0>;
1630 status = "disabled";
1635 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1637 reg = <0x859000 0x1000>;
1639 clocks = <&rpmcc RPM_QDSS_CLK>;
1640 clock-names = "apb_pclk";
1643 arm,cs-dev-assoc = <&etm1>;
1645 status = "disabled";
1650 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1652 reg = <0x85a000 0x1000>;
1654 clocks = <&rpmcc RPM_QDSS_CLK>;
1655 clock-names = "apb_pclk";
1658 arm,cs-dev-assoc = <&etm2>;
1660 status = "disabled";
1665 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1667 reg = <0x85b000 0x1000>;
1669 clocks = <&rpmcc RPM_QDSS_CLK>;
1670 clock-names = "apb_pclk";
1673 arm,cs-dev-assoc = <&etm3>;
1675 status = "disabled";
1679 venus: video-codec@1d00000 {
1680 compatible = "qcom,msm8916-venus";
1681 reg = <0x01d00000 0xff000>;
1682 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1683 power-domains = <&gcc VENUS_GDSC>;
1684 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1685 <&gcc GCC_VENUS0_AHB_CLK>,
1686 <&gcc GCC_VENUS0_AXI_CLK>;
1687 clock-names = "core", "iface", "bus";
1688 iommus = <&apps_iommu 5>;
1689 memory-region = <&venus_mem>;
1693 compatible = "venus-decoder";
1697 compatible = "venus-encoder";
1701 camss: camss@1b00000 {
1702 compatible = "qcom,msm8916-camss";
1703 reg = <0x1b0ac00 0x200>,
1712 reg-names = "csiphy0",
1721 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1722 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1723 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1724 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1725 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1726 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1727 interrupt-names = "csiphy0",
1733 power-domains = <&gcc VFE_GDSC>;
1734 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1735 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1736 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1737 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1738 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1739 <&gcc GCC_CAMSS_CSI0_CLK>,
1740 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1741 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1742 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1743 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1744 <&gcc GCC_CAMSS_CSI1_CLK>,
1745 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1746 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1747 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1748 <&gcc GCC_CAMSS_AHB_CLK>,
1749 <&gcc GCC_CAMSS_VFE0_CLK>,
1750 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1751 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1752 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1753 clock-names = "top_ahb",
1772 vdda-supply = <&pm8916_l2>;
1773 iommus = <&apps_iommu 3>;
1774 status = "disabled";
1776 #address-cells = <1>;
1782 compatible = "qcom,msm8916-cci";
1783 #address-cells = <1>;
1785 reg = <0x1b0c000 0x1000>;
1786 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1787 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1788 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1789 <&gcc GCC_CAMSS_CCI_CLK>,
1790 <&gcc GCC_CAMSS_AHB_CLK>;
1791 clock-names = "camss_top_ahb", "cci_ahb",
1793 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1794 <&gcc GCC_CAMSS_CCI_CLK>;
1795 assigned-clock-rates = <80000000>, <19200000>;
1796 pinctrl-names = "default";
1797 pinctrl-0 = <&cci0_default>;
1798 status = "disabled";
1800 cci_i2c0: i2c-bus@0 {
1802 clock-frequency = <400000>;
1803 #address-cells = <1>;
1810 compatible = "qcom,smd";
1813 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1814 qcom,ipc = <&apcs 8 0>;
1815 qcom,smd-edge = <15>;
1818 compatible = "qcom,rpm-msm8916";
1819 qcom,smd-channels = "rpm_requests";
1822 compatible = "qcom,rpmcc-msm8916";
1826 smd_rpm_regulators: pm8916-regulators {
1827 compatible = "qcom,rpm-pm8916-regulators";
1857 compatible = "qcom,smp2p";
1858 qcom,smem = <435>, <428>;
1860 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1862 qcom,ipc = <&apcs 8 14>;
1864 qcom,local-pid = <0>;
1865 qcom,remote-pid = <1>;
1867 hexagon_smp2p_out: master-kernel {
1868 qcom,entry-name = "master-kernel";
1870 #qcom,smem-state-cells = <1>;
1873 hexagon_smp2p_in: slave-kernel {
1874 qcom,entry-name = "slave-kernel";
1876 interrupt-controller;
1877 #interrupt-cells = <2>;
1882 compatible = "qcom,smp2p";
1883 qcom,smem = <451>, <431>;
1885 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1887 qcom,ipc = <&apcs 8 18>;
1889 qcom,local-pid = <0>;
1890 qcom,remote-pid = <4>;
1892 wcnss_smp2p_out: master-kernel {
1893 qcom,entry-name = "master-kernel";
1895 #qcom,smem-state-cells = <1>;
1898 wcnss_smp2p_in: slave-kernel {
1899 qcom,entry-name = "slave-kernel";
1901 interrupt-controller;
1902 #interrupt-cells = <2>;
1907 compatible = "qcom,smsm";
1909 #address-cells = <1>;
1912 qcom,ipc-1 = <&apcs 8 13>;
1913 qcom,ipc-3 = <&apcs 8 19>;
1918 #qcom,smem-state-cells = <1>;
1921 hexagon_smsm: hexagon@1 {
1923 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1925 interrupt-controller;
1926 #interrupt-cells = <2>;
1929 wcnss_smsm: wcnss@6 {
1931 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1933 interrupt-controller;
1934 #interrupt-cells = <2>;
1939 #include "msm8916-pins.dtsi"