1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/thermal/thermal.h>
13 interrupt-parent = <&intc>;
19 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
20 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
26 device_type = "memory";
27 /* We expect the bootloader to fill in the reg */
37 reg = <0x0 0x86000000 0x0 0x300000>;
41 smem_mem: smem_region@86300000 {
42 reg = <0x0 0x86300000 0x0 0x100000>;
47 reg = <0x0 0x86400000 0x0 0x100000>;
52 reg = <0x0 0x86500000 0x0 0x180000>;
57 reg = <0x0 0x86680000 0x0 0x80000>;
62 compatible = "qcom,rmtfs-mem";
63 reg = <0x0 0x86700000 0x0 0xe0000>;
70 reg = <0x0 0x867e0000 0x0 0x20000>;
74 mpss_mem: mpss@86800000 {
75 reg = <0x0 0x86800000 0x0 0x2b00000>;
79 wcnss_mem: wcnss@89300000 {
80 reg = <0x0 0x89300000 0x0 0x600000>;
84 venus_mem: venus@89900000 {
85 reg = <0x0 0x89900000 0x0 0x600000>;
89 mba_mem: mba@8ea00000 {
91 reg = <0 0x8ea00000 0 0x100000>;
101 compatible = "arm,cortex-a53";
103 next-level-cache = <&L2_0>;
104 enable-method = "psci";
106 operating-points-v2 = <&cpu_opp_table>;
107 #cooling-cells = <2>;
108 power-domains = <&CPU_PD0>;
109 power-domain-names = "psci";
114 compatible = "arm,cortex-a53";
116 next-level-cache = <&L2_0>;
117 enable-method = "psci";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 power-domains = <&CPU_PD1>;
122 power-domain-names = "psci";
127 compatible = "arm,cortex-a53";
129 next-level-cache = <&L2_0>;
130 enable-method = "psci";
132 operating-points-v2 = <&cpu_opp_table>;
133 #cooling-cells = <2>;
134 power-domains = <&CPU_PD2>;
135 power-domain-names = "psci";
140 compatible = "arm,cortex-a53";
142 next-level-cache = <&L2_0>;
143 enable-method = "psci";
145 operating-points-v2 = <&cpu_opp_table>;
146 #cooling-cells = <2>;
147 power-domains = <&CPU_PD3>;
148 power-domain-names = "psci";
152 compatible = "cache";
157 entry-method = "psci";
159 CPU_SLEEP_0: cpu-sleep-0 {
160 compatible = "arm,idle-state";
161 idle-state-name = "standalone-power-collapse";
162 arm,psci-suspend-param = <0x40000002>;
163 entry-latency-us = <130>;
164 exit-latency-us = <150>;
165 min-residency-us = <2000>;
169 CLUSTER_RET: cluster-retention {
170 compatible = "domain-idle-state";
171 arm,psci-suspend-param = <0x41000012>;
172 entry-latency-us = <500>;
173 exit-latency-us = <500>;
174 min-residency-us = <2000>;
177 CLUSTER_PWRDN: cluster-gdhs {
178 compatible = "domain-idle-state";
179 arm,psci-suspend-param = <0x41000032>;
180 entry-latency-us = <2000>;
181 exit-latency-us = <2000>;
182 min-residency-us = <6000>;
188 compatible = "arm,psci-1.0";
192 #power-domain-cells = <0>;
193 power-domains = <&CLUSTER_PD>;
194 domain-idle-states = <&CPU_SLEEP_0>;
198 #power-domain-cells = <0>;
199 power-domains = <&CLUSTER_PD>;
200 domain-idle-states = <&CPU_SLEEP_0>;
204 #power-domain-cells = <0>;
205 power-domains = <&CLUSTER_PD>;
206 domain-idle-states = <&CPU_SLEEP_0>;
210 #power-domain-cells = <0>;
211 power-domains = <&CLUSTER_PD>;
212 domain-idle-states = <&CPU_SLEEP_0>;
215 CLUSTER_PD: cluster-pd {
216 #power-domain-cells = <0>;
217 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
222 compatible = "arm,cortex-a53-pmu";
223 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
228 polling-delay-passive = <250>;
229 polling-delay = <1000>;
231 thermal-sensors = <&tsens 5>;
234 cpu0_1_alert0: trip-point@0 {
235 temperature = <75000>;
239 cpu0_1_crit: cpu_crit {
240 temperature = <110000>;
248 trip = <&cpu0_1_alert0>;
249 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
258 polling-delay-passive = <250>;
259 polling-delay = <1000>;
261 thermal-sensors = <&tsens 4>;
264 cpu2_3_alert0: trip-point@0 {
265 temperature = <75000>;
269 cpu2_3_crit: cpu_crit {
270 temperature = <110000>;
278 trip = <&cpu2_3_alert0>;
279 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
280 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
281 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
282 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
288 polling-delay-passive = <250>;
289 polling-delay = <1000>;
291 thermal-sensors = <&tsens 2>;
294 gpu_alert0: trip-point@0 {
295 temperature = <75000>;
300 temperature = <95000>;
308 polling-delay-passive = <250>;
309 polling-delay = <1000>;
311 thermal-sensors = <&tsens 1>;
314 cam_alert0: trip-point@0 {
315 temperature = <75000>;
323 polling-delay-passive = <250>;
324 polling-delay = <1000>;
326 thermal-sensors = <&tsens 0>;
329 modem_alert0: trip-point@0 {
330 temperature = <85000>;
339 cpu_opp_table: cpu_opp_table {
340 compatible = "operating-points-v2";
344 opp-hz = /bits/ 64 <200000000>;
347 opp-hz = /bits/ 64 <400000000>;
350 opp-hz = /bits/ 64 <800000000>;
353 opp-hz = /bits/ 64 <998400000>;
357 gpu_opp_table: opp_table {
358 compatible = "operating-points-v2";
361 opp-hz = /bits/ 64 <400000000>;
364 opp-hz = /bits/ 64 <19200000>;
369 compatible = "arm,armv8-timer";
370 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
371 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
372 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
373 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
378 compatible = "fixed-clock";
380 clock-frequency = <19200000>;
383 sleep_clk: sleep_clk {
384 compatible = "fixed-clock";
386 clock-frequency = <32768>;
391 compatible = "qcom,smem";
393 memory-region = <&smem_mem>;
394 qcom,rpm-msg-ram = <&rpm_msg_ram>;
396 hwlocks = <&tcsr_mutex 3>;
401 compatible = "qcom,scm";
402 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
403 clock-names = "core", "bus", "iface";
406 qcom,dload-mode = <&tcsr 0x6100>;
411 #address-cells = <1>;
413 ranges = <0 0 0 0xffffffff>;
414 compatible = "simple-bus";
417 compatible = "qcom,pshold";
418 reg = <0x4ab000 0x4>;
421 msmgpio: pinctrl@1000000 {
422 compatible = "qcom,msm8916-pinctrl";
423 reg = <0x1000000 0x300000>;
424 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
426 gpio-ranges = <&msmgpio 0 0 122>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
432 gcc: clock-controller@1800000 {
433 compatible = "qcom,gcc-msm8916";
436 #power-domain-cells = <1>;
437 reg = <0x1800000 0x80000>;
440 tcsr_mutex_regs: syscon@1905000 {
441 compatible = "syscon";
442 reg = <0x1905000 0x20000>;
445 tcsr: syscon@1937000 {
446 compatible = "qcom,tcsr-msm8916", "syscon";
447 reg = <0x1937000 0x30000>;
451 compatible = "qcom,tcsr-mutex";
452 syscon = <&tcsr_mutex_regs 0 0x1000>;
456 rpm_msg_ram: memory@60000 {
457 compatible = "qcom,rpm-msg-ram";
458 reg = <0x60000 0x8000>;
461 blsp1_uart1: serial@78af000 {
462 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
463 reg = <0x78af000 0x200>;
464 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
466 clock-names = "core", "iface";
467 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
468 dma-names = "rx", "tx";
472 a53pll: clock@b016000 {
473 compatible = "qcom,msm8916-a53pll";
474 reg = <0xb016000 0x40>;
478 apcs: mailbox@b011000 {
479 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
480 reg = <0xb011000 0x1000>;
482 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
483 clock-names = "pll", "aux";
487 blsp1_uart2: serial@78b0000 {
488 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
489 reg = <0x78b0000 0x200>;
490 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", "iface";
493 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
494 dma-names = "rx", "tx";
498 blsp_dma: dma@7884000 {
499 compatible = "qcom,bam-v1.7.0";
500 reg = <0x07884000 0x23000>;
501 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
503 clock-names = "bam_clk";
509 blsp_spi1: spi@78b5000 {
510 compatible = "qcom,spi-qup-v2.2.1";
511 reg = <0x078b5000 0x500>;
512 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
514 <&gcc GCC_BLSP1_AHB_CLK>;
515 clock-names = "core", "iface";
516 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
517 dma-names = "rx", "tx";
518 pinctrl-names = "default", "sleep";
519 pinctrl-0 = <&spi1_default>;
520 pinctrl-1 = <&spi1_sleep>;
521 #address-cells = <1>;
526 blsp_spi2: spi@78b6000 {
527 compatible = "qcom,spi-qup-v2.2.1";
528 reg = <0x078b6000 0x500>;
529 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
531 <&gcc GCC_BLSP1_AHB_CLK>;
532 clock-names = "core", "iface";
533 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
534 dma-names = "rx", "tx";
535 pinctrl-names = "default", "sleep";
536 pinctrl-0 = <&spi2_default>;
537 pinctrl-1 = <&spi2_sleep>;
538 #address-cells = <1>;
543 blsp_spi3: spi@78b7000 {
544 compatible = "qcom,spi-qup-v2.2.1";
545 reg = <0x078b7000 0x500>;
546 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", "iface";
550 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
551 dma-names = "rx", "tx";
552 pinctrl-names = "default", "sleep";
553 pinctrl-0 = <&spi3_default>;
554 pinctrl-1 = <&spi3_sleep>;
555 #address-cells = <1>;
560 blsp_spi4: spi@78b8000 {
561 compatible = "qcom,spi-qup-v2.2.1";
562 reg = <0x078b8000 0x500>;
563 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
565 <&gcc GCC_BLSP1_AHB_CLK>;
566 clock-names = "core", "iface";
567 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
568 dma-names = "rx", "tx";
569 pinctrl-names = "default", "sleep";
570 pinctrl-0 = <&spi4_default>;
571 pinctrl-1 = <&spi4_sleep>;
572 #address-cells = <1>;
577 blsp_spi5: spi@78b9000 {
578 compatible = "qcom,spi-qup-v2.2.1";
579 reg = <0x078b9000 0x500>;
580 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
582 <&gcc GCC_BLSP1_AHB_CLK>;
583 clock-names = "core", "iface";
584 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
585 dma-names = "rx", "tx";
586 pinctrl-names = "default", "sleep";
587 pinctrl-0 = <&spi5_default>;
588 pinctrl-1 = <&spi5_sleep>;
589 #address-cells = <1>;
594 blsp_spi6: spi@78ba000 {
595 compatible = "qcom,spi-qup-v2.2.1";
596 reg = <0x078ba000 0x500>;
597 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
599 <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", "iface";
601 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
602 dma-names = "rx", "tx";
603 pinctrl-names = "default", "sleep";
604 pinctrl-0 = <&spi6_default>;
605 pinctrl-1 = <&spi6_sleep>;
606 #address-cells = <1>;
611 blsp_i2c2: i2c@78b6000 {
612 compatible = "qcom,i2c-qup-v2.2.1";
613 reg = <0x078b6000 0x500>;
614 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
616 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
617 clock-names = "iface", "core";
618 pinctrl-names = "default", "sleep";
619 pinctrl-0 = <&i2c2_default>;
620 pinctrl-1 = <&i2c2_sleep>;
621 #address-cells = <1>;
626 blsp_i2c4: i2c@78b8000 {
627 compatible = "qcom,i2c-qup-v2.2.1";
628 reg = <0x078b8000 0x500>;
629 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
631 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
632 clock-names = "iface", "core";
633 pinctrl-names = "default", "sleep";
634 pinctrl-0 = <&i2c4_default>;
635 pinctrl-1 = <&i2c4_sleep>;
636 #address-cells = <1>;
641 blsp_i2c6: i2c@78ba000 {
642 compatible = "qcom,i2c-qup-v2.2.1";
643 reg = <0x078ba000 0x500>;
644 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
646 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
647 clock-names = "iface", "core";
648 pinctrl-names = "default", "sleep";
649 pinctrl-0 = <&i2c6_default>;
650 pinctrl-1 = <&i2c6_sleep>;
651 #address-cells = <1>;
656 lpass: lpass@7708000 {
658 compatible = "qcom,lpass-cpu-apq8016";
659 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
660 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
661 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
662 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
663 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
664 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
665 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
667 clock-names = "ahbix-clk",
674 #sound-dai-cells = <1>;
676 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "lpass-irq-lpaif";
678 reg = <0x07708000 0x10000>;
679 reg-names = "lpass-lpaif";
683 compatible = "qcom,msm8916-wcd-digital-codec";
684 reg = <0x0771c000 0x400>;
685 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
686 <&gcc GCC_CODEC_DIGCODEC_CLK>;
687 clock-names = "ahbix-clk", "mclk";
688 #sound-dai-cells = <1>;
691 sdhc_1: sdhci@7824000 {
692 compatible = "qcom,sdhci-msm-v4";
693 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
694 reg-names = "hc_mem", "core_mem";
696 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
697 interrupt-names = "hc_irq", "pwr_irq";
698 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
699 <&gcc GCC_SDCC1_AHB_CLK>,
701 clock-names = "core", "iface", "xo";
708 sdhc_2: sdhci@7864000 {
709 compatible = "qcom,sdhci-msm-v4";
710 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
711 reg-names = "hc_mem", "core_mem";
713 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
714 interrupt-names = "hc_irq", "pwr_irq";
715 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
716 <&gcc GCC_SDCC2_AHB_CLK>,
718 clock-names = "core", "iface", "xo";
724 compatible = "qcom,ci-hdrc";
725 reg = <0x78d9000 0x200>,
727 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
730 <&gcc GCC_USB_HS_SYSTEM_CLK>;
731 clock-names = "iface", "core";
732 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
733 assigned-clock-rates = <80000000>;
734 resets = <&gcc GCC_USB_HS_BCR>;
735 reset-names = "core";
738 ahb-burst-config = <0>;
739 phy-names = "usb-phy";
740 phys = <&usb_hs_phy>;
746 compatible = "qcom,usb-hs-phy-msm8916",
749 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
750 clock-names = "ref", "sleep";
751 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
752 reset-names = "phy", "por";
753 qcom,init-seq = /bits/ 8 <0x0 0x44
754 0x1 0x6b 0x2 0x24 0x3 0x13>;
759 intc: interrupt-controller@b000000 {
760 compatible = "qcom,msm-qgic2";
761 interrupt-controller;
762 #interrupt-cells = <3>;
763 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
767 #address-cells = <1>;
770 compatible = "arm,armv7-timer-mem";
771 reg = <0xb020000 0x1000>;
772 clock-frequency = <19200000>;
776 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
778 reg = <0xb021000 0x1000>,
784 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
785 reg = <0xb023000 0x1000>;
791 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
792 reg = <0xb024000 0x1000>;
798 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
799 reg = <0xb025000 0x1000>;
805 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
806 reg = <0xb026000 0x1000>;
812 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
813 reg = <0xb027000 0x1000>;
819 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
820 reg = <0xb028000 0x1000>;
825 spmi_bus: spmi@200f000 {
826 compatible = "qcom,spmi-pmic-arb";
827 reg = <0x200f000 0x001000>,
828 <0x2400000 0x400000>,
829 <0x2c00000 0x400000>,
830 <0x3800000 0x200000>,
831 <0x200a000 0x002100>;
832 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
833 interrupt-names = "periph_irq";
834 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
837 #address-cells = <2>;
839 interrupt-controller;
840 #interrupt-cells = <4>;
844 compatible = "qcom,prng";
845 reg = <0x00022000 0x200>;
846 clocks = <&gcc GCC_PRNG_AHB_CLK>;
847 clock-names = "core";
850 qfprom: qfprom@5c000 {
851 compatible = "qcom,qfprom";
852 reg = <0x5c000 0x1000>;
853 #address-cells = <1>;
855 tsens_caldata: caldata@d0 {
858 tsens_calsel: calsel@ec {
863 tsens: thermal-sensor@4a9000 {
864 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
865 reg = <0x4a9000 0x1000>, /* TM */
866 <0x4a8000 0x1000>; /* SROT */
867 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
868 nvmem-cell-names = "calib", "calib_sel";
870 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
871 interrupt-names = "uplow";
872 #thermal-sensor-cells = <1>;
875 apps_iommu: iommu@1ef0000 {
876 #address-cells = <1>;
879 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
880 ranges = <0 0x1e20000 0x40000>;
881 reg = <0x1ef0000 0x3000>;
882 clocks = <&gcc GCC_SMMU_CFG_CLK>,
883 <&gcc GCC_APSS_TCU_CLK>;
884 clock-names = "iface", "bus";
885 qcom,iommu-secure-id = <17>;
889 compatible = "qcom,msm-iommu-v1-sec";
890 reg = <0x3000 0x1000>;
891 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
896 compatible = "qcom,msm-iommu-v1-ns";
897 reg = <0x4000 0x1000>;
898 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
903 compatible = "qcom,msm-iommu-v1-sec";
904 reg = <0x5000 0x1000>;
905 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
909 gpu_iommu: iommu@1f08000 {
910 #address-cells = <1>;
913 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
914 ranges = <0 0x1f08000 0x10000>;
915 clocks = <&gcc GCC_SMMU_CFG_CLK>,
916 <&gcc GCC_GFX_TCU_CLK>;
917 clock-names = "iface", "bus";
918 qcom,iommu-secure-id = <18>;
922 compatible = "qcom,msm-iommu-v1-ns";
923 reg = <0x1000 0x1000>;
924 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
929 compatible = "qcom,msm-iommu-v1-ns";
930 reg = <0x2000 0x1000>;
931 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
936 compatible = "qcom,adreno-306.0", "qcom,adreno";
937 reg = <0x01c00000 0x20000>;
938 reg-names = "kgsl_3d0_reg_memory";
939 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
940 interrupt-names = "kgsl_3d0_irq";
949 <&gcc GCC_OXILI_GFX3D_CLK>,
950 <&gcc GCC_OXILI_AHB_CLK>,
951 <&gcc GCC_OXILI_GMEM_CLK>,
952 <&gcc GCC_BIMC_GFX_CLK>,
953 <&gcc GCC_BIMC_GPU_CLK>,
954 <&gcc GFX3D_CLK_SRC>;
955 power-domains = <&gcc OXILI_GDSC>;
956 operating-points-v2 = <&gpu_opp_table>;
957 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
961 compatible = "qcom,mdss";
962 reg = <0x1a00000 0x1000>,
964 reg-names = "mdss_phys", "vbif_phys";
966 power-domains = <&gcc MDSS_GDSC>;
968 clocks = <&gcc GCC_MDSS_AHB_CLK>,
969 <&gcc GCC_MDSS_AXI_CLK>,
970 <&gcc GCC_MDSS_VSYNC_CLK>;
971 clock-names = "iface",
975 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
977 interrupt-controller;
978 #interrupt-cells = <1>;
980 #address-cells = <1>;
985 compatible = "qcom,mdp5";
986 reg = <0x1a01000 0x89000>;
987 reg-names = "mdp_phys";
989 interrupt-parent = <&mdss>;
992 clocks = <&gcc GCC_MDSS_AHB_CLK>,
993 <&gcc GCC_MDSS_AXI_CLK>,
994 <&gcc GCC_MDSS_MDP_CLK>,
995 <&gcc GCC_MDSS_VSYNC_CLK>;
996 clock-names = "iface",
1001 iommus = <&apps_iommu 4>;
1004 #address-cells = <1>;
1009 mdp5_intf1_out: endpoint {
1010 remote-endpoint = <&dsi0_in>;
1017 compatible = "qcom,mdss-dsi-ctrl";
1018 reg = <0x1a98000 0x25c>;
1019 reg-names = "dsi_ctrl";
1021 interrupt-parent = <&mdss>;
1024 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1025 <&gcc PCLK0_CLK_SRC>;
1026 assigned-clock-parents = <&dsi_phy0 0>,
1029 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1030 <&gcc GCC_MDSS_AHB_CLK>,
1031 <&gcc GCC_MDSS_AXI_CLK>,
1032 <&gcc GCC_MDSS_BYTE0_CLK>,
1033 <&gcc GCC_MDSS_PCLK0_CLK>,
1034 <&gcc GCC_MDSS_ESC0_CLK>;
1035 clock-names = "mdp_core",
1042 phy-names = "dsi-phy";
1045 #address-cells = <1>;
1051 remote-endpoint = <&mdp5_intf1_out>;
1057 dsi0_out: endpoint {
1063 dsi_phy0: dsi-phy@1a98300 {
1064 compatible = "qcom,dsi-phy-28nm-lp";
1065 reg = <0x1a98300 0xd4>,
1068 reg-names = "dsi_pll",
1070 "dsi_phy_regulator";
1075 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1077 clock-names = "iface", "ref";
1083 compatible = "qcom,q6v5-pil";
1084 reg = <0x04080000 0x100>,
1087 reg-names = "qdsp6", "rmb";
1089 interrupts-extended = <&intc 0 24 1>,
1090 <&hexagon_smp2p_in 0 0>,
1091 <&hexagon_smp2p_in 1 0>,
1092 <&hexagon_smp2p_in 2 0>,
1093 <&hexagon_smp2p_in 3 0>;
1094 interrupt-names = "wdog", "fatal", "ready",
1095 "handover", "stop-ack";
1097 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1098 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1099 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1101 clock-names = "iface", "bus", "mem", "xo";
1103 qcom,smem-states = <&hexagon_smp2p_out 0>;
1104 qcom,smem-state-names = "stop";
1107 reset-names = "mss_restart";
1109 cx-supply = <&pm8916_s1>;
1110 mx-supply = <&pm8916_l3>;
1111 pll-supply = <&pm8916_l7>;
1113 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1115 status = "disabled";
1118 memory-region = <&mba_mem>;
1122 memory-region = <&mpss_mem>;
1126 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1128 qcom,smd-edge = <0>;
1129 qcom,ipc = <&apcs 8 12>;
1130 qcom,remote-pid = <1>;
1136 pronto: wcnss@a21b000 {
1137 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1138 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1139 reg-names = "ccu", "dxe", "pmu";
1141 memory-region = <&wcnss_mem>;
1143 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1144 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1145 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1146 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1147 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1148 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1150 vddmx-supply = <&pm8916_l3>;
1151 vddpx-supply = <&pm8916_l7>;
1153 qcom,state = <&wcnss_smp2p_out 0>;
1154 qcom,state-names = "stop";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&wcnss_pin_a>;
1159 status = "disabled";
1162 compatible = "qcom,wcn3620";
1164 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1167 vddxo-supply = <&pm8916_l7>;
1168 vddrfa-supply = <&pm8916_s3>;
1169 vddpa-supply = <&pm8916_l9>;
1170 vdddig-supply = <&pm8916_l5>;
1174 interrupts = <0 142 1>;
1176 qcom,ipc = <&apcs 8 17>;
1177 qcom,smd-edge = <6>;
1178 qcom,remote-pid = <4>;
1183 compatible = "qcom,wcnss";
1184 qcom,smd-channels = "WCNSS_CTRL";
1186 qcom,mmio = <&pronto>;
1189 compatible = "qcom,wcnss-bt";
1193 compatible = "qcom,wcnss-wlan";
1195 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1196 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1197 interrupt-names = "tx", "rx";
1199 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1200 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1207 compatible = "arm,coresight-tpiu", "arm,primecell";
1208 reg = <0x820000 0x1000>;
1210 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1211 clock-names = "apb_pclk", "atclk";
1216 remote-endpoint = <&replicator_out1>;
1223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1224 reg = <0x821000 0x1000>;
1226 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1227 clock-names = "apb_pclk", "atclk";
1230 #address-cells = <1>;
1234 * Not described input ports:
1235 * 0 - connected to Resource and Power Manger CPU ETM
1237 * 2 - connected to Modem CPU ETM
1240 * 6 - connected trought funnel to Wireless CPU ETM
1241 * 7 - connected to STM component
1246 funnel0_in4: endpoint {
1247 remote-endpoint = <&funnel1_out>;
1254 funnel0_out: endpoint {
1255 remote-endpoint = <&etf_in>;
1262 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1263 reg = <0x824000 0x1000>;
1265 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1266 clock-names = "apb_pclk", "atclk";
1269 #address-cells = <1>;
1274 replicator_out0: endpoint {
1275 remote-endpoint = <&etr_in>;
1280 replicator_out1: endpoint {
1281 remote-endpoint = <&tpiu_in>;
1288 replicator_in: endpoint {
1289 remote-endpoint = <&etf_out>;
1296 compatible = "arm,coresight-tmc", "arm,primecell";
1297 reg = <0x825000 0x1000>;
1299 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1300 clock-names = "apb_pclk", "atclk";
1305 remote-endpoint = <&funnel0_out>;
1313 remote-endpoint = <&replicator_in>;
1320 compatible = "arm,coresight-tmc", "arm,primecell";
1321 reg = <0x826000 0x1000>;
1323 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1324 clock-names = "apb_pclk", "atclk";
1329 remote-endpoint = <&replicator_out0>;
1335 funnel@841000 { /* APSS funnel only 4 inputs are used */
1336 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1337 reg = <0x841000 0x1000>;
1339 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1340 clock-names = "apb_pclk", "atclk";
1343 #address-cells = <1>;
1348 funnel1_in0: endpoint {
1349 remote-endpoint = <&etm0_out>;
1354 funnel1_in1: endpoint {
1355 remote-endpoint = <&etm1_out>;
1360 funnel1_in2: endpoint {
1361 remote-endpoint = <&etm2_out>;
1366 funnel1_in3: endpoint {
1367 remote-endpoint = <&etm3_out>;
1374 funnel1_out: endpoint {
1375 remote-endpoint = <&funnel0_in4>;
1382 compatible = "arm,coresight-cpu-debug","arm,primecell";
1383 reg = <0x850000 0x1000>;
1384 clocks = <&rpmcc RPM_QDSS_CLK>;
1385 clock-names = "apb_pclk";
1390 compatible = "arm,coresight-cpu-debug","arm,primecell";
1391 reg = <0x852000 0x1000>;
1392 clocks = <&rpmcc RPM_QDSS_CLK>;
1393 clock-names = "apb_pclk";
1398 compatible = "arm,coresight-cpu-debug","arm,primecell";
1399 reg = <0x854000 0x1000>;
1400 clocks = <&rpmcc RPM_QDSS_CLK>;
1401 clock-names = "apb_pclk";
1406 compatible = "arm,coresight-cpu-debug","arm,primecell";
1407 reg = <0x856000 0x1000>;
1408 clocks = <&rpmcc RPM_QDSS_CLK>;
1409 clock-names = "apb_pclk";
1414 compatible = "arm,coresight-etm4x", "arm,primecell";
1415 reg = <0x85c000 0x1000>;
1417 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1418 clock-names = "apb_pclk", "atclk";
1419 arm,coresight-loses-context-with-cpu;
1425 etm0_out: endpoint {
1426 remote-endpoint = <&funnel1_in0>;
1433 compatible = "arm,coresight-etm4x", "arm,primecell";
1434 reg = <0x85d000 0x1000>;
1436 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1437 clock-names = "apb_pclk", "atclk";
1438 arm,coresight-loses-context-with-cpu;
1444 etm1_out: endpoint {
1445 remote-endpoint = <&funnel1_in1>;
1452 compatible = "arm,coresight-etm4x", "arm,primecell";
1453 reg = <0x85e000 0x1000>;
1455 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1456 clock-names = "apb_pclk", "atclk";
1457 arm,coresight-loses-context-with-cpu;
1463 etm2_out: endpoint {
1464 remote-endpoint = <&funnel1_in2>;
1471 compatible = "arm,coresight-etm4x", "arm,primecell";
1472 reg = <0x85f000 0x1000>;
1474 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1475 clock-names = "apb_pclk", "atclk";
1476 arm,coresight-loses-context-with-cpu;
1482 etm3_out: endpoint {
1483 remote-endpoint = <&funnel1_in3>;
1489 venus: video-codec@1d00000 {
1490 compatible = "qcom,msm8916-venus";
1491 reg = <0x01d00000 0xff000>;
1492 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1493 power-domains = <&gcc VENUS_GDSC>;
1494 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1495 <&gcc GCC_VENUS0_AHB_CLK>,
1496 <&gcc GCC_VENUS0_AXI_CLK>;
1497 clock-names = "core", "iface", "bus";
1498 iommus = <&apps_iommu 5>;
1499 memory-region = <&venus_mem>;
1503 compatible = "venus-decoder";
1507 compatible = "venus-encoder";
1511 camss: camss@1b00000 {
1512 compatible = "qcom,msm8916-camss";
1513 reg = <0x1b0ac00 0x200>,
1522 reg-names = "csiphy0",
1531 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1532 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1533 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1534 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1535 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1536 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1537 interrupt-names = "csiphy0",
1543 power-domains = <&gcc VFE_GDSC>;
1544 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1545 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1546 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1547 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1548 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1549 <&gcc GCC_CAMSS_CSI0_CLK>,
1550 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1551 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1552 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1553 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1554 <&gcc GCC_CAMSS_CSI1_CLK>,
1555 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1556 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1557 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1558 <&gcc GCC_CAMSS_AHB_CLK>,
1559 <&gcc GCC_CAMSS_VFE0_CLK>,
1560 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1561 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1562 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1563 clock-names = "top_ahb",
1582 vdda-supply = <&pm8916_l2>;
1583 iommus = <&apps_iommu 3>;
1584 status = "disabled";
1586 #address-cells = <1>;
1593 compatible = "qcom,smd";
1596 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1597 qcom,ipc = <&apcs 8 0>;
1598 qcom,smd-edge = <15>;
1601 compatible = "qcom,rpm-msm8916";
1602 qcom,smd-channels = "rpm_requests";
1605 compatible = "qcom,rpmcc-msm8916";
1609 smd_rpm_regulators: pm8916-regulators {
1610 compatible = "qcom,rpm-pm8916-regulators";
1640 compatible = "qcom,smp2p";
1641 qcom,smem = <435>, <428>;
1643 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1645 qcom,ipc = <&apcs 8 14>;
1647 qcom,local-pid = <0>;
1648 qcom,remote-pid = <1>;
1650 hexagon_smp2p_out: master-kernel {
1651 qcom,entry-name = "master-kernel";
1653 #qcom,smem-state-cells = <1>;
1656 hexagon_smp2p_in: slave-kernel {
1657 qcom,entry-name = "slave-kernel";
1659 interrupt-controller;
1660 #interrupt-cells = <2>;
1665 compatible = "qcom,smp2p";
1666 qcom,smem = <451>, <431>;
1668 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1670 qcom,ipc = <&apcs 8 18>;
1672 qcom,local-pid = <0>;
1673 qcom,remote-pid = <4>;
1675 wcnss_smp2p_out: master-kernel {
1676 qcom,entry-name = "master-kernel";
1678 #qcom,smem-state-cells = <1>;
1681 wcnss_smp2p_in: slave-kernel {
1682 qcom,entry-name = "slave-kernel";
1684 interrupt-controller;
1685 #interrupt-cells = <2>;
1690 compatible = "qcom,smsm";
1692 #address-cells = <1>;
1695 qcom,ipc-1 = <&apcs 8 13>;
1696 qcom,ipc-3 = <&apcs 8 19>;
1701 #qcom,smem-state-cells = <1>;
1704 hexagon_smsm: hexagon@1 {
1706 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1708 interrupt-controller;
1709 #interrupt-cells = <2>;
1712 wcnss_smsm: wcnss@6 {
1714 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1716 interrupt-controller;
1717 #interrupt-cells = <2>;
1722 #include "msm8916-pins.dtsi"