arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/arm/coresight-cti-dt.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8916.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  22                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  23         };
  24
  25         chosen { };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /* We expect the bootloader to fill in the reg */
  30                 reg = <0 0 0 0>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <2>;
  35                 #size-cells = <2>;
  36                 ranges;
  37
  38                 tz-apps@86000000 {
  39                         reg = <0x0 0x86000000 0x0 0x300000>;
  40                         no-map;
  41                 };
  42
  43                 smem_mem: smem_region@86300000 {
  44                         reg = <0x0 0x86300000 0x0 0x100000>;
  45                         no-map;
  46                 };
  47
  48                 hypervisor@86400000 {
  49                         reg = <0x0 0x86400000 0x0 0x100000>;
  50                         no-map;
  51                 };
  52
  53                 tz@86500000 {
  54                         reg = <0x0 0x86500000 0x0 0x180000>;
  55                         no-map;
  56                 };
  57
  58                 reserved@8668000 {
  59                         reg = <0x0 0x86680000 0x0 0x80000>;
  60                         no-map;
  61                 };
  62
  63                 rmtfs@86700000 {
  64                         compatible = "qcom,rmtfs-mem";
  65                         reg = <0x0 0x86700000 0x0 0xe0000>;
  66                         no-map;
  67
  68                         qcom,client-id = <1>;
  69                 };
  70
  71                 rfsa@867e00000 {
  72                         reg = <0x0 0x867e0000 0x0 0x20000>;
  73                         no-map;
  74                 };
  75
  76                 mpss_mem: mpss@86800000 {
  77                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  78                         no-map;
  79                 };
  80
  81                 wcnss_mem: wcnss@89300000 {
  82                         reg = <0x0 0x89300000 0x0 0x600000>;
  83                         no-map;
  84                 };
  85
  86                 venus_mem: venus@89900000 {
  87                         reg = <0x0 0x89900000 0x0 0x600000>;
  88                         no-map;
  89                 };
  90
  91                 mba_mem: mba@8ea00000 {
  92                         no-map;
  93                         reg = <0 0x8ea00000 0 0x100000>;
  94                 };
  95         };
  96
  97         clocks {
  98                 xo_board: xo-board {
  99                         compatible = "fixed-clock";
 100                         #clock-cells = <0>;
 101                         clock-frequency = <19200000>;
 102                 };
 103
 104                 sleep_clk: sleep-clk {
 105                         compatible = "fixed-clock";
 106                         #clock-cells = <0>;
 107                         clock-frequency = <32768>;
 108                 };
 109         };
 110
 111         cpus {
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114
 115                 CPU0: cpu@0 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53";
 118                         reg = <0x0>;
 119                         next-level-cache = <&L2_0>;
 120                         enable-method = "psci";
 121                         clocks = <&apcs>;
 122                         operating-points-v2 = <&cpu_opp_table>;
 123                         #cooling-cells = <2>;
 124                         power-domains = <&CPU_PD0>;
 125                         power-domain-names = "psci";
 126                 };
 127
 128                 CPU1: cpu@1 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53";
 131                         reg = <0x1>;
 132                         next-level-cache = <&L2_0>;
 133                         enable-method = "psci";
 134                         clocks = <&apcs>;
 135                         operating-points-v2 = <&cpu_opp_table>;
 136                         #cooling-cells = <2>;
 137                         power-domains = <&CPU_PD1>;
 138                         power-domain-names = "psci";
 139                 };
 140
 141                 CPU2: cpu@2 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53";
 144                         reg = <0x2>;
 145                         next-level-cache = <&L2_0>;
 146                         enable-method = "psci";
 147                         clocks = <&apcs>;
 148                         operating-points-v2 = <&cpu_opp_table>;
 149                         #cooling-cells = <2>;
 150                         power-domains = <&CPU_PD2>;
 151                         power-domain-names = "psci";
 152                 };
 153
 154                 CPU3: cpu@3 {
 155                         device_type = "cpu";
 156                         compatible = "arm,cortex-a53";
 157                         reg = <0x3>;
 158                         next-level-cache = <&L2_0>;
 159                         enable-method = "psci";
 160                         clocks = <&apcs>;
 161                         operating-points-v2 = <&cpu_opp_table>;
 162                         #cooling-cells = <2>;
 163                         power-domains = <&CPU_PD3>;
 164                         power-domain-names = "psci";
 165                 };
 166
 167                 L2_0: l2-cache {
 168                         compatible = "cache";
 169                         cache-level = <2>;
 170                 };
 171
 172                 idle-states {
 173                         entry-method = "psci";
 174
 175                         CPU_SLEEP_0: cpu-sleep-0 {
 176                                 compatible = "arm,idle-state";
 177                                 idle-state-name = "standalone-power-collapse";
 178                                 arm,psci-suspend-param = <0x40000002>;
 179                                 entry-latency-us = <130>;
 180                                 exit-latency-us = <150>;
 181                                 min-residency-us = <2000>;
 182                                 local-timer-stop;
 183                         };
 184                 };
 185
 186                 domain-idle-states {
 187
 188                         CLUSTER_RET: cluster-retention {
 189                                 compatible = "domain-idle-state";
 190                                 arm,psci-suspend-param = <0x41000012>;
 191                                 entry-latency-us = <500>;
 192                                 exit-latency-us = <500>;
 193                                 min-residency-us = <2000>;
 194                         };
 195
 196                         CLUSTER_PWRDN: cluster-gdhs {
 197                                 compatible = "domain-idle-state";
 198                                 arm,psci-suspend-param = <0x41000032>;
 199                                 entry-latency-us = <2000>;
 200                                 exit-latency-us = <2000>;
 201                                 min-residency-us = <6000>;
 202                         };
 203                 };
 204         };
 205
 206         cpu_opp_table: cpu-opp-table {
 207                 compatible = "operating-points-v2";
 208                 opp-shared;
 209
 210                 opp-200000000 {
 211                         opp-hz = /bits/ 64 <200000000>;
 212                 };
 213                 opp-400000000 {
 214                         opp-hz = /bits/ 64 <400000000>;
 215                 };
 216                 opp-800000000 {
 217                         opp-hz = /bits/ 64 <800000000>;
 218                 };
 219                 opp-998400000 {
 220                         opp-hz = /bits/ 64 <998400000>;
 221                 };
 222         };
 223
 224         firmware {
 225                 scm: scm {
 226                         compatible = "qcom,scm-msm8916", "qcom,scm";
 227                         clocks = <&gcc GCC_CRYPTO_CLK>,
 228                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 229                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 230                         clock-names = "core", "bus", "iface";
 231                         #reset-cells = <1>;
 232
 233                         qcom,dload-mode = <&tcsr 0x6100>;
 234                 };
 235         };
 236
 237         pmu {
 238                 compatible = "arm,cortex-a53-pmu";
 239                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 240         };
 241
 242         psci {
 243                 compatible = "arm,psci-1.0";
 244                 method = "smc";
 245
 246                 CPU_PD0: power-domain-cpu0 {
 247                         #power-domain-cells = <0>;
 248                         power-domains = <&CLUSTER_PD>;
 249                         domain-idle-states = <&CPU_SLEEP_0>;
 250                 };
 251
 252                 CPU_PD1: power-domain-cpu1 {
 253                         #power-domain-cells = <0>;
 254                         power-domains = <&CLUSTER_PD>;
 255                         domain-idle-states = <&CPU_SLEEP_0>;
 256                 };
 257
 258                 CPU_PD2: power-domain-cpu2 {
 259                         #power-domain-cells = <0>;
 260                         power-domains = <&CLUSTER_PD>;
 261                         domain-idle-states = <&CPU_SLEEP_0>;
 262                 };
 263
 264                 CPU_PD3: power-domain-cpu3 {
 265                         #power-domain-cells = <0>;
 266                         power-domains = <&CLUSTER_PD>;
 267                         domain-idle-states = <&CPU_SLEEP_0>;
 268                 };
 269
 270                 CLUSTER_PD: power-domain-cluster {
 271                         #power-domain-cells = <0>;
 272                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 273                 };
 274         };
 275
 276         smd {
 277                 compatible = "qcom,smd";
 278
 279                 rpm {
 280                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 281                         qcom,ipc = <&apcs 8 0>;
 282                         qcom,smd-edge = <15>;
 283
 284                         rpm_requests: rpm-requests {
 285                                 compatible = "qcom,rpm-msm8916";
 286                                 qcom,smd-channels = "rpm_requests";
 287
 288                                 rpmcc: clock-controller {
 289                                         compatible = "qcom,rpmcc-msm8916";
 290                                         #clock-cells = <1>;
 291                                 };
 292                         };
 293                 };
 294         };
 295
 296         smem {
 297                 compatible = "qcom,smem";
 298
 299                 memory-region = <&smem_mem>;
 300                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 301
 302                 hwlocks = <&tcsr_mutex 3>;
 303         };
 304
 305         smp2p-hexagon {
 306                 compatible = "qcom,smp2p";
 307                 qcom,smem = <435>, <428>;
 308
 309                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 310
 311                 qcom,ipc = <&apcs 8 14>;
 312
 313                 qcom,local-pid = <0>;
 314                 qcom,remote-pid = <1>;
 315
 316                 hexagon_smp2p_out: master-kernel {
 317                         qcom,entry-name = "master-kernel";
 318
 319                         #qcom,smem-state-cells = <1>;
 320                 };
 321
 322                 hexagon_smp2p_in: slave-kernel {
 323                         qcom,entry-name = "slave-kernel";
 324
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                 };
 328         };
 329
 330         smp2p-wcnss {
 331                 compatible = "qcom,smp2p";
 332                 qcom,smem = <451>, <431>;
 333
 334                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 335
 336                 qcom,ipc = <&apcs 8 18>;
 337
 338                 qcom,local-pid = <0>;
 339                 qcom,remote-pid = <4>;
 340
 341                 wcnss_smp2p_out: master-kernel {
 342                         qcom,entry-name = "master-kernel";
 343
 344                         #qcom,smem-state-cells = <1>;
 345                 };
 346
 347                 wcnss_smp2p_in: slave-kernel {
 348                         qcom,entry-name = "slave-kernel";
 349
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353         };
 354
 355         smsm {
 356                 compatible = "qcom,smsm";
 357
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360
 361                 qcom,ipc-1 = <&apcs 8 13>;
 362                 qcom,ipc-3 = <&apcs 8 19>;
 363
 364                 apps_smsm: apps@0 {
 365                         reg = <0>;
 366
 367                         #qcom,smem-state-cells = <1>;
 368                 };
 369
 370                 hexagon_smsm: hexagon@1 {
 371                         reg = <1>;
 372                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 373
 374                         interrupt-controller;
 375                         #interrupt-cells = <2>;
 376                 };
 377
 378                 wcnss_smsm: wcnss@6 {
 379                         reg = <6>;
 380                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 381
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385         };
 386
 387         soc: soc {
 388                 #address-cells = <1>;
 389                 #size-cells = <1>;
 390                 ranges = <0 0 0 0xffffffff>;
 391                 compatible = "simple-bus";
 392
 393                 rng@22000 {
 394                         compatible = "qcom,prng";
 395                         reg = <0x00022000 0x200>;
 396                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 397                         clock-names = "core";
 398                 };
 399
 400                 restart@4ab000 {
 401                         compatible = "qcom,pshold";
 402                         reg = <0x004ab000 0x4>;
 403                 };
 404
 405                 qfprom: qfprom@5c000 {
 406                         compatible = "qcom,qfprom";
 407                         reg = <0x0005c000 0x1000>;
 408                         #address-cells = <1>;
 409                         #size-cells = <1>;
 410                         tsens_caldata: caldata@d0 {
 411                                 reg = <0xd0 0x8>;
 412                         };
 413                         tsens_calsel: calsel@ec {
 414                                 reg = <0xec 0x4>;
 415                         };
 416                 };
 417
 418                 rpm_msg_ram: memory@60000 {
 419                         compatible = "qcom,rpm-msg-ram";
 420                         reg = <0x00060000 0x8000>;
 421                 };
 422
 423                 bimc: interconnect@400000 {
 424                         compatible = "qcom,msm8916-bimc";
 425                         reg = <0x00400000 0x62000>;
 426                         #interconnect-cells = <1>;
 427                         clock-names = "bus", "bus_a";
 428                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 429                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 430                 };
 431
 432                 tsens: thermal-sensor@4a9000 {
 433                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
 434                         reg = <0x004a9000 0x1000>, /* TM */
 435                               <0x004a8000 0x1000>; /* SROT */
 436                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 437                         nvmem-cell-names = "calib", "calib_sel";
 438                         #qcom,sensors = <5>;
 439                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 440                         interrupt-names = "uplow";
 441                         #thermal-sensor-cells = <1>;
 442                 };
 443
 444                 pcnoc: interconnect@500000 {
 445                         compatible = "qcom,msm8916-pcnoc";
 446                         reg = <0x00500000 0x11000>;
 447                         #interconnect-cells = <1>;
 448                         clock-names = "bus", "bus_a";
 449                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
 450                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
 451                 };
 452
 453                 snoc: interconnect@580000 {
 454                         compatible = "qcom,msm8916-snoc";
 455                         reg = <0x00580000 0x14000>;
 456                         #interconnect-cells = <1>;
 457                         clock-names = "bus", "bus_a";
 458                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 459                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 460                 };
 461
 462                 /* System CTIs */
 463                 /* CTI 0 - TMC connections */
 464                 cti0: cti@810000 {
 465                         compatible = "arm,coresight-cti", "arm,primecell";
 466                         reg = <0x00810000 0x1000>;
 467
 468                         clocks = <&rpmcc RPM_QDSS_CLK>;
 469                         clock-names = "apb_pclk";
 470
 471                         status = "disabled";
 472                 };
 473
 474                 /* CTI 1 - TPIU connections */
 475                 cti1: cti@811000 {
 476                         compatible = "arm,coresight-cti", "arm,primecell";
 477                         reg = <0x00811000 0x1000>;
 478
 479                         clocks = <&rpmcc RPM_QDSS_CLK>;
 480                         clock-names = "apb_pclk";
 481
 482                         status = "disabled";
 483                 };
 484
 485                 /* CTIs 2-11 - no information - not instantiated */
 486
 487                 tpiu: tpiu@820000 {
 488                         compatible = "arm,coresight-tpiu", "arm,primecell";
 489                         reg = <0x00820000 0x1000>;
 490
 491                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 492                         clock-names = "apb_pclk", "atclk";
 493
 494                         status = "disabled";
 495
 496                         in-ports {
 497                                 port {
 498                                         tpiu_in: endpoint {
 499                                                 remote-endpoint = <&replicator_out1>;
 500                                         };
 501                                 };
 502                         };
 503                 };
 504
 505                 funnel0: funnel@821000 {
 506                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 507                         reg = <0x00821000 0x1000>;
 508
 509                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 510                         clock-names = "apb_pclk", "atclk";
 511
 512                         status = "disabled";
 513
 514                         in-ports {
 515                                 #address-cells = <1>;
 516                                 #size-cells = <0>;
 517
 518                                 /*
 519                                  * Not described input ports:
 520                                  * 0 - connected to Resource and Power Manger CPU ETM
 521                                  * 1 - not-connected
 522                                  * 2 - connected to Modem CPU ETM
 523                                  * 3 - not-connected
 524                                  * 5 - not-connected
 525                                  * 6 - connected trought funnel to Wireless CPU ETM
 526                                  * 7 - connected to STM component
 527                                  */
 528
 529                                 port@4 {
 530                                         reg = <4>;
 531                                         funnel0_in4: endpoint {
 532                                                 remote-endpoint = <&funnel1_out>;
 533                                         };
 534                                 };
 535                         };
 536
 537                         out-ports {
 538                                 port {
 539                                         funnel0_out: endpoint {
 540                                                 remote-endpoint = <&etf_in>;
 541                                         };
 542                                 };
 543                         };
 544                 };
 545
 546                 replicator: replicator@824000 {
 547                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 548                         reg = <0x00824000 0x1000>;
 549
 550                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 551                         clock-names = "apb_pclk", "atclk";
 552
 553                         status = "disabled";
 554
 555                         out-ports {
 556                                 #address-cells = <1>;
 557                                 #size-cells = <0>;
 558
 559                                 port@0 {
 560                                         reg = <0>;
 561                                         replicator_out0: endpoint {
 562                                                 remote-endpoint = <&etr_in>;
 563                                         };
 564                                 };
 565                                 port@1 {
 566                                         reg = <1>;
 567                                         replicator_out1: endpoint {
 568                                                 remote-endpoint = <&tpiu_in>;
 569                                         };
 570                                 };
 571                         };
 572
 573                         in-ports {
 574                                 port {
 575                                         replicator_in: endpoint {
 576                                                 remote-endpoint = <&etf_out>;
 577                                         };
 578                                 };
 579                         };
 580                 };
 581
 582                 etf: etf@825000 {
 583                         compatible = "arm,coresight-tmc", "arm,primecell";
 584                         reg = <0x00825000 0x1000>;
 585
 586                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 587                         clock-names = "apb_pclk", "atclk";
 588
 589                         status = "disabled";
 590
 591                         in-ports {
 592                                 port {
 593                                         etf_in: endpoint {
 594                                                 remote-endpoint = <&funnel0_out>;
 595                                         };
 596                                 };
 597                         };
 598
 599                         out-ports {
 600                                 port {
 601                                         etf_out: endpoint {
 602                                                 remote-endpoint = <&replicator_in>;
 603                                         };
 604                                 };
 605                         };
 606                 };
 607
 608                 etr: etr@826000 {
 609                         compatible = "arm,coresight-tmc", "arm,primecell";
 610                         reg = <0x00826000 0x1000>;
 611
 612                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 613                         clock-names = "apb_pclk", "atclk";
 614
 615                         status = "disabled";
 616
 617                         in-ports {
 618                                 port {
 619                                         etr_in: endpoint {
 620                                                 remote-endpoint = <&replicator_out0>;
 621                                         };
 622                                 };
 623                         };
 624                 };
 625
 626                 funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
 627                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 628                         reg = <0x00841000 0x1000>;
 629
 630                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 631                         clock-names = "apb_pclk", "atclk";
 632
 633                         status = "disabled";
 634
 635                         in-ports {
 636                                 #address-cells = <1>;
 637                                 #size-cells = <0>;
 638
 639                                 port@0 {
 640                                         reg = <0>;
 641                                         funnel1_in0: endpoint {
 642                                                 remote-endpoint = <&etm0_out>;
 643                                         };
 644                                 };
 645                                 port@1 {
 646                                         reg = <1>;
 647                                         funnel1_in1: endpoint {
 648                                                 remote-endpoint = <&etm1_out>;
 649                                         };
 650                                 };
 651                                 port@2 {
 652                                         reg = <2>;
 653                                         funnel1_in2: endpoint {
 654                                                 remote-endpoint = <&etm2_out>;
 655                                         };
 656                                 };
 657                                 port@3 {
 658                                         reg = <3>;
 659                                         funnel1_in3: endpoint {
 660                                                 remote-endpoint = <&etm3_out>;
 661                                         };
 662                                 };
 663                         };
 664
 665                         out-ports {
 666                                 port {
 667                                         funnel1_out: endpoint {
 668                                                 remote-endpoint = <&funnel0_in4>;
 669                                         };
 670                                 };
 671                         };
 672                 };
 673
 674                 debug0: debug@850000 {
 675                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 676                         reg = <0x00850000 0x1000>;
 677                         clocks = <&rpmcc RPM_QDSS_CLK>;
 678                         clock-names = "apb_pclk";
 679                         cpu = <&CPU0>;
 680                         status = "disabled";
 681                 };
 682
 683                 debug1: debug@852000 {
 684                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 685                         reg = <0x00852000 0x1000>;
 686                         clocks = <&rpmcc RPM_QDSS_CLK>;
 687                         clock-names = "apb_pclk";
 688                         cpu = <&CPU1>;
 689                         status = "disabled";
 690                 };
 691
 692                 debug2: debug@854000 {
 693                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 694                         reg = <0x00854000 0x1000>;
 695                         clocks = <&rpmcc RPM_QDSS_CLK>;
 696                         clock-names = "apb_pclk";
 697                         cpu = <&CPU2>;
 698                         status = "disabled";
 699                 };
 700
 701                 debug3: debug@856000 {
 702                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 703                         reg = <0x00856000 0x1000>;
 704                         clocks = <&rpmcc RPM_QDSS_CLK>;
 705                         clock-names = "apb_pclk";
 706                         cpu = <&CPU3>;
 707                         status = "disabled";
 708                 };
 709
 710                 /* Core CTIs; CTIs 12-15 */
 711                 /* CTI - CPU-0 */
 712                 cti12: cti@858000 {
 713                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 714                                      "arm,primecell";
 715                         reg = <0x00858000 0x1000>;
 716
 717                         clocks = <&rpmcc RPM_QDSS_CLK>;
 718                         clock-names = "apb_pclk";
 719
 720                         cpu = <&CPU0>;
 721                         arm,cs-dev-assoc = <&etm0>;
 722
 723                         status = "disabled";
 724                 };
 725
 726                 /* CTI - CPU-1 */
 727                 cti13: cti@859000 {
 728                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 729                                      "arm,primecell";
 730                         reg = <0x00859000 0x1000>;
 731
 732                         clocks = <&rpmcc RPM_QDSS_CLK>;
 733                         clock-names = "apb_pclk";
 734
 735                         cpu = <&CPU1>;
 736                         arm,cs-dev-assoc = <&etm1>;
 737
 738                         status = "disabled";
 739                 };
 740
 741                 /* CTI - CPU-2 */
 742                 cti14: cti@85a000 {
 743                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 744                                      "arm,primecell";
 745                         reg = <0x0085a000 0x1000>;
 746
 747                         clocks = <&rpmcc RPM_QDSS_CLK>;
 748                         clock-names = "apb_pclk";
 749
 750                         cpu = <&CPU2>;
 751                         arm,cs-dev-assoc = <&etm2>;
 752
 753                         status = "disabled";
 754                 };
 755
 756                 /* CTI - CPU-3 */
 757                 cti15: cti@85b000 {
 758                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 759                                      "arm,primecell";
 760                         reg = <0x0085b000 0x1000>;
 761
 762                         clocks = <&rpmcc RPM_QDSS_CLK>;
 763                         clock-names = "apb_pclk";
 764
 765                         cpu = <&CPU3>;
 766                         arm,cs-dev-assoc = <&etm3>;
 767
 768                         status = "disabled";
 769                 };
 770
 771                 etm0: etm@85c000 {
 772                         compatible = "arm,coresight-etm4x", "arm,primecell";
 773                         reg = <0x0085c000 0x1000>;
 774
 775                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 776                         clock-names = "apb_pclk", "atclk";
 777                         arm,coresight-loses-context-with-cpu;
 778
 779                         cpu = <&CPU0>;
 780
 781                         status = "disabled";
 782
 783                         out-ports {
 784                                 port {
 785                                         etm0_out: endpoint {
 786                                                 remote-endpoint = <&funnel1_in0>;
 787                                         };
 788                                 };
 789                         };
 790                 };
 791
 792                 etm1: etm@85d000 {
 793                         compatible = "arm,coresight-etm4x", "arm,primecell";
 794                         reg = <0x0085d000 0x1000>;
 795
 796                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 797                         clock-names = "apb_pclk", "atclk";
 798                         arm,coresight-loses-context-with-cpu;
 799
 800                         cpu = <&CPU1>;
 801
 802                         status = "disabled";
 803
 804                         out-ports {
 805                                 port {
 806                                         etm1_out: endpoint {
 807                                                 remote-endpoint = <&funnel1_in1>;
 808                                         };
 809                                 };
 810                         };
 811                 };
 812
 813                 etm2: etm@85e000 {
 814                         compatible = "arm,coresight-etm4x", "arm,primecell";
 815                         reg = <0x0085e000 0x1000>;
 816
 817                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 818                         clock-names = "apb_pclk", "atclk";
 819                         arm,coresight-loses-context-with-cpu;
 820
 821                         cpu = <&CPU2>;
 822
 823                         status = "disabled";
 824
 825                         out-ports {
 826                                 port {
 827                                         etm2_out: endpoint {
 828                                                 remote-endpoint = <&funnel1_in2>;
 829                                         };
 830                                 };
 831                         };
 832                 };
 833
 834                 etm3: etm@85f000 {
 835                         compatible = "arm,coresight-etm4x", "arm,primecell";
 836                         reg = <0x0085f000 0x1000>;
 837
 838                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 839                         clock-names = "apb_pclk", "atclk";
 840                         arm,coresight-loses-context-with-cpu;
 841
 842                         cpu = <&CPU3>;
 843
 844                         status = "disabled";
 845
 846                         out-ports {
 847                                 port {
 848                                         etm3_out: endpoint {
 849                                                 remote-endpoint = <&funnel1_in3>;
 850                                         };
 851                                 };
 852                         };
 853                 };
 854
 855                 msmgpio: pinctrl@1000000 {
 856                         compatible = "qcom,msm8916-pinctrl";
 857                         reg = <0x01000000 0x300000>;
 858                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 859                         gpio-controller;
 860                         gpio-ranges = <&msmgpio 0 0 122>;
 861                         #gpio-cells = <2>;
 862                         interrupt-controller;
 863                         #interrupt-cells = <2>;
 864                 };
 865
 866                 gcc: clock-controller@1800000 {
 867                         compatible = "qcom,gcc-msm8916";
 868                         #clock-cells = <1>;
 869                         #reset-cells = <1>;
 870                         #power-domain-cells = <1>;
 871                         reg = <0x01800000 0x80000>;
 872                 };
 873
 874                 tcsr_mutex: hwlock@1905000 {
 875                         compatible = "qcom,tcsr-mutex";
 876                         reg = <0x01905000 0x20000>;
 877                         #hwlock-cells = <1>;
 878                 };
 879
 880                 tcsr: syscon@1937000 {
 881                         compatible = "qcom,tcsr-msm8916", "syscon";
 882                         reg = <0x01937000 0x30000>;
 883                 };
 884
 885                 mdss: mdss@1a00000 {
 886                         compatible = "qcom,mdss";
 887                         reg = <0x01a00000 0x1000>,
 888                               <0x01ac8000 0x3000>;
 889                         reg-names = "mdss_phys", "vbif_phys";
 890
 891                         power-domains = <&gcc MDSS_GDSC>;
 892
 893                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 894                                  <&gcc GCC_MDSS_AXI_CLK>,
 895                                  <&gcc GCC_MDSS_VSYNC_CLK>;
 896                         clock-names = "iface",
 897                                       "bus",
 898                                       "vsync";
 899
 900                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 901
 902                         interrupt-controller;
 903                         #interrupt-cells = <1>;
 904
 905                         #address-cells = <1>;
 906                         #size-cells = <1>;
 907                         ranges;
 908
 909                         mdp: mdp@1a01000 {
 910                                 compatible = "qcom,mdp5";
 911                                 reg = <0x01a01000 0x89000>;
 912                                 reg-names = "mdp_phys";
 913
 914                                 interrupt-parent = <&mdss>;
 915                                 interrupts = <0>;
 916
 917                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 918                                          <&gcc GCC_MDSS_AXI_CLK>,
 919                                          <&gcc GCC_MDSS_MDP_CLK>,
 920                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 921                                 clock-names = "iface",
 922                                               "bus",
 923                                               "core",
 924                                               "vsync";
 925
 926                                 iommus = <&apps_iommu 4>;
 927
 928                                 ports {
 929                                         #address-cells = <1>;
 930                                         #size-cells = <0>;
 931
 932                                         port@0 {
 933                                                 reg = <0>;
 934                                                 mdp5_intf1_out: endpoint {
 935                                                         remote-endpoint = <&dsi0_in>;
 936                                                 };
 937                                         };
 938                                 };
 939                         };
 940
 941                         dsi0: dsi@1a98000 {
 942                                 compatible = "qcom,mdss-dsi-ctrl";
 943                                 reg = <0x01a98000 0x25c>;
 944                                 reg-names = "dsi_ctrl";
 945
 946                                 interrupt-parent = <&mdss>;
 947                                 interrupts = <4>;
 948
 949                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 950                                                   <&gcc PCLK0_CLK_SRC>;
 951                                 assigned-clock-parents = <&dsi_phy0 0>,
 952                                                          <&dsi_phy0 1>;
 953
 954                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 955                                          <&gcc GCC_MDSS_AHB_CLK>,
 956                                          <&gcc GCC_MDSS_AXI_CLK>,
 957                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 958                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 959                                          <&gcc GCC_MDSS_ESC0_CLK>;
 960                                 clock-names = "mdp_core",
 961                                               "iface",
 962                                               "bus",
 963                                               "byte",
 964                                               "pixel",
 965                                               "core";
 966                                 phys = <&dsi_phy0>;
 967                                 phy-names = "dsi-phy";
 968
 969                                 #address-cells = <1>;
 970                                 #size-cells = <0>;
 971
 972                                 ports {
 973                                         #address-cells = <1>;
 974                                         #size-cells = <0>;
 975
 976                                         port@0 {
 977                                                 reg = <0>;
 978                                                 dsi0_in: endpoint {
 979                                                         remote-endpoint = <&mdp5_intf1_out>;
 980                                                 };
 981                                         };
 982
 983                                         port@1 {
 984                                                 reg = <1>;
 985                                                 dsi0_out: endpoint {
 986                                                 };
 987                                         };
 988                                 };
 989                         };
 990
 991                         dsi_phy0: dsi-phy@1a98300 {
 992                                 compatible = "qcom,dsi-phy-28nm-lp";
 993                                 reg = <0x01a98300 0xd4>,
 994                                       <0x01a98500 0x280>,
 995                                       <0x01a98780 0x30>;
 996                                 reg-names = "dsi_pll",
 997                                             "dsi_phy",
 998                                             "dsi_phy_regulator";
 999
1000                                 #clock-cells = <1>;
1001                                 #phy-cells = <0>;
1002
1003                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1004                                          <&xo_board>;
1005                                 clock-names = "iface", "ref";
1006                         };
1007                 };
1008
1009                 camss: camss@1b00000 {
1010                         compatible = "qcom,msm8916-camss";
1011                         reg = <0x01b0ac00 0x200>,
1012                                 <0x01b00030 0x4>,
1013                                 <0x01b0b000 0x200>,
1014                                 <0x01b00038 0x4>,
1015                                 <0x01b08000 0x100>,
1016                                 <0x01b08400 0x100>,
1017                                 <0x01b0a000 0x500>,
1018                                 <0x01b00020 0x10>,
1019                                 <0x01b10000 0x1000>;
1020                         reg-names = "csiphy0",
1021                                 "csiphy0_clk_mux",
1022                                 "csiphy1",
1023                                 "csiphy1_clk_mux",
1024                                 "csid0",
1025                                 "csid1",
1026                                 "ispif",
1027                                 "csi_clk_mux",
1028                                 "vfe0";
1029                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1030                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1031                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1032                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1033                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1034                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1035                         interrupt-names = "csiphy0",
1036                                 "csiphy1",
1037                                 "csid0",
1038                                 "csid1",
1039                                 "ispif",
1040                                 "vfe0";
1041                         power-domains = <&gcc VFE_GDSC>;
1042                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1043                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1044                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1045                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1046                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1047                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1048                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1049                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1050                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1051                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1052                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1053                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1054                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1055                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1056                                 <&gcc GCC_CAMSS_AHB_CLK>,
1057                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1058                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1059                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1060                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1061                         clock-names = "top_ahb",
1062                                 "ispif_ahb",
1063                                 "csiphy0_timer",
1064                                 "csiphy1_timer",
1065                                 "csi0_ahb",
1066                                 "csi0",
1067                                 "csi0_phy",
1068                                 "csi0_pix",
1069                                 "csi0_rdi",
1070                                 "csi1_ahb",
1071                                 "csi1",
1072                                 "csi1_phy",
1073                                 "csi1_pix",
1074                                 "csi1_rdi",
1075                                 "ahb",
1076                                 "vfe0",
1077                                 "csi_vfe0",
1078                                 "vfe_ahb",
1079                                 "vfe_axi";
1080                         iommus = <&apps_iommu 3>;
1081                         status = "disabled";
1082                         ports {
1083                                 #address-cells = <1>;
1084                                 #size-cells = <0>;
1085                         };
1086                 };
1087
1088                 cci: cci@1b0c000 {
1089                         compatible = "qcom,msm8916-cci";
1090                         #address-cells = <1>;
1091                         #size-cells = <0>;
1092                         reg = <0x01b0c000 0x1000>;
1093                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1094                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1095                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1096                                 <&gcc GCC_CAMSS_CCI_CLK>,
1097                                 <&gcc GCC_CAMSS_AHB_CLK>;
1098                         clock-names = "camss_top_ahb", "cci_ahb",
1099                                           "cci", "camss_ahb";
1100                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1101                                           <&gcc GCC_CAMSS_CCI_CLK>;
1102                         assigned-clock-rates = <80000000>, <19200000>;
1103                         pinctrl-names = "default";
1104                         pinctrl-0 = <&cci0_default>;
1105                         status = "disabled";
1106
1107                         cci_i2c0: i2c-bus@0 {
1108                                 reg = <0>;
1109                                 clock-frequency = <400000>;
1110                                 #address-cells = <1>;
1111                                 #size-cells = <0>;
1112                         };
1113                 };
1114
1115                 gpu@1c00000 {
1116                         compatible = "qcom,adreno-306.0", "qcom,adreno";
1117                         reg = <0x01c00000 0x20000>;
1118                         reg-names = "kgsl_3d0_reg_memory";
1119                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1120                         interrupt-names = "kgsl_3d0_irq";
1121                         clock-names =
1122                             "core",
1123                             "iface",
1124                             "mem",
1125                             "mem_iface",
1126                             "alt_mem_iface",
1127                             "gfx3d";
1128                         clocks =
1129                             <&gcc GCC_OXILI_GFX3D_CLK>,
1130                             <&gcc GCC_OXILI_AHB_CLK>,
1131                             <&gcc GCC_OXILI_GMEM_CLK>,
1132                             <&gcc GCC_BIMC_GFX_CLK>,
1133                             <&gcc GCC_BIMC_GPU_CLK>,
1134                             <&gcc GFX3D_CLK_SRC>;
1135                         power-domains = <&gcc OXILI_GDSC>;
1136                         operating-points-v2 = <&gpu_opp_table>;
1137                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1138
1139                         gpu_opp_table: opp-table {
1140                                 compatible = "operating-points-v2";
1141
1142                                 opp-400000000 {
1143                                         opp-hz = /bits/ 64 <400000000>;
1144                                 };
1145                                 opp-19200000 {
1146                                         opp-hz = /bits/ 64 <19200000>;
1147                                 };
1148                         };
1149                 };
1150
1151                 venus: video-codec@1d00000 {
1152                         compatible = "qcom,msm8916-venus";
1153                         reg = <0x01d00000 0xff000>;
1154                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1155                         power-domains = <&gcc VENUS_GDSC>;
1156                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1157                                  <&gcc GCC_VENUS0_AHB_CLK>,
1158                                  <&gcc GCC_VENUS0_AXI_CLK>;
1159                         clock-names = "core", "iface", "bus";
1160                         iommus = <&apps_iommu 5>;
1161                         memory-region = <&venus_mem>;
1162                         status = "okay";
1163
1164                         video-decoder {
1165                                 compatible = "venus-decoder";
1166                         };
1167
1168                         video-encoder {
1169                                 compatible = "venus-encoder";
1170                         };
1171                 };
1172
1173                 apps_iommu: iommu@1ef0000 {
1174                         #address-cells = <1>;
1175                         #size-cells = <1>;
1176                         #iommu-cells = <1>;
1177                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1178                         ranges = <0 0x01e20000 0x40000>;
1179                         reg = <0x01ef0000 0x3000>;
1180                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1181                                  <&gcc GCC_APSS_TCU_CLK>;
1182                         clock-names = "iface", "bus";
1183                         qcom,iommu-secure-id = <17>;
1184
1185                         // vfe:
1186                         iommu-ctx@3000 {
1187                                 compatible = "qcom,msm-iommu-v1-sec";
1188                                 reg = <0x3000 0x1000>;
1189                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1190                         };
1191
1192                         // mdp_0:
1193                         iommu-ctx@4000 {
1194                                 compatible = "qcom,msm-iommu-v1-ns";
1195                                 reg = <0x4000 0x1000>;
1196                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1197                         };
1198
1199                         // venus_ns:
1200                         iommu-ctx@5000 {
1201                                 compatible = "qcom,msm-iommu-v1-sec";
1202                                 reg = <0x5000 0x1000>;
1203                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1204                         };
1205                 };
1206
1207                 gpu_iommu: iommu@1f08000 {
1208                         #address-cells = <1>;
1209                         #size-cells = <1>;
1210                         #iommu-cells = <1>;
1211                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1212                         ranges = <0 0x01f08000 0x10000>;
1213                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1214                                  <&gcc GCC_GFX_TCU_CLK>;
1215                         clock-names = "iface", "bus";
1216                         qcom,iommu-secure-id = <18>;
1217
1218                         // gfx3d_user:
1219                         iommu-ctx@1000 {
1220                                 compatible = "qcom,msm-iommu-v1-ns";
1221                                 reg = <0x1000 0x1000>;
1222                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1223                         };
1224
1225                         // gfx3d_priv:
1226                         iommu-ctx@2000 {
1227                                 compatible = "qcom,msm-iommu-v1-ns";
1228                                 reg = <0x2000 0x1000>;
1229                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1230                         };
1231                 };
1232
1233                 spmi_bus: spmi@200f000 {
1234                         compatible = "qcom,spmi-pmic-arb";
1235                         reg = <0x0200f000 0x001000>,
1236                               <0x02400000 0x400000>,
1237                               <0x02c00000 0x400000>,
1238                               <0x03800000 0x200000>,
1239                               <0x0200a000 0x002100>;
1240                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1241                         interrupt-names = "periph_irq";
1242                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1243                         qcom,ee = <0>;
1244                         qcom,channel = <0>;
1245                         #address-cells = <2>;
1246                         #size-cells = <0>;
1247                         interrupt-controller;
1248                         #interrupt-cells = <4>;
1249                 };
1250
1251                 mpss: remoteproc@4080000 {
1252                         compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1253                         reg = <0x04080000 0x100>,
1254                               <0x04020000 0x040>;
1255
1256                         reg-names = "qdsp6", "rmb";
1257
1258                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1259                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1260                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1261                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1262                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1263                         interrupt-names = "wdog", "fatal", "ready",
1264                                           "handover", "stop-ack";
1265
1266                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1267                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1268                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1269                                  <&xo_board>;
1270                         clock-names = "iface", "bus", "mem", "xo";
1271
1272                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1273                         qcom,smem-state-names = "stop";
1274
1275                         resets = <&scm 0>;
1276                         reset-names = "mss_restart";
1277
1278                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1279
1280                         status = "disabled";
1281
1282                         mba {
1283                                 memory-region = <&mba_mem>;
1284                         };
1285
1286                         mpss {
1287                                 memory-region = <&mpss_mem>;
1288                         };
1289
1290                         smd-edge {
1291                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1292
1293                                 qcom,smd-edge = <0>;
1294                                 qcom,ipc = <&apcs 8 12>;
1295                                 qcom,remote-pid = <1>;
1296
1297                                 label = "hexagon";
1298
1299                                 fastrpc {
1300                                         compatible = "qcom,fastrpc";
1301                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
1302                                         label = "adsp";
1303
1304                                         #address-cells = <1>;
1305                                         #size-cells = <0>;
1306
1307                                         cb@1 {
1308                                                 compatible = "qcom,fastrpc-compute-cb";
1309                                                 reg = <1>;
1310                                         };
1311                                 };
1312                         };
1313                 };
1314
1315                 sound: sound@7702000 {
1316                         status = "disabled";
1317                         compatible = "qcom,apq8016-sbc-sndcard";
1318                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
1319                         reg-names = "mic-iomux", "spkr-iomux";
1320                 };
1321
1322                 lpass: audio-controller@7708000 {
1323                         status = "disabled";
1324                         compatible = "qcom,lpass-cpu-apq8016";
1325                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1326                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1327                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1328                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1329                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1330                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1331                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1332
1333                         clock-names = "ahbix-clk",
1334                                         "pcnoc-mport-clk",
1335                                         "pcnoc-sway-clk",
1336                                         "mi2s-bit-clk0",
1337                                         "mi2s-bit-clk1",
1338                                         "mi2s-bit-clk2",
1339                                         "mi2s-bit-clk3";
1340                         #sound-dai-cells = <1>;
1341
1342                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1343                         interrupt-names = "lpass-irq-lpaif";
1344                         reg = <0x07708000 0x10000>;
1345                         reg-names = "lpass-lpaif";
1346
1347                         #address-cells = <1>;
1348                         #size-cells = <0>;
1349                 };
1350
1351                 lpass_codec: audio-codec@771c000 {
1352                         compatible = "qcom,msm8916-wcd-digital-codec";
1353                         reg = <0x0771c000 0x400>;
1354                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1355                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
1356                         clock-names = "ahbix-clk", "mclk";
1357                         #sound-dai-cells = <1>;
1358                 };
1359
1360                 sdhc_1: sdhci@7824000 {
1361                         compatible = "qcom,sdhci-msm-v4";
1362                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1363                         reg-names = "hc_mem", "core_mem";
1364
1365                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1366                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1367                         interrupt-names = "hc_irq", "pwr_irq";
1368                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1369                                  <&gcc GCC_SDCC1_AHB_CLK>,
1370                                  <&xo_board>;
1371                         clock-names = "core", "iface", "xo";
1372                         mmc-ddr-1_8v;
1373                         bus-width = <8>;
1374                         non-removable;
1375                         status = "disabled";
1376                 };
1377
1378                 sdhc_2: sdhci@7864000 {
1379                         compatible = "qcom,sdhci-msm-v4";
1380                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1381                         reg-names = "hc_mem", "core_mem";
1382
1383                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1384                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1385                         interrupt-names = "hc_irq", "pwr_irq";
1386                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1387                                  <&gcc GCC_SDCC2_AHB_CLK>,
1388                                  <&xo_board>;
1389                         clock-names = "core", "iface", "xo";
1390                         bus-width = <4>;
1391                         status = "disabled";
1392                 };
1393
1394                 blsp_dma: dma@7884000 {
1395                         compatible = "qcom,bam-v1.7.0";
1396                         reg = <0x07884000 0x23000>;
1397                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1398                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1399                         clock-names = "bam_clk";
1400                         #dma-cells = <1>;
1401                         qcom,ee = <0>;
1402                         status = "disabled";
1403                 };
1404
1405                 blsp1_uart1: serial@78af000 {
1406                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1407                         reg = <0x078af000 0x200>;
1408                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1409                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1410                         clock-names = "core", "iface";
1411                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
1412                         dma-names = "rx", "tx";
1413                         pinctrl-names = "default", "sleep";
1414                         pinctrl-0 = <&blsp1_uart1_default>;
1415                         pinctrl-1 = <&blsp1_uart1_sleep>;
1416                         status = "disabled";
1417                 };
1418
1419                 blsp1_uart2: serial@78b0000 {
1420                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1421                         reg = <0x078b0000 0x200>;
1422                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1423                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1424                         clock-names = "core", "iface";
1425                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
1426                         dma-names = "rx", "tx";
1427                         pinctrl-names = "default", "sleep";
1428                         pinctrl-0 = <&blsp1_uart2_default>;
1429                         pinctrl-1 = <&blsp1_uart2_sleep>;
1430                         status = "disabled";
1431                 };
1432
1433                 blsp_i2c1: i2c@78b5000 {
1434                         compatible = "qcom,i2c-qup-v2.2.1";
1435                         reg = <0x078b5000 0x500>;
1436                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1437                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1438                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
1439                         clock-names = "iface", "core";
1440                         pinctrl-names = "default", "sleep";
1441                         pinctrl-0 = <&i2c1_default>;
1442                         pinctrl-1 = <&i2c1_sleep>;
1443                         #address-cells = <1>;
1444                         #size-cells = <0>;
1445                         status = "disabled";
1446                 };
1447
1448                 blsp_spi1: spi@78b5000 {
1449                         compatible = "qcom,spi-qup-v2.2.1";
1450                         reg = <0x078b5000 0x500>;
1451                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1452                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1453                                  <&gcc GCC_BLSP1_AHB_CLK>;
1454                         clock-names = "core", "iface";
1455                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
1456                         dma-names = "rx", "tx";
1457                         pinctrl-names = "default", "sleep";
1458                         pinctrl-0 = <&spi1_default>;
1459                         pinctrl-1 = <&spi1_sleep>;
1460                         #address-cells = <1>;
1461                         #size-cells = <0>;
1462                         status = "disabled";
1463                 };
1464
1465                 blsp_i2c2: i2c@78b6000 {
1466                         compatible = "qcom,i2c-qup-v2.2.1";
1467                         reg = <0x078b6000 0x500>;
1468                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1469                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1470                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
1471                         clock-names = "iface", "core";
1472                         pinctrl-names = "default", "sleep";
1473                         pinctrl-0 = <&i2c2_default>;
1474                         pinctrl-1 = <&i2c2_sleep>;
1475                         #address-cells = <1>;
1476                         #size-cells = <0>;
1477                         status = "disabled";
1478                 };
1479
1480                 blsp_spi2: spi@78b6000 {
1481                         compatible = "qcom,spi-qup-v2.2.1";
1482                         reg = <0x078b6000 0x500>;
1483                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1484                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1485                                  <&gcc GCC_BLSP1_AHB_CLK>;
1486                         clock-names = "core", "iface";
1487                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
1488                         dma-names = "rx", "tx";
1489                         pinctrl-names = "default", "sleep";
1490                         pinctrl-0 = <&spi2_default>;
1491                         pinctrl-1 = <&spi2_sleep>;
1492                         #address-cells = <1>;
1493                         #size-cells = <0>;
1494                         status = "disabled";
1495                 };
1496
1497                 blsp_spi3: spi@78b7000 {
1498                         compatible = "qcom,spi-qup-v2.2.1";
1499                         reg = <0x078b7000 0x500>;
1500                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1501                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1502                                  <&gcc GCC_BLSP1_AHB_CLK>;
1503                         clock-names = "core", "iface";
1504                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
1505                         dma-names = "rx", "tx";
1506                         pinctrl-names = "default", "sleep";
1507                         pinctrl-0 = <&spi3_default>;
1508                         pinctrl-1 = <&spi3_sleep>;
1509                         #address-cells = <1>;
1510                         #size-cells = <0>;
1511                         status = "disabled";
1512                 };
1513
1514                 blsp_i2c4: i2c@78b8000 {
1515                         compatible = "qcom,i2c-qup-v2.2.1";
1516                         reg = <0x078b8000 0x500>;
1517                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1518                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1519                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1520                         clock-names = "iface", "core";
1521                         pinctrl-names = "default", "sleep";
1522                         pinctrl-0 = <&i2c4_default>;
1523                         pinctrl-1 = <&i2c4_sleep>;
1524                         #address-cells = <1>;
1525                         #size-cells = <0>;
1526                         status = "disabled";
1527                 };
1528
1529                 blsp_spi4: spi@78b8000 {
1530                         compatible = "qcom,spi-qup-v2.2.1";
1531                         reg = <0x078b8000 0x500>;
1532                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1533                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1534                                  <&gcc GCC_BLSP1_AHB_CLK>;
1535                         clock-names = "core", "iface";
1536                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
1537                         dma-names = "rx", "tx";
1538                         pinctrl-names = "default", "sleep";
1539                         pinctrl-0 = <&spi4_default>;
1540                         pinctrl-1 = <&spi4_sleep>;
1541                         #address-cells = <1>;
1542                         #size-cells = <0>;
1543                         status = "disabled";
1544                 };
1545
1546                 blsp_i2c5: i2c@78b9000 {
1547                         compatible = "qcom,i2c-qup-v2.2.1";
1548                         reg = <0x078b9000 0x500>;
1549                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1550                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1551                                  <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
1552                         clock-names = "iface", "core";
1553                         pinctrl-names = "default", "sleep";
1554                         pinctrl-0 = <&i2c5_default>;
1555                         pinctrl-1 = <&i2c5_sleep>;
1556                         #address-cells = <1>;
1557                         #size-cells = <0>;
1558                         status = "disabled";
1559                 };
1560
1561                 blsp_spi5: spi@78b9000 {
1562                         compatible = "qcom,spi-qup-v2.2.1";
1563                         reg = <0x078b9000 0x500>;
1564                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1565                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1566                                  <&gcc GCC_BLSP1_AHB_CLK>;
1567                         clock-names = "core", "iface";
1568                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
1569                         dma-names = "rx", "tx";
1570                         pinctrl-names = "default", "sleep";
1571                         pinctrl-0 = <&spi5_default>;
1572                         pinctrl-1 = <&spi5_sleep>;
1573                         #address-cells = <1>;
1574                         #size-cells = <0>;
1575                         status = "disabled";
1576                 };
1577
1578                 blsp_i2c6: i2c@78ba000 {
1579                         compatible = "qcom,i2c-qup-v2.2.1";
1580                         reg = <0x078ba000 0x500>;
1581                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1582                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1583                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
1584                         clock-names = "iface", "core";
1585                         pinctrl-names = "default", "sleep";
1586                         pinctrl-0 = <&i2c6_default>;
1587                         pinctrl-1 = <&i2c6_sleep>;
1588                         #address-cells = <1>;
1589                         #size-cells = <0>;
1590                         status = "disabled";
1591                 };
1592
1593                 blsp_spi6: spi@78ba000 {
1594                         compatible = "qcom,spi-qup-v2.2.1";
1595                         reg = <0x078ba000 0x500>;
1596                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1597                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1598                                  <&gcc GCC_BLSP1_AHB_CLK>;
1599                         clock-names = "core", "iface";
1600                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
1601                         dma-names = "rx", "tx";
1602                         pinctrl-names = "default", "sleep";
1603                         pinctrl-0 = <&spi6_default>;
1604                         pinctrl-1 = <&spi6_sleep>;
1605                         #address-cells = <1>;
1606                         #size-cells = <0>;
1607                         status = "disabled";
1608                 };
1609
1610                 usb: usb@78d9000 {
1611                         compatible = "qcom,ci-hdrc";
1612                         reg = <0x078d9000 0x200>,
1613                               <0x078d9200 0x200>;
1614                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1615                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1616                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1617                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
1618                         clock-names = "iface", "core";
1619                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1620                         assigned-clock-rates = <80000000>;
1621                         resets = <&gcc GCC_USB_HS_BCR>;
1622                         reset-names = "core";
1623                         phy_type = "ulpi";
1624                         dr_mode = "otg";
1625                         hnp-disable;
1626                         srp-disable;
1627                         adp-disable;
1628                         ahb-burst-config = <0>;
1629                         phy-names = "usb-phy";
1630                         phys = <&usb_hs_phy>;
1631                         status = "disabled";
1632                         #reset-cells = <1>;
1633
1634                         ulpi {
1635                                 usb_hs_phy: phy {
1636                                         compatible = "qcom,usb-hs-phy-msm8916",
1637                                                      "qcom,usb-hs-phy";
1638                                         #phy-cells = <0>;
1639                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1640                                         clock-names = "ref", "sleep";
1641                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1642                                         reset-names = "phy", "por";
1643                                         qcom,init-seq = /bits/ 8 <0x0 0x44
1644                                                 0x1 0x6b 0x2 0x24 0x3 0x13>;
1645                                 };
1646                         };
1647                 };
1648
1649                 pronto: remoteproc@a21b000 {
1650                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1651                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1652                         reg-names = "ccu", "dxe", "pmu";
1653
1654                         memory-region = <&wcnss_mem>;
1655
1656                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1657                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1658                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1659                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1660                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1661                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1662
1663                         qcom,state = <&wcnss_smp2p_out 0>;
1664                         qcom,state-names = "stop";
1665
1666                         pinctrl-names = "default";
1667                         pinctrl-0 = <&wcnss_pin_a>;
1668
1669                         status = "disabled";
1670
1671                         iris {
1672                                 compatible = "qcom,wcn3620";
1673
1674                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1675                                 clock-names = "xo";
1676                         };
1677
1678                         smd-edge {
1679                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1680
1681                                 qcom,ipc = <&apcs 8 17>;
1682                                 qcom,smd-edge = <6>;
1683                                 qcom,remote-pid = <4>;
1684
1685                                 label = "pronto";
1686
1687                                 wcnss {
1688                                         compatible = "qcom,wcnss";
1689                                         qcom,smd-channels = "WCNSS_CTRL";
1690
1691                                         qcom,mmio = <&pronto>;
1692
1693                                         bt {
1694                                                 compatible = "qcom,wcnss-bt";
1695                                         };
1696
1697                                         wifi {
1698                                                 compatible = "qcom,wcnss-wlan";
1699
1700                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1701                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1702                                                 interrupt-names = "tx", "rx";
1703
1704                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1705                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1706                                         };
1707                                 };
1708                         };
1709                 };
1710
1711                 intc: interrupt-controller@b000000 {
1712                         compatible = "qcom,msm-qgic2";
1713                         interrupt-controller;
1714                         #interrupt-cells = <3>;
1715                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1716                 };
1717
1718                 apcs: mailbox@b011000 {
1719                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1720                         reg = <0x0b011000 0x1000>;
1721                         #mbox-cells = <1>;
1722                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1723                         clock-names = "pll", "aux";
1724                         #clock-cells = <0>;
1725                 };
1726
1727                 a53pll: clock@b016000 {
1728                         compatible = "qcom,msm8916-a53pll";
1729                         reg = <0x0b016000 0x40>;
1730                         #clock-cells = <0>;
1731                 };
1732
1733                 timer@b020000 {
1734                         #address-cells = <1>;
1735                         #size-cells = <1>;
1736                         ranges;
1737                         compatible = "arm,armv7-timer-mem";
1738                         reg = <0x0b020000 0x1000>;
1739                         clock-frequency = <19200000>;
1740
1741                         frame@b021000 {
1742                                 frame-number = <0>;
1743                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1744                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1745                                 reg = <0x0b021000 0x1000>,
1746                                       <0x0b022000 0x1000>;
1747                         };
1748
1749                         frame@b023000 {
1750                                 frame-number = <1>;
1751                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1752                                 reg = <0x0b023000 0x1000>;
1753                                 status = "disabled";
1754                         };
1755
1756                         frame@b024000 {
1757                                 frame-number = <2>;
1758                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1759                                 reg = <0x0b024000 0x1000>;
1760                                 status = "disabled";
1761                         };
1762
1763                         frame@b025000 {
1764                                 frame-number = <3>;
1765                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1766                                 reg = <0x0b025000 0x1000>;
1767                                 status = "disabled";
1768                         };
1769
1770                         frame@b026000 {
1771                                 frame-number = <4>;
1772                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1773                                 reg = <0x0b026000 0x1000>;
1774                                 status = "disabled";
1775                         };
1776
1777                         frame@b027000 {
1778                                 frame-number = <5>;
1779                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1780                                 reg = <0x0b027000 0x1000>;
1781                                 status = "disabled";
1782                         };
1783
1784                         frame@b028000 {
1785                                 frame-number = <6>;
1786                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1787                                 reg = <0x0b028000 0x1000>;
1788                                 status = "disabled";
1789                         };
1790                 };
1791         };
1792
1793         thermal-zones {
1794                 cpu0-1-thermal {
1795                         polling-delay-passive = <250>;
1796                         polling-delay = <1000>;
1797
1798                         thermal-sensors = <&tsens 5>;
1799
1800                         trips {
1801                                 cpu0_1_alert0: trip-point0 {
1802                                         temperature = <75000>;
1803                                         hysteresis = <2000>;
1804                                         type = "passive";
1805                                 };
1806                                 cpu0_1_crit: cpu_crit {
1807                                         temperature = <110000>;
1808                                         hysteresis = <2000>;
1809                                         type = "critical";
1810                                 };
1811                         };
1812
1813                         cooling-maps {
1814                                 map0 {
1815                                         trip = <&cpu0_1_alert0>;
1816                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1817                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1818                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1819                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1820                                 };
1821                         };
1822                 };
1823
1824                 cpu2-3-thermal {
1825                         polling-delay-passive = <250>;
1826                         polling-delay = <1000>;
1827
1828                         thermal-sensors = <&tsens 4>;
1829
1830                         trips {
1831                                 cpu2_3_alert0: trip-point0 {
1832                                         temperature = <75000>;
1833                                         hysteresis = <2000>;
1834                                         type = "passive";
1835                                 };
1836                                 cpu2_3_crit: cpu_crit {
1837                                         temperature = <110000>;
1838                                         hysteresis = <2000>;
1839                                         type = "critical";
1840                                 };
1841                         };
1842
1843                         cooling-maps {
1844                                 map0 {
1845                                         trip = <&cpu2_3_alert0>;
1846                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1847                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1848                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1849                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1850                                 };
1851                         };
1852                 };
1853
1854                 gpu-thermal {
1855                         polling-delay-passive = <250>;
1856                         polling-delay = <1000>;
1857
1858                         thermal-sensors = <&tsens 2>;
1859
1860                         trips {
1861                                 gpu_alert0: trip-point0 {
1862                                         temperature = <75000>;
1863                                         hysteresis = <2000>;
1864                                         type = "passive";
1865                                 };
1866                                 gpu_crit: gpu_crit {
1867                                         temperature = <95000>;
1868                                         hysteresis = <2000>;
1869                                         type = "critical";
1870                                 };
1871                         };
1872                 };
1873
1874                 camera-thermal {
1875                         polling-delay-passive = <250>;
1876                         polling-delay = <1000>;
1877
1878                         thermal-sensors = <&tsens 1>;
1879
1880                         trips {
1881                                 cam_alert0: trip-point0 {
1882                                         temperature = <75000>;
1883                                         hysteresis = <2000>;
1884                                         type = "hot";
1885                                 };
1886                         };
1887                 };
1888
1889                 modem-thermal {
1890                         polling-delay-passive = <250>;
1891                         polling-delay = <1000>;
1892
1893                         thermal-sensors = <&tsens 0>;
1894
1895                         trips {
1896                                 modem_alert0: trip-point0 {
1897                                         temperature = <85000>;
1898                                         hysteresis = <2000>;
1899                                         type = "hot";
1900                                 };
1901                         };
1902                 };
1903
1904         };
1905
1906         timer {
1907                 compatible = "arm,armv8-timer";
1908                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1909                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1910                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1911                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1912         };
1913 };
1914
1915 #include "msm8916-pins.dtsi"