1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
22 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
23 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
29 device_type = "memory";
30 /* We expect the bootloader to fill in the reg */
40 reg = <0x0 0x86000000 0x0 0x300000>;
44 smem_mem: smem_region@86300000 {
45 reg = <0x0 0x86300000 0x0 0x100000>;
50 reg = <0x0 0x86400000 0x0 0x100000>;
55 reg = <0x0 0x86500000 0x0 0x180000>;
60 reg = <0x0 0x86680000 0x0 0x80000>;
65 compatible = "qcom,rmtfs-mem";
66 reg = <0x0 0x86700000 0x0 0xe0000>;
73 reg = <0x0 0x867e0000 0x0 0x20000>;
77 mpss_mem: mpss@86800000 {
78 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 wcnss_mem: wcnss@89300000 {
83 reg = <0x0 0x89300000 0x0 0x600000>;
87 venus_mem: venus@89900000 {
88 reg = <0x0 0x89900000 0x0 0x600000>;
92 mba_mem: mba@8ea00000 {
94 reg = <0 0x8ea00000 0 0x100000>;
100 compatible = "fixed-clock";
102 clock-frequency = <19200000>;
105 sleep_clk: sleep-clk {
106 compatible = "fixed-clock";
108 clock-frequency = <32768>;
113 #address-cells = <1>;
118 compatible = "arm,cortex-a53";
120 next-level-cache = <&L2_0>;
121 enable-method = "psci";
123 operating-points-v2 = <&cpu_opp_table>;
124 #cooling-cells = <2>;
125 power-domains = <&CPU_PD0>;
126 power-domain-names = "psci";
131 compatible = "arm,cortex-a53";
133 next-level-cache = <&L2_0>;
134 enable-method = "psci";
136 operating-points-v2 = <&cpu_opp_table>;
137 #cooling-cells = <2>;
138 power-domains = <&CPU_PD1>;
139 power-domain-names = "psci";
144 compatible = "arm,cortex-a53";
146 next-level-cache = <&L2_0>;
147 enable-method = "psci";
149 operating-points-v2 = <&cpu_opp_table>;
150 #cooling-cells = <2>;
151 power-domains = <&CPU_PD2>;
152 power-domain-names = "psci";
157 compatible = "arm,cortex-a53";
159 next-level-cache = <&L2_0>;
160 enable-method = "psci";
162 operating-points-v2 = <&cpu_opp_table>;
163 #cooling-cells = <2>;
164 power-domains = <&CPU_PD3>;
165 power-domain-names = "psci";
169 compatible = "cache";
174 entry-method = "psci";
176 CPU_SLEEP_0: cpu-sleep-0 {
177 compatible = "arm,idle-state";
178 idle-state-name = "standalone-power-collapse";
179 arm,psci-suspend-param = <0x40000002>;
180 entry-latency-us = <130>;
181 exit-latency-us = <150>;
182 min-residency-us = <2000>;
189 CLUSTER_RET: cluster-retention {
190 compatible = "domain-idle-state";
191 arm,psci-suspend-param = <0x41000012>;
192 entry-latency-us = <500>;
193 exit-latency-us = <500>;
194 min-residency-us = <2000>;
197 CLUSTER_PWRDN: cluster-gdhs {
198 compatible = "domain-idle-state";
199 arm,psci-suspend-param = <0x41000032>;
200 entry-latency-us = <2000>;
201 exit-latency-us = <2000>;
202 min-residency-us = <6000>;
207 cpu_opp_table: cpu-opp-table {
208 compatible = "operating-points-v2";
212 opp-hz = /bits/ 64 <200000000>;
215 opp-hz = /bits/ 64 <400000000>;
218 opp-hz = /bits/ 64 <800000000>;
221 opp-hz = /bits/ 64 <998400000>;
227 compatible = "qcom,scm-msm8916", "qcom,scm";
228 clocks = <&gcc GCC_CRYPTO_CLK>,
229 <&gcc GCC_CRYPTO_AXI_CLK>,
230 <&gcc GCC_CRYPTO_AHB_CLK>;
231 clock-names = "core", "bus", "iface";
234 qcom,dload-mode = <&tcsr 0x6100>;
239 compatible = "arm,cortex-a53-pmu";
240 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
244 compatible = "arm,psci-1.0";
247 CPU_PD0: power-domain-cpu0 {
248 #power-domain-cells = <0>;
249 power-domains = <&CLUSTER_PD>;
250 domain-idle-states = <&CPU_SLEEP_0>;
253 CPU_PD1: power-domain-cpu1 {
254 #power-domain-cells = <0>;
255 power-domains = <&CLUSTER_PD>;
256 domain-idle-states = <&CPU_SLEEP_0>;
259 CPU_PD2: power-domain-cpu2 {
260 #power-domain-cells = <0>;
261 power-domains = <&CLUSTER_PD>;
262 domain-idle-states = <&CPU_SLEEP_0>;
265 CPU_PD3: power-domain-cpu3 {
266 #power-domain-cells = <0>;
267 power-domains = <&CLUSTER_PD>;
268 domain-idle-states = <&CPU_SLEEP_0>;
271 CLUSTER_PD: power-domain-cluster {
272 #power-domain-cells = <0>;
273 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
278 compatible = "qcom,smd";
281 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
282 qcom,ipc = <&apcs 8 0>;
283 qcom,smd-edge = <15>;
285 rpm_requests: rpm-requests {
286 compatible = "qcom,rpm-msm8916";
287 qcom,smd-channels = "rpm_requests";
289 rpmcc: clock-controller {
290 compatible = "qcom,rpmcc-msm8916";
294 rpmpd: power-controller {
295 compatible = "qcom,msm8916-rpmpd";
296 #power-domain-cells = <1>;
297 operating-points-v2 = <&rpmpd_opp_table>;
299 rpmpd_opp_table: opp-table {
300 compatible = "operating-points-v2";
302 rpmpd_opp_ret: opp1 {
305 rpmpd_opp_svs_krait: opp2 {
308 rpmpd_opp_svs_soc: opp3 {
311 rpmpd_opp_nom: opp4 {
314 rpmpd_opp_turbo: opp5 {
317 rpmpd_opp_super_turbo: opp6 {
327 compatible = "qcom,smem";
329 memory-region = <&smem_mem>;
330 qcom,rpm-msg-ram = <&rpm_msg_ram>;
332 hwlocks = <&tcsr_mutex 3>;
336 compatible = "qcom,smp2p";
337 qcom,smem = <435>, <428>;
339 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
341 qcom,ipc = <&apcs 8 14>;
343 qcom,local-pid = <0>;
344 qcom,remote-pid = <1>;
346 hexagon_smp2p_out: master-kernel {
347 qcom,entry-name = "master-kernel";
349 #qcom,smem-state-cells = <1>;
352 hexagon_smp2p_in: slave-kernel {
353 qcom,entry-name = "slave-kernel";
355 interrupt-controller;
356 #interrupt-cells = <2>;
361 compatible = "qcom,smp2p";
362 qcom,smem = <451>, <431>;
364 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
366 qcom,ipc = <&apcs 8 18>;
368 qcom,local-pid = <0>;
369 qcom,remote-pid = <4>;
371 wcnss_smp2p_out: master-kernel {
372 qcom,entry-name = "master-kernel";
374 #qcom,smem-state-cells = <1>;
377 wcnss_smp2p_in: slave-kernel {
378 qcom,entry-name = "slave-kernel";
380 interrupt-controller;
381 #interrupt-cells = <2>;
386 compatible = "qcom,smsm";
388 #address-cells = <1>;
391 qcom,ipc-1 = <&apcs 8 13>;
392 qcom,ipc-3 = <&apcs 8 19>;
397 #qcom,smem-state-cells = <1>;
400 hexagon_smsm: hexagon@1 {
402 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
408 wcnss_smsm: wcnss@6 {
410 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
418 #address-cells = <1>;
420 ranges = <0 0 0 0xffffffff>;
421 compatible = "simple-bus";
424 compatible = "qcom,prng";
425 reg = <0x00022000 0x200>;
426 clocks = <&gcc GCC_PRNG_AHB_CLK>;
427 clock-names = "core";
431 compatible = "qcom,pshold";
432 reg = <0x004ab000 0x4>;
435 qfprom: qfprom@5c000 {
436 compatible = "qcom,qfprom";
437 reg = <0x0005c000 0x1000>;
438 #address-cells = <1>;
440 tsens_caldata: caldata@d0 {
443 tsens_calsel: calsel@ec {
448 rpm_msg_ram: memory@60000 {
449 compatible = "qcom,rpm-msg-ram";
450 reg = <0x00060000 0x8000>;
453 bimc: interconnect@400000 {
454 compatible = "qcom,msm8916-bimc";
455 reg = <0x00400000 0x62000>;
456 #interconnect-cells = <1>;
457 clock-names = "bus", "bus_a";
458 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
459 <&rpmcc RPM_SMD_BIMC_A_CLK>;
462 tsens: thermal-sensor@4a9000 {
463 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
464 reg = <0x004a9000 0x1000>, /* TM */
465 <0x004a8000 0x1000>; /* SROT */
466 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
467 nvmem-cell-names = "calib", "calib_sel";
469 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-names = "uplow";
471 #thermal-sensor-cells = <1>;
474 pcnoc: interconnect@500000 {
475 compatible = "qcom,msm8916-pcnoc";
476 reg = <0x00500000 0x11000>;
477 #interconnect-cells = <1>;
478 clock-names = "bus", "bus_a";
479 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
480 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
483 snoc: interconnect@580000 {
484 compatible = "qcom,msm8916-snoc";
485 reg = <0x00580000 0x14000>;
486 #interconnect-cells = <1>;
487 clock-names = "bus", "bus_a";
488 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
489 <&rpmcc RPM_SMD_SNOC_A_CLK>;
493 /* CTI 0 - TMC connections */
495 compatible = "arm,coresight-cti", "arm,primecell";
496 reg = <0x00810000 0x1000>;
498 clocks = <&rpmcc RPM_QDSS_CLK>;
499 clock-names = "apb_pclk";
504 /* CTI 1 - TPIU connections */
506 compatible = "arm,coresight-cti", "arm,primecell";
507 reg = <0x00811000 0x1000>;
509 clocks = <&rpmcc RPM_QDSS_CLK>;
510 clock-names = "apb_pclk";
515 /* CTIs 2-11 - no information - not instantiated */
518 compatible = "arm,coresight-tpiu", "arm,primecell";
519 reg = <0x00820000 0x1000>;
521 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
522 clock-names = "apb_pclk", "atclk";
529 remote-endpoint = <&replicator_out1>;
535 funnel0: funnel@821000 {
536 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
537 reg = <0x00821000 0x1000>;
539 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
540 clock-names = "apb_pclk", "atclk";
545 #address-cells = <1>;
549 * Not described input ports:
550 * 0 - connected to Resource and Power Manger CPU ETM
552 * 2 - connected to Modem CPU ETM
555 * 6 - connected trought funnel to Wireless CPU ETM
556 * 7 - connected to STM component
561 funnel0_in4: endpoint {
562 remote-endpoint = <&funnel1_out>;
569 funnel0_out: endpoint {
570 remote-endpoint = <&etf_in>;
576 replicator: replicator@824000 {
577 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
578 reg = <0x00824000 0x1000>;
580 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
581 clock-names = "apb_pclk", "atclk";
586 #address-cells = <1>;
591 replicator_out0: endpoint {
592 remote-endpoint = <&etr_in>;
597 replicator_out1: endpoint {
598 remote-endpoint = <&tpiu_in>;
605 replicator_in: endpoint {
606 remote-endpoint = <&etf_out>;
613 compatible = "arm,coresight-tmc", "arm,primecell";
614 reg = <0x00825000 0x1000>;
616 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
617 clock-names = "apb_pclk", "atclk";
624 remote-endpoint = <&funnel0_out>;
632 remote-endpoint = <&replicator_in>;
639 compatible = "arm,coresight-tmc", "arm,primecell";
640 reg = <0x00826000 0x1000>;
642 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
643 clock-names = "apb_pclk", "atclk";
650 remote-endpoint = <&replicator_out0>;
656 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
657 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
658 reg = <0x00841000 0x1000>;
660 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
661 clock-names = "apb_pclk", "atclk";
666 #address-cells = <1>;
671 funnel1_in0: endpoint {
672 remote-endpoint = <&etm0_out>;
677 funnel1_in1: endpoint {
678 remote-endpoint = <&etm1_out>;
683 funnel1_in2: endpoint {
684 remote-endpoint = <&etm2_out>;
689 funnel1_in3: endpoint {
690 remote-endpoint = <&etm3_out>;
697 funnel1_out: endpoint {
698 remote-endpoint = <&funnel0_in4>;
704 debug0: debug@850000 {
705 compatible = "arm,coresight-cpu-debug", "arm,primecell";
706 reg = <0x00850000 0x1000>;
707 clocks = <&rpmcc RPM_QDSS_CLK>;
708 clock-names = "apb_pclk";
713 debug1: debug@852000 {
714 compatible = "arm,coresight-cpu-debug", "arm,primecell";
715 reg = <0x00852000 0x1000>;
716 clocks = <&rpmcc RPM_QDSS_CLK>;
717 clock-names = "apb_pclk";
722 debug2: debug@854000 {
723 compatible = "arm,coresight-cpu-debug", "arm,primecell";
724 reg = <0x00854000 0x1000>;
725 clocks = <&rpmcc RPM_QDSS_CLK>;
726 clock-names = "apb_pclk";
731 debug3: debug@856000 {
732 compatible = "arm,coresight-cpu-debug", "arm,primecell";
733 reg = <0x00856000 0x1000>;
734 clocks = <&rpmcc RPM_QDSS_CLK>;
735 clock-names = "apb_pclk";
740 /* Core CTIs; CTIs 12-15 */
743 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
745 reg = <0x00858000 0x1000>;
747 clocks = <&rpmcc RPM_QDSS_CLK>;
748 clock-names = "apb_pclk";
751 arm,cs-dev-assoc = <&etm0>;
758 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
760 reg = <0x00859000 0x1000>;
762 clocks = <&rpmcc RPM_QDSS_CLK>;
763 clock-names = "apb_pclk";
766 arm,cs-dev-assoc = <&etm1>;
773 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
775 reg = <0x0085a000 0x1000>;
777 clocks = <&rpmcc RPM_QDSS_CLK>;
778 clock-names = "apb_pclk";
781 arm,cs-dev-assoc = <&etm2>;
788 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
790 reg = <0x0085b000 0x1000>;
792 clocks = <&rpmcc RPM_QDSS_CLK>;
793 clock-names = "apb_pclk";
796 arm,cs-dev-assoc = <&etm3>;
802 compatible = "arm,coresight-etm4x", "arm,primecell";
803 reg = <0x0085c000 0x1000>;
805 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
806 clock-names = "apb_pclk", "atclk";
807 arm,coresight-loses-context-with-cpu;
816 remote-endpoint = <&funnel1_in0>;
823 compatible = "arm,coresight-etm4x", "arm,primecell";
824 reg = <0x0085d000 0x1000>;
826 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
827 clock-names = "apb_pclk", "atclk";
828 arm,coresight-loses-context-with-cpu;
837 remote-endpoint = <&funnel1_in1>;
844 compatible = "arm,coresight-etm4x", "arm,primecell";
845 reg = <0x0085e000 0x1000>;
847 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
848 clock-names = "apb_pclk", "atclk";
849 arm,coresight-loses-context-with-cpu;
858 remote-endpoint = <&funnel1_in2>;
865 compatible = "arm,coresight-etm4x", "arm,primecell";
866 reg = <0x0085f000 0x1000>;
868 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
869 clock-names = "apb_pclk", "atclk";
870 arm,coresight-loses-context-with-cpu;
879 remote-endpoint = <&funnel1_in3>;
885 msmgpio: pinctrl@1000000 {
886 compatible = "qcom,msm8916-pinctrl";
887 reg = <0x01000000 0x300000>;
888 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
890 gpio-ranges = <&msmgpio 0 0 122>;
892 interrupt-controller;
893 #interrupt-cells = <2>;
896 gcc: clock-controller@1800000 {
897 compatible = "qcom,gcc-msm8916";
900 #power-domain-cells = <1>;
901 reg = <0x01800000 0x80000>;
904 tcsr_mutex: hwlock@1905000 {
905 compatible = "qcom,tcsr-mutex";
906 reg = <0x01905000 0x20000>;
910 tcsr: syscon@1937000 {
911 compatible = "qcom,tcsr-msm8916", "syscon";
912 reg = <0x01937000 0x30000>;
917 compatible = "qcom,mdss";
918 reg = <0x01a00000 0x1000>,
920 reg-names = "mdss_phys", "vbif_phys";
922 power-domains = <&gcc MDSS_GDSC>;
924 clocks = <&gcc GCC_MDSS_AHB_CLK>,
925 <&gcc GCC_MDSS_AXI_CLK>,
926 <&gcc GCC_MDSS_VSYNC_CLK>;
927 clock-names = "iface",
931 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
933 interrupt-controller;
934 #interrupt-cells = <1>;
936 #address-cells = <1>;
941 compatible = "qcom,mdp5";
942 reg = <0x01a01000 0x89000>;
943 reg-names = "mdp_phys";
945 interrupt-parent = <&mdss>;
948 clocks = <&gcc GCC_MDSS_AHB_CLK>,
949 <&gcc GCC_MDSS_AXI_CLK>,
950 <&gcc GCC_MDSS_MDP_CLK>,
951 <&gcc GCC_MDSS_VSYNC_CLK>;
952 clock-names = "iface",
957 iommus = <&apps_iommu 4>;
960 #address-cells = <1>;
965 mdp5_intf1_out: endpoint {
966 remote-endpoint = <&dsi0_in>;
973 compatible = "qcom,mdss-dsi-ctrl";
974 reg = <0x01a98000 0x25c>;
975 reg-names = "dsi_ctrl";
977 interrupt-parent = <&mdss>;
980 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
981 <&gcc PCLK0_CLK_SRC>;
982 assigned-clock-parents = <&dsi_phy0 0>,
985 clocks = <&gcc GCC_MDSS_MDP_CLK>,
986 <&gcc GCC_MDSS_AHB_CLK>,
987 <&gcc GCC_MDSS_AXI_CLK>,
988 <&gcc GCC_MDSS_BYTE0_CLK>,
989 <&gcc GCC_MDSS_PCLK0_CLK>,
990 <&gcc GCC_MDSS_ESC0_CLK>;
991 clock-names = "mdp_core",
998 phy-names = "dsi-phy";
1000 #address-cells = <1>;
1004 #address-cells = <1>;
1010 remote-endpoint = <&mdp5_intf1_out>;
1016 dsi0_out: endpoint {
1022 dsi_phy0: dsi-phy@1a98300 {
1023 compatible = "qcom,dsi-phy-28nm-lp";
1024 reg = <0x01a98300 0xd4>,
1027 reg-names = "dsi_pll",
1029 "dsi_phy_regulator";
1034 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1036 clock-names = "iface", "ref";
1040 camss: camss@1b00000 {
1041 compatible = "qcom,msm8916-camss";
1042 reg = <0x01b0ac00 0x200>,
1050 <0x01b10000 0x1000>;
1051 reg-names = "csiphy0",
1060 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1061 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1062 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1063 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1064 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1065 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1066 interrupt-names = "csiphy0",
1072 power-domains = <&gcc VFE_GDSC>;
1073 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1074 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1075 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1076 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1077 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1078 <&gcc GCC_CAMSS_CSI0_CLK>,
1079 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1080 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1081 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1082 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1083 <&gcc GCC_CAMSS_CSI1_CLK>,
1084 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1085 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1086 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1087 <&gcc GCC_CAMSS_AHB_CLK>,
1088 <&gcc GCC_CAMSS_VFE0_CLK>,
1089 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1090 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1091 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1092 clock-names = "top_ahb",
1111 iommus = <&apps_iommu 3>;
1112 status = "disabled";
1114 #address-cells = <1>;
1120 compatible = "qcom,msm8916-cci";
1121 #address-cells = <1>;
1123 reg = <0x01b0c000 0x1000>;
1124 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1125 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1126 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1127 <&gcc GCC_CAMSS_CCI_CLK>,
1128 <&gcc GCC_CAMSS_AHB_CLK>;
1129 clock-names = "camss_top_ahb", "cci_ahb",
1131 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1132 <&gcc GCC_CAMSS_CCI_CLK>;
1133 assigned-clock-rates = <80000000>, <19200000>;
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&cci0_default>;
1136 status = "disabled";
1138 cci_i2c0: i2c-bus@0 {
1140 clock-frequency = <400000>;
1141 #address-cells = <1>;
1147 compatible = "qcom,adreno-306.0", "qcom,adreno";
1148 reg = <0x01c00000 0x20000>;
1149 reg-names = "kgsl_3d0_reg_memory";
1150 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1151 interrupt-names = "kgsl_3d0_irq";
1160 <&gcc GCC_OXILI_GFX3D_CLK>,
1161 <&gcc GCC_OXILI_AHB_CLK>,
1162 <&gcc GCC_OXILI_GMEM_CLK>,
1163 <&gcc GCC_BIMC_GFX_CLK>,
1164 <&gcc GCC_BIMC_GPU_CLK>,
1165 <&gcc GFX3D_CLK_SRC>;
1166 power-domains = <&gcc OXILI_GDSC>;
1167 operating-points-v2 = <&gpu_opp_table>;
1168 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1170 gpu_opp_table: opp-table {
1171 compatible = "operating-points-v2";
1174 opp-hz = /bits/ 64 <400000000>;
1177 opp-hz = /bits/ 64 <19200000>;
1182 venus: video-codec@1d00000 {
1183 compatible = "qcom,msm8916-venus";
1184 reg = <0x01d00000 0xff000>;
1185 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1186 power-domains = <&gcc VENUS_GDSC>;
1187 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1188 <&gcc GCC_VENUS0_AHB_CLK>,
1189 <&gcc GCC_VENUS0_AXI_CLK>;
1190 clock-names = "core", "iface", "bus";
1191 iommus = <&apps_iommu 5>;
1192 memory-region = <&venus_mem>;
1196 compatible = "venus-decoder";
1200 compatible = "venus-encoder";
1204 apps_iommu: iommu@1ef0000 {
1205 #address-cells = <1>;
1208 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1209 ranges = <0 0x01e20000 0x40000>;
1210 reg = <0x01ef0000 0x3000>;
1211 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1212 <&gcc GCC_APSS_TCU_CLK>;
1213 clock-names = "iface", "bus";
1214 qcom,iommu-secure-id = <17>;
1218 compatible = "qcom,msm-iommu-v1-sec";
1219 reg = <0x3000 0x1000>;
1220 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1225 compatible = "qcom,msm-iommu-v1-ns";
1226 reg = <0x4000 0x1000>;
1227 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1232 compatible = "qcom,msm-iommu-v1-sec";
1233 reg = <0x5000 0x1000>;
1234 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1238 gpu_iommu: iommu@1f08000 {
1239 #address-cells = <1>;
1242 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1243 ranges = <0 0x01f08000 0x10000>;
1244 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1245 <&gcc GCC_GFX_TCU_CLK>;
1246 clock-names = "iface", "bus";
1247 qcom,iommu-secure-id = <18>;
1251 compatible = "qcom,msm-iommu-v1-ns";
1252 reg = <0x1000 0x1000>;
1253 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1258 compatible = "qcom,msm-iommu-v1-ns";
1259 reg = <0x2000 0x1000>;
1260 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1264 spmi_bus: spmi@200f000 {
1265 compatible = "qcom,spmi-pmic-arb";
1266 reg = <0x0200f000 0x001000>,
1267 <0x02400000 0x400000>,
1268 <0x02c00000 0x400000>,
1269 <0x03800000 0x200000>,
1270 <0x0200a000 0x002100>;
1271 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1272 interrupt-names = "periph_irq";
1273 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1276 #address-cells = <2>;
1278 interrupt-controller;
1279 #interrupt-cells = <4>;
1282 mpss: remoteproc@4080000 {
1283 compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1284 reg = <0x04080000 0x100>,
1287 reg-names = "qdsp6", "rmb";
1289 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1290 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1291 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1292 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1293 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1294 interrupt-names = "wdog", "fatal", "ready",
1295 "handover", "stop-ack";
1297 power-domains = <&rpmpd MSM8916_VDDCX>,
1298 <&rpmpd MSM8916_VDDMX>;
1299 power-domain-names = "cx", "mx";
1301 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1302 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1303 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1305 clock-names = "iface", "bus", "mem", "xo";
1307 qcom,smem-states = <&hexagon_smp2p_out 0>;
1308 qcom,smem-state-names = "stop";
1311 reset-names = "mss_restart";
1313 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1315 status = "disabled";
1318 memory-region = <&mba_mem>;
1322 memory-region = <&mpss_mem>;
1326 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1328 qcom,smd-edge = <0>;
1329 qcom,ipc = <&apcs 8 12>;
1330 qcom,remote-pid = <1>;
1335 compatible = "qcom,fastrpc";
1336 qcom,smd-channels = "fastrpcsmd-apps-dsp";
1339 #address-cells = <1>;
1343 compatible = "qcom,fastrpc-compute-cb";
1350 sound: sound@7702000 {
1351 status = "disabled";
1352 compatible = "qcom,apq8016-sbc-sndcard";
1353 reg = <0x07702000 0x4>, <0x07702004 0x4>;
1354 reg-names = "mic-iomux", "spkr-iomux";
1357 lpass: audio-controller@7708000 {
1358 status = "disabled";
1359 compatible = "qcom,lpass-cpu-apq8016";
1360 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1361 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1362 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1363 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1364 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1365 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1366 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1368 clock-names = "ahbix-clk",
1375 #sound-dai-cells = <1>;
1377 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1378 interrupt-names = "lpass-irq-lpaif";
1379 reg = <0x07708000 0x10000>;
1380 reg-names = "lpass-lpaif";
1382 #address-cells = <1>;
1386 lpass_codec: audio-codec@771c000 {
1387 compatible = "qcom,msm8916-wcd-digital-codec";
1388 reg = <0x0771c000 0x400>;
1389 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1390 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1391 clock-names = "ahbix-clk", "mclk";
1392 #sound-dai-cells = <1>;
1395 sdhc_1: sdhci@7824000 {
1396 compatible = "qcom,sdhci-msm-v4";
1397 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1398 reg-names = "hc_mem", "core_mem";
1400 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1402 interrupt-names = "hc_irq", "pwr_irq";
1403 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1404 <&gcc GCC_SDCC1_AHB_CLK>,
1406 clock-names = "core", "iface", "xo";
1410 status = "disabled";
1413 sdhc_2: sdhci@7864000 {
1414 compatible = "qcom,sdhci-msm-v4";
1415 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1416 reg-names = "hc_mem", "core_mem";
1418 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1420 interrupt-names = "hc_irq", "pwr_irq";
1421 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1422 <&gcc GCC_SDCC2_AHB_CLK>,
1424 clock-names = "core", "iface", "xo";
1426 status = "disabled";
1429 blsp_dma: dma-controller@7884000 {
1430 compatible = "qcom,bam-v1.7.0";
1431 reg = <0x07884000 0x23000>;
1432 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1434 clock-names = "bam_clk";
1437 status = "disabled";
1440 blsp1_uart1: serial@78af000 {
1441 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1442 reg = <0x078af000 0x200>;
1443 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1445 clock-names = "core", "iface";
1446 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
1447 dma-names = "rx", "tx";
1448 pinctrl-names = "default", "sleep";
1449 pinctrl-0 = <&blsp1_uart1_default>;
1450 pinctrl-1 = <&blsp1_uart1_sleep>;
1451 status = "disabled";
1454 blsp1_uart2: serial@78b0000 {
1455 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1456 reg = <0x078b0000 0x200>;
1457 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1459 clock-names = "core", "iface";
1460 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
1461 dma-names = "rx", "tx";
1462 pinctrl-names = "default", "sleep";
1463 pinctrl-0 = <&blsp1_uart2_default>;
1464 pinctrl-1 = <&blsp1_uart2_sleep>;
1465 status = "disabled";
1468 blsp_i2c1: i2c@78b5000 {
1469 compatible = "qcom,i2c-qup-v2.2.1";
1470 reg = <0x078b5000 0x500>;
1471 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1473 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
1474 clock-names = "iface", "core";
1475 pinctrl-names = "default", "sleep";
1476 pinctrl-0 = <&i2c1_default>;
1477 pinctrl-1 = <&i2c1_sleep>;
1478 #address-cells = <1>;
1480 status = "disabled";
1483 blsp_spi1: spi@78b5000 {
1484 compatible = "qcom,spi-qup-v2.2.1";
1485 reg = <0x078b5000 0x500>;
1486 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1487 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1488 <&gcc GCC_BLSP1_AHB_CLK>;
1489 clock-names = "core", "iface";
1490 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
1491 dma-names = "rx", "tx";
1492 pinctrl-names = "default", "sleep";
1493 pinctrl-0 = <&spi1_default>;
1494 pinctrl-1 = <&spi1_sleep>;
1495 #address-cells = <1>;
1497 status = "disabled";
1500 blsp_i2c2: i2c@78b6000 {
1501 compatible = "qcom,i2c-qup-v2.2.1";
1502 reg = <0x078b6000 0x500>;
1503 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1504 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1505 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
1506 clock-names = "iface", "core";
1507 pinctrl-names = "default", "sleep";
1508 pinctrl-0 = <&i2c2_default>;
1509 pinctrl-1 = <&i2c2_sleep>;
1510 #address-cells = <1>;
1512 status = "disabled";
1515 blsp_spi2: spi@78b6000 {
1516 compatible = "qcom,spi-qup-v2.2.1";
1517 reg = <0x078b6000 0x500>;
1518 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1519 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1520 <&gcc GCC_BLSP1_AHB_CLK>;
1521 clock-names = "core", "iface";
1522 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
1523 dma-names = "rx", "tx";
1524 pinctrl-names = "default", "sleep";
1525 pinctrl-0 = <&spi2_default>;
1526 pinctrl-1 = <&spi2_sleep>;
1527 #address-cells = <1>;
1529 status = "disabled";
1532 blsp_i2c3: i2c@78b7000 {
1533 compatible = "qcom,i2c-qup-v2.2.1";
1534 reg = <0x078b7000 0x500>;
1535 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1536 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1537 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1538 clock-names = "iface", "core";
1539 pinctrl-names = "default", "sleep";
1540 pinctrl-0 = <&i2c3_default>;
1541 pinctrl-1 = <&i2c3_sleep>;
1542 #address-cells = <1>;
1544 status = "disabled";
1547 blsp_spi3: spi@78b7000 {
1548 compatible = "qcom,spi-qup-v2.2.1";
1549 reg = <0x078b7000 0x500>;
1550 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1552 <&gcc GCC_BLSP1_AHB_CLK>;
1553 clock-names = "core", "iface";
1554 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
1555 dma-names = "rx", "tx";
1556 pinctrl-names = "default", "sleep";
1557 pinctrl-0 = <&spi3_default>;
1558 pinctrl-1 = <&spi3_sleep>;
1559 #address-cells = <1>;
1561 status = "disabled";
1564 blsp_i2c4: i2c@78b8000 {
1565 compatible = "qcom,i2c-qup-v2.2.1";
1566 reg = <0x078b8000 0x500>;
1567 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1568 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1569 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1570 clock-names = "iface", "core";
1571 pinctrl-names = "default", "sleep";
1572 pinctrl-0 = <&i2c4_default>;
1573 pinctrl-1 = <&i2c4_sleep>;
1574 #address-cells = <1>;
1576 status = "disabled";
1579 blsp_spi4: spi@78b8000 {
1580 compatible = "qcom,spi-qup-v2.2.1";
1581 reg = <0x078b8000 0x500>;
1582 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1583 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1584 <&gcc GCC_BLSP1_AHB_CLK>;
1585 clock-names = "core", "iface";
1586 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
1587 dma-names = "rx", "tx";
1588 pinctrl-names = "default", "sleep";
1589 pinctrl-0 = <&spi4_default>;
1590 pinctrl-1 = <&spi4_sleep>;
1591 #address-cells = <1>;
1593 status = "disabled";
1596 blsp_i2c5: i2c@78b9000 {
1597 compatible = "qcom,i2c-qup-v2.2.1";
1598 reg = <0x078b9000 0x500>;
1599 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1600 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1601 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
1602 clock-names = "iface", "core";
1603 pinctrl-names = "default", "sleep";
1604 pinctrl-0 = <&i2c5_default>;
1605 pinctrl-1 = <&i2c5_sleep>;
1606 #address-cells = <1>;
1608 status = "disabled";
1611 blsp_spi5: spi@78b9000 {
1612 compatible = "qcom,spi-qup-v2.2.1";
1613 reg = <0x078b9000 0x500>;
1614 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1616 <&gcc GCC_BLSP1_AHB_CLK>;
1617 clock-names = "core", "iface";
1618 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
1619 dma-names = "rx", "tx";
1620 pinctrl-names = "default", "sleep";
1621 pinctrl-0 = <&spi5_default>;
1622 pinctrl-1 = <&spi5_sleep>;
1623 #address-cells = <1>;
1625 status = "disabled";
1628 blsp_i2c6: i2c@78ba000 {
1629 compatible = "qcom,i2c-qup-v2.2.1";
1630 reg = <0x078ba000 0x500>;
1631 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1632 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1633 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
1634 clock-names = "iface", "core";
1635 pinctrl-names = "default", "sleep";
1636 pinctrl-0 = <&i2c6_default>;
1637 pinctrl-1 = <&i2c6_sleep>;
1638 #address-cells = <1>;
1640 status = "disabled";
1643 blsp_spi6: spi@78ba000 {
1644 compatible = "qcom,spi-qup-v2.2.1";
1645 reg = <0x078ba000 0x500>;
1646 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1647 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1648 <&gcc GCC_BLSP1_AHB_CLK>;
1649 clock-names = "core", "iface";
1650 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
1651 dma-names = "rx", "tx";
1652 pinctrl-names = "default", "sleep";
1653 pinctrl-0 = <&spi6_default>;
1654 pinctrl-1 = <&spi6_sleep>;
1655 #address-cells = <1>;
1657 status = "disabled";
1661 compatible = "qcom,ci-hdrc";
1662 reg = <0x078d9000 0x200>,
1664 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1665 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1666 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1667 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1668 clock-names = "iface", "core";
1669 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1670 assigned-clock-rates = <80000000>;
1671 resets = <&gcc GCC_USB_HS_BCR>;
1672 reset-names = "core";
1678 ahb-burst-config = <0>;
1679 phy-names = "usb-phy";
1680 phys = <&usb_hs_phy>;
1681 status = "disabled";
1686 compatible = "qcom,usb-hs-phy-msm8916",
1689 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1690 clock-names = "ref", "sleep";
1691 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1692 reset-names = "phy", "por";
1693 qcom,init-seq = /bits/ 8 <0x0 0x44
1694 0x1 0x6b 0x2 0x24 0x3 0x13>;
1699 pronto: remoteproc@a21b000 {
1700 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1701 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1702 reg-names = "ccu", "dxe", "pmu";
1704 memory-region = <&wcnss_mem>;
1706 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1707 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1708 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1709 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1710 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1711 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1713 power-domains = <&rpmpd MSM8916_VDDCX>,
1714 <&rpmpd MSM8916_VDDMX>;
1715 power-domain-names = "cx", "mx";
1717 qcom,state = <&wcnss_smp2p_out 0>;
1718 qcom,state-names = "stop";
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&wcnss_pin_a>;
1723 status = "disabled";
1726 compatible = "qcom,wcn3620";
1728 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1733 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1735 qcom,ipc = <&apcs 8 17>;
1736 qcom,smd-edge = <6>;
1737 qcom,remote-pid = <4>;
1742 compatible = "qcom,wcnss";
1743 qcom,smd-channels = "WCNSS_CTRL";
1745 qcom,mmio = <&pronto>;
1748 compatible = "qcom,wcnss-bt";
1752 compatible = "qcom,wcnss-wlan";
1754 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1756 interrupt-names = "tx", "rx";
1758 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1759 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1765 intc: interrupt-controller@b000000 {
1766 compatible = "qcom,msm-qgic2";
1767 interrupt-controller;
1768 #interrupt-cells = <3>;
1769 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1772 apcs: mailbox@b011000 {
1773 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1774 reg = <0x0b011000 0x1000>;
1776 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1777 clock-names = "pll", "aux";
1781 a53pll: clock@b016000 {
1782 compatible = "qcom,msm8916-a53pll";
1783 reg = <0x0b016000 0x40>;
1788 #address-cells = <1>;
1791 compatible = "arm,armv7-timer-mem";
1792 reg = <0x0b020000 0x1000>;
1793 clock-frequency = <19200000>;
1797 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1799 reg = <0x0b021000 0x1000>,
1800 <0x0b022000 0x1000>;
1805 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1806 reg = <0x0b023000 0x1000>;
1807 status = "disabled";
1812 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1813 reg = <0x0b024000 0x1000>;
1814 status = "disabled";
1819 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1820 reg = <0x0b025000 0x1000>;
1821 status = "disabled";
1826 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1827 reg = <0x0b026000 0x1000>;
1828 status = "disabled";
1833 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1834 reg = <0x0b027000 0x1000>;
1835 status = "disabled";
1840 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1841 reg = <0x0b028000 0x1000>;
1842 status = "disabled";
1849 polling-delay-passive = <250>;
1850 polling-delay = <1000>;
1852 thermal-sensors = <&tsens 5>;
1855 cpu0_1_alert0: trip-point0 {
1856 temperature = <75000>;
1857 hysteresis = <2000>;
1860 cpu0_1_crit: cpu_crit {
1861 temperature = <110000>;
1862 hysteresis = <2000>;
1869 trip = <&cpu0_1_alert0>;
1870 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1871 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1872 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1873 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1879 polling-delay-passive = <250>;
1880 polling-delay = <1000>;
1882 thermal-sensors = <&tsens 4>;
1885 cpu2_3_alert0: trip-point0 {
1886 temperature = <75000>;
1887 hysteresis = <2000>;
1890 cpu2_3_crit: cpu_crit {
1891 temperature = <110000>;
1892 hysteresis = <2000>;
1899 trip = <&cpu2_3_alert0>;
1900 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1901 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1902 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1909 polling-delay-passive = <250>;
1910 polling-delay = <1000>;
1912 thermal-sensors = <&tsens 2>;
1915 gpu_alert0: trip-point0 {
1916 temperature = <75000>;
1917 hysteresis = <2000>;
1920 gpu_crit: gpu_crit {
1921 temperature = <95000>;
1922 hysteresis = <2000>;
1929 polling-delay-passive = <250>;
1930 polling-delay = <1000>;
1932 thermal-sensors = <&tsens 1>;
1935 cam_alert0: trip-point0 {
1936 temperature = <75000>;
1937 hysteresis = <2000>;
1944 polling-delay-passive = <250>;
1945 polling-delay = <1000>;
1947 thermal-sensors = <&tsens 0>;
1950 modem_alert0: trip-point0 {
1951 temperature = <85000>;
1952 hysteresis = <2000>;
1961 compatible = "arm,armv8-timer";
1962 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1963 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1964 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1965 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1969 #include "msm8916-pins.dtsi"