1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
22 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
23 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
29 device_type = "memory";
30 /* We expect the bootloader to fill in the reg */
31 reg = <0 0x80000000 0 0>;
40 reg = <0x0 0x86000000 0x0 0x300000>;
44 smem_mem: smem_region@86300000 {
45 reg = <0x0 0x86300000 0x0 0x100000>;
50 reg = <0x0 0x86400000 0x0 0x100000>;
55 reg = <0x0 0x86500000 0x0 0x180000>;
60 reg = <0x0 0x86680000 0x0 0x80000>;
65 compatible = "qcom,rmtfs-mem";
66 reg = <0x0 0x86700000 0x0 0xe0000>;
73 reg = <0x0 0x867e0000 0x0 0x20000>;
77 mpss_mem: mpss@86800000 {
78 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 wcnss_mem: wcnss@89300000 {
83 reg = <0x0 0x89300000 0x0 0x600000>;
87 venus_mem: venus@89900000 {
88 reg = <0x0 0x89900000 0x0 0x600000>;
92 mba_mem: mba@8ea00000 {
94 reg = <0 0x8ea00000 0 0x100000>;
100 compatible = "fixed-clock";
102 clock-frequency = <19200000>;
105 sleep_clk: sleep-clk {
106 compatible = "fixed-clock";
108 clock-frequency = <32768>;
113 #address-cells = <1>;
118 compatible = "arm,cortex-a53";
120 next-level-cache = <&L2_0>;
121 enable-method = "psci";
123 operating-points-v2 = <&cpu_opp_table>;
124 #cooling-cells = <2>;
125 power-domains = <&CPU_PD0>;
126 power-domain-names = "psci";
131 compatible = "arm,cortex-a53";
133 next-level-cache = <&L2_0>;
134 enable-method = "psci";
136 operating-points-v2 = <&cpu_opp_table>;
137 #cooling-cells = <2>;
138 power-domains = <&CPU_PD1>;
139 power-domain-names = "psci";
144 compatible = "arm,cortex-a53";
146 next-level-cache = <&L2_0>;
147 enable-method = "psci";
149 operating-points-v2 = <&cpu_opp_table>;
150 #cooling-cells = <2>;
151 power-domains = <&CPU_PD2>;
152 power-domain-names = "psci";
157 compatible = "arm,cortex-a53";
159 next-level-cache = <&L2_0>;
160 enable-method = "psci";
162 operating-points-v2 = <&cpu_opp_table>;
163 #cooling-cells = <2>;
164 power-domains = <&CPU_PD3>;
165 power-domain-names = "psci";
169 compatible = "cache";
174 entry-method = "psci";
176 CPU_SLEEP_0: cpu-sleep-0 {
177 compatible = "arm,idle-state";
178 idle-state-name = "standalone-power-collapse";
179 arm,psci-suspend-param = <0x40000002>;
180 entry-latency-us = <130>;
181 exit-latency-us = <150>;
182 min-residency-us = <2000>;
189 CLUSTER_RET: cluster-retention {
190 compatible = "domain-idle-state";
191 arm,psci-suspend-param = <0x41000012>;
192 entry-latency-us = <500>;
193 exit-latency-us = <500>;
194 min-residency-us = <2000>;
197 CLUSTER_PWRDN: cluster-gdhs {
198 compatible = "domain-idle-state";
199 arm,psci-suspend-param = <0x41000032>;
200 entry-latency-us = <2000>;
201 exit-latency-us = <2000>;
202 min-residency-us = <6000>;
207 cpu_opp_table: cpu-opp-table {
208 compatible = "operating-points-v2";
212 opp-hz = /bits/ 64 <200000000>;
215 opp-hz = /bits/ 64 <400000000>;
218 opp-hz = /bits/ 64 <800000000>;
221 opp-hz = /bits/ 64 <998400000>;
227 compatible = "qcom,scm-msm8916", "qcom,scm";
228 clocks = <&gcc GCC_CRYPTO_CLK>,
229 <&gcc GCC_CRYPTO_AXI_CLK>,
230 <&gcc GCC_CRYPTO_AHB_CLK>;
231 clock-names = "core", "bus", "iface";
234 qcom,dload-mode = <&tcsr 0x6100>;
239 compatible = "arm,cortex-a53-pmu";
240 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
244 compatible = "arm,psci-1.0";
247 CPU_PD0: power-domain-cpu0 {
248 #power-domain-cells = <0>;
249 power-domains = <&CLUSTER_PD>;
250 domain-idle-states = <&CPU_SLEEP_0>;
253 CPU_PD1: power-domain-cpu1 {
254 #power-domain-cells = <0>;
255 power-domains = <&CLUSTER_PD>;
256 domain-idle-states = <&CPU_SLEEP_0>;
259 CPU_PD2: power-domain-cpu2 {
260 #power-domain-cells = <0>;
261 power-domains = <&CLUSTER_PD>;
262 domain-idle-states = <&CPU_SLEEP_0>;
265 CPU_PD3: power-domain-cpu3 {
266 #power-domain-cells = <0>;
267 power-domains = <&CLUSTER_PD>;
268 domain-idle-states = <&CPU_SLEEP_0>;
271 CLUSTER_PD: power-domain-cluster {
272 #power-domain-cells = <0>;
273 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
278 compatible = "qcom,smd";
281 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
282 qcom,ipc = <&apcs 8 0>;
283 qcom,smd-edge = <15>;
285 rpm_requests: rpm-requests {
286 compatible = "qcom,rpm-msm8916";
287 qcom,smd-channels = "rpm_requests";
289 rpmcc: clock-controller {
290 compatible = "qcom,rpmcc-msm8916";
294 rpmpd: power-controller {
295 compatible = "qcom,msm8916-rpmpd";
296 #power-domain-cells = <1>;
297 operating-points-v2 = <&rpmpd_opp_table>;
299 rpmpd_opp_table: opp-table {
300 compatible = "operating-points-v2";
302 rpmpd_opp_ret: opp1 {
305 rpmpd_opp_svs_krait: opp2 {
308 rpmpd_opp_svs_soc: opp3 {
311 rpmpd_opp_nom: opp4 {
314 rpmpd_opp_turbo: opp5 {
317 rpmpd_opp_super_turbo: opp6 {
327 compatible = "qcom,smem";
329 memory-region = <&smem_mem>;
330 qcom,rpm-msg-ram = <&rpm_msg_ram>;
332 hwlocks = <&tcsr_mutex 3>;
336 compatible = "qcom,smp2p";
337 qcom,smem = <435>, <428>;
339 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
341 qcom,ipc = <&apcs 8 14>;
343 qcom,local-pid = <0>;
344 qcom,remote-pid = <1>;
346 hexagon_smp2p_out: master-kernel {
347 qcom,entry-name = "master-kernel";
349 #qcom,smem-state-cells = <1>;
352 hexagon_smp2p_in: slave-kernel {
353 qcom,entry-name = "slave-kernel";
355 interrupt-controller;
356 #interrupt-cells = <2>;
361 compatible = "qcom,smp2p";
362 qcom,smem = <451>, <431>;
364 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
366 qcom,ipc = <&apcs 8 18>;
368 qcom,local-pid = <0>;
369 qcom,remote-pid = <4>;
371 wcnss_smp2p_out: master-kernel {
372 qcom,entry-name = "master-kernel";
374 #qcom,smem-state-cells = <1>;
377 wcnss_smp2p_in: slave-kernel {
378 qcom,entry-name = "slave-kernel";
380 interrupt-controller;
381 #interrupt-cells = <2>;
386 compatible = "qcom,smsm";
388 #address-cells = <1>;
391 qcom,ipc-1 = <&apcs 8 13>;
392 qcom,ipc-3 = <&apcs 8 19>;
397 #qcom,smem-state-cells = <1>;
400 hexagon_smsm: hexagon@1 {
402 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
408 wcnss_smsm: wcnss@6 {
410 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
418 #address-cells = <1>;
420 ranges = <0 0 0 0xffffffff>;
421 compatible = "simple-bus";
424 compatible = "qcom,prng";
425 reg = <0x00022000 0x200>;
426 clocks = <&gcc GCC_PRNG_AHB_CLK>;
427 clock-names = "core";
431 compatible = "qcom,pshold";
432 reg = <0x004ab000 0x4>;
435 qfprom: qfprom@5c000 {
436 compatible = "qcom,qfprom";
437 reg = <0x0005c000 0x1000>;
438 #address-cells = <1>;
440 tsens_caldata: caldata@d0 {
443 tsens_calsel: calsel@ec {
448 rpm_msg_ram: memory@60000 {
449 compatible = "qcom,rpm-msg-ram";
450 reg = <0x00060000 0x8000>;
453 bimc: interconnect@400000 {
454 compatible = "qcom,msm8916-bimc";
455 reg = <0x00400000 0x62000>;
456 #interconnect-cells = <1>;
457 clock-names = "bus", "bus_a";
458 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
459 <&rpmcc RPM_SMD_BIMC_A_CLK>;
462 tsens: thermal-sensor@4a9000 {
463 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
464 reg = <0x004a9000 0x1000>, /* TM */
465 <0x004a8000 0x1000>; /* SROT */
466 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
467 nvmem-cell-names = "calib", "calib_sel";
469 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-names = "uplow";
471 #thermal-sensor-cells = <1>;
474 pcnoc: interconnect@500000 {
475 compatible = "qcom,msm8916-pcnoc";
476 reg = <0x00500000 0x11000>;
477 #interconnect-cells = <1>;
478 clock-names = "bus", "bus_a";
479 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
480 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
483 snoc: interconnect@580000 {
484 compatible = "qcom,msm8916-snoc";
485 reg = <0x00580000 0x14000>;
486 #interconnect-cells = <1>;
487 clock-names = "bus", "bus_a";
488 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
489 <&rpmcc RPM_SMD_SNOC_A_CLK>;
493 compatible = "arm,coresight-stm", "arm,primecell";
494 reg = <0x00802000 0x1000>,
495 <0x09280000 0x180000>;
496 reg-names = "stm-base", "stm-stimulus-base";
498 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
499 clock-names = "apb_pclk", "atclk";
506 remote-endpoint = <&funnel0_in7>;
513 /* CTI 0 - TMC connections */
515 compatible = "arm,coresight-cti", "arm,primecell";
516 reg = <0x00810000 0x1000>;
518 clocks = <&rpmcc RPM_QDSS_CLK>;
519 clock-names = "apb_pclk";
524 /* CTI 1 - TPIU connections */
526 compatible = "arm,coresight-cti", "arm,primecell";
527 reg = <0x00811000 0x1000>;
529 clocks = <&rpmcc RPM_QDSS_CLK>;
530 clock-names = "apb_pclk";
535 /* CTIs 2-11 - no information - not instantiated */
538 compatible = "arm,coresight-tpiu", "arm,primecell";
539 reg = <0x00820000 0x1000>;
541 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
542 clock-names = "apb_pclk", "atclk";
549 remote-endpoint = <&replicator_out1>;
555 funnel0: funnel@821000 {
556 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
557 reg = <0x00821000 0x1000>;
559 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
560 clock-names = "apb_pclk", "atclk";
565 #address-cells = <1>;
569 * Not described input ports:
570 * 0 - connected to Resource and Power Manger CPU ETM
572 * 2 - connected to Modem CPU ETM
575 * 6 - connected trought funnel to Wireless CPU ETM
576 * 7 - connected to STM component
581 funnel0_in4: endpoint {
582 remote-endpoint = <&funnel1_out>;
588 funnel0_in7: endpoint {
589 remote-endpoint = <&stm_out>;
596 funnel0_out: endpoint {
597 remote-endpoint = <&etf_in>;
603 replicator: replicator@824000 {
604 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
605 reg = <0x00824000 0x1000>;
607 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
608 clock-names = "apb_pclk", "atclk";
613 #address-cells = <1>;
618 replicator_out0: endpoint {
619 remote-endpoint = <&etr_in>;
624 replicator_out1: endpoint {
625 remote-endpoint = <&tpiu_in>;
632 replicator_in: endpoint {
633 remote-endpoint = <&etf_out>;
640 compatible = "arm,coresight-tmc", "arm,primecell";
641 reg = <0x00825000 0x1000>;
643 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
644 clock-names = "apb_pclk", "atclk";
651 remote-endpoint = <&funnel0_out>;
659 remote-endpoint = <&replicator_in>;
666 compatible = "arm,coresight-tmc", "arm,primecell";
667 reg = <0x00826000 0x1000>;
669 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
670 clock-names = "apb_pclk", "atclk";
677 remote-endpoint = <&replicator_out0>;
683 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
684 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
685 reg = <0x00841000 0x1000>;
687 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
688 clock-names = "apb_pclk", "atclk";
693 #address-cells = <1>;
698 funnel1_in0: endpoint {
699 remote-endpoint = <&etm0_out>;
704 funnel1_in1: endpoint {
705 remote-endpoint = <&etm1_out>;
710 funnel1_in2: endpoint {
711 remote-endpoint = <&etm2_out>;
716 funnel1_in3: endpoint {
717 remote-endpoint = <&etm3_out>;
724 funnel1_out: endpoint {
725 remote-endpoint = <&funnel0_in4>;
731 debug0: debug@850000 {
732 compatible = "arm,coresight-cpu-debug", "arm,primecell";
733 reg = <0x00850000 0x1000>;
734 clocks = <&rpmcc RPM_QDSS_CLK>;
735 clock-names = "apb_pclk";
740 debug1: debug@852000 {
741 compatible = "arm,coresight-cpu-debug", "arm,primecell";
742 reg = <0x00852000 0x1000>;
743 clocks = <&rpmcc RPM_QDSS_CLK>;
744 clock-names = "apb_pclk";
749 debug2: debug@854000 {
750 compatible = "arm,coresight-cpu-debug", "arm,primecell";
751 reg = <0x00854000 0x1000>;
752 clocks = <&rpmcc RPM_QDSS_CLK>;
753 clock-names = "apb_pclk";
758 debug3: debug@856000 {
759 compatible = "arm,coresight-cpu-debug", "arm,primecell";
760 reg = <0x00856000 0x1000>;
761 clocks = <&rpmcc RPM_QDSS_CLK>;
762 clock-names = "apb_pclk";
767 /* Core CTIs; CTIs 12-15 */
770 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
772 reg = <0x00858000 0x1000>;
774 clocks = <&rpmcc RPM_QDSS_CLK>;
775 clock-names = "apb_pclk";
778 arm,cs-dev-assoc = <&etm0>;
785 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
787 reg = <0x00859000 0x1000>;
789 clocks = <&rpmcc RPM_QDSS_CLK>;
790 clock-names = "apb_pclk";
793 arm,cs-dev-assoc = <&etm1>;
800 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
802 reg = <0x0085a000 0x1000>;
804 clocks = <&rpmcc RPM_QDSS_CLK>;
805 clock-names = "apb_pclk";
808 arm,cs-dev-assoc = <&etm2>;
815 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
817 reg = <0x0085b000 0x1000>;
819 clocks = <&rpmcc RPM_QDSS_CLK>;
820 clock-names = "apb_pclk";
823 arm,cs-dev-assoc = <&etm3>;
829 compatible = "arm,coresight-etm4x", "arm,primecell";
830 reg = <0x0085c000 0x1000>;
832 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
833 clock-names = "apb_pclk", "atclk";
834 arm,coresight-loses-context-with-cpu;
843 remote-endpoint = <&funnel1_in0>;
850 compatible = "arm,coresight-etm4x", "arm,primecell";
851 reg = <0x0085d000 0x1000>;
853 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
854 clock-names = "apb_pclk", "atclk";
855 arm,coresight-loses-context-with-cpu;
864 remote-endpoint = <&funnel1_in1>;
871 compatible = "arm,coresight-etm4x", "arm,primecell";
872 reg = <0x0085e000 0x1000>;
874 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
875 clock-names = "apb_pclk", "atclk";
876 arm,coresight-loses-context-with-cpu;
885 remote-endpoint = <&funnel1_in2>;
892 compatible = "arm,coresight-etm4x", "arm,primecell";
893 reg = <0x0085f000 0x1000>;
895 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
896 clock-names = "apb_pclk", "atclk";
897 arm,coresight-loses-context-with-cpu;
906 remote-endpoint = <&funnel1_in3>;
912 msmgpio: pinctrl@1000000 {
913 compatible = "qcom,msm8916-pinctrl";
914 reg = <0x01000000 0x300000>;
915 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
917 gpio-ranges = <&msmgpio 0 0 122>;
919 interrupt-controller;
920 #interrupt-cells = <2>;
923 gcc: clock-controller@1800000 {
924 compatible = "qcom,gcc-msm8916";
927 #power-domain-cells = <1>;
928 reg = <0x01800000 0x80000>;
931 tcsr_mutex: hwlock@1905000 {
932 compatible = "qcom,tcsr-mutex";
933 reg = <0x01905000 0x20000>;
937 tcsr: syscon@1937000 {
938 compatible = "qcom,tcsr-msm8916", "syscon";
939 reg = <0x01937000 0x30000>;
944 compatible = "qcom,mdss";
945 reg = <0x01a00000 0x1000>,
947 reg-names = "mdss_phys", "vbif_phys";
949 power-domains = <&gcc MDSS_GDSC>;
951 clocks = <&gcc GCC_MDSS_AHB_CLK>,
952 <&gcc GCC_MDSS_AXI_CLK>,
953 <&gcc GCC_MDSS_VSYNC_CLK>;
954 clock-names = "iface",
958 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
960 interrupt-controller;
961 #interrupt-cells = <1>;
963 #address-cells = <1>;
968 compatible = "qcom,mdp5";
969 reg = <0x01a01000 0x89000>;
970 reg-names = "mdp_phys";
972 interrupt-parent = <&mdss>;
975 clocks = <&gcc GCC_MDSS_AHB_CLK>,
976 <&gcc GCC_MDSS_AXI_CLK>,
977 <&gcc GCC_MDSS_MDP_CLK>,
978 <&gcc GCC_MDSS_VSYNC_CLK>;
979 clock-names = "iface",
984 iommus = <&apps_iommu 4>;
987 #address-cells = <1>;
992 mdp5_intf1_out: endpoint {
993 remote-endpoint = <&dsi0_in>;
1000 compatible = "qcom,mdss-dsi-ctrl";
1001 reg = <0x01a98000 0x25c>;
1002 reg-names = "dsi_ctrl";
1004 interrupt-parent = <&mdss>;
1007 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1008 <&gcc PCLK0_CLK_SRC>;
1009 assigned-clock-parents = <&dsi_phy0 0>,
1012 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1013 <&gcc GCC_MDSS_AHB_CLK>,
1014 <&gcc GCC_MDSS_AXI_CLK>,
1015 <&gcc GCC_MDSS_BYTE0_CLK>,
1016 <&gcc GCC_MDSS_PCLK0_CLK>,
1017 <&gcc GCC_MDSS_ESC0_CLK>;
1018 clock-names = "mdp_core",
1025 phy-names = "dsi-phy";
1027 #address-cells = <1>;
1031 #address-cells = <1>;
1037 remote-endpoint = <&mdp5_intf1_out>;
1043 dsi0_out: endpoint {
1049 dsi_phy0: dsi-phy@1a98300 {
1050 compatible = "qcom,dsi-phy-28nm-lp";
1051 reg = <0x01a98300 0xd4>,
1054 reg-names = "dsi_pll",
1056 "dsi_phy_regulator";
1061 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1063 clock-names = "iface", "ref";
1067 camss: camss@1b00000 {
1068 compatible = "qcom,msm8916-camss";
1069 reg = <0x01b0ac00 0x200>,
1077 <0x01b10000 0x1000>;
1078 reg-names = "csiphy0",
1087 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1088 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1089 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1090 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1091 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1092 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1093 interrupt-names = "csiphy0",
1099 power-domains = <&gcc VFE_GDSC>;
1100 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1101 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1102 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1103 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1104 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1105 <&gcc GCC_CAMSS_CSI0_CLK>,
1106 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1107 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1108 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1109 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1110 <&gcc GCC_CAMSS_CSI1_CLK>,
1111 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1112 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1113 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1114 <&gcc GCC_CAMSS_AHB_CLK>,
1115 <&gcc GCC_CAMSS_VFE0_CLK>,
1116 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1117 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1118 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1119 clock-names = "top_ahb",
1138 iommus = <&apps_iommu 3>;
1139 status = "disabled";
1141 #address-cells = <1>;
1147 compatible = "qcom,msm8916-cci";
1148 #address-cells = <1>;
1150 reg = <0x01b0c000 0x1000>;
1151 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1152 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1153 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1154 <&gcc GCC_CAMSS_CCI_CLK>,
1155 <&gcc GCC_CAMSS_AHB_CLK>;
1156 clock-names = "camss_top_ahb", "cci_ahb",
1158 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1159 <&gcc GCC_CAMSS_CCI_CLK>;
1160 assigned-clock-rates = <80000000>, <19200000>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&cci0_default>;
1163 status = "disabled";
1165 cci_i2c0: i2c-bus@0 {
1167 clock-frequency = <400000>;
1168 #address-cells = <1>;
1174 compatible = "qcom,adreno-306.0", "qcom,adreno";
1175 reg = <0x01c00000 0x20000>;
1176 reg-names = "kgsl_3d0_reg_memory";
1177 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "kgsl_3d0_irq";
1187 <&gcc GCC_OXILI_GFX3D_CLK>,
1188 <&gcc GCC_OXILI_AHB_CLK>,
1189 <&gcc GCC_OXILI_GMEM_CLK>,
1190 <&gcc GCC_BIMC_GFX_CLK>,
1191 <&gcc GCC_BIMC_GPU_CLK>,
1192 <&gcc GFX3D_CLK_SRC>;
1193 power-domains = <&gcc OXILI_GDSC>;
1194 operating-points-v2 = <&gpu_opp_table>;
1195 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1197 gpu_opp_table: opp-table {
1198 compatible = "operating-points-v2";
1201 opp-hz = /bits/ 64 <400000000>;
1204 opp-hz = /bits/ 64 <19200000>;
1209 venus: video-codec@1d00000 {
1210 compatible = "qcom,msm8916-venus";
1211 reg = <0x01d00000 0xff000>;
1212 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1213 power-domains = <&gcc VENUS_GDSC>;
1214 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1215 <&gcc GCC_VENUS0_AHB_CLK>,
1216 <&gcc GCC_VENUS0_AXI_CLK>;
1217 clock-names = "core", "iface", "bus";
1218 iommus = <&apps_iommu 5>;
1219 memory-region = <&venus_mem>;
1223 compatible = "venus-decoder";
1227 compatible = "venus-encoder";
1231 apps_iommu: iommu@1ef0000 {
1232 #address-cells = <1>;
1235 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1236 ranges = <0 0x01e20000 0x40000>;
1237 reg = <0x01ef0000 0x3000>;
1238 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1239 <&gcc GCC_APSS_TCU_CLK>;
1240 clock-names = "iface", "bus";
1241 qcom,iommu-secure-id = <17>;
1245 compatible = "qcom,msm-iommu-v1-sec";
1246 reg = <0x3000 0x1000>;
1247 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1252 compatible = "qcom,msm-iommu-v1-ns";
1253 reg = <0x4000 0x1000>;
1254 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1259 compatible = "qcom,msm-iommu-v1-sec";
1260 reg = <0x5000 0x1000>;
1261 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1265 gpu_iommu: iommu@1f08000 {
1266 #address-cells = <1>;
1269 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1270 ranges = <0 0x01f08000 0x10000>;
1271 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1272 <&gcc GCC_GFX_TCU_CLK>;
1273 clock-names = "iface", "bus";
1274 qcom,iommu-secure-id = <18>;
1278 compatible = "qcom,msm-iommu-v1-ns";
1279 reg = <0x1000 0x1000>;
1280 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1285 compatible = "qcom,msm-iommu-v1-ns";
1286 reg = <0x2000 0x1000>;
1287 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1291 spmi_bus: spmi@200f000 {
1292 compatible = "qcom,spmi-pmic-arb";
1293 reg = <0x0200f000 0x001000>,
1294 <0x02400000 0x400000>,
1295 <0x02c00000 0x400000>,
1296 <0x03800000 0x200000>,
1297 <0x0200a000 0x002100>;
1298 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1299 interrupt-names = "periph_irq";
1300 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1303 #address-cells = <2>;
1305 interrupt-controller;
1306 #interrupt-cells = <4>;
1309 mpss: remoteproc@4080000 {
1310 compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1311 reg = <0x04080000 0x100>,
1314 reg-names = "qdsp6", "rmb";
1316 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1317 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1318 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1319 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1320 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1321 interrupt-names = "wdog", "fatal", "ready",
1322 "handover", "stop-ack";
1324 power-domains = <&rpmpd MSM8916_VDDCX>,
1325 <&rpmpd MSM8916_VDDMX>;
1326 power-domain-names = "cx", "mx";
1328 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1329 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1330 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1332 clock-names = "iface", "bus", "mem", "xo";
1334 qcom,smem-states = <&hexagon_smp2p_out 0>;
1335 qcom,smem-state-names = "stop";
1338 reset-names = "mss_restart";
1340 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1342 status = "disabled";
1345 memory-region = <&mba_mem>;
1349 memory-region = <&mpss_mem>;
1353 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1355 qcom,smd-edge = <0>;
1356 qcom,ipc = <&apcs 8 12>;
1357 qcom,remote-pid = <1>;
1362 compatible = "qcom,fastrpc";
1363 qcom,smd-channels = "fastrpcsmd-apps-dsp";
1366 #address-cells = <1>;
1370 compatible = "qcom,fastrpc-compute-cb";
1377 sound: sound@7702000 {
1378 status = "disabled";
1379 compatible = "qcom,apq8016-sbc-sndcard";
1380 reg = <0x07702000 0x4>, <0x07702004 0x4>;
1381 reg-names = "mic-iomux", "spkr-iomux";
1384 lpass: audio-controller@7708000 {
1385 status = "disabled";
1386 compatible = "qcom,lpass-cpu-apq8016";
1387 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1388 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1389 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1390 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1391 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1392 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1393 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1395 clock-names = "ahbix-clk",
1402 #sound-dai-cells = <1>;
1404 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1405 interrupt-names = "lpass-irq-lpaif";
1406 reg = <0x07708000 0x10000>;
1407 reg-names = "lpass-lpaif";
1409 #address-cells = <1>;
1413 lpass_codec: audio-codec@771c000 {
1414 compatible = "qcom,msm8916-wcd-digital-codec";
1415 reg = <0x0771c000 0x400>;
1416 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1417 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1418 clock-names = "ahbix-clk", "mclk";
1419 #sound-dai-cells = <1>;
1422 sdhc_1: sdhci@7824000 {
1423 compatible = "qcom,sdhci-msm-v4";
1424 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1425 reg-names = "hc_mem", "core_mem";
1427 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc_irq", "pwr_irq";
1430 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1431 <&gcc GCC_SDCC1_AHB_CLK>,
1433 clock-names = "core", "iface", "xo";
1437 status = "disabled";
1440 sdhc_2: sdhci@7864000 {
1441 compatible = "qcom,sdhci-msm-v4";
1442 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1443 reg-names = "hc_mem", "core_mem";
1445 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1447 interrupt-names = "hc_irq", "pwr_irq";
1448 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1449 <&gcc GCC_SDCC2_AHB_CLK>,
1451 clock-names = "core", "iface", "xo";
1453 status = "disabled";
1456 blsp_dma: dma-controller@7884000 {
1457 compatible = "qcom,bam-v1.7.0";
1458 reg = <0x07884000 0x23000>;
1459 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1460 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1461 clock-names = "bam_clk";
1464 status = "disabled";
1467 blsp1_uart1: serial@78af000 {
1468 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1469 reg = <0x078af000 0x200>;
1470 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1472 clock-names = "core", "iface";
1473 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
1474 dma-names = "rx", "tx";
1475 pinctrl-names = "default", "sleep";
1476 pinctrl-0 = <&blsp1_uart1_default>;
1477 pinctrl-1 = <&blsp1_uart1_sleep>;
1478 status = "disabled";
1481 blsp1_uart2: serial@78b0000 {
1482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1483 reg = <0x078b0000 0x200>;
1484 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1486 clock-names = "core", "iface";
1487 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
1488 dma-names = "rx", "tx";
1489 pinctrl-names = "default", "sleep";
1490 pinctrl-0 = <&blsp1_uart2_default>;
1491 pinctrl-1 = <&blsp1_uart2_sleep>;
1492 status = "disabled";
1495 blsp_i2c1: i2c@78b5000 {
1496 compatible = "qcom,i2c-qup-v2.2.1";
1497 reg = <0x078b5000 0x500>;
1498 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1500 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
1501 clock-names = "iface", "core";
1502 pinctrl-names = "default", "sleep";
1503 pinctrl-0 = <&i2c1_default>;
1504 pinctrl-1 = <&i2c1_sleep>;
1505 #address-cells = <1>;
1507 status = "disabled";
1510 blsp_spi1: spi@78b5000 {
1511 compatible = "qcom,spi-qup-v2.2.1";
1512 reg = <0x078b5000 0x500>;
1513 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1514 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1515 <&gcc GCC_BLSP1_AHB_CLK>;
1516 clock-names = "core", "iface";
1517 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
1518 dma-names = "rx", "tx";
1519 pinctrl-names = "default", "sleep";
1520 pinctrl-0 = <&spi1_default>;
1521 pinctrl-1 = <&spi1_sleep>;
1522 #address-cells = <1>;
1524 status = "disabled";
1527 blsp_i2c2: i2c@78b6000 {
1528 compatible = "qcom,i2c-qup-v2.2.1";
1529 reg = <0x078b6000 0x500>;
1530 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1531 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1532 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
1533 clock-names = "iface", "core";
1534 pinctrl-names = "default", "sleep";
1535 pinctrl-0 = <&i2c2_default>;
1536 pinctrl-1 = <&i2c2_sleep>;
1537 #address-cells = <1>;
1539 status = "disabled";
1542 blsp_spi2: spi@78b6000 {
1543 compatible = "qcom,spi-qup-v2.2.1";
1544 reg = <0x078b6000 0x500>;
1545 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1546 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1547 <&gcc GCC_BLSP1_AHB_CLK>;
1548 clock-names = "core", "iface";
1549 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
1550 dma-names = "rx", "tx";
1551 pinctrl-names = "default", "sleep";
1552 pinctrl-0 = <&spi2_default>;
1553 pinctrl-1 = <&spi2_sleep>;
1554 #address-cells = <1>;
1556 status = "disabled";
1559 blsp_i2c3: i2c@78b7000 {
1560 compatible = "qcom,i2c-qup-v2.2.1";
1561 reg = <0x078b7000 0x500>;
1562 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1563 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1564 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1565 clock-names = "iface", "core";
1566 pinctrl-names = "default", "sleep";
1567 pinctrl-0 = <&i2c3_default>;
1568 pinctrl-1 = <&i2c3_sleep>;
1569 #address-cells = <1>;
1571 status = "disabled";
1574 blsp_spi3: spi@78b7000 {
1575 compatible = "qcom,spi-qup-v2.2.1";
1576 reg = <0x078b7000 0x500>;
1577 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1578 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1579 <&gcc GCC_BLSP1_AHB_CLK>;
1580 clock-names = "core", "iface";
1581 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
1582 dma-names = "rx", "tx";
1583 pinctrl-names = "default", "sleep";
1584 pinctrl-0 = <&spi3_default>;
1585 pinctrl-1 = <&spi3_sleep>;
1586 #address-cells = <1>;
1588 status = "disabled";
1591 blsp_i2c4: i2c@78b8000 {
1592 compatible = "qcom,i2c-qup-v2.2.1";
1593 reg = <0x078b8000 0x500>;
1594 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1595 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1596 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1597 clock-names = "iface", "core";
1598 pinctrl-names = "default", "sleep";
1599 pinctrl-0 = <&i2c4_default>;
1600 pinctrl-1 = <&i2c4_sleep>;
1601 #address-cells = <1>;
1603 status = "disabled";
1606 blsp_spi4: spi@78b8000 {
1607 compatible = "qcom,spi-qup-v2.2.1";
1608 reg = <0x078b8000 0x500>;
1609 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1610 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1611 <&gcc GCC_BLSP1_AHB_CLK>;
1612 clock-names = "core", "iface";
1613 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
1614 dma-names = "rx", "tx";
1615 pinctrl-names = "default", "sleep";
1616 pinctrl-0 = <&spi4_default>;
1617 pinctrl-1 = <&spi4_sleep>;
1618 #address-cells = <1>;
1620 status = "disabled";
1623 blsp_i2c5: i2c@78b9000 {
1624 compatible = "qcom,i2c-qup-v2.2.1";
1625 reg = <0x078b9000 0x500>;
1626 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1627 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1628 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
1629 clock-names = "iface", "core";
1630 pinctrl-names = "default", "sleep";
1631 pinctrl-0 = <&i2c5_default>;
1632 pinctrl-1 = <&i2c5_sleep>;
1633 #address-cells = <1>;
1635 status = "disabled";
1638 blsp_spi5: spi@78b9000 {
1639 compatible = "qcom,spi-qup-v2.2.1";
1640 reg = <0x078b9000 0x500>;
1641 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1643 <&gcc GCC_BLSP1_AHB_CLK>;
1644 clock-names = "core", "iface";
1645 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
1646 dma-names = "rx", "tx";
1647 pinctrl-names = "default", "sleep";
1648 pinctrl-0 = <&spi5_default>;
1649 pinctrl-1 = <&spi5_sleep>;
1650 #address-cells = <1>;
1652 status = "disabled";
1655 blsp_i2c6: i2c@78ba000 {
1656 compatible = "qcom,i2c-qup-v2.2.1";
1657 reg = <0x078ba000 0x500>;
1658 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1659 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1660 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
1661 clock-names = "iface", "core";
1662 pinctrl-names = "default", "sleep";
1663 pinctrl-0 = <&i2c6_default>;
1664 pinctrl-1 = <&i2c6_sleep>;
1665 #address-cells = <1>;
1667 status = "disabled";
1670 blsp_spi6: spi@78ba000 {
1671 compatible = "qcom,spi-qup-v2.2.1";
1672 reg = <0x078ba000 0x500>;
1673 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1674 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1675 <&gcc GCC_BLSP1_AHB_CLK>;
1676 clock-names = "core", "iface";
1677 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
1678 dma-names = "rx", "tx";
1679 pinctrl-names = "default", "sleep";
1680 pinctrl-0 = <&spi6_default>;
1681 pinctrl-1 = <&spi6_sleep>;
1682 #address-cells = <1>;
1684 status = "disabled";
1688 compatible = "qcom,ci-hdrc";
1689 reg = <0x078d9000 0x200>,
1691 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1692 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1693 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1694 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1695 clock-names = "iface", "core";
1696 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1697 assigned-clock-rates = <80000000>;
1698 resets = <&gcc GCC_USB_HS_BCR>;
1699 reset-names = "core";
1705 ahb-burst-config = <0>;
1706 phy-names = "usb-phy";
1707 phys = <&usb_hs_phy>;
1708 status = "disabled";
1713 compatible = "qcom,usb-hs-phy-msm8916",
1716 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1717 clock-names = "ref", "sleep";
1718 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1719 reset-names = "phy", "por";
1720 qcom,init-seq = /bits/ 8 <0x0 0x44
1721 0x1 0x6b 0x2 0x24 0x3 0x13>;
1726 pronto: remoteproc@a21b000 {
1727 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1728 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1729 reg-names = "ccu", "dxe", "pmu";
1731 memory-region = <&wcnss_mem>;
1733 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1734 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1735 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1736 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1737 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1738 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1740 power-domains = <&rpmpd MSM8916_VDDCX>,
1741 <&rpmpd MSM8916_VDDMX>;
1742 power-domain-names = "cx", "mx";
1744 qcom,state = <&wcnss_smp2p_out 0>;
1745 qcom,state-names = "stop";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&wcnss_pin_a>;
1750 status = "disabled";
1753 compatible = "qcom,wcn3620";
1755 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1760 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1762 qcom,ipc = <&apcs 8 17>;
1763 qcom,smd-edge = <6>;
1764 qcom,remote-pid = <4>;
1769 compatible = "qcom,wcnss";
1770 qcom,smd-channels = "WCNSS_CTRL";
1772 qcom,mmio = <&pronto>;
1775 compatible = "qcom,wcnss-bt";
1779 compatible = "qcom,wcnss-wlan";
1781 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1783 interrupt-names = "tx", "rx";
1785 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1786 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1792 intc: interrupt-controller@b000000 {
1793 compatible = "qcom,msm-qgic2";
1794 interrupt-controller;
1795 #interrupt-cells = <3>;
1796 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1797 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1798 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1801 apcs: mailbox@b011000 {
1802 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1803 reg = <0x0b011000 0x1000>;
1805 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1806 clock-names = "pll", "aux";
1810 a53pll: clock@b016000 {
1811 compatible = "qcom,msm8916-a53pll";
1812 reg = <0x0b016000 0x40>;
1817 #address-cells = <1>;
1820 compatible = "arm,armv7-timer-mem";
1821 reg = <0x0b020000 0x1000>;
1822 clock-frequency = <19200000>;
1826 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1828 reg = <0x0b021000 0x1000>,
1829 <0x0b022000 0x1000>;
1834 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1835 reg = <0x0b023000 0x1000>;
1836 status = "disabled";
1841 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1842 reg = <0x0b024000 0x1000>;
1843 status = "disabled";
1848 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1849 reg = <0x0b025000 0x1000>;
1850 status = "disabled";
1855 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1856 reg = <0x0b026000 0x1000>;
1857 status = "disabled";
1862 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1863 reg = <0x0b027000 0x1000>;
1864 status = "disabled";
1869 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1870 reg = <0x0b028000 0x1000>;
1871 status = "disabled";
1878 polling-delay-passive = <250>;
1879 polling-delay = <1000>;
1881 thermal-sensors = <&tsens 5>;
1884 cpu0_1_alert0: trip-point0 {
1885 temperature = <75000>;
1886 hysteresis = <2000>;
1889 cpu0_1_crit: cpu_crit {
1890 temperature = <110000>;
1891 hysteresis = <2000>;
1898 trip = <&cpu0_1_alert0>;
1899 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1900 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1901 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1902 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1908 polling-delay-passive = <250>;
1909 polling-delay = <1000>;
1911 thermal-sensors = <&tsens 4>;
1914 cpu2_3_alert0: trip-point0 {
1915 temperature = <75000>;
1916 hysteresis = <2000>;
1919 cpu2_3_crit: cpu_crit {
1920 temperature = <110000>;
1921 hysteresis = <2000>;
1928 trip = <&cpu2_3_alert0>;
1929 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1930 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1931 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1932 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1938 polling-delay-passive = <250>;
1939 polling-delay = <1000>;
1941 thermal-sensors = <&tsens 2>;
1944 gpu_alert0: trip-point0 {
1945 temperature = <75000>;
1946 hysteresis = <2000>;
1949 gpu_crit: gpu_crit {
1950 temperature = <95000>;
1951 hysteresis = <2000>;
1958 polling-delay-passive = <250>;
1959 polling-delay = <1000>;
1961 thermal-sensors = <&tsens 1>;
1964 cam_alert0: trip-point0 {
1965 temperature = <75000>;
1966 hysteresis = <2000>;
1973 polling-delay-passive = <250>;
1974 polling-delay = <1000>;
1976 thermal-sensors = <&tsens 0>;
1979 modem_alert0: trip-point0 {
1980 temperature = <85000>;
1981 hysteresis = <2000>;
1990 compatible = "arm,armv8-timer";
1991 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1992 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1993 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1994 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1998 #include "msm8916-pins.dtsi"