arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         model = "Qualcomm Technologies, Inc. IPQ8074";
  11         compatible = "qcom,ipq8074";
  12
  13         clocks {
  14                 sleep_clk: sleep_clk {
  15                         compatible = "fixed-clock";
  16                         clock-frequency = <32000>;
  17                         #clock-cells = <0>;
  18                 };
  19
  20                 xo: xo {
  21                         compatible = "fixed-clock";
  22                         clock-frequency = <19200000>;
  23                         #clock-cells = <0>;
  24                 };
  25         };
  26
  27         cpus {
  28                 #address-cells = <0x1>;
  29                 #size-cells = <0x0>;
  30
  31                 CPU0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x0>;
  35                         next-level-cache = <&L2_0>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 CPU1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         enable-method = "psci";
  43                         reg = <0x1>;
  44                         next-level-cache = <&L2_0>;
  45                 };
  46
  47                 CPU2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         enable-method = "psci";
  51                         reg = <0x2>;
  52                         next-level-cache = <&L2_0>;
  53                 };
  54
  55                 CPU3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         enable-method = "psci";
  59                         reg = <0x3>;
  60                         next-level-cache = <&L2_0>;
  61                 };
  62
  63                 L2_0: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <0x2>;
  66                 };
  67         };
  68
  69         pmu {
  70                 compatible = "arm,armv8-pmuv3";
  71                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         soc: soc {
  80                 #address-cells = <0x1>;
  81                 #size-cells = <0x1>;
  82                 ranges = <0 0 0 0xffffffff>;
  83                 compatible = "simple-bus";
  84
  85                 pcie_phy0: phy@86000 {
  86                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  87                         reg = <0x00086000 0x1000>;
  88                         #phy-cells = <0>;
  89                         clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  90                         clock-names = "pipe_clk";
  91                         clock-output-names = "pcie20_phy0_pipe_clk";
  92
  93                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
  94                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
  95                         reset-names = "phy",
  96                                       "common";
  97                         status = "disabled";
  98                 };
  99
 100                 pcie_phy1: phy@8e000 {
 101                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 102                         reg = <0x0008e000 0x1000>;
 103                         #phy-cells = <0>;
 104                         clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 105                         clock-names = "pipe_clk";
 106                         clock-output-names = "pcie20_phy1_pipe_clk";
 107
 108                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 109                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
 110                         reset-names = "phy",
 111                                       "common";
 112                         status = "disabled";
 113                 };
 114
 115                 tlmm: pinctrl@1000000 {
 116                         compatible = "qcom,ipq8074-pinctrl";
 117                         reg = <0x01000000 0x300000>;
 118                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 119                         gpio-controller;
 120                         gpio-ranges = <&tlmm 0 0 70>;
 121                         #gpio-cells = <0x2>;
 122                         interrupt-controller;
 123                         #interrupt-cells = <0x2>;
 124
 125                         serial_4_pins: serial4-pinmux {
 126                                 pins = "gpio23", "gpio24";
 127                                 function = "blsp4_uart1";
 128                                 drive-strength = <8>;
 129                                 bias-disable;
 130                         };
 131
 132                         i2c_0_pins: i2c-0-pinmux {
 133                                 pins = "gpio42", "gpio43";
 134                                 function = "blsp1_i2c";
 135                                 drive-strength = <8>;
 136                                 bias-disable;
 137                         };
 138
 139                         spi_0_pins: spi-0-pins {
 140                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 141                                 function = "blsp0_spi";
 142                                 drive-strength = <8>;
 143                                 bias-disable;
 144                         };
 145
 146                         hsuart_pins: hsuart-pins {
 147                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 148                                 function = "blsp2_uart";
 149                                 drive-strength = <8>;
 150                                 bias-disable;
 151                         };
 152
 153                         qpic_pins: qpic-pins {
 154                                 pins = "gpio1", "gpio3", "gpio4",
 155                                        "gpio5", "gpio6", "gpio7",
 156                                        "gpio8", "gpio10", "gpio11",
 157                                        "gpio12", "gpio13", "gpio14",
 158                                        "gpio15", "gpio16", "gpio17";
 159                                 function = "qpic";
 160                                 drive-strength = <8>;
 161                                 bias-disable;
 162                         };
 163                 };
 164
 165                 gcc: gcc@1800000 {
 166                         compatible = "qcom,gcc-ipq8074";
 167                         reg = <0x01800000 0x80000>;
 168                         #clock-cells = <0x1>;
 169                         #reset-cells = <0x1>;
 170                 };
 171
 172                 blsp_dma: dma@7884000 {
 173                         compatible = "qcom,bam-v1.7.0";
 174                         reg = <0x07884000 0x2b000>;
 175                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 176                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 177                         clock-names = "bam_clk";
 178                         #dma-cells = <1>;
 179                         qcom,ee = <0>;
 180                 };
 181
 182                 blsp1_uart1: serial@78af000 {
 183                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 184                         reg = <0x078af000 0x200>;
 185                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 186                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 187                                  <&gcc GCC_BLSP1_AHB_CLK>;
 188                         clock-names = "core", "iface";
 189                         status = "disabled";
 190                 };
 191
 192                 blsp1_uart3: serial@78b1000 {
 193                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 194                         reg = <0x078b1000 0x200>;
 195                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 197                                 <&gcc GCC_BLSP1_AHB_CLK>;
 198                         clock-names = "core", "iface";
 199                         dmas = <&blsp_dma 4>,
 200                                 <&blsp_dma 5>;
 201                         dma-names = "tx", "rx";
 202                         pinctrl-0 = <&hsuart_pins>;
 203                         pinctrl-names = "default";
 204                         status = "disabled";
 205                 };
 206
 207                 blsp1_uart5: serial@78b3000 {
 208                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 209                         reg = <0x078b3000 0x200>;
 210                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 211                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 212                                  <&gcc GCC_BLSP1_AHB_CLK>;
 213                         clock-names = "core", "iface";
 214                         pinctrl-0 = <&serial_4_pins>;
 215                         pinctrl-names = "default";
 216                         status = "disabled";
 217                 };
 218
 219                 blsp1_spi1: spi@78b5000 {
 220                         compatible = "qcom,spi-qup-v2.2.1";
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         reg = <0x078b5000 0x600>;
 224                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 225                         spi-max-frequency = <50000000>;
 226                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 227                                 <&gcc GCC_BLSP1_AHB_CLK>;
 228                         clock-names = "core", "iface";
 229                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 230                         dma-names = "tx", "rx";
 231                         pinctrl-0 = <&spi_0_pins>;
 232                         pinctrl-names = "default";
 233                         status = "disabled";
 234                 };
 235
 236                 blsp1_i2c2: i2c@78b6000 {
 237                         compatible = "qcom,i2c-qup-v2.2.1";
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         reg = <0x078b6000 0x600>;
 241                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 243                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 244                         clock-names = "iface", "core";
 245                         clock-frequency = <400000>;
 246                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 247                         dma-names = "rx", "tx";
 248                         pinctrl-0 = <&i2c_0_pins>;
 249                         pinctrl-names = "default";
 250                         status = "disabled";
 251                 };
 252
 253                 blsp1_i2c3: i2c@78b7000 {
 254                         compatible = "qcom,i2c-qup-v2.2.1";
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         reg = <0x078b7000 0x600>;
 258                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 260                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 261                         clock-names = "iface", "core";
 262                         clock-frequency = <100000>;
 263                         dmas = <&blsp_dma 17>, <&blsp_dma 16>;
 264                         dma-names = "rx", "tx";
 265                         status = "disabled";
 266                 };
 267
 268                 qpic_bam: dma@7984000 {
 269                         compatible = "qcom,bam-v1.7.0";
 270                         reg = <0x07984000 0x1a000>;
 271                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 273                         clock-names = "bam_clk";
 274                         #dma-cells = <1>;
 275                         qcom,ee = <0>;
 276                         status = "disabled";
 277                 };
 278
 279                 qpic_nand: nand@79b0000 {
 280                         compatible = "qcom,ipq8074-nand";
 281                         reg = <0x079b0000 0x10000>;
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         clocks = <&gcc GCC_QPIC_CLK>,
 285                                  <&gcc GCC_QPIC_AHB_CLK>;
 286                         clock-names = "core", "aon";
 287
 288                         dmas = <&qpic_bam 0>,
 289                                <&qpic_bam 1>,
 290                                <&qpic_bam 2>;
 291                         dma-names = "tx", "rx", "cmd";
 292                         pinctrl-0 = <&qpic_pins>;
 293                         pinctrl-names = "default";
 294                         status = "disabled";
 295                 };
 296
 297                 intc: interrupt-controller@b000000 {
 298                         compatible = "qcom,msm-qgic2";
 299                         interrupt-controller;
 300                         #interrupt-cells = <0x3>;
 301                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 302                 };
 303
 304                 timer {
 305                         compatible = "arm,armv8-timer";
 306                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 307                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 308                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 309                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 310                 };
 311
 312                 timer@b120000 {
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         ranges;
 316                         compatible = "arm,armv7-timer-mem";
 317                         reg = <0x0b120000 0x1000>;
 318                         clock-frequency = <19200000>;
 319
 320                         frame@b120000 {
 321                                 frame-number = <0>;
 322                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 323                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 324                                 reg = <0x0b121000 0x1000>,
 325                                       <0x0b122000 0x1000>;
 326                         };
 327
 328                         frame@b123000 {
 329                                 frame-number = <1>;
 330                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 331                                 reg = <0x0b123000 0x1000>;
 332                                 status = "disabled";
 333                         };
 334
 335                         frame@b124000 {
 336                                 frame-number = <2>;
 337                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 338                                 reg = <0x0b124000 0x1000>;
 339                                 status = "disabled";
 340                         };
 341
 342                         frame@b125000 {
 343                                 frame-number = <3>;
 344                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 345                                 reg = <0x0b125000 0x1000>;
 346                                 status = "disabled";
 347                         };
 348
 349                         frame@b126000 {
 350                                 frame-number = <4>;
 351                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 352                                 reg = <0x0b126000 0x1000>;
 353                                 status = "disabled";
 354                         };
 355
 356                         frame@b127000 {
 357                                 frame-number = <5>;
 358                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 359                                 reg = <0x0b127000 0x1000>;
 360                                 status = "disabled";
 361                         };
 362
 363                         frame@b128000 {
 364                                 frame-number = <6>;
 365                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 366                                 reg = <0x0b128000 0x1000>;
 367                                 status = "disabled";
 368                         };
 369                 };
 370
 371                 pcie1: pci@10000000 {
 372                         compatible = "qcom,pcie-ipq8074";
 373                         reg =  <0x10000000 0xf1d
 374                                 0x10000f20 0xa8
 375                                 0x00088000 0x2000
 376                                 0x10100000 0x1000>;
 377                         reg-names = "dbi", "elbi", "parf", "config";
 378                         device_type = "pci";
 379                         linux,pci-domain = <1>;
 380                         bus-range = <0x00 0xff>;
 381                         num-lanes = <1>;
 382                         #address-cells = <3>;
 383                         #size-cells = <2>;
 384
 385                         phys = <&pcie_phy1>;
 386                         phy-names = "pciephy";
 387
 388                         ranges = <0x81000000 0 0x10200000 0x10200000
 389                                   0 0x100000   /* downstream I/O */
 390                                   0x82000000 0 0x10300000 0x10300000
 391                                   0 0xd00000>; /* non-prefetchable memory */
 392
 393                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 394                         interrupt-names = "msi";
 395                         #interrupt-cells = <1>;
 396                         interrupt-map-mask = <0 0 0 0x7>;
 397                         interrupt-map = <0 0 0 1 &intc 0 142
 398                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 399                                         <0 0 0 2 &intc 0 143
 400                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 401                                         <0 0 0 3 &intc 0 144
 402                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 403                                         <0 0 0 4 &intc 0 145
 404                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 405
 406                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 407                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 408                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 409                                  <&gcc GCC_PCIE1_AHB_CLK>,
 410                                  <&gcc GCC_PCIE1_AUX_CLK>;
 411                         clock-names = "iface",
 412                                       "axi_m",
 413                                       "axi_s",
 414                                       "ahb",
 415                                       "aux";
 416                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 417                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 418                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 419                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 420                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 421                                  <&gcc GCC_PCIE1_AHB_ARES>,
 422                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 423                         reset-names = "pipe",
 424                                       "sleep",
 425                                       "sticky",
 426                                       "axi_m",
 427                                       "axi_s",
 428                                       "ahb",
 429                                       "axi_m_sticky";
 430                         status = "disabled";
 431                 };
 432
 433                 pcie0: pci@20000000 {
 434                         compatible = "qcom,pcie-ipq8074";
 435                         reg =  <0x20000000 0xf1d
 436                                 0x20000f20 0xa8
 437                                 0x00080000 0x2000
 438                                 0x20100000 0x1000>;
 439                         reg-names = "dbi", "elbi", "parf", "config";
 440                         device_type = "pci";
 441                         linux,pci-domain = <0>;
 442                         bus-range = <0x00 0xff>;
 443                         num-lanes = <1>;
 444                         #address-cells = <3>;
 445                         #size-cells = <2>;
 446
 447                         phys = <&pcie_phy0>;
 448                         phy-names = "pciephy";
 449
 450                         ranges = <0x81000000 0 0x20200000 0x20200000
 451                                   0 0x100000   /* downstream I/O */
 452                                   0x82000000 0 0x20300000 0x20300000
 453                                   0 0xd00000>; /* non-prefetchable memory */
 454
 455                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 456                         interrupt-names = "msi";
 457                         #interrupt-cells = <1>;
 458                         interrupt-map-mask = <0 0 0 0x7>;
 459                         interrupt-map = <0 0 0 1 &intc 0 75
 460                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 461                                         <0 0 0 2 &intc 0 78
 462                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 463                                         <0 0 0 3 &intc 0 79
 464                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 465                                         <0 0 0 4 &intc 0 83
 466                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 467
 468                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 469                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 470                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 471                                  <&gcc GCC_PCIE0_AHB_CLK>,
 472                                  <&gcc GCC_PCIE0_AUX_CLK>;
 473
 474                         clock-names = "iface",
 475                                       "axi_m",
 476                                       "axi_s",
 477                                       "ahb",
 478                                       "aux";
 479                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 480                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 481                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 482                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 483                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 484                                  <&gcc GCC_PCIE0_AHB_ARES>,
 485                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
 486                         reset-names = "pipe",
 487                                       "sleep",
 488                                       "sticky",
 489                                       "axi_m",
 490                                       "axi_s",
 491                                       "ahb",
 492                                       "axi_m_sticky";
 493                         status = "disabled";
 494                 };
 495         };
 496 };