arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         model = "Qualcomm Technologies, Inc. IPQ8074";
  11         compatible = "qcom,ipq8074";
  12
  13         clocks {
  14                 sleep_clk: sleep_clk {
  15                         compatible = "fixed-clock";
  16                         clock-frequency = <32000>;
  17                         #clock-cells = <0>;
  18                 };
  19
  20                 xo: xo {
  21                         compatible = "fixed-clock";
  22                         clock-frequency = <19200000>;
  23                         #clock-cells = <0>;
  24                 };
  25         };
  26
  27         cpus {
  28                 #address-cells = <0x1>;
  29                 #size-cells = <0x0>;
  30
  31                 CPU0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x0>;
  35                         next-level-cache = <&L2_0>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 CPU1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         enable-method = "psci";
  43                         reg = <0x1>;
  44                         next-level-cache = <&L2_0>;
  45                 };
  46
  47                 CPU2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         enable-method = "psci";
  51                         reg = <0x2>;
  52                         next-level-cache = <&L2_0>;
  53                 };
  54
  55                 CPU3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         enable-method = "psci";
  59                         reg = <0x3>;
  60                         next-level-cache = <&L2_0>;
  61                 };
  62
  63                 L2_0: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <0x2>;
  66                 };
  67         };
  68
  69         pmu {
  70                 compatible = "arm,cortex-a53-pmu";
  71                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         soc: soc {
  80                 #address-cells = <0x1>;
  81                 #size-cells = <0x1>;
  82                 ranges = <0 0 0 0xffffffff>;
  83                 compatible = "simple-bus";
  84
  85                 ssphy_1: phy@58000 {
  86                         compatible = "qcom,ipq8074-qmp-usb3-phy";
  87                         reg = <0x00058000 0x1c4>;
  88                         #clock-cells = <1>;
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         ranges;
  92
  93                         clocks = <&gcc GCC_USB1_AUX_CLK>,
  94                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
  95                                 <&xo>;
  96                         clock-names = "aux", "cfg_ahb", "ref";
  97
  98                         resets =  <&gcc GCC_USB1_PHY_BCR>,
  99                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
 100                         reset-names = "phy","common";
 101                         status = "disabled";
 102
 103                         usb1_ssphy: lane@58200 {
 104                                 reg = <0x00058200 0x130>,       /* Tx */
 105                                       <0x00058400 0x200>,     /* Rx */
 106                                       <0x00058800 0x1f8>,     /* PCS  */
 107                                       <0x00058600 0x044>;     /* PCS misc*/
 108                                 #phy-cells = <0>;
 109                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
 110                                 clock-names = "pipe0";
 111                                 clock-output-names = "gcc_usb1_pipe_clk_src";
 112                         };
 113                 };
 114
 115                 qusb_phy_1: phy@59000 {
 116                         compatible = "qcom,ipq8074-qusb2-phy";
 117                         reg = <0x00059000 0x180>;
 118                         #phy-cells = <0>;
 119
 120                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 121                                  <&xo>;
 122                         clock-names = "cfg_ahb", "ref";
 123
 124                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 125                         status = "disabled";
 126                 };
 127
 128                 ssphy_0: phy@78000 {
 129                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 130                         reg = <0x00078000 0x1c4>;
 131                         #clock-cells = <1>;
 132                         #address-cells = <1>;
 133                         #size-cells = <1>;
 134                         ranges;
 135
 136                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 137                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 138                                 <&xo>;
 139                         clock-names = "aux", "cfg_ahb", "ref";
 140
 141                         resets =  <&gcc GCC_USB0_PHY_BCR>,
 142                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
 143                         reset-names = "phy","common";
 144                         status = "disabled";
 145
 146                         usb0_ssphy: lane@78200 {
 147                                 reg = <0x00078200 0x130>,       /* Tx */
 148                                       <0x00078400 0x200>,     /* Rx */
 149                                       <0x00078800 0x1f8>,     /* PCS  */
 150                                       <0x00078600 0x044>;     /* PCS misc*/
 151                                 #phy-cells = <0>;
 152                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 153                                 clock-names = "pipe0";
 154                                 clock-output-names = "gcc_usb0_pipe_clk_src";
 155                         };
 156                 };
 157
 158                 qusb_phy_0: phy@79000 {
 159                         compatible = "qcom,ipq8074-qusb2-phy";
 160                         reg = <0x00079000 0x180>;
 161                         #phy-cells = <0>;
 162
 163                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 164                                  <&xo>;
 165                         clock-names = "cfg_ahb", "ref";
 166
 167                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 168                 };
 169
 170                 pcie_phy0: phy@86000 {
 171                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 172                         reg = <0x00086000 0x1000>;
 173                         #phy-cells = <0>;
 174                         clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 175                         clock-names = "pipe_clk";
 176                         clock-output-names = "pcie20_phy0_pipe_clk";
 177
 178                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 179                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 180                         reset-names = "phy",
 181                                       "common";
 182                         status = "disabled";
 183                 };
 184
 185                 pcie_phy1: phy@8e000 {
 186                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 187                         reg = <0x0008e000 0x1000>;
 188                         #phy-cells = <0>;
 189                         clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 190                         clock-names = "pipe_clk";
 191                         clock-output-names = "pcie20_phy1_pipe_clk";
 192
 193                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 194                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
 195                         reset-names = "phy",
 196                                       "common";
 197                         status = "disabled";
 198                 };
 199
 200                 tlmm: pinctrl@1000000 {
 201                         compatible = "qcom,ipq8074-pinctrl";
 202                         reg = <0x01000000 0x300000>;
 203                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 204                         gpio-controller;
 205                         gpio-ranges = <&tlmm 0 0 70>;
 206                         #gpio-cells = <0x2>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <0x2>;
 209
 210                         serial_4_pins: serial4-pinmux {
 211                                 pins = "gpio23", "gpio24";
 212                                 function = "blsp4_uart1";
 213                                 drive-strength = <8>;
 214                                 bias-disable;
 215                         };
 216
 217                         i2c_0_pins: i2c-0-pinmux {
 218                                 pins = "gpio42", "gpio43";
 219                                 function = "blsp1_i2c";
 220                                 drive-strength = <8>;
 221                                 bias-disable;
 222                         };
 223
 224                         spi_0_pins: spi-0-pins {
 225                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 226                                 function = "blsp0_spi";
 227                                 drive-strength = <8>;
 228                                 bias-disable;
 229                         };
 230
 231                         hsuart_pins: hsuart-pins {
 232                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 233                                 function = "blsp2_uart";
 234                                 drive-strength = <8>;
 235                                 bias-disable;
 236                         };
 237
 238                         qpic_pins: qpic-pins {
 239                                 pins = "gpio1", "gpio3", "gpio4",
 240                                        "gpio5", "gpio6", "gpio7",
 241                                        "gpio8", "gpio10", "gpio11",
 242                                        "gpio12", "gpio13", "gpio14",
 243                                        "gpio15", "gpio16", "gpio17";
 244                                 function = "qpic";
 245                                 drive-strength = <8>;
 246                                 bias-disable;
 247                         };
 248                 };
 249
 250                 gcc: gcc@1800000 {
 251                         compatible = "qcom,gcc-ipq8074";
 252                         reg = <0x01800000 0x80000>;
 253                         #clock-cells = <0x1>;
 254                         #reset-cells = <0x1>;
 255                 };
 256
 257                 sdhc_1: sdhci@7824900 {
 258                         compatible = "qcom,sdhci-msm-v4";
 259                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 260                         reg-names = "hc_mem", "core_mem";
 261
 262                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 263                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 264                         interrupt-names = "hc_irq", "pwr_irq";
 265
 266                         clocks = <&xo>,
 267                                  <&gcc GCC_SDCC1_AHB_CLK>,
 268                                  <&gcc GCC_SDCC1_APPS_CLK>;
 269                         clock-names = "xo", "iface", "core";
 270                         max-frequency = <384000000>;
 271                         mmc-ddr-1_8v;
 272                         mmc-hs200-1_8v;
 273                         mmc-hs400-1_8v;
 274                         bus-width = <8>;
 275
 276                         status = "disabled";
 277                 };
 278
 279                 blsp_dma: dma-controller@7884000 {
 280                         compatible = "qcom,bam-v1.7.0";
 281                         reg = <0x07884000 0x2b000>;
 282                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 284                         clock-names = "bam_clk";
 285                         #dma-cells = <1>;
 286                         qcom,ee = <0>;
 287                 };
 288
 289                 blsp1_uart1: serial@78af000 {
 290                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 291                         reg = <0x078af000 0x200>;
 292                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 294                                  <&gcc GCC_BLSP1_AHB_CLK>;
 295                         clock-names = "core", "iface";
 296                         status = "disabled";
 297                 };
 298
 299                 blsp1_uart3: serial@78b1000 {
 300                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 301                         reg = <0x078b1000 0x200>;
 302                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 304                                 <&gcc GCC_BLSP1_AHB_CLK>;
 305                         clock-names = "core", "iface";
 306                         dmas = <&blsp_dma 4>,
 307                                 <&blsp_dma 5>;
 308                         dma-names = "tx", "rx";
 309                         pinctrl-0 = <&hsuart_pins>;
 310                         pinctrl-names = "default";
 311                         status = "disabled";
 312                 };
 313
 314                 blsp1_uart5: serial@78b3000 {
 315                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 316                         reg = <0x078b3000 0x200>;
 317                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 319                                  <&gcc GCC_BLSP1_AHB_CLK>;
 320                         clock-names = "core", "iface";
 321                         pinctrl-0 = <&serial_4_pins>;
 322                         pinctrl-names = "default";
 323                         status = "disabled";
 324                 };
 325
 326                 blsp1_spi1: spi@78b5000 {
 327                         compatible = "qcom,spi-qup-v2.2.1";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         reg = <0x078b5000 0x600>;
 331                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 332                         spi-max-frequency = <50000000>;
 333                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 334                                 <&gcc GCC_BLSP1_AHB_CLK>;
 335                         clock-names = "core", "iface";
 336                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 337                         dma-names = "tx", "rx";
 338                         pinctrl-0 = <&spi_0_pins>;
 339                         pinctrl-names = "default";
 340                         status = "disabled";
 341                 };
 342
 343                 blsp1_i2c2: i2c@78b6000 {
 344                         compatible = "qcom,i2c-qup-v2.2.1";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         reg = <0x078b6000 0x600>;
 348                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 349                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 350                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 351                         clock-names = "iface", "core";
 352                         clock-frequency = <400000>;
 353                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 354                         dma-names = "rx", "tx";
 355                         pinctrl-0 = <&i2c_0_pins>;
 356                         pinctrl-names = "default";
 357                         status = "disabled";
 358                 };
 359
 360                 blsp1_i2c3: i2c@78b7000 {
 361                         compatible = "qcom,i2c-qup-v2.2.1";
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         reg = <0x078b7000 0x600>;
 365                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 367                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 368                         clock-names = "iface", "core";
 369                         clock-frequency = <100000>;
 370                         dmas = <&blsp_dma 17>, <&blsp_dma 16>;
 371                         dma-names = "rx", "tx";
 372                         status = "disabled";
 373                 };
 374
 375                 qpic_bam: dma-controller@7984000 {
 376                         compatible = "qcom,bam-v1.7.0";
 377                         reg = <0x07984000 0x1a000>;
 378                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 379                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 380                         clock-names = "bam_clk";
 381                         #dma-cells = <1>;
 382                         qcom,ee = <0>;
 383                         status = "disabled";
 384                 };
 385
 386                 qpic_nand: nand@79b0000 {
 387                         compatible = "qcom,ipq8074-nand";
 388                         reg = <0x079b0000 0x10000>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         clocks = <&gcc GCC_QPIC_CLK>,
 392                                  <&gcc GCC_QPIC_AHB_CLK>;
 393                         clock-names = "core", "aon";
 394
 395                         dmas = <&qpic_bam 0>,
 396                                <&qpic_bam 1>,
 397                                <&qpic_bam 2>;
 398                         dma-names = "tx", "rx", "cmd";
 399                         pinctrl-0 = <&qpic_pins>;
 400                         pinctrl-names = "default";
 401                         status = "disabled";
 402                 };
 403
 404                 usb_0: usb@8af8800 {
 405                         compatible = "qcom,dwc3";
 406                         reg = <0x08af8800 0x400>;
 407                         #address-cells = <1>;
 408                         #size-cells = <1>;
 409                         ranges;
 410
 411                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 412                                 <&gcc GCC_USB0_MASTER_CLK>,
 413                                 <&gcc GCC_USB0_SLEEP_CLK>,
 414                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 415                         clock-names = "sys_noc_axi",
 416                                 "master",
 417                                 "sleep",
 418                                 "mock_utmi";
 419
 420                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 421                                           <&gcc GCC_USB0_MASTER_CLK>,
 422                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 423                         assigned-clock-rates = <133330000>,
 424                                                 <133330000>,
 425                                                 <19200000>;
 426
 427                         resets = <&gcc GCC_USB0_BCR>;
 428                         status = "disabled";
 429
 430                         dwc_0: dwc3@8a00000 {
 431                                 compatible = "snps,dwc3";
 432                                 reg = <0x8a00000 0xcd00>;
 433                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 434                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 435                                 phy-names = "usb2-phy", "usb3-phy";
 436                                 tx-fifo-resize;
 437                                 snps,is-utmi-l1-suspend;
 438                                 snps,hird-threshold = /bits/ 8 <0x0>;
 439                                 snps,dis_u2_susphy_quirk;
 440                                 snps,dis_u3_susphy_quirk;
 441                                 dr_mode = "host";
 442                         };
 443                 };
 444
 445                 usb_1: usb@8cf8800 {
 446                         compatible = "qcom,dwc3";
 447                         reg = <0x08cf8800 0x400>;
 448                         #address-cells = <1>;
 449                         #size-cells = <1>;
 450                         ranges;
 451
 452                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 453                                 <&gcc GCC_USB1_MASTER_CLK>,
 454                                 <&gcc GCC_USB1_SLEEP_CLK>,
 455                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 456                         clock-names = "sys_noc_axi",
 457                                 "master",
 458                                 "sleep",
 459                                 "mock_utmi";
 460
 461                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 462                                           <&gcc GCC_USB1_MASTER_CLK>,
 463                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 464                         assigned-clock-rates = <133330000>,
 465                                                 <133330000>,
 466                                                 <19200000>;
 467
 468                         resets = <&gcc GCC_USB1_BCR>;
 469                         status = "disabled";
 470
 471                         dwc_1: dwc3@8c00000 {
 472                                 compatible = "snps,dwc3";
 473                                 reg = <0x8c00000 0xcd00>;
 474                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 475                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
 476                                 phy-names = "usb2-phy", "usb3-phy";
 477                                 tx-fifo-resize;
 478                                 snps,is-utmi-l1-suspend;
 479                                 snps,hird-threshold = /bits/ 8 <0x0>;
 480                                 snps,dis_u2_susphy_quirk;
 481                                 snps,dis_u3_susphy_quirk;
 482                                 dr_mode = "host";
 483                         };
 484                 };
 485
 486                 intc: interrupt-controller@b000000 {
 487                         compatible = "qcom,msm-qgic2";
 488                         interrupt-controller;
 489                         #interrupt-cells = <0x3>;
 490                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 491                 };
 492
 493                 timer {
 494                         compatible = "arm,armv8-timer";
 495                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 496                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 497                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 498                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 499                 };
 500
 501                 watchdog: watchdog@b017000 {
 502                         compatible = "qcom,kpss-wdt";
 503                         reg = <0xb017000 0x1000>;
 504                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 505                         clocks = <&sleep_clk>;
 506                         timeout-sec = <30>;
 507                 };
 508
 509                 timer@b120000 {
 510                         #address-cells = <1>;
 511                         #size-cells = <1>;
 512                         ranges;
 513                         compatible = "arm,armv7-timer-mem";
 514                         reg = <0x0b120000 0x1000>;
 515                         clock-frequency = <19200000>;
 516
 517                         frame@b120000 {
 518                                 frame-number = <0>;
 519                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 520                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 521                                 reg = <0x0b121000 0x1000>,
 522                                       <0x0b122000 0x1000>;
 523                         };
 524
 525                         frame@b123000 {
 526                                 frame-number = <1>;
 527                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 528                                 reg = <0x0b123000 0x1000>;
 529                                 status = "disabled";
 530                         };
 531
 532                         frame@b124000 {
 533                                 frame-number = <2>;
 534                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 535                                 reg = <0x0b124000 0x1000>;
 536                                 status = "disabled";
 537                         };
 538
 539                         frame@b125000 {
 540                                 frame-number = <3>;
 541                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 542                                 reg = <0x0b125000 0x1000>;
 543                                 status = "disabled";
 544                         };
 545
 546                         frame@b126000 {
 547                                 frame-number = <4>;
 548                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 549                                 reg = <0x0b126000 0x1000>;
 550                                 status = "disabled";
 551                         };
 552
 553                         frame@b127000 {
 554                                 frame-number = <5>;
 555                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 556                                 reg = <0x0b127000 0x1000>;
 557                                 status = "disabled";
 558                         };
 559
 560                         frame@b128000 {
 561                                 frame-number = <6>;
 562                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 563                                 reg = <0x0b128000 0x1000>;
 564                                 status = "disabled";
 565                         };
 566                 };
 567
 568                 pcie1: pci@10000000 {
 569                         compatible = "qcom,pcie-ipq8074";
 570                         reg =  <0x10000000 0xf1d
 571                                 0x10000f20 0xa8
 572                                 0x00088000 0x2000
 573                                 0x10100000 0x1000>;
 574                         reg-names = "dbi", "elbi", "parf", "config";
 575                         device_type = "pci";
 576                         linux,pci-domain = <1>;
 577                         bus-range = <0x00 0xff>;
 578                         num-lanes = <1>;
 579                         #address-cells = <3>;
 580                         #size-cells = <2>;
 581
 582                         phys = <&pcie_phy1>;
 583                         phy-names = "pciephy";
 584
 585                         ranges = <0x81000000 0 0x10200000 0x10200000
 586                                   0 0x100000   /* downstream I/O */
 587                                   0x82000000 0 0x10300000 0x10300000
 588                                   0 0xd00000>; /* non-prefetchable memory */
 589
 590                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 591                         interrupt-names = "msi";
 592                         #interrupt-cells = <1>;
 593                         interrupt-map-mask = <0 0 0 0x7>;
 594                         interrupt-map = <0 0 0 1 &intc 0 142
 595                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 596                                         <0 0 0 2 &intc 0 143
 597                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 598                                         <0 0 0 3 &intc 0 144
 599                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 600                                         <0 0 0 4 &intc 0 145
 601                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 602
 603                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 604                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 605                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 606                                  <&gcc GCC_PCIE1_AHB_CLK>,
 607                                  <&gcc GCC_PCIE1_AUX_CLK>;
 608                         clock-names = "iface",
 609                                       "axi_m",
 610                                       "axi_s",
 611                                       "ahb",
 612                                       "aux";
 613                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 614                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 615                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 616                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 617                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 618                                  <&gcc GCC_PCIE1_AHB_ARES>,
 619                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 620                         reset-names = "pipe",
 621                                       "sleep",
 622                                       "sticky",
 623                                       "axi_m",
 624                                       "axi_s",
 625                                       "ahb",
 626                                       "axi_m_sticky";
 627                         status = "disabled";
 628                 };
 629
 630                 pcie0: pci@20000000 {
 631                         compatible = "qcom,pcie-ipq8074";
 632                         reg =  <0x20000000 0xf1d
 633                                 0x20000f20 0xa8
 634                                 0x00080000 0x2000
 635                                 0x20100000 0x1000>;
 636                         reg-names = "dbi", "elbi", "parf", "config";
 637                         device_type = "pci";
 638                         linux,pci-domain = <0>;
 639                         bus-range = <0x00 0xff>;
 640                         num-lanes = <1>;
 641                         #address-cells = <3>;
 642                         #size-cells = <2>;
 643
 644                         phys = <&pcie_phy0>;
 645                         phy-names = "pciephy";
 646
 647                         ranges = <0x81000000 0 0x20200000 0x20200000
 648                                   0 0x100000   /* downstream I/O */
 649                                   0x82000000 0 0x20300000 0x20300000
 650                                   0 0xd00000>; /* non-prefetchable memory */
 651
 652                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 653                         interrupt-names = "msi";
 654                         #interrupt-cells = <1>;
 655                         interrupt-map-mask = <0 0 0 0x7>;
 656                         interrupt-map = <0 0 0 1 &intc 0 75
 657                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 658                                         <0 0 0 2 &intc 0 78
 659                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 660                                         <0 0 0 3 &intc 0 79
 661                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 662                                         <0 0 0 4 &intc 0 83
 663                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 664
 665                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 666                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 667                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 668                                  <&gcc GCC_PCIE0_AHB_CLK>,
 669                                  <&gcc GCC_PCIE0_AUX_CLK>;
 670
 671                         clock-names = "iface",
 672                                       "axi_m",
 673                                       "axi_s",
 674                                       "ahb",
 675                                       "aux";
 676                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 677                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 678                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 679                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 680                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 681                                  <&gcc GCC_PCIE0_AHB_ARES>,
 682                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
 683                         reset-names = "pipe",
 684                                       "sleep",
 685                                       "sticky",
 686                                       "axi_m",
 687                                       "axi_s",
 688                                       "ahb",
 689                                       "axi_m_sticky";
 690                         status = "disabled";
 691                 };
 692         };
 693 };