arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         model = "Qualcomm Technologies, Inc. IPQ8074";
  14         compatible = "qcom,ipq8074";
  15         interrupt-parent = <&intc>;
  16
  17         clocks {
  18                 sleep_clk: sleep_clk {
  19                         compatible = "fixed-clock";
  20                         clock-frequency = <32768>;
  21                         #clock-cells = <0>;
  22                 };
  23
  24                 xo: xo {
  25                         compatible = "fixed-clock";
  26                         clock-frequency = <19200000>;
  27                         #clock-cells = <0>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 CPU0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         reg = <0x0>;
  39                         next-level-cache = <&L2_0>;
  40                         enable-method = "psci";
  41                 };
  42
  43                 CPU1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         enable-method = "psci";
  47                         reg = <0x1>;
  48                         next-level-cache = <&L2_0>;
  49                 };
  50
  51                 CPU2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         enable-method = "psci";
  55                         reg = <0x2>;
  56                         next-level-cache = <&L2_0>;
  57                 };
  58
  59                 CPU3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53";
  62                         enable-method = "psci";
  63                         reg = <0x3>;
  64                         next-level-cache = <&L2_0>;
  65                 };
  66
  67                 L2_0: l2-cache {
  68                         compatible = "cache";
  69                         cache-level = <0x2>;
  70                 };
  71         };
  72
  73         pmu {
  74                 compatible = "arm,cortex-a53-pmu";
  75                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         reserved-memory {
  84                 #address-cells = <2>;
  85                 #size-cells = <2>;
  86                 ranges;
  87
  88                 smem@4ab00000 {
  89                         compatible = "qcom,smem";
  90                         reg = <0x0 0x4ab00000 0x0 0x00100000>;
  91                         no-map;
  92
  93                         hwlocks = <&tcsr_mutex 0>;
  94                 };
  95
  96                 memory@4ac00000 {
  97                         no-map;
  98                         reg = <0x0 0x4ac00000 0x0 0x00400000>;
  99                 };
 100         };
 101
 102         firmware {
 103                 scm {
 104                         compatible = "qcom,scm-ipq8074", "qcom,scm";
 105                         qcom,dload-mode = <&tcsr 0x6100>;
 106                 };
 107         };
 108
 109         soc: soc@0 {
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges = <0 0 0 0xffffffff>;
 113                 compatible = "simple-bus";
 114
 115                 ssphy_1: phy@58000 {
 116                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 117                         reg = <0x00058000 0x1c4>;
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120                         ranges;
 121
 122                         clocks = <&gcc GCC_USB1_AUX_CLK>,
 123                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 124                                 <&xo>;
 125                         clock-names = "aux", "cfg_ahb", "ref";
 126
 127                         resets = <&gcc GCC_USB1_PHY_BCR>,
 128                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
 129                         reset-names = "phy","common";
 130                         status = "disabled";
 131
 132                         usb1_ssphy: phy@58200 {
 133                                 reg = <0x00058200 0x130>,     /* Tx */
 134                                       <0x00058400 0x200>,     /* Rx */
 135                                       <0x00058800 0x1f8>,     /* PCS */
 136                                       <0x00058600 0x044>;     /* PCS misc */
 137                                 #phy-cells = <0>;
 138                                 #clock-cells = <0>;
 139                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
 140                                 clock-names = "pipe0";
 141                                 clock-output-names = "usb3phy_1_cc_pipe_clk";
 142                         };
 143                 };
 144
 145                 qusb_phy_1: phy@59000 {
 146                         compatible = "qcom,ipq8074-qusb2-phy";
 147                         reg = <0x00059000 0x180>;
 148                         #phy-cells = <0>;
 149
 150                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 151                                  <&xo>;
 152                         clock-names = "cfg_ahb", "ref";
 153
 154                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 155                         status = "disabled";
 156                 };
 157
 158                 ssphy_0: phy@78000 {
 159                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 160                         reg = <0x00078000 0x1c4>;
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges;
 164
 165                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 166                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 167                                 <&xo>;
 168                         clock-names = "aux", "cfg_ahb", "ref";
 169
 170                         resets = <&gcc GCC_USB0_PHY_BCR>,
 171                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
 172                         reset-names = "phy","common";
 173                         status = "disabled";
 174
 175                         usb0_ssphy: phy@78200 {
 176                                 reg = <0x00078200 0x130>,     /* Tx */
 177                                       <0x00078400 0x200>,     /* Rx */
 178                                       <0x00078800 0x1f8>,     /* PCS */
 179                                       <0x00078600 0x044>;     /* PCS misc */
 180                                 #phy-cells = <0>;
 181                                 #clock-cells = <0>;
 182                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 183                                 clock-names = "pipe0";
 184                                 clock-output-names = "usb3phy_0_cc_pipe_clk";
 185                         };
 186                 };
 187
 188                 qusb_phy_0: phy@79000 {
 189                         compatible = "qcom,ipq8074-qusb2-phy";
 190                         reg = <0x00079000 0x180>;
 191                         #phy-cells = <0>;
 192
 193                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 194                                  <&xo>;
 195                         clock-names = "cfg_ahb", "ref";
 196
 197                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 198                         status = "disabled";
 199                 };
 200
 201                 pcie_qmp0: phy@84000 {
 202                         compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
 203                         reg = <0x00084000 0x1bc>;
 204                         #address-cells = <1>;
 205                         #size-cells = <1>;
 206                         ranges;
 207
 208                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 209                                 <&gcc GCC_PCIE0_AHB_CLK>;
 210                         clock-names = "aux", "cfg_ahb";
 211                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 212                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 213                         reset-names = "phy",
 214                                       "common";
 215                         status = "disabled";
 216
 217                         pcie_phy0: phy@84200 {
 218                                 reg = <0x84200 0x16c>,
 219                                       <0x84400 0x200>,
 220                                       <0x84800 0x1f0>,
 221                                       <0x84c00 0xf4>;
 222                                 #phy-cells = <0>;
 223                                 #clock-cells = <0>;
 224                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 225                                 clock-names = "pipe0";
 226                                 clock-output-names = "pcie20_phy0_pipe_clk";
 227                         };
 228                 };
 229
 230                 pcie_qmp1: phy@8e000 {
 231                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 232                         reg = <0x0008e000 0x1c4>;
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                         ranges;
 236
 237                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
 238                                 <&gcc GCC_PCIE1_AHB_CLK>;
 239                         clock-names = "aux", "cfg_ahb";
 240                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 241                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
 242                         reset-names = "phy",
 243                                       "common";
 244                         status = "disabled";
 245
 246                         pcie_phy1: phy@8e200 {
 247                                 reg = <0x8e200 0x130>,
 248                                       <0x8e400 0x200>,
 249                                       <0x8e800 0x1f8>;
 250                                 #phy-cells = <0>;
 251                                 #clock-cells = <0>;
 252                                 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 253                                 clock-names = "pipe0";
 254                                 clock-output-names = "pcie20_phy1_pipe_clk";
 255                         };
 256                 };
 257
 258                 mdio: mdio@90000 {
 259                         compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
 260                         reg = <0x00090000 0x64>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263
 264                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 265                         clock-names = "gcc_mdio_ahb_clk";
 266
 267                         status = "disabled";
 268                 };
 269
 270                 qfprom: efuse@a4000 {
 271                         compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
 272                         reg = <0x000a4000 0x2000>;
 273                         #address-cells = <1>;
 274                         #size-cells = <1>;
 275                 };
 276
 277                 prng: rng@e3000 {
 278                         compatible = "qcom,prng-ee";
 279                         reg = <0x000e3000 0x1000>;
 280                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 281                         clock-names = "core";
 282                         status = "disabled";
 283                 };
 284
 285                 tsens: thermal-sensor@4a9000 {
 286                         compatible = "qcom,ipq8074-tsens";
 287                         reg = <0x4a9000 0x1000>, /* TM */
 288                               <0x4a8000 0x1000>; /* SROT */
 289                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 290                         interrupt-names = "combined";
 291                         #qcom,sensors = <16>;
 292                         #thermal-sensor-cells = <1>;
 293                 };
 294
 295                 cryptobam: dma-controller@704000 {
 296                         compatible = "qcom,bam-v1.7.0";
 297                         reg = <0x00704000 0x20000>;
 298                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 300                         clock-names = "bam_clk";
 301                         #dma-cells = <1>;
 302                         qcom,ee = <1>;
 303                         qcom,controlled-remotely;
 304                         status = "disabled";
 305                 };
 306
 307                 crypto: crypto@73a000 {
 308                         compatible = "qcom,crypto-v5.1";
 309                         reg = <0x0073a000 0x6000>;
 310                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 311                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 312                                  <&gcc GCC_CRYPTO_CLK>;
 313                         clock-names = "iface", "bus", "core";
 314                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 315                         dma-names = "rx", "tx";
 316                         status = "disabled";
 317                 };
 318
 319                 tlmm: pinctrl@1000000 {
 320                         compatible = "qcom,ipq8074-pinctrl";
 321                         reg = <0x01000000 0x300000>;
 322                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 323                         gpio-controller;
 324                         gpio-ranges = <&tlmm 0 0 70>;
 325                         #gpio-cells = <2>;
 326                         interrupt-controller;
 327                         #interrupt-cells = <2>;
 328
 329                         serial_4_pins: serial4-state {
 330                                 pins = "gpio23", "gpio24";
 331                                 function = "blsp4_uart1";
 332                                 drive-strength = <8>;
 333                                 bias-disable;
 334                         };
 335
 336                         i2c_0_pins: i2c-0-state {
 337                                 pins = "gpio42", "gpio43";
 338                                 function = "blsp1_i2c";
 339                                 drive-strength = <8>;
 340                                 bias-disable;
 341                         };
 342
 343                         spi_0_pins: spi-0-state {
 344                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 345                                 function = "blsp0_spi";
 346                                 drive-strength = <8>;
 347                                 bias-disable;
 348                         };
 349
 350                         hsuart_pins: hsuart-state {
 351                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 352                                 function = "blsp2_uart";
 353                                 drive-strength = <8>;
 354                                 bias-disable;
 355                         };
 356
 357                         qpic_pins: qpic-state {
 358                                 pins = "gpio1", "gpio3", "gpio4",
 359                                        "gpio5", "gpio6", "gpio7",
 360                                        "gpio8", "gpio10", "gpio11",
 361                                        "gpio12", "gpio13", "gpio14",
 362                                        "gpio15", "gpio16", "gpio17";
 363                                 function = "qpic";
 364                                 drive-strength = <8>;
 365                                 bias-disable;
 366                         };
 367                 };
 368
 369                 gcc: gcc@1800000 {
 370                         compatible = "qcom,gcc-ipq8074";
 371                         reg = <0x01800000 0x80000>;
 372                         clocks = <&xo>, <&sleep_clk>;
 373                         clock-names = "xo", "sleep_clk";
 374                         #clock-cells = <1>;
 375                         #power-domain-cells = <1>;
 376                         #reset-cells = <1>;
 377                 };
 378
 379                 tcsr_mutex: hwlock@1905000 {
 380                         compatible = "qcom,tcsr-mutex";
 381                         reg = <0x01905000 0x20000>;
 382                         #hwlock-cells = <1>;
 383                 };
 384
 385                 tcsr: syscon@1937000 {
 386                         compatible = "qcom,tcsr-ipq8074", "syscon";
 387                         reg = <0x01937000 0x21000>;
 388                 };
 389
 390                 spmi_bus: spmi@200f000 {
 391                         compatible = "qcom,spmi-pmic-arb";
 392                         reg = <0x0200f000 0x001000>,
 393                               <0x02400000 0x800000>,
 394                               <0x02c00000 0x800000>,
 395                               <0x03800000 0x200000>,
 396                               <0x0200a000 0x000700>;
 397                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 398                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 399                         interrupt-names = "periph_irq";
 400                         qcom,ee = <0>;
 401                         qcom,channel = <0>;
 402                         #address-cells = <2>;
 403                         #size-cells = <0>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <4>;
 406                 };
 407
 408                 sdhc_1: mmc@7824900 {
 409                         compatible = "qcom,sdhci-msm-v4";
 410                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 411                         reg-names = "hc", "core";
 412
 413                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 414                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 415                         interrupt-names = "hc_irq", "pwr_irq";
 416
 417                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 418                                  <&gcc GCC_SDCC1_APPS_CLK>,
 419                                  <&xo>;
 420                         clock-names = "iface", "core", "xo";
 421                         resets = <&gcc GCC_SDCC1_BCR>;
 422                         max-frequency = <384000000>;
 423                         mmc-ddr-1_8v;
 424                         mmc-hs200-1_8v;
 425                         mmc-hs400-1_8v;
 426                         bus-width = <8>;
 427
 428                         status = "disabled";
 429                 };
 430
 431                 blsp_dma: dma-controller@7884000 {
 432                         compatible = "qcom,bam-v1.7.0";
 433                         reg = <0x07884000 0x2b000>;
 434                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 436                         clock-names = "bam_clk";
 437                         #dma-cells = <1>;
 438                         qcom,ee = <0>;
 439                 };
 440
 441                 blsp1_uart1: serial@78af000 {
 442                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 443                         reg = <0x078af000 0x200>;
 444                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 446                                  <&gcc GCC_BLSP1_AHB_CLK>;
 447                         clock-names = "core", "iface";
 448                         status = "disabled";
 449                 };
 450
 451                 blsp1_uart3: serial@78b1000 {
 452                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 453                         reg = <0x078b1000 0x200>;
 454                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 456                                 <&gcc GCC_BLSP1_AHB_CLK>;
 457                         clock-names = "core", "iface";
 458                         dmas = <&blsp_dma 4>,
 459                                 <&blsp_dma 5>;
 460                         dma-names = "tx", "rx";
 461                         pinctrl-0 = <&hsuart_pins>;
 462                         pinctrl-names = "default";
 463                         status = "disabled";
 464                 };
 465
 466                 blsp1_uart5: serial@78b3000 {
 467                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 468                         reg = <0x078b3000 0x200>;
 469                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 471                                  <&gcc GCC_BLSP1_AHB_CLK>;
 472                         clock-names = "core", "iface";
 473                         pinctrl-0 = <&serial_4_pins>;
 474                         pinctrl-names = "default";
 475                         status = "disabled";
 476                 };
 477
 478                 blsp1_spi1: spi@78b5000 {
 479                         compatible = "qcom,spi-qup-v2.2.1";
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         reg = <0x078b5000 0x600>;
 483                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 484                         spi-max-frequency = <50000000>;
 485                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 486                                 <&gcc GCC_BLSP1_AHB_CLK>;
 487                         clock-names = "core", "iface";
 488                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 489                         dma-names = "tx", "rx";
 490                         pinctrl-0 = <&spi_0_pins>;
 491                         pinctrl-names = "default";
 492                         status = "disabled";
 493                 };
 494
 495                 blsp1_i2c2: i2c@78b6000 {
 496                         compatible = "qcom,i2c-qup-v2.2.1";
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         reg = <0x078b6000 0x600>;
 500                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 502                                  <&gcc GCC_BLSP1_AHB_CLK>;
 503                         clock-names = "core", "iface";
 504                         clock-frequency = <400000>;
 505                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 506                         dma-names = "tx", "rx";
 507                         pinctrl-0 = <&i2c_0_pins>;
 508                         pinctrl-names = "default";
 509                         status = "disabled";
 510                 };
 511
 512                 blsp1_i2c3: i2c@78b7000 {
 513                         compatible = "qcom,i2c-qup-v2.2.1";
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         reg = <0x078b7000 0x600>;
 517                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 518                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 519                                  <&gcc GCC_BLSP1_AHB_CLK>;
 520                         clock-names = "core", "iface";
 521                         clock-frequency = <100000>;
 522                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 523                         dma-names = "tx", "rx";
 524                         status = "disabled";
 525                 };
 526
 527                 blsp1_i2c5: i2c@78b9000 {
 528                         compatible = "qcom,i2c-qup-v2.2.1";
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         reg = <0x78b9000 0x600>;
 532                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 534                                  <&gcc GCC_BLSP1_AHB_CLK>;
 535                         clock-names = "core", "iface";
 536                         clock-frequency = <400000>;
 537                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 538                         dma-names = "tx", "rx";
 539                         status = "disabled";
 540                 };
 541
 542                 blsp1_spi5: spi@78b9000 {
 543                         compatible = "qcom,spi-qup-v2.2.1";
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         reg = <0x78b9000 0x600>;
 547                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 549                                  <&gcc GCC_BLSP1_AHB_CLK>;
 550                         clock-names = "core", "iface";
 551                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 552                         dma-names = "tx", "rx";
 553                         status = "disabled";
 554                 };
 555
 556                 blsp1_i2c6: i2c@78ba000 {
 557                         compatible = "qcom,i2c-qup-v2.2.1";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         reg = <0x078ba000 0x600>;
 561                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 563                                  <&gcc GCC_BLSP1_AHB_CLK>;
 564                         clock-names = "core", "iface";
 565                         clock-frequency = <100000>;
 566                         dmas = <&blsp_dma 22>, <&blsp_dma 23>;
 567                         dma-names = "tx", "rx";
 568                         status = "disabled";
 569                 };
 570
 571                 qpic_bam: dma-controller@7984000 {
 572                         compatible = "qcom,bam-v1.7.0";
 573                         reg = <0x07984000 0x1a000>;
 574                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 576                         clock-names = "bam_clk";
 577                         #dma-cells = <1>;
 578                         qcom,ee = <0>;
 579                         status = "disabled";
 580                 };
 581
 582                 qpic_nand: nand-controller@79b0000 {
 583                         compatible = "qcom,ipq8074-nand";
 584                         reg = <0x079b0000 0x10000>;
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         clocks = <&gcc GCC_QPIC_CLK>,
 588                                  <&gcc GCC_QPIC_AHB_CLK>;
 589                         clock-names = "core", "aon";
 590
 591                         dmas = <&qpic_bam 0>,
 592                                <&qpic_bam 1>,
 593                                <&qpic_bam 2>;
 594                         dma-names = "tx", "rx", "cmd";
 595                         pinctrl-0 = <&qpic_pins>;
 596                         pinctrl-names = "default";
 597                         status = "disabled";
 598                 };
 599
 600                 usb_0: usb@8af8800 {
 601                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 602                         reg = <0x08af8800 0x400>;
 603                         #address-cells = <1>;
 604                         #size-cells = <1>;
 605                         ranges;
 606
 607                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 608                                 <&gcc GCC_USB0_MASTER_CLK>,
 609                                 <&gcc GCC_USB0_SLEEP_CLK>,
 610                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 611                         clock-names = "cfg_noc",
 612                                 "core",
 613                                 "sleep",
 614                                 "mock_utmi";
 615
 616                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 617                                           <&gcc GCC_USB0_MASTER_CLK>,
 618                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 619                         assigned-clock-rates = <133330000>,
 620                                                 <133330000>,
 621                                                 <19200000>;
 622
 623                         power-domains = <&gcc USB0_GDSC>;
 624
 625                         resets = <&gcc GCC_USB0_BCR>;
 626                         status = "disabled";
 627
 628                         dwc_0: usb@8a00000 {
 629                                 compatible = "snps,dwc3";
 630                                 reg = <0x8a00000 0xcd00>;
 631                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 632                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 633                                 phy-names = "usb2-phy", "usb3-phy";
 634                                 snps,is-utmi-l1-suspend;
 635                                 snps,hird-threshold = /bits/ 8 <0x0>;
 636                                 snps,dis_u2_susphy_quirk;
 637                                 snps,dis_u3_susphy_quirk;
 638                                 dr_mode = "host";
 639                         };
 640                 };
 641
 642                 usb_1: usb@8cf8800 {
 643                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 644                         reg = <0x08cf8800 0x400>;
 645                         #address-cells = <1>;
 646                         #size-cells = <1>;
 647                         ranges;
 648
 649                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 650                                 <&gcc GCC_USB1_MASTER_CLK>,
 651                                 <&gcc GCC_USB1_SLEEP_CLK>,
 652                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 653                         clock-names = "cfg_noc",
 654                                 "core",
 655                                 "sleep",
 656                                 "mock_utmi";
 657
 658                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 659                                           <&gcc GCC_USB1_MASTER_CLK>,
 660                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 661                         assigned-clock-rates = <133330000>,
 662                                                 <133330000>,
 663                                                 <19200000>;
 664
 665                         power-domains = <&gcc USB1_GDSC>;
 666
 667                         resets = <&gcc GCC_USB1_BCR>;
 668                         status = "disabled";
 669
 670                         dwc_1: usb@8c00000 {
 671                                 compatible = "snps,dwc3";
 672                                 reg = <0x8c00000 0xcd00>;
 673                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 674                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
 675                                 phy-names = "usb2-phy", "usb3-phy";
 676                                 snps,is-utmi-l1-suspend;
 677                                 snps,hird-threshold = /bits/ 8 <0x0>;
 678                                 snps,dis_u2_susphy_quirk;
 679                                 snps,dis_u3_susphy_quirk;
 680                                 dr_mode = "host";
 681                         };
 682                 };
 683
 684                 intc: interrupt-controller@b000000 {
 685                         compatible = "qcom,msm-qgic2";
 686                         #address-cells = <1>;
 687                         #size-cells = <1>;
 688                         interrupt-controller;
 689                         #interrupt-cells = <3>;
 690                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 691                         ranges = <0 0xb00a000 0xffd>;
 692
 693                         v2m@0 {
 694                                 compatible = "arm,gic-v2m-frame";
 695                                 msi-controller;
 696                                 reg = <0x0 0xffd>;
 697                         };
 698                 };
 699
 700                 watchdog: watchdog@b017000 {
 701                         compatible = "qcom,kpss-wdt";
 702                         reg = <0xb017000 0x1000>;
 703                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 704                         clocks = <&sleep_clk>;
 705                         timeout-sec = <30>;
 706                 };
 707
 708                 apcs_glb: mailbox@b111000 {
 709                         compatible = "qcom,ipq8074-apcs-apps-global",
 710                                      "qcom,ipq6018-apcs-apps-global";
 711                         reg = <0x0b111000 0x1000>;
 712                         clocks = <&a53pll>, <&xo>;
 713                         clock-names = "pll", "xo";
 714
 715                         #clock-cells = <1>;
 716                         #mbox-cells = <1>;
 717                 };
 718
 719                 a53pll: clock@b116000 {
 720                         compatible = "qcom,ipq8074-a53pll";
 721                         reg = <0x0b116000 0x40>;
 722                         #clock-cells = <0>;
 723                         clocks = <&xo>;
 724                         clock-names = "xo";
 725                 };
 726
 727                 timer@b120000 {
 728                         #address-cells = <1>;
 729                         #size-cells = <1>;
 730                         ranges;
 731                         compatible = "arm,armv7-timer-mem";
 732                         reg = <0x0b120000 0x1000>;
 733
 734                         frame@b120000 {
 735                                 frame-number = <0>;
 736                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 737                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 738                                 reg = <0x0b121000 0x1000>,
 739                                       <0x0b122000 0x1000>;
 740                         };
 741
 742                         frame@b123000 {
 743                                 frame-number = <1>;
 744                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 745                                 reg = <0x0b123000 0x1000>;
 746                                 status = "disabled";
 747                         };
 748
 749                         frame@b124000 {
 750                                 frame-number = <2>;
 751                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 752                                 reg = <0x0b124000 0x1000>;
 753                                 status = "disabled";
 754                         };
 755
 756                         frame@b125000 {
 757                                 frame-number = <3>;
 758                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 759                                 reg = <0x0b125000 0x1000>;
 760                                 status = "disabled";
 761                         };
 762
 763                         frame@b126000 {
 764                                 frame-number = <4>;
 765                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 766                                 reg = <0x0b126000 0x1000>;
 767                                 status = "disabled";
 768                         };
 769
 770                         frame@b127000 {
 771                                 frame-number = <5>;
 772                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 773                                 reg = <0x0b127000 0x1000>;
 774                                 status = "disabled";
 775                         };
 776
 777                         frame@b128000 {
 778                                 frame-number = <6>;
 779                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 780                                 reg = <0x0b128000 0x1000>;
 781                                 status = "disabled";
 782                         };
 783                 };
 784
 785                 pcie1: pci@10000000 {
 786                         compatible = "qcom,pcie-ipq8074";
 787                         reg =  <0x10000000 0xf1d>,
 788                                <0x10000f20 0xa8>,
 789                                <0x00088000 0x2000>,
 790                                <0x10100000 0x1000>;
 791                         reg-names = "dbi", "elbi", "parf", "config";
 792                         device_type = "pci";
 793                         linux,pci-domain = <1>;
 794                         bus-range = <0x00 0xff>;
 795                         num-lanes = <1>;
 796                         max-link-speed = <2>;
 797                         #address-cells = <3>;
 798                         #size-cells = <2>;
 799
 800                         phys = <&pcie_phy1>;
 801                         phy-names = "pciephy";
 802
 803                         ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
 804                                  <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
 805
 806                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 807                         interrupt-names = "msi";
 808                         #interrupt-cells = <1>;
 809                         interrupt-map-mask = <0 0 0 0x7>;
 810                         interrupt-map = <0 0 0 1 &intc 0 142
 811                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 812                                         <0 0 0 2 &intc 0 143
 813                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 814                                         <0 0 0 3 &intc 0 144
 815                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 816                                         <0 0 0 4 &intc 0 145
 817                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 818
 819                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 820                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 821                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 822                                  <&gcc GCC_PCIE1_AHB_CLK>,
 823                                  <&gcc GCC_PCIE1_AUX_CLK>;
 824                         clock-names = "iface",
 825                                       "axi_m",
 826                                       "axi_s",
 827                                       "ahb",
 828                                       "aux";
 829                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 830                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 831                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 832                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 833                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 834                                  <&gcc GCC_PCIE1_AHB_ARES>,
 835                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 836                         reset-names = "pipe",
 837                                       "sleep",
 838                                       "sticky",
 839                                       "axi_m",
 840                                       "axi_s",
 841                                       "ahb",
 842                                       "axi_m_sticky";
 843                         status = "disabled";
 844                 };
 845
 846                 pcie0: pci@20000000 {
 847                         compatible = "qcom,pcie-ipq8074-gen3";
 848                         reg = <0x20000000 0xf1d>,
 849                               <0x20000f20 0xa8>,
 850                               <0x20001000 0x1000>,
 851                               <0x00080000 0x4000>,
 852                               <0x20100000 0x1000>;
 853                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 854                         device_type = "pci";
 855                         linux,pci-domain = <0>;
 856                         bus-range = <0x00 0xff>;
 857                         num-lanes = <1>;
 858                         max-link-speed = <3>;
 859                         #address-cells = <3>;
 860                         #size-cells = <2>;
 861
 862                         phys = <&pcie_phy0>;
 863                         phy-names = "pciephy";
 864
 865                         ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
 866                                  <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
 867
 868                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 869                         interrupt-names = "msi";
 870                         #interrupt-cells = <1>;
 871                         interrupt-map-mask = <0 0 0 0x7>;
 872                         interrupt-map = <0 0 0 1 &intc 0 75
 873                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 874                                         <0 0 0 2 &intc 0 78
 875                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 876                                         <0 0 0 3 &intc 0 79
 877                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 878                                         <0 0 0 4 &intc 0 83
 879                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 880
 881                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 882                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 883                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 884                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 885                                  <&gcc GCC_PCIE0_RCHNG_CLK>;
 886                         clock-names = "iface",
 887                                       "axi_m",
 888                                       "axi_s",
 889                                       "axi_bridge",
 890                                       "rchng";
 891
 892                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 893                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 894                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 895                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 896                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 897                                  <&gcc GCC_PCIE0_AHB_ARES>,
 898                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 899                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 900                         reset-names = "pipe",
 901                                       "sleep",
 902                                       "sticky",
 903                                       "axi_m",
 904                                       "axi_s",
 905                                       "ahb",
 906                                       "axi_m_sticky",
 907                                       "axi_s_sticky";
 908                         status = "disabled";
 909                 };
 910         };
 911
 912         timer {
 913                 compatible = "arm,armv8-timer";
 914                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 915                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 916                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 917                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 918         };
 919
 920         thermal-zones {
 921                 nss-top-thermal {
 922                         polling-delay-passive = <250>;
 923                         polling-delay = <1000>;
 924
 925                         thermal-sensors = <&tsens 4>;
 926                 };
 927
 928                 nss0-thermal {
 929                         polling-delay-passive = <250>;
 930                         polling-delay = <1000>;
 931
 932                         thermal-sensors = <&tsens 5>;
 933                 };
 934
 935                 nss1-thermal {
 936                         polling-delay-passive = <250>;
 937                         polling-delay = <1000>;
 938
 939                         thermal-sensors = <&tsens 6>;
 940                 };
 941
 942                 wcss-phya0-thermal {
 943                         polling-delay-passive = <250>;
 944                         polling-delay = <1000>;
 945
 946                         thermal-sensors = <&tsens 7>;
 947                 };
 948
 949                 wcss-phya1-thermal {
 950                         polling-delay-passive = <250>;
 951                         polling-delay = <1000>;
 952
 953                         thermal-sensors = <&tsens 8>;
 954                 };
 955
 956                 cpu0_thermal: cpu0-thermal {
 957                         polling-delay-passive = <250>;
 958                         polling-delay = <1000>;
 959
 960                         thermal-sensors = <&tsens 9>;
 961                 };
 962
 963                 cpu1_thermal: cpu1-thermal {
 964                         polling-delay-passive = <250>;
 965                         polling-delay = <1000>;
 966
 967                         thermal-sensors = <&tsens 10>;
 968                 };
 969
 970                 cpu2_thermal: cpu2-thermal {
 971                         polling-delay-passive = <250>;
 972                         polling-delay = <1000>;
 973
 974                         thermal-sensors = <&tsens 11>;
 975                 };
 976
 977                 cpu3_thermal: cpu3-thermal {
 978                         polling-delay-passive = <250>;
 979                         polling-delay = <1000>;
 980
 981                         thermal-sensors = <&tsens 12>;
 982                 };
 983
 984                 cluster_thermal: cluster-thermal {
 985                         polling-delay-passive = <250>;
 986                         polling-delay = <1000>;
 987
 988                         thermal-sensors = <&tsens 13>;
 989                 };
 990
 991                 wcss-phyb0-thermal {
 992                         polling-delay-passive = <250>;
 993                         polling-delay = <1000>;
 994
 995                         thermal-sensors = <&tsens 14>;
 996                 };
 997
 998                 wcss-phyb1-thermal {
 999                         polling-delay-passive = <250>;
1000                         polling-delay = <1000>;
1001
1002                         thermal-sensors = <&tsens 15>;
1003                 };
1004         };
1005 };