arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         model = "Qualcomm Technologies, Inc. IPQ8074";
  14         compatible = "qcom,ipq8074";
  15         interrupt-parent = <&intc>;
  16
  17         clocks {
  18                 sleep_clk: sleep_clk {
  19                         compatible = "fixed-clock";
  20                         clock-frequency = <32768>;
  21                         #clock-cells = <0>;
  22                 };
  23
  24                 xo: xo {
  25                         compatible = "fixed-clock";
  26                         clock-frequency = <19200000>;
  27                         #clock-cells = <0>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 CPU0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         reg = <0x0>;
  39                         next-level-cache = <&L2_0>;
  40                         enable-method = "psci";
  41                 };
  42
  43                 CPU1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         enable-method = "psci";
  47                         reg = <0x1>;
  48                         next-level-cache = <&L2_0>;
  49                 };
  50
  51                 CPU2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         enable-method = "psci";
  55                         reg = <0x2>;
  56                         next-level-cache = <&L2_0>;
  57                 };
  58
  59                 CPU3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53";
  62                         enable-method = "psci";
  63                         reg = <0x3>;
  64                         next-level-cache = <&L2_0>;
  65                 };
  66
  67                 L2_0: l2-cache {
  68                         compatible = "cache";
  69                         cache-level = <2>;
  70                         cache-unified;
  71                 };
  72         };
  73
  74         pmu {
  75                 compatible = "arm,cortex-a53-pmu";
  76                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  77         };
  78
  79         psci {
  80                 compatible = "arm,psci-1.0";
  81                 method = "smc";
  82         };
  83
  84         reserved-memory {
  85                 #address-cells = <2>;
  86                 #size-cells = <2>;
  87                 ranges;
  88
  89                 bootloader@4a600000 {
  90                         reg = <0x0 0x4a600000 0x0 0x400000>;
  91                         no-map;
  92                 };
  93
  94                 sbl@4aa00000 {
  95                         reg = <0x0 0x4aa00000 0x0 0x100000>;
  96                         no-map;
  97                 };
  98
  99                 smem@4ab00000 {
 100                         compatible = "qcom,smem";
 101                         reg = <0x0 0x4ab00000 0x0 0x100000>;
 102                         no-map;
 103
 104                         hwlocks = <&tcsr_mutex 0>;
 105                 };
 106
 107                 memory@4ac00000 {
 108                         reg = <0x0 0x4ac00000 0x0 0x400000>;
 109                         no-map;
 110                 };
 111         };
 112
 113         firmware {
 114                 scm {
 115                         compatible = "qcom,scm-ipq8074", "qcom,scm";
 116                         qcom,dload-mode = <&tcsr 0x6100>;
 117                 };
 118         };
 119
 120         soc: soc@0 {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges = <0 0 0 0xffffffff>;
 124                 compatible = "simple-bus";
 125
 126                 ssphy_1: phy@58000 {
 127                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 128                         reg = <0x00058000 0x1c4>;
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131                         ranges;
 132
 133                         clocks = <&gcc GCC_USB1_AUX_CLK>,
 134                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 135                                 <&xo>;
 136                         clock-names = "aux", "cfg_ahb", "ref";
 137
 138                         resets = <&gcc GCC_USB1_PHY_BCR>,
 139                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
 140                         reset-names = "phy","common";
 141                         status = "disabled";
 142
 143                         usb1_ssphy: phy@58200 {
 144                                 reg = <0x00058200 0x130>,     /* Tx */
 145                                       <0x00058400 0x200>,     /* Rx */
 146                                       <0x00058800 0x1f8>,     /* PCS */
 147                                       <0x00058600 0x044>;     /* PCS misc */
 148                                 #phy-cells = <0>;
 149                                 #clock-cells = <0>;
 150                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
 151                                 clock-names = "pipe0";
 152                                 clock-output-names = "usb3phy_1_cc_pipe_clk";
 153                         };
 154                 };
 155
 156                 qusb_phy_1: phy@59000 {
 157                         compatible = "qcom,ipq8074-qusb2-phy";
 158                         reg = <0x00059000 0x180>;
 159                         #phy-cells = <0>;
 160
 161                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 162                                  <&xo>;
 163                         clock-names = "cfg_ahb", "ref";
 164
 165                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 166                         status = "disabled";
 167                 };
 168
 169                 ssphy_0: phy@78000 {
 170                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 171                         reg = <0x00078000 0x1c4>;
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         ranges;
 175
 176                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 177                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 178                                 <&xo>;
 179                         clock-names = "aux", "cfg_ahb", "ref";
 180
 181                         resets = <&gcc GCC_USB0_PHY_BCR>,
 182                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
 183                         reset-names = "phy","common";
 184                         status = "disabled";
 185
 186                         usb0_ssphy: phy@78200 {
 187                                 reg = <0x00078200 0x130>,     /* Tx */
 188                                       <0x00078400 0x200>,     /* Rx */
 189                                       <0x00078800 0x1f8>,     /* PCS */
 190                                       <0x00078600 0x044>;     /* PCS misc */
 191                                 #phy-cells = <0>;
 192                                 #clock-cells = <0>;
 193                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 194                                 clock-names = "pipe0";
 195                                 clock-output-names = "usb3phy_0_cc_pipe_clk";
 196                         };
 197                 };
 198
 199                 qusb_phy_0: phy@79000 {
 200                         compatible = "qcom,ipq8074-qusb2-phy";
 201                         reg = <0x00079000 0x180>;
 202                         #phy-cells = <0>;
 203
 204                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 205                                  <&xo>;
 206                         clock-names = "cfg_ahb", "ref";
 207
 208                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 209                         status = "disabled";
 210                 };
 211
 212                 pcie_qmp0: phy@84000 {
 213                         compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
 214                         reg = <0x00084000 0x1000>;
 215
 216                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 217                                  <&gcc GCC_PCIE0_AHB_CLK>,
 218                                  <&gcc GCC_PCIE0_PIPE_CLK>;
 219                         clock-names = "aux",
 220                                       "cfg_ahb",
 221                                       "pipe";
 222
 223                         clock-output-names = "pcie20_phy0_pipe_clk";
 224                         #clock-cells = <0>;
 225
 226                         #phy-cells = <0>;
 227
 228                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 229                                  <&gcc GCC_PCIE0PHY_PHY_BCR>;
 230                         reset-names = "phy",
 231                                       "common";
 232                         status = "disabled";
 233                 };
 234
 235                 pcie_qmp1: phy@8e000 {
 236                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 237                         reg = <0x0008e000 0x1000>;
 238
 239                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
 240                                  <&gcc GCC_PCIE1_AHB_CLK>,
 241                                  <&gcc GCC_PCIE1_PIPE_CLK>;
 242                         clock-names = "aux",
 243                                       "cfg_ahb",
 244                                       "pipe";
 245
 246                         clock-output-names = "pcie20_phy1_pipe_clk";
 247                         #clock-cells = <0>;
 248
 249                         #phy-cells = <0>;
 250
 251                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 252                                  <&gcc GCC_PCIE1PHY_PHY_BCR>;
 253                         reset-names = "phy",
 254                                       "common";
 255                         status = "disabled";
 256                 };
 257
 258                 mdio: mdio@90000 {
 259                         compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
 260                         reg = <0x00090000 0x64>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263
 264                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 265                         clock-names = "gcc_mdio_ahb_clk";
 266
 267                         status = "disabled";
 268                 };
 269
 270                 qfprom: efuse@a4000 {
 271                         compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
 272                         reg = <0x000a4000 0x2000>;
 273                         #address-cells = <1>;
 274                         #size-cells = <1>;
 275                 };
 276
 277                 prng: rng@e3000 {
 278                         compatible = "qcom,prng-ee";
 279                         reg = <0x000e3000 0x1000>;
 280                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 281                         clock-names = "core";
 282                         status = "disabled";
 283                 };
 284
 285                 tsens: thermal-sensor@4a9000 {
 286                         compatible = "qcom,ipq8074-tsens";
 287                         reg = <0x4a9000 0x1000>, /* TM */
 288                               <0x4a8000 0x1000>; /* SROT */
 289                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 290                         interrupt-names = "combined";
 291                         #qcom,sensors = <16>;
 292                         #thermal-sensor-cells = <1>;
 293                 };
 294
 295                 cryptobam: dma-controller@704000 {
 296                         compatible = "qcom,bam-v1.7.0";
 297                         reg = <0x00704000 0x20000>;
 298                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 300                         clock-names = "bam_clk";
 301                         #dma-cells = <1>;
 302                         qcom,ee = <1>;
 303                         qcom,controlled-remotely;
 304                         status = "disabled";
 305                 };
 306
 307                 crypto: crypto@73a000 {
 308                         compatible = "qcom,crypto-v5.1";
 309                         reg = <0x0073a000 0x6000>;
 310                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 311                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 312                                  <&gcc GCC_CRYPTO_CLK>;
 313                         clock-names = "iface", "bus", "core";
 314                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 315                         dma-names = "rx", "tx";
 316                         status = "disabled";
 317                 };
 318
 319                 tlmm: pinctrl@1000000 {
 320                         compatible = "qcom,ipq8074-pinctrl";
 321                         reg = <0x01000000 0x300000>;
 322                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 323                         gpio-controller;
 324                         gpio-ranges = <&tlmm 0 0 70>;
 325                         #gpio-cells = <2>;
 326                         interrupt-controller;
 327                         #interrupt-cells = <2>;
 328
 329                         serial_4_pins: serial4-state {
 330                                 pins = "gpio23", "gpio24";
 331                                 function = "blsp4_uart1";
 332                                 drive-strength = <8>;
 333                                 bias-disable;
 334                         };
 335
 336                         i2c_0_pins: i2c-0-state {
 337                                 pins = "gpio42", "gpio43";
 338                                 function = "blsp1_i2c";
 339                                 drive-strength = <8>;
 340                                 bias-disable;
 341                         };
 342
 343                         spi_0_pins: spi-0-state {
 344                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 345                                 function = "blsp0_spi";
 346                                 drive-strength = <8>;
 347                                 bias-disable;
 348                         };
 349
 350                         hsuart_pins: hsuart-state {
 351                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 352                                 function = "blsp2_uart";
 353                                 drive-strength = <8>;
 354                                 bias-disable;
 355                         };
 356
 357                         qpic_pins: qpic-state {
 358                                 pins = "gpio1", "gpio3", "gpio4",
 359                                        "gpio5", "gpio6", "gpio7",
 360                                        "gpio8", "gpio10", "gpio11",
 361                                        "gpio12", "gpio13", "gpio14",
 362                                        "gpio15", "gpio16", "gpio17";
 363                                 function = "qpic";
 364                                 drive-strength = <8>;
 365                                 bias-disable;
 366                         };
 367                 };
 368
 369                 gcc: gcc@1800000 {
 370                         compatible = "qcom,gcc-ipq8074";
 371                         reg = <0x01800000 0x80000>;
 372                         clocks = <&xo>, <&sleep_clk>;
 373                         clock-names = "xo", "sleep_clk";
 374                         #clock-cells = <1>;
 375                         #power-domain-cells = <1>;
 376                         #reset-cells = <1>;
 377                 };
 378
 379                 tcsr_mutex: hwlock@1905000 {
 380                         compatible = "qcom,tcsr-mutex";
 381                         reg = <0x01905000 0x20000>;
 382                         #hwlock-cells = <1>;
 383                 };
 384
 385                 tcsr: syscon@1937000 {
 386                         compatible = "qcom,tcsr-ipq8074", "syscon";
 387                         reg = <0x01937000 0x21000>;
 388                 };
 389
 390                 spmi_bus: spmi@200f000 {
 391                         compatible = "qcom,spmi-pmic-arb";
 392                         reg = <0x0200f000 0x001000>,
 393                               <0x02400000 0x800000>,
 394                               <0x02c00000 0x800000>,
 395                               <0x03800000 0x200000>,
 396                               <0x0200a000 0x000700>;
 397                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 398                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 399                         interrupt-names = "periph_irq";
 400                         qcom,ee = <0>;
 401                         qcom,channel = <0>;
 402                         #address-cells = <2>;
 403                         #size-cells = <0>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <4>;
 406                 };
 407
 408                 sdhc_1: mmc@7824900 {
 409                         compatible = "qcom,sdhci-msm-v4";
 410                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 411                         reg-names = "hc", "core";
 412
 413                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 414                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 415                         interrupt-names = "hc_irq", "pwr_irq";
 416
 417                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 418                                  <&gcc GCC_SDCC1_APPS_CLK>,
 419                                  <&xo>;
 420                         clock-names = "iface", "core", "xo";
 421                         resets = <&gcc GCC_SDCC1_BCR>;
 422                         max-frequency = <384000000>;
 423                         mmc-ddr-1_8v;
 424                         mmc-hs200-1_8v;
 425                         mmc-hs400-1_8v;
 426                         bus-width = <8>;
 427
 428                         status = "disabled";
 429                 };
 430
 431                 blsp_dma: dma-controller@7884000 {
 432                         compatible = "qcom,bam-v1.7.0";
 433                         reg = <0x07884000 0x2b000>;
 434                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 436                         clock-names = "bam_clk";
 437                         #dma-cells = <1>;
 438                         qcom,ee = <0>;
 439                 };
 440
 441                 blsp1_uart1: serial@78af000 {
 442                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 443                         reg = <0x078af000 0x200>;
 444                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 446                                  <&gcc GCC_BLSP1_AHB_CLK>;
 447                         clock-names = "core", "iface";
 448                         status = "disabled";
 449                 };
 450
 451                 blsp1_uart3: serial@78b1000 {
 452                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 453                         reg = <0x078b1000 0x200>;
 454                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 456                                 <&gcc GCC_BLSP1_AHB_CLK>;
 457                         clock-names = "core", "iface";
 458                         dmas = <&blsp_dma 4>,
 459                                 <&blsp_dma 5>;
 460                         dma-names = "tx", "rx";
 461                         pinctrl-0 = <&hsuart_pins>;
 462                         pinctrl-names = "default";
 463                         status = "disabled";
 464                 };
 465
 466                 blsp1_uart5: serial@78b3000 {
 467                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 468                         reg = <0x078b3000 0x200>;
 469                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 471                                  <&gcc GCC_BLSP1_AHB_CLK>;
 472                         clock-names = "core", "iface";
 473                         pinctrl-0 = <&serial_4_pins>;
 474                         pinctrl-names = "default";
 475                         status = "disabled";
 476                 };
 477
 478                 blsp1_spi1: spi@78b5000 {
 479                         compatible = "qcom,spi-qup-v2.2.1";
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         reg = <0x078b5000 0x600>;
 483                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 485                                 <&gcc GCC_BLSP1_AHB_CLK>;
 486                         clock-names = "core", "iface";
 487                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 488                         dma-names = "tx", "rx";
 489                         pinctrl-0 = <&spi_0_pins>;
 490                         pinctrl-names = "default";
 491                         status = "disabled";
 492                 };
 493
 494                 blsp1_i2c2: i2c@78b6000 {
 495                         compatible = "qcom,i2c-qup-v2.2.1";
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         reg = <0x078b6000 0x600>;
 499                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 501                                  <&gcc GCC_BLSP1_AHB_CLK>;
 502                         clock-names = "core", "iface";
 503                         clock-frequency = <400000>;
 504                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 505                         dma-names = "tx", "rx";
 506                         pinctrl-0 = <&i2c_0_pins>;
 507                         pinctrl-names = "default";
 508                         status = "disabled";
 509                 };
 510
 511                 blsp1_i2c3: i2c@78b7000 {
 512                         compatible = "qcom,i2c-qup-v2.2.1";
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         reg = <0x078b7000 0x600>;
 516                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 518                                  <&gcc GCC_BLSP1_AHB_CLK>;
 519                         clock-names = "core", "iface";
 520                         clock-frequency = <100000>;
 521                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 522                         dma-names = "tx", "rx";
 523                         status = "disabled";
 524                 };
 525
 526                 blsp1_i2c5: i2c@78b9000 {
 527                         compatible = "qcom,i2c-qup-v2.2.1";
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         reg = <0x78b9000 0x600>;
 531                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 533                                  <&gcc GCC_BLSP1_AHB_CLK>;
 534                         clock-names = "core", "iface";
 535                         clock-frequency = <400000>;
 536                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 537                         dma-names = "tx", "rx";
 538                         status = "disabled";
 539                 };
 540
 541                 blsp1_spi5: spi@78b9000 {
 542                         compatible = "qcom,spi-qup-v2.2.1";
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         reg = <0x78b9000 0x600>;
 546                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 548                                  <&gcc GCC_BLSP1_AHB_CLK>;
 549                         clock-names = "core", "iface";
 550                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 551                         dma-names = "tx", "rx";
 552                         status = "disabled";
 553                 };
 554
 555                 blsp1_i2c6: i2c@78ba000 {
 556                         compatible = "qcom,i2c-qup-v2.2.1";
 557                         #address-cells = <1>;
 558                         #size-cells = <0>;
 559                         reg = <0x078ba000 0x600>;
 560                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 562                                  <&gcc GCC_BLSP1_AHB_CLK>;
 563                         clock-names = "core", "iface";
 564                         clock-frequency = <100000>;
 565                         dmas = <&blsp_dma 22>, <&blsp_dma 23>;
 566                         dma-names = "tx", "rx";
 567                         status = "disabled";
 568                 };
 569
 570                 qpic_bam: dma-controller@7984000 {
 571                         compatible = "qcom,bam-v1.7.0";
 572                         reg = <0x07984000 0x1a000>;
 573                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 575                         clock-names = "bam_clk";
 576                         #dma-cells = <1>;
 577                         qcom,ee = <0>;
 578                         status = "disabled";
 579                 };
 580
 581                 qpic_nand: nand-controller@79b0000 {
 582                         compatible = "qcom,ipq8074-nand";
 583                         reg = <0x079b0000 0x10000>;
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         clocks = <&gcc GCC_QPIC_CLK>,
 587                                  <&gcc GCC_QPIC_AHB_CLK>;
 588                         clock-names = "core", "aon";
 589
 590                         dmas = <&qpic_bam 0>,
 591                                <&qpic_bam 1>,
 592                                <&qpic_bam 2>;
 593                         dma-names = "tx", "rx", "cmd";
 594                         pinctrl-0 = <&qpic_pins>;
 595                         pinctrl-names = "default";
 596                         status = "disabled";
 597                 };
 598
 599                 usb_0: usb@8af8800 {
 600                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 601                         reg = <0x08af8800 0x400>;
 602                         #address-cells = <1>;
 603                         #size-cells = <1>;
 604                         ranges;
 605
 606                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 607                                 <&gcc GCC_USB0_MASTER_CLK>,
 608                                 <&gcc GCC_USB0_SLEEP_CLK>,
 609                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 610                         clock-names = "cfg_noc",
 611                                 "core",
 612                                 "sleep",
 613                                 "mock_utmi";
 614
 615                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 616                                           <&gcc GCC_USB0_MASTER_CLK>,
 617                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 618                         assigned-clock-rates = <133330000>,
 619                                                 <133330000>,
 620                                                 <19200000>;
 621
 622                         power-domains = <&gcc USB0_GDSC>;
 623
 624                         resets = <&gcc GCC_USB0_BCR>;
 625                         status = "disabled";
 626
 627                         dwc_0: usb@8a00000 {
 628                                 compatible = "snps,dwc3";
 629                                 reg = <0x8a00000 0xcd00>;
 630                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 631                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 632                                 phy-names = "usb2-phy", "usb3-phy";
 633                                 snps,is-utmi-l1-suspend;
 634                                 snps,hird-threshold = /bits/ 8 <0x0>;
 635                                 snps,dis_u2_susphy_quirk;
 636                                 snps,dis_u3_susphy_quirk;
 637                                 dr_mode = "host";
 638                         };
 639                 };
 640
 641                 usb_1: usb@8cf8800 {
 642                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 643                         reg = <0x08cf8800 0x400>;
 644                         #address-cells = <1>;
 645                         #size-cells = <1>;
 646                         ranges;
 647
 648                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 649                                 <&gcc GCC_USB1_MASTER_CLK>,
 650                                 <&gcc GCC_USB1_SLEEP_CLK>,
 651                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 652                         clock-names = "cfg_noc",
 653                                 "core",
 654                                 "sleep",
 655                                 "mock_utmi";
 656
 657                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 658                                           <&gcc GCC_USB1_MASTER_CLK>,
 659                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 660                         assigned-clock-rates = <133330000>,
 661                                                 <133330000>,
 662                                                 <19200000>;
 663
 664                         power-domains = <&gcc USB1_GDSC>;
 665
 666                         resets = <&gcc GCC_USB1_BCR>;
 667                         status = "disabled";
 668
 669                         dwc_1: usb@8c00000 {
 670                                 compatible = "snps,dwc3";
 671                                 reg = <0x8c00000 0xcd00>;
 672                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 673                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
 674                                 phy-names = "usb2-phy", "usb3-phy";
 675                                 snps,is-utmi-l1-suspend;
 676                                 snps,hird-threshold = /bits/ 8 <0x0>;
 677                                 snps,dis_u2_susphy_quirk;
 678                                 snps,dis_u3_susphy_quirk;
 679                                 dr_mode = "host";
 680                         };
 681                 };
 682
 683                 intc: interrupt-controller@b000000 {
 684                         compatible = "qcom,msm-qgic2";
 685                         #address-cells = <1>;
 686                         #size-cells = <1>;
 687                         interrupt-controller;
 688                         #interrupt-cells = <3>;
 689                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 690                         ranges = <0 0xb00a000 0xffd>;
 691
 692                         v2m@0 {
 693                                 compatible = "arm,gic-v2m-frame";
 694                                 msi-controller;
 695                                 reg = <0x0 0xffd>;
 696                         };
 697                 };
 698
 699                 watchdog: watchdog@b017000 {
 700                         compatible = "qcom,kpss-wdt";
 701                         reg = <0xb017000 0x1000>;
 702                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 703                         clocks = <&sleep_clk>;
 704                         timeout-sec = <30>;
 705                 };
 706
 707                 apcs_glb: mailbox@b111000 {
 708                         compatible = "qcom,ipq8074-apcs-apps-global",
 709                                      "qcom,ipq6018-apcs-apps-global";
 710                         reg = <0x0b111000 0x1000>;
 711                         clocks = <&a53pll>, <&xo>;
 712                         clock-names = "pll", "xo";
 713
 714                         #clock-cells = <1>;
 715                         #mbox-cells = <1>;
 716                 };
 717
 718                 a53pll: clock@b116000 {
 719                         compatible = "qcom,ipq8074-a53pll";
 720                         reg = <0x0b116000 0x40>;
 721                         #clock-cells = <0>;
 722                         clocks = <&xo>;
 723                         clock-names = "xo";
 724                 };
 725
 726                 timer@b120000 {
 727                         #address-cells = <1>;
 728                         #size-cells = <1>;
 729                         ranges;
 730                         compatible = "arm,armv7-timer-mem";
 731                         reg = <0x0b120000 0x1000>;
 732
 733                         frame@b120000 {
 734                                 frame-number = <0>;
 735                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 736                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 737                                 reg = <0x0b121000 0x1000>,
 738                                       <0x0b122000 0x1000>;
 739                         };
 740
 741                         frame@b123000 {
 742                                 frame-number = <1>;
 743                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 744                                 reg = <0x0b123000 0x1000>;
 745                                 status = "disabled";
 746                         };
 747
 748                         frame@b124000 {
 749                                 frame-number = <2>;
 750                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 751                                 reg = <0x0b124000 0x1000>;
 752                                 status = "disabled";
 753                         };
 754
 755                         frame@b125000 {
 756                                 frame-number = <3>;
 757                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 758                                 reg = <0x0b125000 0x1000>;
 759                                 status = "disabled";
 760                         };
 761
 762                         frame@b126000 {
 763                                 frame-number = <4>;
 764                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 765                                 reg = <0x0b126000 0x1000>;
 766                                 status = "disabled";
 767                         };
 768
 769                         frame@b127000 {
 770                                 frame-number = <5>;
 771                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 772                                 reg = <0x0b127000 0x1000>;
 773                                 status = "disabled";
 774                         };
 775
 776                         frame@b128000 {
 777                                 frame-number = <6>;
 778                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 779                                 reg = <0x0b128000 0x1000>;
 780                                 status = "disabled";
 781                         };
 782                 };
 783
 784                 pcie1: pci@10000000 {
 785                         compatible = "qcom,pcie-ipq8074";
 786                         reg = <0x10000000 0xf1d>,
 787                               <0x10000f20 0xa8>,
 788                               <0x00088000 0x2000>,
 789                               <0x10100000 0x1000>;
 790                         reg-names = "dbi", "elbi", "parf", "config";
 791                         device_type = "pci";
 792                         linux,pci-domain = <1>;
 793                         bus-range = <0x00 0xff>;
 794                         num-lanes = <1>;
 795                         max-link-speed = <2>;
 796                         #address-cells = <3>;
 797                         #size-cells = <2>;
 798
 799                         phys = <&pcie_qmp1>;
 800                         phy-names = "pciephy";
 801
 802                         ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
 803                                  <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
 804
 805                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 806                         interrupt-names = "msi";
 807                         #interrupt-cells = <1>;
 808                         interrupt-map-mask = <0 0 0 0x7>;
 809                         interrupt-map = <0 0 0 1 &intc 0 142
 810                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 811                                         <0 0 0 2 &intc 0 143
 812                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 813                                         <0 0 0 3 &intc 0 144
 814                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 815                                         <0 0 0 4 &intc 0 145
 816                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 817
 818                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 819                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 820                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 821                                  <&gcc GCC_PCIE1_AHB_CLK>,
 822                                  <&gcc GCC_PCIE1_AUX_CLK>;
 823                         clock-names = "iface",
 824                                       "axi_m",
 825                                       "axi_s",
 826                                       "ahb",
 827                                       "aux";
 828                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 829                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 830                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 831                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 832                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 833                                  <&gcc GCC_PCIE1_AHB_ARES>,
 834                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 835                         reset-names = "pipe",
 836                                       "sleep",
 837                                       "sticky",
 838                                       "axi_m",
 839                                       "axi_s",
 840                                       "ahb",
 841                                       "axi_m_sticky";
 842                         status = "disabled";
 843                 };
 844
 845                 pcie0: pci@20000000 {
 846                         compatible = "qcom,pcie-ipq8074-gen3";
 847                         reg = <0x20000000 0xf1d>,
 848                               <0x20000f20 0xa8>,
 849                               <0x20001000 0x1000>,
 850                               <0x00080000 0x4000>,
 851                               <0x20100000 0x1000>;
 852                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 853                         device_type = "pci";
 854                         linux,pci-domain = <0>;
 855                         bus-range = <0x00 0xff>;
 856                         num-lanes = <1>;
 857                         max-link-speed = <3>;
 858                         #address-cells = <3>;
 859                         #size-cells = <2>;
 860
 861                         phys = <&pcie_qmp0>;
 862                         phy-names = "pciephy";
 863
 864                         ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
 865                                  <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
 866
 867                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 868                         interrupt-names = "msi";
 869                         #interrupt-cells = <1>;
 870                         interrupt-map-mask = <0 0 0 0x7>;
 871                         interrupt-map = <0 0 0 1 &intc 0 75
 872                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 873                                         <0 0 0 2 &intc 0 78
 874                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 875                                         <0 0 0 3 &intc 0 79
 876                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 877                                         <0 0 0 4 &intc 0 83
 878                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 879
 880                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 881                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 882                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 883                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 884                                  <&gcc GCC_PCIE0_RCHNG_CLK>;
 885                         clock-names = "iface",
 886                                       "axi_m",
 887                                       "axi_s",
 888                                       "axi_bridge",
 889                                       "rchng";
 890
 891                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 892                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 893                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 894                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 895                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 896                                  <&gcc GCC_PCIE0_AHB_ARES>,
 897                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 898                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 899                         reset-names = "pipe",
 900                                       "sleep",
 901                                       "sticky",
 902                                       "axi_m",
 903                                       "axi_s",
 904                                       "ahb",
 905                                       "axi_m_sticky",
 906                                       "axi_s_sticky";
 907                         status = "disabled";
 908                 };
 909         };
 910
 911         timer {
 912                 compatible = "arm,armv8-timer";
 913                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 914                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 915                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 916                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 917         };
 918
 919         thermal-zones {
 920                 nss-top-thermal {
 921                         polling-delay-passive = <250>;
 922                         polling-delay = <1000>;
 923
 924                         thermal-sensors = <&tsens 4>;
 925
 926                         trips {
 927                                 nss-top-crit {
 928                                         temperature = <110000>;
 929                                         hysteresis = <1000>;
 930                                         type = "critical";
 931                                 };
 932                         };
 933                 };
 934
 935                 nss0-thermal {
 936                         polling-delay-passive = <250>;
 937                         polling-delay = <1000>;
 938
 939                         thermal-sensors = <&tsens 5>;
 940
 941                         trips {
 942                                 nss-0-crit {
 943                                         temperature = <110000>;
 944                                         hysteresis = <1000>;
 945                                         type = "critical";
 946                                 };
 947                         };
 948                 };
 949
 950                 nss1-thermal {
 951                         polling-delay-passive = <250>;
 952                         polling-delay = <1000>;
 953
 954                         thermal-sensors = <&tsens 6>;
 955
 956                         trips {
 957                                 nss-1-crit {
 958                                         temperature = <110000>;
 959                                         hysteresis = <1000>;
 960                                         type = "critical";
 961                                 };
 962                         };
 963                 };
 964
 965                 wcss-phya0-thermal {
 966                         polling-delay-passive = <250>;
 967                         polling-delay = <1000>;
 968
 969                         thermal-sensors = <&tsens 7>;
 970
 971                         trips {
 972                                 wcss-phya0-crit {
 973                                         temperature = <110000>;
 974                                         hysteresis = <1000>;
 975                                         type = "critical";
 976                                 };
 977                         };
 978                 };
 979
 980                 wcss-phya1-thermal {
 981                         polling-delay-passive = <250>;
 982                         polling-delay = <1000>;
 983
 984                         thermal-sensors = <&tsens 8>;
 985
 986                         trips {
 987                                 wcss-phya1-crit {
 988                                         temperature = <110000>;
 989                                         hysteresis = <1000>;
 990                                         type = "critical";
 991                                 };
 992                         };
 993                 };
 994
 995                 cpu0_thermal: cpu0-thermal {
 996                         polling-delay-passive = <250>;
 997                         polling-delay = <1000>;
 998
 999                         thermal-sensors = <&tsens 9>;
1000
1001                         trips {
1002                                 cpu0-crit {
1003                                         temperature = <110000>;
1004                                         hysteresis = <1000>;
1005                                         type = "critical";
1006                                 };
1007                         };
1008                 };
1009
1010                 cpu1_thermal: cpu1-thermal {
1011                         polling-delay-passive = <250>;
1012                         polling-delay = <1000>;
1013
1014                         thermal-sensors = <&tsens 10>;
1015
1016                         trips {
1017                                 cpu1-crit {
1018                                         temperature = <110000>;
1019                                         hysteresis = <1000>;
1020                                         type = "critical";
1021                                 };
1022                         };
1023                 };
1024
1025                 cpu2_thermal: cpu2-thermal {
1026                         polling-delay-passive = <250>;
1027                         polling-delay = <1000>;
1028
1029                         thermal-sensors = <&tsens 11>;
1030
1031                         trips {
1032                                 cpu2-crit {
1033                                         temperature = <110000>;
1034                                         hysteresis = <1000>;
1035                                         type = "critical";
1036                                 };
1037                         };
1038                 };
1039
1040                 cpu3_thermal: cpu3-thermal {
1041                         polling-delay-passive = <250>;
1042                         polling-delay = <1000>;
1043
1044                         thermal-sensors = <&tsens 12>;
1045
1046                         trips {
1047                                 cpu3-crit {
1048                                         temperature = <110000>;
1049                                         hysteresis = <1000>;
1050                                         type = "critical";
1051                                 };
1052                         };
1053                 };
1054
1055                 cluster_thermal: cluster-thermal {
1056                         polling-delay-passive = <250>;
1057                         polling-delay = <1000>;
1058
1059                         thermal-sensors = <&tsens 13>;
1060
1061                         trips {
1062                                 cluster-crit {
1063                                         temperature = <110000>;
1064                                         hysteresis = <1000>;
1065                                         type = "critical";
1066                                 };
1067                         };
1068                 };
1069
1070                 wcss-phyb0-thermal {
1071                         polling-delay-passive = <250>;
1072                         polling-delay = <1000>;
1073
1074                         thermal-sensors = <&tsens 14>;
1075
1076                         trips {
1077                                 wcss-phyb0-crit {
1078                                         temperature = <110000>;
1079                                         hysteresis = <1000>;
1080                                         type = "critical";
1081                                 };
1082                         };
1083                 };
1084
1085                 wcss-phyb1-thermal {
1086                         polling-delay-passive = <250>;
1087                         polling-delay = <1000>;
1088
1089                         thermal-sensors = <&tsens 15>;
1090
1091                         trips {
1092                                 wcss-phyb1-crit {
1093                                         temperature = <110000>;
1094                                         hysteresis = <1000>;
1095                                         type = "critical";
1096                                 };
1097                         };
1098                 };
1099         };
1100 };