arch/arm64/boot/dts/qcom/ipq6018.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * IPQ6018 SoC device tree source
   4  *
   5  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  11 #include <dt-bindings/clock/qcom,apss-ipq.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&intc>;
  17
  18         clocks {
  19                 sleep_clk: sleep-clk {
  20                         compatible = "fixed-clock";
  21                         clock-frequency = <32000>;
  22                         #clock-cells = <0>;
  23                 };
  24
  25                 xo: xo {
  26                         compatible = "fixed-clock";
  27                         clock-frequency = <24000000>;
  28                         #clock-cells = <0>;
  29                 };
  30         };
  31
  32         cpus: cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 CPU0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         reg = <0x0>;
  40                         enable-method = "psci";
  41                         next-level-cache = <&L2_0>;
  42                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  43                         clock-names = "cpu";
  44                         operating-points-v2 = <&cpu_opp_table>;
  45                         cpu-supply = <&ipq6018_s2>;
  46                 };
  47
  48                 CPU1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         enable-method = "psci";
  52                         reg = <0x1>;
  53                         next-level-cache = <&L2_0>;
  54                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  55                         clock-names = "cpu";
  56                         operating-points-v2 = <&cpu_opp_table>;
  57                         cpu-supply = <&ipq6018_s2>;
  58                 };
  59
  60                 CPU2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         enable-method = "psci";
  64                         reg = <0x2>;
  65                         next-level-cache = <&L2_0>;
  66                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  67                         clock-names = "cpu";
  68                         operating-points-v2 = <&cpu_opp_table>;
  69                         cpu-supply = <&ipq6018_s2>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         enable-method = "psci";
  76                         reg = <0x3>;
  77                         next-level-cache = <&L2_0>;
  78                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  79                         clock-names = "cpu";
  80                         operating-points-v2 = <&cpu_opp_table>;
  81                         cpu-supply = <&ipq6018_s2>;
  82                 };
  83
  84                 L2_0: l2-cache {
  85                         compatible = "cache";
  86                         cache-level = <0x2>;
  87                 };
  88         };
  89
  90         firmware {
  91                 scm {
  92                         compatible = "qcom,scm-ipq6018", "qcom,scm";
  93                 };
  94         };
  95
  96         cpu_opp_table: opp-table-cpu {
  97                 compatible = "operating-points-v2";
  98                 opp-shared;
  99
 100                 opp-864000000 {
 101                         opp-hz = /bits/ 64 <864000000>;
 102                         opp-microvolt = <725000>;
 103                         clock-latency-ns = <200000>;
 104                 };
 105
 106                 opp-1056000000 {
 107                         opp-hz = /bits/ 64 <1056000000>;
 108                         opp-microvolt = <787500>;
 109                         clock-latency-ns = <200000>;
 110                 };
 111
 112                 opp-1320000000 {
 113                         opp-hz = /bits/ 64 <1320000000>;
 114                         opp-microvolt = <862500>;
 115                         clock-latency-ns = <200000>;
 116                 };
 117
 118                 opp-1440000000 {
 119                         opp-hz = /bits/ 64 <1440000000>;
 120                         opp-microvolt = <925000>;
 121                         clock-latency-ns = <200000>;
 122                 };
 123
 124                 opp-1608000000 {
 125                         opp-hz = /bits/ 64 <1608000000>;
 126                         opp-microvolt = <987500>;
 127                         clock-latency-ns = <200000>;
 128                 };
 129
 130                 opp-1800000000 {
 131                         opp-hz = /bits/ 64 <1800000000>;
 132                         opp-microvolt = <1062500>;
 133                         clock-latency-ns = <200000>;
 134                 };
 135         };
 136
 137         pmuv8: pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 140         };
 141
 142         psci: psci {
 143                 compatible = "arm,psci-1.0";
 144                 method = "smc";
 145         };
 146
 147         reserved-memory {
 148                 #address-cells = <2>;
 149                 #size-cells = <2>;
 150                 ranges;
 151
 152                 rpm_msg_ram: memory@60000 {
 153                         reg = <0x0 0x00060000 0x0 0x6000>;
 154                         no-map;
 155                 };
 156
 157                 tz: memory@4a600000 {
 158                         reg = <0x0 0x4a600000 0x0 0x00400000>;
 159                         no-map;
 160                 };
 161
 162                 smem_region: memory@4aa00000 {
 163                         reg = <0x0 0x4aa00000 0x0 0x00100000>;
 164                         no-map;
 165                 };
 166
 167                 q6_region: memory@4ab00000 {
 168                         reg = <0x0 0x4ab00000 0x0 0x05500000>;
 169                         no-map;
 170                 };
 171         };
 172
 173         rpm-glink {
 174                 compatible = "qcom,glink-rpm";
 175                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 176                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 177                 mboxes = <&apcs_glb 0>;
 178
 179                 rpm_requests: rpm-requests {
 180                         compatible = "qcom,rpm-ipq6018";
 181                         qcom,glink-channels = "rpm_requests";
 182
 183                         regulators {
 184                                 compatible = "qcom,rpm-mp5496-regulators";
 185
 186                                 ipq6018_s2: s2 {
 187                                         regulator-min-microvolt = <725000>;
 188                                         regulator-max-microvolt = <1062500>;
 189                                         regulator-always-on;
 190                                 };
 191                         };
 192                 };
 193         };
 194
 195         smem {
 196                 compatible = "qcom,smem";
 197                 memory-region = <&smem_region>;
 198                 hwlocks = <&tcsr_mutex 0>;
 199         };
 200
 201         soc: soc {
 202                 #address-cells = <2>;
 203                 #size-cells = <2>;
 204                 ranges = <0 0 0 0 0x0 0xffffffff>;
 205                 dma-ranges;
 206                 compatible = "simple-bus";
 207
 208                 qusb_phy_1: qusb@59000 {
 209                         compatible = "qcom,ipq6018-qusb2-phy";
 210                         reg = <0x0 0x00059000 0x0 0x180>;
 211                         #phy-cells = <0>;
 212
 213                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 214                                  <&xo>;
 215                         clock-names = "cfg_ahb", "ref";
 216
 217                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 218                         status = "disabled";
 219                 };
 220
 221                 ssphy_0: ssphy@78000 {
 222                         compatible = "qcom,ipq6018-qmp-usb3-phy";
 223                         reg = <0x0 0x00078000 0x0 0x1c4>;
 224                         #address-cells = <2>;
 225                         #size-cells = <2>;
 226                         ranges;
 227
 228                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 229                                  <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
 230                         clock-names = "aux", "cfg_ahb", "ref";
 231
 232                         resets = <&gcc GCC_USB0_PHY_BCR>,
 233                                  <&gcc GCC_USB3PHY_0_PHY_BCR>;
 234                         reset-names = "phy","common";
 235                         status = "disabled";
 236
 237                         usb0_ssphy: phy@78200 {
 238                                 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
 239                                       <0x0 0x00078400 0x0 0x200>, /* Rx */
 240                                       <0x0 0x00078800 0x0 0x1f8>, /* PCS */
 241                                       <0x0 0x00078600 0x0 0x044>; /* PCS misc */
 242                                 #phy-cells = <0>;
 243                                 #clock-cells = <0>;
 244                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 245                                 clock-names = "pipe0";
 246                                 clock-output-names = "gcc_usb0_pipe_clk_src";
 247                         };
 248                 };
 249
 250                 qusb_phy_0: qusb@79000 {
 251                         compatible = "qcom,ipq6018-qusb2-phy";
 252                         reg = <0x0 0x00079000 0x0 0x180>;
 253                         #phy-cells = <0>;
 254
 255                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 256                                 <&xo>;
 257                         clock-names = "cfg_ahb", "ref";
 258
 259                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 260                         status = "disabled";
 261                 };
 262
 263                 pcie_phy: phy@84000 {
 264                         compatible = "qcom,ipq6018-qmp-pcie-phy";
 265                         reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
 266                         status = "disabled";
 267                         #address-cells = <2>;
 268                         #size-cells = <2>;
 269                         ranges;
 270
 271                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 272                                 <&gcc GCC_PCIE0_AHB_CLK>;
 273                         clock-names = "aux", "cfg_ahb";
 274
 275                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 276                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 277                         reset-names = "phy",
 278                                       "common";
 279
 280                         pcie_phy0: phy@84200 {
 281                                 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
 282                                       <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
 283                                       <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
 284                                       <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
 285                                 #phy-cells = <0>;
 286
 287                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 288                                 clock-names = "pipe0";
 289                                 clock-output-names = "gcc_pcie0_pipe_clk_src";
 290                                 #clock-cells = <0>;
 291                         };
 292                 };
 293
 294                 mdio: mdio@90000 {
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
 298                         reg = <0x0 0x00090000 0x0 0x64>;
 299                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 300                         clock-names = "gcc_mdio_ahb_clk";
 301                         status = "disabled";
 302                 };
 303
 304                 prng: qrng@e1000 {
 305                         compatible = "qcom,prng-ee";
 306                         reg = <0x0 0x000e3000 0x0 0x1000>;
 307                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 308                         clock-names = "core";
 309                 };
 310
 311                 cryptobam: dma-controller@704000 {
 312                         compatible = "qcom,bam-v1.7.0";
 313                         reg = <0x0 0x00704000 0x0 0x20000>;
 314                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 315                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 316                         clock-names = "bam_clk";
 317                         #dma-cells = <1>;
 318                         qcom,ee = <1>;
 319                         qcom,controlled-remotely;
 320                 };
 321
 322                 crypto: crypto@73a000 {
 323                         compatible = "qcom,crypto-v5.1";
 324                         reg = <0x0 0x0073a000 0x0 0x6000>;
 325                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 326                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 327                                  <&gcc GCC_CRYPTO_CLK>;
 328                         clock-names = "iface", "bus", "core";
 329                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 330                         dma-names = "rx", "tx";
 331                 };
 332
 333                 tlmm: pinctrl@1000000 {
 334                         compatible = "qcom,ipq6018-pinctrl";
 335                         reg = <0x0 0x01000000 0x0 0x300000>;
 336                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 337                         gpio-controller;
 338                         #gpio-cells = <2>;
 339                         gpio-ranges = <&tlmm 0 0 80>;
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342
 343                         serial_3_pins: serial3-state {
 344                                 pins = "gpio44", "gpio45";
 345                                 function = "blsp2_uart";
 346                                 drive-strength = <8>;
 347                                 bias-pull-down;
 348                         };
 349
 350                         qpic_pins: qpic-state {
 351                                 pins = "gpio1", "gpio3", "gpio4",
 352                                         "gpio5", "gpio6", "gpio7",
 353                                         "gpio8", "gpio10", "gpio11",
 354                                         "gpio12", "gpio13", "gpio14",
 355                                         "gpio15", "gpio17";
 356                                 function = "qpic_pad";
 357                                 drive-strength = <8>;
 358                                 bias-disable;
 359                         };
 360                 };
 361
 362                 gcc: gcc@1800000 {
 363                         compatible = "qcom,gcc-ipq6018";
 364                         reg = <0x0 0x01800000 0x0 0x80000>;
 365                         clocks = <&xo>, <&sleep_clk>;
 366                         clock-names = "xo", "sleep_clk";
 367                         #clock-cells = <1>;
 368                         #reset-cells = <1>;
 369                 };
 370
 371                 tcsr_mutex: hwlock@1905000 {
 372                         compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
 373                         reg = <0x0 0x01905000 0x0 0x1000>;
 374                         #hwlock-cells = <1>;
 375                 };
 376
 377                 tcsr: syscon@1937000 {
 378                         compatible = "qcom,tcsr-ipq6018", "syscon";
 379                         reg = <0x0 0x01937000 0x0 0x21000>;
 380                 };
 381
 382                 usb2: usb@70f8800 {
 383                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 384                         reg = <0x0 0x070f8800 0x0 0x400>;
 385                         #address-cells = <2>;
 386                         #size-cells = <2>;
 387                         ranges;
 388                         clocks = <&gcc GCC_USB1_MASTER_CLK>,
 389                                  <&gcc GCC_USB1_SLEEP_CLK>,
 390                                  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 391                         clock-names = "core",
 392                                       "sleep",
 393                                       "mock_utmi";
 394
 395                         assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
 396                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 397                         assigned-clock-rates = <133330000>,
 398                                                <24000000>;
 399                         resets = <&gcc GCC_USB1_BCR>;
 400                         status = "disabled";
 401
 402                         dwc_1: usb@7000000 {
 403                                 compatible = "snps,dwc3";
 404                                 reg = <0x0 0x07000000 0x0 0xcd00>;
 405                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 406                                 phys = <&qusb_phy_1>;
 407                                 phy-names = "usb2-phy";
 408                                 tx-fifo-resize;
 409                                 snps,is-utmi-l1-suspend;
 410                                 snps,hird-threshold = /bits/ 8 <0x0>;
 411                                 snps,dis_u2_susphy_quirk;
 412                                 snps,dis_u3_susphy_quirk;
 413                                 dr_mode = "host";
 414                         };
 415                 };
 416
 417                 blsp_dma: dma-controller@7884000 {
 418                         compatible = "qcom,bam-v1.7.0";
 419                         reg = <0x0 0x07884000 0x0 0x2b000>;
 420                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 422                         clock-names = "bam_clk";
 423                         #dma-cells = <1>;
 424                         qcom,ee = <0>;
 425                 };
 426
 427                 blsp1_uart3: serial@78b1000 {
 428                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 429                         reg = <0x0 0x078b1000 0x0 0x200>;
 430                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 432                                  <&gcc GCC_BLSP1_AHB_CLK>;
 433                         clock-names = "core", "iface";
 434                         status = "disabled";
 435                 };
 436
 437                 blsp1_spi1: spi@78b5000 {
 438                         compatible = "qcom,spi-qup-v2.2.1";
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         reg = <0x0 0x078b5000 0x0 0x600>;
 442                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 443                         spi-max-frequency = <50000000>;
 444                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 445                                  <&gcc GCC_BLSP1_AHB_CLK>;
 446                         clock-names = "core", "iface";
 447                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 448                         dma-names = "tx", "rx";
 449                         status = "disabled";
 450                 };
 451
 452                 blsp1_spi2: spi@78b6000 {
 453                         compatible = "qcom,spi-qup-v2.2.1";
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         reg = <0x0 0x078b6000 0x0 0x600>;
 457                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 458                         spi-max-frequency = <50000000>;
 459                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 460                                  <&gcc GCC_BLSP1_AHB_CLK>;
 461                         clock-names = "core", "iface";
 462                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 463                         dma-names = "tx", "rx";
 464                         status = "disabled";
 465                 };
 466
 467                 blsp1_i2c2: i2c@78b6000 {
 468                         compatible = "qcom,i2c-qup-v2.2.1";
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         reg = <0x0 0x078b6000 0x0 0x600>;
 472                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 474                                  <&gcc GCC_BLSP1_AHB_CLK>;
 475                         clock-names = "core", "iface";
 476                         clock-frequency = <400000>;
 477                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 478                         dma-names = "tx", "rx";
 479                         status = "disabled";
 480                 };
 481
 482                 blsp1_i2c3: i2c@78b7000 {
 483                         compatible = "qcom,i2c-qup-v2.2.1";
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         reg = <0x0 0x078b7000 0x0 0x600>;
 487                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 488                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 489                                  <&gcc GCC_BLSP1_AHB_CLK>;
 490                         clock-names = "core", "iface";
 491                         clock-frequency = <400000>;
 492                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 493                         dma-names = "tx", "rx";
 494                         status = "disabled";
 495                 };
 496
 497                 qpic_bam: dma-controller@7984000 {
 498                         compatible = "qcom,bam-v1.7.0";
 499                         reg = <0x0 0x07984000 0x0 0x1a000>;
 500                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 502                         clock-names = "bam_clk";
 503                         #dma-cells = <1>;
 504                         qcom,ee = <0>;
 505                         status = "disabled";
 506                 };
 507
 508                 qpic_nand: nand-controller@79b0000 {
 509                         compatible = "qcom,ipq6018-nand";
 510                         reg = <0x0 0x079b0000 0x0 0x10000>;
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         clocks = <&gcc GCC_QPIC_CLK>,
 514                                  <&gcc GCC_QPIC_AHB_CLK>;
 515                         clock-names = "core", "aon";
 516
 517                         dmas = <&qpic_bam 0>,
 518                                <&qpic_bam 1>,
 519                                <&qpic_bam 2>;
 520                         dma-names = "tx", "rx", "cmd";
 521                         pinctrl-0 = <&qpic_pins>;
 522                         pinctrl-names = "default";
 523                         status = "disabled";
 524                 };
 525
 526                 usb3: usb@8af8800 {
 527                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 528                         reg = <0x0 0x08af8800 0x0 0x400>;
 529                         #address-cells = <2>;
 530                         #size-cells = <2>;
 531                         ranges;
 532
 533                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 534                                 <&gcc GCC_USB0_MASTER_CLK>,
 535                                 <&gcc GCC_USB0_SLEEP_CLK>,
 536                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 537                         clock-names = "cfg_noc",
 538                                 "core",
 539                                 "sleep",
 540                                 "mock_utmi";
 541
 542                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 543                                           <&gcc GCC_USB0_MASTER_CLK>,
 544                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 545                         assigned-clock-rates = <133330000>,
 546                                                <133330000>,
 547                                                <20000000>;
 548
 549                         resets = <&gcc GCC_USB0_BCR>;
 550                         status = "disabled";
 551
 552                         dwc_0: usb@8a00000 {
 553                                 compatible = "snps,dwc3";
 554                                 reg = <0x0 0x08a00000 0x0 0xcd00>;
 555                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 556                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 557                                 phy-names = "usb2-phy", "usb3-phy";
 558                                 clocks = <&xo>;
 559                                 clock-names = "ref";
 560                                 tx-fifo-resize;
 561                                 snps,is-utmi-l1-suspend;
 562                                 snps,hird-threshold = /bits/ 8 <0x0>;
 563                                 snps,dis_u2_susphy_quirk;
 564                                 snps,dis_u3_susphy_quirk;
 565                                 dr_mode = "host";
 566                         };
 567                 };
 568
 569                 intc: interrupt-controller@b000000 {
 570                         compatible = "qcom,msm-qgic2";
 571                         #address-cells = <2>;
 572                         #size-cells = <2>;
 573                         interrupt-controller;
 574                         #interrupt-cells = <0x3>;
 575                         reg = <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
 576                               <0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
 577                               <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
 578                               <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
 579                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 580                         ranges = <0 0 0 0xb00a000 0 0xffd>;
 581
 582                         v2m@0 {
 583                                 compatible = "arm,gic-v2m-frame";
 584                                 msi-controller;
 585                                 reg = <0x0 0x0 0x0 0xffd>;
 586                         };
 587                 };
 588
 589                 watchdog@b017000 {
 590                         compatible = "qcom,kpss-wdt";
 591                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 592                         reg = <0x0 0x0b017000 0x0 0x40>;
 593                         clocks = <&sleep_clk>;
 594                         timeout-sec = <10>;
 595                 };
 596
 597                 apcs_glb: mailbox@b111000 {
 598                         compatible = "qcom,ipq6018-apcs-apps-global";
 599                         reg = <0x0 0x0b111000 0x0 0x1000>;
 600                         #clock-cells = <1>;
 601                         clocks = <&a53pll>, <&xo>;
 602                         clock-names = "pll", "xo";
 603                         #mbox-cells = <1>;
 604                 };
 605
 606                 a53pll: clock@b116000 {
 607                         compatible = "qcom,ipq6018-a53pll";
 608                         reg = <0x0 0x0b116000 0x0 0x40>;
 609                         #clock-cells = <0>;
 610                         clocks = <&xo>;
 611                         clock-names = "xo";
 612                 };
 613
 614                 timer@b120000 {
 615                         #address-cells = <1>;
 616                         #size-cells = <1>;
 617                         ranges = <0 0 0 0x10000000>;
 618                         compatible = "arm,armv7-timer-mem";
 619                         reg = <0x0 0x0b120000 0x0 0x1000>;
 620
 621                         frame@b120000 {
 622                                 frame-number = <0>;
 623                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 624                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 625                                 reg = <0x0b121000 0x1000>,
 626                                       <0x0b122000 0x1000>;
 627                         };
 628
 629                         frame@b123000 {
 630                                 frame-number = <1>;
 631                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 632                                 reg = <0x0b123000 0x1000>;
 633                                 status = "disabled";
 634                         };
 635
 636                         frame@b124000 {
 637                                 frame-number = <2>;
 638                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 639                                 reg = <0x0b124000 0x1000>;
 640                                 status = "disabled";
 641                         };
 642
 643                         frame@b125000 {
 644                                 frame-number = <3>;
 645                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 646                                 reg = <0x0b125000 0x1000>;
 647                                 status = "disabled";
 648                         };
 649
 650                         frame@b126000 {
 651                                 frame-number = <4>;
 652                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 653                                 reg = <0x0b126000 0x1000>;
 654                                 status = "disabled";
 655                         };
 656
 657                         frame@b127000 {
 658                                 frame-number = <5>;
 659                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 660                                 reg = <0x0b127000 0x1000>;
 661                                 status = "disabled";
 662                         };
 663
 664                         frame@b128000 {
 665                                 frame-number = <6>;
 666                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 667                                 reg = <0x0b128000 0x1000>;
 668                                 status = "disabled";
 669                         };
 670                 };
 671
 672                 q6v5_wcss: remoteproc@cd00000 {
 673                         compatible = "qcom,ipq6018-wcss-pil";
 674                         reg = <0x0 0x0cd00000 0x0 0x4040>,
 675                               <0x0 0x004ab000 0x0 0x20>;
 676                         reg-names = "qdsp6",
 677                                     "rmb";
 678                         interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
 679                                               <&wcss_smp2p_in 0 0>,
 680                                               <&wcss_smp2p_in 1 0>,
 681                                               <&wcss_smp2p_in 2 0>,
 682                                               <&wcss_smp2p_in 3 0>;
 683                         interrupt-names = "wdog",
 684                                           "fatal",
 685                                           "ready",
 686                                           "handover",
 687                                           "stop-ack";
 688
 689                         resets = <&gcc GCC_WCSSAON_RESET>,
 690                                  <&gcc GCC_WCSS_BCR>,
 691                                  <&gcc GCC_WCSS_Q6_BCR>;
 692
 693                         reset-names = "wcss_aon_reset",
 694                                       "wcss_reset",
 695                                       "wcss_q6_reset";
 696
 697                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 698                         clock-names = "prng";
 699
 700                         qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
 701
 702                         qcom,smem-states = <&wcss_smp2p_out 0>,
 703                                            <&wcss_smp2p_out 1>;
 704                         qcom,smem-state-names = "shutdown",
 705                                                 "stop";
 706
 707                         memory-region = <&q6_region>;
 708
 709                         glink-edge {
 710                                 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
 711                                 label = "rtr";
 712                                 qcom,remote-pid = <1>;
 713                                 mboxes = <&apcs_glb 8>;
 714
 715                                 qrtr_requests {
 716                                         qcom,glink-channels = "IPCRTR";
 717                                 };
 718                         };
 719                 };
 720
 721                 pcie0: pci@20000000 {
 722                         compatible = "qcom,pcie-ipq6018";
 723                         reg = <0x0 0x20000000 0x0 0xf1d>,
 724                               <0x0 0x20000f20 0x0 0xa8>,
 725                               <0x0 0x20001000 0x0 0x1000>,
 726                               <0x0 0x80000 0x0 0x4000>,
 727                               <0x0 0x20100000 0x0 0x1000>;
 728                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 729
 730                         device_type = "pci";
 731                         linux,pci-domain = <0>;
 732                         bus-range = <0x00 0xff>;
 733                         num-lanes = <1>;
 734                         max-link-speed = <3>;
 735                         #address-cells = <3>;
 736                         #size-cells = <2>;
 737
 738                         phys = <&pcie_phy0>;
 739                         phy-names = "pciephy";
 740
 741                         ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
 742                                  <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
 743
 744                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 745                         interrupt-names = "msi";
 746
 747                         #interrupt-cells = <1>;
 748                         interrupt-map-mask = <0 0 0 0x7>;
 749                         interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 750                                         <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 751                                         <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 752                                         <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 753
 754                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 755                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 756                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 757                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 758                                  <&gcc PCIE0_RCHNG_CLK>;
 759                         clock-names = "iface",
 760                                       "axi_m",
 761                                       "axi_s",
 762                                       "axi_bridge",
 763                                       "rchng";
 764
 765                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 766                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 767                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 768                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 769                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 770                                  <&gcc GCC_PCIE0_AHB_ARES>,
 771                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 772                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 773                         reset-names = "pipe",
 774                                       "sleep",
 775                                       "sticky",
 776                                       "axi_m",
 777                                       "axi_s",
 778                                       "ahb",
 779                                       "axi_m_sticky",
 780                                       "axi_s_sticky";
 781
 782                         status = "disabled";
 783                 };
 784         };
 785
 786         timer {
 787                 compatible = "arm,armv8-timer";
 788                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 789                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 790                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 791                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 792         };
 793
 794         wcss: wcss-smp2p {
 795                 compatible = "qcom,smp2p";
 796                 qcom,smem = <435>, <428>;
 797
 798                 interrupt-parent = <&intc>;
 799                 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
 800
 801                 mboxes = <&apcs_glb 9>;
 802
 803                 qcom,local-pid = <0>;
 804                 qcom,remote-pid = <1>;
 805
 806                 wcss_smp2p_out: master-kernel {
 807                         qcom,entry-name = "master-kernel";
 808                         #qcom,smem-state-cells = <1>;
 809                 };
 810
 811                 wcss_smp2p_in: slave-kernel {
 812                         qcom,entry-name = "slave-kernel";
 813                         interrupt-controller;
 814                         #interrupt-cells = <2>;
 815                 };
 816         };
 817 };