1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ6018 SoC device tree source
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
92 compatible = "qcom,scm-ipq6018", "qcom,scm";
96 cpu_opp_table: opp-table-cpu {
97 compatible = "operating-points-v2";
101 opp-hz = /bits/ 64 <864000000>;
102 opp-microvolt = <725000>;
103 clock-latency-ns = <200000>;
107 opp-hz = /bits/ 64 <1056000000>;
108 opp-microvolt = <787500>;
109 clock-latency-ns = <200000>;
113 opp-hz = /bits/ 64 <1320000000>;
114 opp-microvolt = <862500>;
115 clock-latency-ns = <200000>;
119 opp-hz = /bits/ 64 <1440000000>;
120 opp-microvolt = <925000>;
121 clock-latency-ns = <200000>;
125 opp-hz = /bits/ 64 <1608000000>;
126 opp-microvolt = <987500>;
127 clock-latency-ns = <200000>;
131 opp-hz = /bits/ 64 <1800000000>;
132 opp-microvolt = <1062500>;
133 clock-latency-ns = <200000>;
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
143 compatible = "arm,psci-1.0";
148 #address-cells = <2>;
152 rpm_msg_ram: memory@60000 {
153 reg = <0x0 0x00060000 0x0 0x6000>;
157 tz: memory@4a600000 {
158 reg = <0x0 0x4a600000 0x0 0x00400000>;
162 smem_region: memory@4aa00000 {
163 reg = <0x0 0x4aa00000 0x0 0x00100000>;
167 q6_region: memory@4ab00000 {
168 reg = <0x0 0x4ab00000 0x0 0x05500000>;
174 compatible = "qcom,glink-rpm";
175 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
176 qcom,rpm-msg-ram = <&rpm_msg_ram>;
177 mboxes = <&apcs_glb 0>;
179 rpm_requests: rpm-requests {
180 compatible = "qcom,rpm-ipq6018";
181 qcom,glink-channels = "rpm_requests";
184 compatible = "qcom,rpm-mp5496-regulators";
187 regulator-min-microvolt = <725000>;
188 regulator-max-microvolt = <1062500>;
196 compatible = "qcom,smem";
197 memory-region = <&smem_region>;
198 hwlocks = <&tcsr_mutex 0>;
202 #address-cells = <2>;
204 ranges = <0 0 0 0 0x0 0xffffffff>;
206 compatible = "simple-bus";
208 qusb_phy_1: qusb@59000 {
209 compatible = "qcom,ipq6018-qusb2-phy";
210 reg = <0x0 0x00059000 0x0 0x180>;
213 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
215 clock-names = "cfg_ahb", "ref";
217 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
221 ssphy_0: ssphy@78000 {
222 compatible = "qcom,ipq6018-qmp-usb3-phy";
223 reg = <0x0 0x00078000 0x0 0x1c4>;
224 #address-cells = <2>;
228 clocks = <&gcc GCC_USB0_AUX_CLK>,
229 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
230 clock-names = "aux", "cfg_ahb", "ref";
232 resets = <&gcc GCC_USB0_PHY_BCR>,
233 <&gcc GCC_USB3PHY_0_PHY_BCR>;
234 reset-names = "phy","common";
237 usb0_ssphy: phy@78200 {
238 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
239 <0x0 0x00078400 0x0 0x200>, /* Rx */
240 <0x0 0x00078800 0x0 0x1f8>, /* PCS */
241 <0x0 0x00078600 0x0 0x044>; /* PCS misc */
244 clocks = <&gcc GCC_USB0_PIPE_CLK>;
245 clock-names = "pipe0";
246 clock-output-names = "gcc_usb0_pipe_clk_src";
250 qusb_phy_0: qusb@79000 {
251 compatible = "qcom,ipq6018-qusb2-phy";
252 reg = <0x0 0x00079000 0x0 0x180>;
255 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
257 clock-names = "cfg_ahb", "ref";
259 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
263 pcie_phy: phy@84000 {
264 compatible = "qcom,ipq6018-qmp-pcie-phy";
265 reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
267 #address-cells = <2>;
271 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
272 <&gcc GCC_PCIE0_AHB_CLK>;
273 clock-names = "aux", "cfg_ahb";
275 resets = <&gcc GCC_PCIE0_PHY_BCR>,
276 <&gcc GCC_PCIE0PHY_PHY_BCR>;
280 pcie_phy0: phy@84200 {
281 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
282 <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
283 <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
284 <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
287 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
288 clock-names = "pipe0";
289 clock-output-names = "gcc_pcie0_pipe_clk_src";
295 #address-cells = <1>;
297 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
298 reg = <0x0 0x00090000 0x0 0x64>;
299 clocks = <&gcc GCC_MDIO_AHB_CLK>;
300 clock-names = "gcc_mdio_ahb_clk";
305 compatible = "qcom,prng-ee";
306 reg = <0x0 0x000e3000 0x0 0x1000>;
307 clocks = <&gcc GCC_PRNG_AHB_CLK>;
308 clock-names = "core";
311 cryptobam: dma-controller@704000 {
312 compatible = "qcom,bam-v1.7.0";
313 reg = <0x0 0x00704000 0x0 0x20000>;
314 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
316 clock-names = "bam_clk";
319 qcom,controlled-remotely;
322 crypto: crypto@73a000 {
323 compatible = "qcom,crypto-v5.1";
324 reg = <0x0 0x0073a000 0x0 0x6000>;
325 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
326 <&gcc GCC_CRYPTO_AXI_CLK>,
327 <&gcc GCC_CRYPTO_CLK>;
328 clock-names = "iface", "bus", "core";
329 dmas = <&cryptobam 2>, <&cryptobam 3>;
330 dma-names = "rx", "tx";
333 tlmm: pinctrl@1000000 {
334 compatible = "qcom,ipq6018-pinctrl";
335 reg = <0x0 0x01000000 0x0 0x300000>;
336 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
339 gpio-ranges = <&tlmm 0 0 80>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
343 serial_3_pins: serial3-state {
344 pins = "gpio44", "gpio45";
345 function = "blsp2_uart";
346 drive-strength = <8>;
350 qpic_pins: qpic-state {
351 pins = "gpio1", "gpio3", "gpio4",
352 "gpio5", "gpio6", "gpio7",
353 "gpio8", "gpio10", "gpio11",
354 "gpio12", "gpio13", "gpio14",
356 function = "qpic_pad";
357 drive-strength = <8>;
363 compatible = "qcom,gcc-ipq6018";
364 reg = <0x0 0x01800000 0x0 0x80000>;
365 clocks = <&xo>, <&sleep_clk>;
366 clock-names = "xo", "sleep_clk";
371 tcsr_mutex: hwlock@1905000 {
372 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
373 reg = <0x0 0x01905000 0x0 0x1000>;
377 tcsr: syscon@1937000 {
378 compatible = "qcom,tcsr-ipq6018", "syscon";
379 reg = <0x0 0x01937000 0x0 0x21000>;
383 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
384 reg = <0x0 0x070f8800 0x0 0x400>;
385 #address-cells = <2>;
388 clocks = <&gcc GCC_USB1_MASTER_CLK>,
389 <&gcc GCC_USB1_SLEEP_CLK>,
390 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
391 clock-names = "core",
395 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
396 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
397 assigned-clock-rates = <133330000>,
399 resets = <&gcc GCC_USB1_BCR>;
403 compatible = "snps,dwc3";
404 reg = <0x0 0x07000000 0x0 0xcd00>;
405 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
406 phys = <&qusb_phy_1>;
407 phy-names = "usb2-phy";
409 snps,is-utmi-l1-suspend;
410 snps,hird-threshold = /bits/ 8 <0x0>;
411 snps,dis_u2_susphy_quirk;
412 snps,dis_u3_susphy_quirk;
417 blsp_dma: dma-controller@7884000 {
418 compatible = "qcom,bam-v1.7.0";
419 reg = <0x0 0x07884000 0x0 0x2b000>;
420 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
422 clock-names = "bam_clk";
427 blsp1_uart3: serial@78b1000 {
428 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
429 reg = <0x0 0x078b1000 0x0 0x200>;
430 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
432 <&gcc GCC_BLSP1_AHB_CLK>;
433 clock-names = "core", "iface";
437 blsp1_spi1: spi@78b5000 {
438 compatible = "qcom,spi-qup-v2.2.1";
439 #address-cells = <1>;
441 reg = <0x0 0x078b5000 0x0 0x600>;
442 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
443 spi-max-frequency = <50000000>;
444 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
445 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", "iface";
447 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
448 dma-names = "tx", "rx";
452 blsp1_spi2: spi@78b6000 {
453 compatible = "qcom,spi-qup-v2.2.1";
454 #address-cells = <1>;
456 reg = <0x0 0x078b6000 0x0 0x600>;
457 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
458 spi-max-frequency = <50000000>;
459 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
460 <&gcc GCC_BLSP1_AHB_CLK>;
461 clock-names = "core", "iface";
462 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
463 dma-names = "tx", "rx";
467 blsp1_i2c2: i2c@78b6000 {
468 compatible = "qcom,i2c-qup-v2.2.1";
469 #address-cells = <1>;
471 reg = <0x0 0x078b6000 0x0 0x600>;
472 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
474 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", "iface";
476 clock-frequency = <400000>;
477 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
478 dma-names = "tx", "rx";
482 blsp1_i2c3: i2c@78b7000 {
483 compatible = "qcom,i2c-qup-v2.2.1";
484 #address-cells = <1>;
486 reg = <0x0 0x078b7000 0x0 0x600>;
487 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
489 <&gcc GCC_BLSP1_AHB_CLK>;
490 clock-names = "core", "iface";
491 clock-frequency = <400000>;
492 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
493 dma-names = "tx", "rx";
497 qpic_bam: dma-controller@7984000 {
498 compatible = "qcom,bam-v1.7.0";
499 reg = <0x0 0x07984000 0x0 0x1a000>;
500 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&gcc GCC_QPIC_AHB_CLK>;
502 clock-names = "bam_clk";
508 qpic_nand: nand-controller@79b0000 {
509 compatible = "qcom,ipq6018-nand";
510 reg = <0x0 0x079b0000 0x0 0x10000>;
511 #address-cells = <1>;
513 clocks = <&gcc GCC_QPIC_CLK>,
514 <&gcc GCC_QPIC_AHB_CLK>;
515 clock-names = "core", "aon";
517 dmas = <&qpic_bam 0>,
520 dma-names = "tx", "rx", "cmd";
521 pinctrl-0 = <&qpic_pins>;
522 pinctrl-names = "default";
527 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
528 reg = <0x0 0x08af8800 0x0 0x400>;
529 #address-cells = <2>;
533 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
534 <&gcc GCC_USB0_MASTER_CLK>,
535 <&gcc GCC_USB0_SLEEP_CLK>,
536 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
537 clock-names = "cfg_noc",
542 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
543 <&gcc GCC_USB0_MASTER_CLK>,
544 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
545 assigned-clock-rates = <133330000>,
549 resets = <&gcc GCC_USB0_BCR>;
553 compatible = "snps,dwc3";
554 reg = <0x0 0x08a00000 0x0 0xcd00>;
555 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
556 phys = <&qusb_phy_0>, <&usb0_ssphy>;
557 phy-names = "usb2-phy", "usb3-phy";
561 snps,is-utmi-l1-suspend;
562 snps,hird-threshold = /bits/ 8 <0x0>;
563 snps,dis_u2_susphy_quirk;
564 snps,dis_u3_susphy_quirk;
569 intc: interrupt-controller@b000000 {
570 compatible = "qcom,msm-qgic2";
571 #address-cells = <2>;
573 interrupt-controller;
574 #interrupt-cells = <0x3>;
575 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
576 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
577 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
578 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
579 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
580 ranges = <0 0 0 0xb00a000 0 0xffd>;
583 compatible = "arm,gic-v2m-frame";
585 reg = <0x0 0x0 0x0 0xffd>;
590 compatible = "qcom,kpss-wdt";
591 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
592 reg = <0x0 0x0b017000 0x0 0x40>;
593 clocks = <&sleep_clk>;
597 apcs_glb: mailbox@b111000 {
598 compatible = "qcom,ipq6018-apcs-apps-global";
599 reg = <0x0 0x0b111000 0x0 0x1000>;
601 clocks = <&a53pll>, <&xo>;
602 clock-names = "pll", "xo";
606 a53pll: clock@b116000 {
607 compatible = "qcom,ipq6018-a53pll";
608 reg = <0x0 0x0b116000 0x0 0x40>;
615 #address-cells = <1>;
617 ranges = <0 0 0 0x10000000>;
618 compatible = "arm,armv7-timer-mem";
619 reg = <0x0 0x0b120000 0x0 0x1000>;
623 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
625 reg = <0x0b121000 0x1000>,
631 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
632 reg = <0x0b123000 0x1000>;
638 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
639 reg = <0x0b124000 0x1000>;
645 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
646 reg = <0x0b125000 0x1000>;
652 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
653 reg = <0x0b126000 0x1000>;
659 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
660 reg = <0x0b127000 0x1000>;
666 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
667 reg = <0x0b128000 0x1000>;
672 q6v5_wcss: remoteproc@cd00000 {
673 compatible = "qcom,ipq6018-wcss-pil";
674 reg = <0x0 0x0cd00000 0x0 0x4040>,
675 <0x0 0x004ab000 0x0 0x20>;
678 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
679 <&wcss_smp2p_in 0 0>,
680 <&wcss_smp2p_in 1 0>,
681 <&wcss_smp2p_in 2 0>,
682 <&wcss_smp2p_in 3 0>;
683 interrupt-names = "wdog",
689 resets = <&gcc GCC_WCSSAON_RESET>,
691 <&gcc GCC_WCSS_Q6_BCR>;
693 reset-names = "wcss_aon_reset",
697 clocks = <&gcc GCC_PRNG_AHB_CLK>;
698 clock-names = "prng";
700 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
702 qcom,smem-states = <&wcss_smp2p_out 0>,
704 qcom,smem-state-names = "shutdown",
707 memory-region = <&q6_region>;
710 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
712 qcom,remote-pid = <1>;
713 mboxes = <&apcs_glb 8>;
716 qcom,glink-channels = "IPCRTR";
721 pcie0: pci@20000000 {
722 compatible = "qcom,pcie-ipq6018";
723 reg = <0x0 0x20000000 0x0 0xf1d>,
724 <0x0 0x20000f20 0x0 0xa8>,
725 <0x0 0x20001000 0x0 0x1000>,
726 <0x0 0x80000 0x0 0x4000>,
727 <0x0 0x20100000 0x0 0x1000>;
728 reg-names = "dbi", "elbi", "atu", "parf", "config";
731 linux,pci-domain = <0>;
732 bus-range = <0x00 0xff>;
734 max-link-speed = <3>;
735 #address-cells = <3>;
739 phy-names = "pciephy";
741 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
742 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
744 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "msi";
747 #interrupt-cells = <1>;
748 interrupt-map-mask = <0 0 0 0x7>;
749 interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
750 <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
751 <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
752 <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
754 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
755 <&gcc GCC_PCIE0_AXI_M_CLK>,
756 <&gcc GCC_PCIE0_AXI_S_CLK>,
757 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
758 <&gcc PCIE0_RCHNG_CLK>;
759 clock-names = "iface",
765 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
766 <&gcc GCC_PCIE0_SLEEP_ARES>,
767 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
768 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
769 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
770 <&gcc GCC_PCIE0_AHB_ARES>,
771 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
772 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
773 reset-names = "pipe",
787 compatible = "arm,armv8-timer";
788 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
789 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
790 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
791 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
795 compatible = "qcom,smp2p";
796 qcom,smem = <435>, <428>;
798 interrupt-parent = <&intc>;
799 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
801 mboxes = <&apcs_glb 9>;
803 qcom,local-pid = <0>;
804 qcom,remote-pid = <1>;
806 wcss_smp2p_out: master-kernel {
807 qcom,entry-name = "master-kernel";
808 #qcom,smem-state-cells = <1>;
811 wcss_smp2p_in: slave-kernel {
812 qcom,entry-name = "slave-kernel";
813 interrupt-controller;
814 #interrupt-cells = <2>;