arch/arm64/boot/dts/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/reset/tegra194-reset.h>
   9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
  10 #include <dt-bindings/memory/tegra194-mc.h>
  11
  12 / {
  13         compatible = "nvidia,tegra194";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         /* control backbone */
  19         bus@0 {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges = <0x0 0x0 0x0 0x40000000>;
  24
  25                 misc@100000 {
  26                         compatible = "nvidia,tegra194-misc";
  27                         reg = <0x00100000 0xf000>,
  28                               <0x0010f000 0x1000>;
  29                 };
  30
  31                 gpio: gpio@2200000 {
  32                         compatible = "nvidia,tegra194-gpio";
  33                         reg-names = "security", "gpio";
  34                         reg = <0x2200000 0x10000>,
  35                               <0x2210000 0x10000>;
  36                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  37                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  42                         #interrupt-cells = <2>;
  43                         interrupt-controller;
  44                         #gpio-cells = <2>;
  45                         gpio-controller;
  46                 };
  47
  48                 ethernet@2490000 {
  49                         compatible = "nvidia,tegra194-eqos",
  50                                      "nvidia,tegra186-eqos",
  51                                      "snps,dwc-qos-ethernet-4.10";
  52                         reg = <0x02490000 0x10000>;
  53                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  55                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  56                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  57                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  58                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  59                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  60                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  61                         reset-names = "eqos";
  62                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
  63                                         <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
  64                         interconnect-names = "dma-mem", "write";
  65                         status = "disabled";
  66
  67                         snps,write-requests = <1>;
  68                         snps,read-requests = <3>;
  69                         snps,burst-map = <0x7>;
  70                         snps,txpbl = <16>;
  71                         snps,rxpbl = <8>;
  72                 };
  73
  74                 aconnect@2900000 {
  75                         compatible = "nvidia,tegra194-aconnect",
  76                                      "nvidia,tegra210-aconnect";
  77                         clocks = <&bpmp TEGRA194_CLK_APE>,
  78                                  <&bpmp TEGRA194_CLK_APB2APE>;
  79                         clock-names = "ape", "apb2ape";
  80                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83                         ranges = <0x02900000 0x02900000 0x200000>;
  84                         status = "disabled";
  85
  86                         adma: dma-controller@2930000 {
  87                                 compatible = "nvidia,tegra194-adma",
  88                                              "nvidia,tegra186-adma";
  89                                 reg = <0x02930000 0x20000>;
  90                                 interrupt-parent = <&agic>;
  91                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  92                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  93                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  94                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  95                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  96                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  97                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  98                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  99                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 100                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 101                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 102                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 103                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 104                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 105                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 106                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 107                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 108                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 109                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 110                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 111                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 112                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 113                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 114                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 115                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 116                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 117                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 118                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 119                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 120                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 121                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 122                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 123                                 #dma-cells = <1>;
 124                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 125                                 clock-names = "d_audio";
 126                                 status = "disabled";
 127                         };
 128
 129                         agic: interrupt-controller@2a40000 {
 130                                 compatible = "nvidia,tegra194-agic",
 131                                              "nvidia,tegra210-agic";
 132                                 #interrupt-cells = <3>;
 133                                 interrupt-controller;
 134                                 reg = <0x02a41000 0x1000>,
 135                                       <0x02a42000 0x2000>;
 136                                 interrupts = <GIC_SPI 145
 137                                               (GIC_CPU_MASK_SIMPLE(4) |
 138                                                IRQ_TYPE_LEVEL_HIGH)>;
 139                                 clocks = <&bpmp TEGRA194_CLK_APE>;
 140                                 clock-names = "clk";
 141                                 status = "disabled";
 142                         };
 143
 144                         tegra_ahub: ahub@2900800 {
 145                                 compatible = "nvidia,tegra194-ahub",
 146                                              "nvidia,tegra186-ahub";
 147                                 reg = <0x02900800 0x800>;
 148                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 149                                 clock-names = "ahub";
 150                                 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
 151                                 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 152                                 #address-cells = <1>;
 153                                 #size-cells = <1>;
 154                                 ranges = <0x02900800 0x02900800 0x11800>;
 155                                 status = "disabled";
 156
 157                                 tegra_admaif: admaif@290f000 {
 158                                         compatible = "nvidia,tegra194-admaif",
 159                                                      "nvidia,tegra186-admaif";
 160                                         reg = <0x0290f000 0x1000>;
 161                                         dmas = <&adma 1>, <&adma 1>,
 162                                                <&adma 2>, <&adma 2>,
 163                                                <&adma 3>, <&adma 3>,
 164                                                <&adma 4>, <&adma 4>,
 165                                                <&adma 5>, <&adma 5>,
 166                                                <&adma 6>, <&adma 6>,
 167                                                <&adma 7>, <&adma 7>,
 168                                                <&adma 8>, <&adma 8>,
 169                                                <&adma 9>, <&adma 9>,
 170                                                <&adma 10>, <&adma 10>,
 171                                                <&adma 11>, <&adma 11>,
 172                                                <&adma 12>, <&adma 12>,
 173                                                <&adma 13>, <&adma 13>,
 174                                                <&adma 14>, <&adma 14>,
 175                                                <&adma 15>, <&adma 15>,
 176                                                <&adma 16>, <&adma 16>,
 177                                                <&adma 17>, <&adma 17>,
 178                                                <&adma 18>, <&adma 18>,
 179                                                <&adma 19>, <&adma 19>,
 180                                                <&adma 20>, <&adma 20>;
 181                                         dma-names = "rx1", "tx1",
 182                                                     "rx2", "tx2",
 183                                                     "rx3", "tx3",
 184                                                     "rx4", "tx4",
 185                                                     "rx5", "tx5",
 186                                                     "rx6", "tx6",
 187                                                     "rx7", "tx7",
 188                                                     "rx8", "tx8",
 189                                                     "rx9", "tx9",
 190                                                     "rx10", "tx10",
 191                                                     "rx11", "tx11",
 192                                                     "rx12", "tx12",
 193                                                     "rx13", "tx13",
 194                                                     "rx14", "tx14",
 195                                                     "rx15", "tx15",
 196                                                     "rx16", "tx16",
 197                                                     "rx17", "tx17",
 198                                                     "rx18", "tx18",
 199                                                     "rx19", "tx19",
 200                                                     "rx20", "tx20";
 201                                         status = "disabled";
 202                                 };
 203
 204                                 tegra_i2s1: i2s@2901000 {
 205                                         compatible = "nvidia,tegra194-i2s",
 206                                                      "nvidia,tegra210-i2s";
 207                                         reg = <0x2901000 0x100>;
 208                                         clocks = <&bpmp TEGRA194_CLK_I2S1>,
 209                                                  <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
 210                                         clock-names = "i2s", "sync_input";
 211                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
 212                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 213                                         assigned-clock-rates = <1536000>;
 214                                         sound-name-prefix = "I2S1";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 tegra_i2s2: i2s@2901100 {
 219                                         compatible = "nvidia,tegra194-i2s",
 220                                                      "nvidia,tegra210-i2s";
 221                                         reg = <0x2901100 0x100>;
 222                                         clocks = <&bpmp TEGRA194_CLK_I2S2>,
 223                                                  <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
 224                                         clock-names = "i2s", "sync_input";
 225                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
 226                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 227                                         assigned-clock-rates = <1536000>;
 228                                         sound-name-prefix = "I2S2";
 229                                         status = "disabled";
 230                                 };
 231
 232                                 tegra_i2s3: i2s@2901200 {
 233                                         compatible = "nvidia,tegra194-i2s",
 234                                                      "nvidia,tegra210-i2s";
 235                                         reg = <0x2901200 0x100>;
 236                                         clocks = <&bpmp TEGRA194_CLK_I2S3>,
 237                                                  <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
 238                                         clock-names = "i2s", "sync_input";
 239                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
 240                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 241                                         assigned-clock-rates = <1536000>;
 242                                         sound-name-prefix = "I2S3";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 tegra_i2s4: i2s@2901300 {
 247                                         compatible = "nvidia,tegra194-i2s",
 248                                                      "nvidia,tegra210-i2s";
 249                                         reg = <0x2901300 0x100>;
 250                                         clocks = <&bpmp TEGRA194_CLK_I2S4>,
 251                                                  <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
 252                                         clock-names = "i2s", "sync_input";
 253                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
 254                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 255                                         assigned-clock-rates = <1536000>;
 256                                         sound-name-prefix = "I2S4";
 257                                         status = "disabled";
 258                                 };
 259
 260                                 tegra_i2s5: i2s@2901400 {
 261                                         compatible = "nvidia,tegra194-i2s",
 262                                                      "nvidia,tegra210-i2s";
 263                                         reg = <0x2901400 0x100>;
 264                                         clocks = <&bpmp TEGRA194_CLK_I2S5>,
 265                                                  <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
 266                                         clock-names = "i2s", "sync_input";
 267                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
 268                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 269                                         assigned-clock-rates = <1536000>;
 270                                         sound-name-prefix = "I2S5";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 tegra_i2s6: i2s@2901500 {
 275                                         compatible = "nvidia,tegra194-i2s",
 276                                                      "nvidia,tegra210-i2s";
 277                                         reg = <0x2901500 0x100>;
 278                                         clocks = <&bpmp TEGRA194_CLK_I2S6>,
 279                                                  <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
 280                                         clock-names = "i2s", "sync_input";
 281                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
 282                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 283                                         assigned-clock-rates = <1536000>;
 284                                         sound-name-prefix = "I2S6";
 285                                         status = "disabled";
 286                                 };
 287
 288                                 tegra_dmic1: dmic@2904000 {
 289                                         compatible = "nvidia,tegra194-dmic",
 290                                                      "nvidia,tegra210-dmic";
 291                                         reg = <0x2904000 0x100>;
 292                                         clocks = <&bpmp TEGRA194_CLK_DMIC1>;
 293                                         clock-names = "dmic";
 294                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
 295                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 296                                         assigned-clock-rates = <3072000>;
 297                                         sound-name-prefix = "DMIC1";
 298                                         status = "disabled";
 299                                 };
 300
 301                                 tegra_dmic2: dmic@2904100 {
 302                                         compatible = "nvidia,tegra194-dmic",
 303                                                      "nvidia,tegra210-dmic";
 304                                         reg = <0x2904100 0x100>;
 305                                         clocks = <&bpmp TEGRA194_CLK_DMIC2>;
 306                                         clock-names = "dmic";
 307                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
 308                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 309                                         assigned-clock-rates = <3072000>;
 310                                         sound-name-prefix = "DMIC2";
 311                                         status = "disabled";
 312                                 };
 313
 314                                 tegra_dmic3: dmic@2904200 {
 315                                         compatible = "nvidia,tegra194-dmic",
 316                                                      "nvidia,tegra210-dmic";
 317                                         reg = <0x2904200 0x100>;
 318                                         clocks = <&bpmp TEGRA194_CLK_DMIC3>;
 319                                         clock-names = "dmic";
 320                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
 321                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 322                                         assigned-clock-rates = <3072000>;
 323                                         sound-name-prefix = "DMIC3";
 324                                         status = "disabled";
 325                                 };
 326
 327                                 tegra_dmic4: dmic@2904300 {
 328                                         compatible = "nvidia,tegra194-dmic",
 329                                                      "nvidia,tegra210-dmic";
 330                                         reg = <0x2904300 0x100>;
 331                                         clocks = <&bpmp TEGRA194_CLK_DMIC4>;
 332                                         clock-names = "dmic";
 333                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
 334                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 335                                         assigned-clock-rates = <3072000>;
 336                                         sound-name-prefix = "DMIC4";
 337                                         status = "disabled";
 338                                 };
 339
 340                                 tegra_dspk1: dspk@2905000 {
 341                                         compatible = "nvidia,tegra194-dspk",
 342                                                      "nvidia,tegra186-dspk";
 343                                         reg = <0x2905000 0x100>;
 344                                         clocks = <&bpmp TEGRA194_CLK_DSPK1>;
 345                                         clock-names = "dspk";
 346                                         assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
 347                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 348                                         assigned-clock-rates = <12288000>;
 349                                         sound-name-prefix = "DSPK1";
 350                                         status = "disabled";
 351                                 };
 352
 353                                 tegra_dspk2: dspk@2905100 {
 354                                         compatible = "nvidia,tegra194-dspk",
 355                                                      "nvidia,tegra186-dspk";
 356                                         reg = <0x2905100 0x100>;
 357                                         clocks = <&bpmp TEGRA194_CLK_DSPK2>;
 358                                         clock-names = "dspk";
 359                                         assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
 360                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 361                                         assigned-clock-rates = <12288000>;
 362                                         sound-name-prefix = "DSPK2";
 363                                         status = "disabled";
 364                                 };
 365                         };
 366                 };
 367
 368                 pinmux: pinmux@2430000 {
 369                         compatible = "nvidia,tegra194-pinmux";
 370                         reg = <0x2430000 0x17000>,
 371                               <0xc300000 0x4000>;
 372
 373                         status = "okay";
 374
 375                         pex_rst_c5_out_state: pex_rst_c5_out {
 376                                 pex_rst {
 377                                         nvidia,pins = "pex_l5_rst_n_pgg1";
 378                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 379                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 380                                         nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 381                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 382                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 383                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 384                                 };
 385                         };
 386
 387                         clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
 388                                 clkreq {
 389                                         nvidia,pins = "pex_l5_clkreq_n_pgg0";
 390                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 391                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 392                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 393                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 394                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 395                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 396                                 };
 397                         };
 398                 };
 399
 400                 mc: memory-controller@2c00000 {
 401                         compatible = "nvidia,tegra194-mc";
 402                         reg = <0x02c00000 0x100000>,
 403                               <0x02b80000 0x040000>,
 404                               <0x01700000 0x100000>;
 405                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 406                         #interconnect-cells = <1>;
 407                         status = "disabled";
 408
 409                         #address-cells = <2>;
 410                         #size-cells = <2>;
 411
 412                         ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
 413                                  <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
 414                                  <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
 415
 416                         /*
 417                          * Bit 39 of addresses passing through the memory
 418                          * controller selects the XBAR format used when memory
 419                          * is accessed. This is used to transparently access
 420                          * memory in the XBAR format used by the discrete GPU
 421                          * (bit 39 set) or Tegra (bit 39 clear).
 422                          *
 423                          * As a consequence, the operating system must ensure
 424                          * that bit 39 is never used implicitly, for example
 425                          * via an I/O virtual address mapping of an IOMMU. If
 426                          * devices require access to the XBAR switch, their
 427                          * drivers must set this bit explicitly.
 428                          *
 429                          * Limit the DMA range for memory clients to [38:0].
 430                          */
 431                         dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
 432
 433                         emc: external-memory-controller@2c60000 {
 434                                 compatible = "nvidia,tegra194-emc";
 435                                 reg = <0x0 0x02c60000 0x0 0x90000>,
 436                                       <0x0 0x01780000 0x0 0x80000>;
 437                                 clocks = <&bpmp TEGRA194_CLK_EMC>;
 438                                 clock-names = "emc";
 439
 440                                 #interconnect-cells = <0>;
 441
 442                                 nvidia,bpmp = <&bpmp>;
 443                         };
 444                 };
 445
 446                 uarta: serial@3100000 {
 447                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 448                         reg = <0x03100000 0x40>;
 449                         reg-shift = <2>;
 450                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
 452                         clock-names = "serial";
 453                         resets = <&bpmp TEGRA194_RESET_UARTA>;
 454                         reset-names = "serial";
 455                         status = "disabled";
 456                 };
 457
 458                 uartb: serial@3110000 {
 459                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 460                         reg = <0x03110000 0x40>;
 461                         reg-shift = <2>;
 462                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
 464                         clock-names = "serial";
 465                         resets = <&bpmp TEGRA194_RESET_UARTB>;
 466                         reset-names = "serial";
 467                         status = "disabled";
 468                 };
 469
 470                 uartd: serial@3130000 {
 471                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 472                         reg = <0x03130000 0x40>;
 473                         reg-shift = <2>;
 474                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 475                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
 476                         clock-names = "serial";
 477                         resets = <&bpmp TEGRA194_RESET_UARTD>;
 478                         reset-names = "serial";
 479                         status = "disabled";
 480                 };
 481
 482                 uarte: serial@3140000 {
 483                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 484                         reg = <0x03140000 0x40>;
 485                         reg-shift = <2>;
 486                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 488                         clock-names = "serial";
 489                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 490                         reset-names = "serial";
 491                         status = "disabled";
 492                 };
 493
 494                 uartf: serial@3150000 {
 495                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 496                         reg = <0x03150000 0x40>;
 497                         reg-shift = <2>;
 498                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 500                         clock-names = "serial";
 501                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 502                         reset-names = "serial";
 503                         status = "disabled";
 504                 };
 505
 506                 gen1_i2c: i2c@3160000 {
 507                         compatible = "nvidia,tegra194-i2c";
 508                         reg = <0x03160000 0x10000>;
 509                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 513                         clock-names = "div-clk";
 514                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 515                         reset-names = "i2c";
 516                         status = "disabled";
 517                 };
 518
 519                 uarth: serial@3170000 {
 520                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 521                         reg = <0x03170000 0x40>;
 522                         reg-shift = <2>;
 523                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 525                         clock-names = "serial";
 526                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 527                         reset-names = "serial";
 528                         status = "disabled";
 529                 };
 530
 531                 cam_i2c: i2c@3180000 {
 532                         compatible = "nvidia,tegra194-i2c";
 533                         reg = <0x03180000 0x10000>;
 534                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 538                         clock-names = "div-clk";
 539                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 540                         reset-names = "i2c";
 541                         status = "disabled";
 542                 };
 543
 544                 /* shares pads with dpaux1 */
 545                 dp_aux_ch1_i2c: i2c@3190000 {
 546                         compatible = "nvidia,tegra194-i2c";
 547                         reg = <0x03190000 0x10000>;
 548                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 552                         clock-names = "div-clk";
 553                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 554                         reset-names = "i2c";
 555                         pinctrl-0 = <&state_dpaux1_i2c>;
 556                         pinctrl-1 = <&state_dpaux1_off>;
 557                         pinctrl-names = "default", "idle";
 558                         status = "disabled";
 559                 };
 560
 561                 /* shares pads with dpaux0 */
 562                 dp_aux_ch0_i2c: i2c@31b0000 {
 563                         compatible = "nvidia,tegra194-i2c";
 564                         reg = <0x031b0000 0x10000>;
 565                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 569                         clock-names = "div-clk";
 570                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 571                         reset-names = "i2c";
 572                         pinctrl-0 = <&state_dpaux0_i2c>;
 573                         pinctrl-1 = <&state_dpaux0_off>;
 574                         pinctrl-names = "default", "idle";
 575                         status = "disabled";
 576                 };
 577
 578                 /* shares pads with dpaux2 */
 579                 dp_aux_ch2_i2c: i2c@31c0000 {
 580                         compatible = "nvidia,tegra194-i2c";
 581                         reg = <0x031c0000 0x10000>;
 582                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 586                         clock-names = "div-clk";
 587                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 588                         reset-names = "i2c";
 589                         pinctrl-0 = <&state_dpaux2_i2c>;
 590                         pinctrl-1 = <&state_dpaux2_off>;
 591                         pinctrl-names = "default", "idle";
 592                         status = "disabled";
 593                 };
 594
 595                 /* shares pads with dpaux3 */
 596                 dp_aux_ch3_i2c: i2c@31e0000 {
 597                         compatible = "nvidia,tegra194-i2c";
 598                         reg = <0x031e0000 0x10000>;
 599                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 603                         clock-names = "div-clk";
 604                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 605                         reset-names = "i2c";
 606                         pinctrl-0 = <&state_dpaux3_i2c>;
 607                         pinctrl-1 = <&state_dpaux3_off>;
 608                         pinctrl-names = "default", "idle";
 609                         status = "disabled";
 610                 };
 611
 612                 spi@3270000 {
 613                         compatible = "nvidia,tegra194-qspi";
 614                         reg = <0x3270000 0x1000>;
 615                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         clocks = <&bpmp TEGRA194_CLK_QSPI0>,
 619                                  <&bpmp TEGRA194_CLK_QSPI0_PM>;
 620                         clock-names = "qspi", "qspi_out";
 621                         resets = <&bpmp TEGRA194_RESET_QSPI0>;
 622                         reset-names = "qspi";
 623                         status = "disabled";
 624                 };
 625
 626                 spi@3300000 {
 627                         compatible = "nvidia,tegra194-qspi";
 628                         reg = <0x3300000 0x1000>;
 629                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                         clocks = <&bpmp TEGRA194_CLK_QSPI1>,
 633                                  <&bpmp TEGRA194_CLK_QSPI1_PM>;
 634                         clock-names = "qspi", "qspi_out";
 635                         resets = <&bpmp TEGRA194_RESET_QSPI1>;
 636                         reset-names = "qspi";
 637                         status = "disabled";
 638                 };
 639
 640                 pwm1: pwm@3280000 {
 641                         compatible = "nvidia,tegra194-pwm",
 642                                      "nvidia,tegra186-pwm";
 643                         reg = <0x3280000 0x10000>;
 644                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 645                         clock-names = "pwm";
 646                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 647                         reset-names = "pwm";
 648                         status = "disabled";
 649                         #pwm-cells = <2>;
 650                 };
 651
 652                 pwm2: pwm@3290000 {
 653                         compatible = "nvidia,tegra194-pwm",
 654                                      "nvidia,tegra186-pwm";
 655                         reg = <0x3290000 0x10000>;
 656                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 657                         clock-names = "pwm";
 658                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 659                         reset-names = "pwm";
 660                         status = "disabled";
 661                         #pwm-cells = <2>;
 662                 };
 663
 664                 pwm3: pwm@32a0000 {
 665                         compatible = "nvidia,tegra194-pwm",
 666                                      "nvidia,tegra186-pwm";
 667                         reg = <0x32a0000 0x10000>;
 668                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 669                         clock-names = "pwm";
 670                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 671                         reset-names = "pwm";
 672                         status = "disabled";
 673                         #pwm-cells = <2>;
 674                 };
 675
 676                 pwm5: pwm@32c0000 {
 677                         compatible = "nvidia,tegra194-pwm",
 678                                      "nvidia,tegra186-pwm";
 679                         reg = <0x32c0000 0x10000>;
 680                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 681                         clock-names = "pwm";
 682                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 683                         reset-names = "pwm";
 684                         status = "disabled";
 685                         #pwm-cells = <2>;
 686                 };
 687
 688                 pwm6: pwm@32d0000 {
 689                         compatible = "nvidia,tegra194-pwm",
 690                                      "nvidia,tegra186-pwm";
 691                         reg = <0x32d0000 0x10000>;
 692                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 693                         clock-names = "pwm";
 694                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 695                         reset-names = "pwm";
 696                         status = "disabled";
 697                         #pwm-cells = <2>;
 698                 };
 699
 700                 pwm7: pwm@32e0000 {
 701                         compatible = "nvidia,tegra194-pwm",
 702                                      "nvidia,tegra186-pwm";
 703                         reg = <0x32e0000 0x10000>;
 704                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 705                         clock-names = "pwm";
 706                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 707                         reset-names = "pwm";
 708                         status = "disabled";
 709                         #pwm-cells = <2>;
 710                 };
 711
 712                 pwm8: pwm@32f0000 {
 713                         compatible = "nvidia,tegra194-pwm",
 714                                      "nvidia,tegra186-pwm";
 715                         reg = <0x32f0000 0x10000>;
 716                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 717                         clock-names = "pwm";
 718                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 719                         reset-names = "pwm";
 720                         status = "disabled";
 721                         #pwm-cells = <2>;
 722                 };
 723
 724                 sdmmc1: mmc@3400000 {
 725                         compatible = "nvidia,tegra194-sdhci";
 726                         reg = <0x03400000 0x10000>;
 727                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 728                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
 729                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 730                         clock-names = "sdhci", "tmclk";
 731                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 732                         reset-names = "sdhci";
 733                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
 734                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
 735                         interconnect-names = "dma-mem", "write";
 736                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 737                                                                         <0x07>;
 738                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 739                                                                         <0x07>;
 740                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 741                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 742                                                                         <0x07>;
 743                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 744                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 745                         nvidia,default-tap = <0x9>;
 746                         nvidia,default-trim = <0x5>;
 747                         status = "disabled";
 748                 };
 749
 750                 sdmmc3: mmc@3440000 {
 751                         compatible = "nvidia,tegra194-sdhci";
 752                         reg = <0x03440000 0x10000>;
 753                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 754                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
 755                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 756                         clock-names = "sdhci", "tmclk";
 757                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 758                         reset-names = "sdhci";
 759                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
 760                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
 761                         interconnect-names = "dma-mem", "write";
 762                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 763                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 764                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 765                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 766                                                                         <0x07>;
 767                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 768                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 769                                                                         <0x07>;
 770                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 771                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 772                         nvidia,default-tap = <0x9>;
 773                         nvidia,default-trim = <0x5>;
 774                         status = "disabled";
 775                 };
 776
 777                 sdmmc4: mmc@3460000 {
 778                         compatible = "nvidia,tegra194-sdhci";
 779                         reg = <0x03460000 0x10000>;
 780                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 781                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 782                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 783                         clock-names = "sdhci", "tmclk";
 784                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 785                                           <&bpmp TEGRA194_CLK_PLLC4>;
 786                         assigned-clock-parents =
 787                                           <&bpmp TEGRA194_CLK_PLLC4>;
 788                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 789                         reset-names = "sdhci";
 790                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
 791                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
 792                         interconnect-names = "dma-mem", "write";
 793                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 794                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 795                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 796                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 797                                                                         <0x0a>;
 798                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 799                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 800                                                                         <0x0a>;
 801                         nvidia,default-tap = <0x8>;
 802                         nvidia,default-trim = <0x14>;
 803                         nvidia,dqs-trim = <40>;
 804                         supports-cqe;
 805                         status = "disabled";
 806                 };
 807
 808                 hda@3510000 {
 809                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 810                         reg = <0x3510000 0x10000>;
 811                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 813                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
 814                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
 815                         clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 816                         resets = <&bpmp TEGRA194_RESET_HDA>,
 817                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
 818                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
 819                         reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 820                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 821                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
 822                                         <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
 823                         interconnect-names = "dma-mem", "write";
 824                         status = "disabled";
 825                 };
 826
 827                 xusb_padctl: padctl@3520000 {
 828                         compatible = "nvidia,tegra194-xusb-padctl";
 829                         reg = <0x03520000 0x1000>,
 830                               <0x03540000 0x1000>;
 831                         reg-names = "padctl", "ao";
 832                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 833
 834                         resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
 835                         reset-names = "padctl";
 836
 837                         status = "disabled";
 838
 839                         pads {
 840                                 usb2 {
 841                                         clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
 842                                         clock-names = "trk";
 843
 844                                         lanes {
 845                                                 usb2-0 {
 846                                                         nvidia,function = "xusb";
 847                                                         status = "disabled";
 848                                                         #phy-cells = <0>;
 849                                                 };
 850
 851                                                 usb2-1 {
 852                                                         nvidia,function = "xusb";
 853                                                         status = "disabled";
 854                                                         #phy-cells = <0>;
 855                                                 };
 856
 857                                                 usb2-2 {
 858                                                         nvidia,function = "xusb";
 859                                                         status = "disabled";
 860                                                         #phy-cells = <0>;
 861                                                 };
 862
 863                                                 usb2-3 {
 864                                                         nvidia,function = "xusb";
 865                                                         status = "disabled";
 866                                                         #phy-cells = <0>;
 867                                                 };
 868                                         };
 869                                 };
 870
 871                                 usb3 {
 872                                         lanes {
 873                                                 usb3-0 {
 874                                                         nvidia,function = "xusb";
 875                                                         status = "disabled";
 876                                                         #phy-cells = <0>;
 877                                                 };
 878
 879                                                 usb3-1 {
 880                                                         nvidia,function = "xusb";
 881                                                         status = "disabled";
 882                                                         #phy-cells = <0>;
 883                                                 };
 884
 885                                                 usb3-2 {
 886                                                         nvidia,function = "xusb";
 887                                                         status = "disabled";
 888                                                         #phy-cells = <0>;
 889                                                 };
 890
 891                                                 usb3-3 {
 892                                                         nvidia,function = "xusb";
 893                                                         status = "disabled";
 894                                                         #phy-cells = <0>;
 895                                                 };
 896                                         };
 897                                 };
 898                         };
 899
 900                         ports {
 901                                 usb2-0 {
 902                                         status = "disabled";
 903                                 };
 904
 905                                 usb2-1 {
 906                                         status = "disabled";
 907                                 };
 908
 909                                 usb2-2 {
 910                                         status = "disabled";
 911                                 };
 912
 913                                 usb2-3 {
 914                                         status = "disabled";
 915                                 };
 916
 917                                 usb3-0 {
 918                                         status = "disabled";
 919                                 };
 920
 921                                 usb3-1 {
 922                                         status = "disabled";
 923                                 };
 924
 925                                 usb3-2 {
 926                                         status = "disabled";
 927                                 };
 928
 929                                 usb3-3 {
 930                                         status = "disabled";
 931                                 };
 932                         };
 933                 };
 934
 935                 usb@3550000 {
 936                         compatible = "nvidia,tegra194-xudc";
 937                         reg = <0x03550000 0x8000>,
 938                               <0x03558000 0x1000>;
 939                         reg-names = "base", "fpci";
 940                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 941                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
 942                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
 943                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
 944                                  <&bpmp TEGRA194_CLK_XUSB_FS>;
 945                         clock-names = "dev", "ss", "ss_src", "fs_src";
 946                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
 947                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
 948                         power-domain-names = "dev", "ss";
 949                         nvidia,xusb-padctl = <&xusb_padctl>;
 950                         status = "disabled";
 951                 };
 952
 953                 usb@3610000 {
 954                         compatible = "nvidia,tegra194-xusb";
 955                         reg = <0x03610000 0x40000>,
 956                               <0x03600000 0x10000>;
 957                         reg-names = "hcd", "fpci";
 958
 959                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 960                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 961
 962                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
 963                                  <&bpmp TEGRA194_CLK_XUSB_FALCON>,
 964                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
 965                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
 966                                  <&bpmp TEGRA194_CLK_CLK_M>,
 967                                  <&bpmp TEGRA194_CLK_XUSB_FS>,
 968                                  <&bpmp TEGRA194_CLK_UTMIPLL>,
 969                                  <&bpmp TEGRA194_CLK_CLK_M>,
 970                                  <&bpmp TEGRA194_CLK_PLLE>;
 971                         clock-names = "xusb_host", "xusb_falcon_src",
 972                                       "xusb_ss", "xusb_ss_src", "xusb_hs_src",
 973                                       "xusb_fs_src", "pll_u_480m", "clk_m",
 974                                       "pll_e";
 975
 976                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
 977                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
 978                         power-domain-names = "xusb_host", "xusb_ss";
 979
 980                         nvidia,xusb-padctl = <&xusb_padctl>;
 981                         status = "disabled";
 982                 };
 983
 984                 fuse@3820000 {
 985                         compatible = "nvidia,tegra194-efuse";
 986                         reg = <0x03820000 0x10000>;
 987                         clocks = <&bpmp TEGRA194_CLK_FUSE>;
 988                         clock-names = "fuse";
 989                 };
 990
 991                 gic: interrupt-controller@3881000 {
 992                         compatible = "arm,gic-400";
 993                         #interrupt-cells = <3>;
 994                         interrupt-controller;
 995                         reg = <0x03881000 0x1000>,
 996                               <0x03882000 0x2000>,
 997                               <0x03884000 0x2000>,
 998                               <0x03886000 0x2000>;
 999                         interrupts = <GIC_PPI 9
1000                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1001                         interrupt-parent = <&gic>;
1002                 };
1003
1004                 cec@3960000 {
1005                         compatible = "nvidia,tegra194-cec";
1006                         reg = <0x03960000 0x10000>;
1007                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1008                         clocks = <&bpmp TEGRA194_CLK_CEC>;
1009                         clock-names = "cec";
1010                         status = "disabled";
1011                 };
1012
1013                 hsp_top0: hsp@3c00000 {
1014                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1015                         reg = <0x03c00000 0xa0000>;
1016                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1017                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1018                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1019                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1020                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1021                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1022                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1023                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1024                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1025                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1026                                           "shared3", "shared4", "shared5", "shared6",
1027                                           "shared7";
1028                         #mbox-cells = <2>;
1029                 };
1030
1031                 p2u_hsio_0: phy@3e10000 {
1032                         compatible = "nvidia,tegra194-p2u";
1033                         reg = <0x03e10000 0x10000>;
1034                         reg-names = "ctl";
1035
1036                         #phy-cells = <0>;
1037                 };
1038
1039                 p2u_hsio_1: phy@3e20000 {
1040                         compatible = "nvidia,tegra194-p2u";
1041                         reg = <0x03e20000 0x10000>;
1042                         reg-names = "ctl";
1043
1044                         #phy-cells = <0>;
1045                 };
1046
1047                 p2u_hsio_2: phy@3e30000 {
1048                         compatible = "nvidia,tegra194-p2u";
1049                         reg = <0x03e30000 0x10000>;
1050                         reg-names = "ctl";
1051
1052                         #phy-cells = <0>;
1053                 };
1054
1055                 p2u_hsio_3: phy@3e40000 {
1056                         compatible = "nvidia,tegra194-p2u";
1057                         reg = <0x03e40000 0x10000>;
1058                         reg-names = "ctl";
1059
1060                         #phy-cells = <0>;
1061                 };
1062
1063                 p2u_hsio_4: phy@3e50000 {
1064                         compatible = "nvidia,tegra194-p2u";
1065                         reg = <0x03e50000 0x10000>;
1066                         reg-names = "ctl";
1067
1068                         #phy-cells = <0>;
1069                 };
1070
1071                 p2u_hsio_5: phy@3e60000 {
1072                         compatible = "nvidia,tegra194-p2u";
1073                         reg = <0x03e60000 0x10000>;
1074                         reg-names = "ctl";
1075
1076                         #phy-cells = <0>;
1077                 };
1078
1079                 p2u_hsio_6: phy@3e70000 {
1080                         compatible = "nvidia,tegra194-p2u";
1081                         reg = <0x03e70000 0x10000>;
1082                         reg-names = "ctl";
1083
1084                         #phy-cells = <0>;
1085                 };
1086
1087                 p2u_hsio_7: phy@3e80000 {
1088                         compatible = "nvidia,tegra194-p2u";
1089                         reg = <0x03e80000 0x10000>;
1090                         reg-names = "ctl";
1091
1092                         #phy-cells = <0>;
1093                 };
1094
1095                 p2u_hsio_8: phy@3e90000 {
1096                         compatible = "nvidia,tegra194-p2u";
1097                         reg = <0x03e90000 0x10000>;
1098                         reg-names = "ctl";
1099
1100                         #phy-cells = <0>;
1101                 };
1102
1103                 p2u_hsio_9: phy@3ea0000 {
1104                         compatible = "nvidia,tegra194-p2u";
1105                         reg = <0x03ea0000 0x10000>;
1106                         reg-names = "ctl";
1107
1108                         #phy-cells = <0>;
1109                 };
1110
1111                 p2u_nvhs_0: phy@3eb0000 {
1112                         compatible = "nvidia,tegra194-p2u";
1113                         reg = <0x03eb0000 0x10000>;
1114                         reg-names = "ctl";
1115
1116                         #phy-cells = <0>;
1117                 };
1118
1119                 p2u_nvhs_1: phy@3ec0000 {
1120                         compatible = "nvidia,tegra194-p2u";
1121                         reg = <0x03ec0000 0x10000>;
1122                         reg-names = "ctl";
1123
1124                         #phy-cells = <0>;
1125                 };
1126
1127                 p2u_nvhs_2: phy@3ed0000 {
1128                         compatible = "nvidia,tegra194-p2u";
1129                         reg = <0x03ed0000 0x10000>;
1130                         reg-names = "ctl";
1131
1132                         #phy-cells = <0>;
1133                 };
1134
1135                 p2u_nvhs_3: phy@3ee0000 {
1136                         compatible = "nvidia,tegra194-p2u";
1137                         reg = <0x03ee0000 0x10000>;
1138                         reg-names = "ctl";
1139
1140                         #phy-cells = <0>;
1141                 };
1142
1143                 p2u_nvhs_4: phy@3ef0000 {
1144                         compatible = "nvidia,tegra194-p2u";
1145                         reg = <0x03ef0000 0x10000>;
1146                         reg-names = "ctl";
1147
1148                         #phy-cells = <0>;
1149                 };
1150
1151                 p2u_nvhs_5: phy@3f00000 {
1152                         compatible = "nvidia,tegra194-p2u";
1153                         reg = <0x03f00000 0x10000>;
1154                         reg-names = "ctl";
1155
1156                         #phy-cells = <0>;
1157                 };
1158
1159                 p2u_nvhs_6: phy@3f10000 {
1160                         compatible = "nvidia,tegra194-p2u";
1161                         reg = <0x03f10000 0x10000>;
1162                         reg-names = "ctl";
1163
1164                         #phy-cells = <0>;
1165                 };
1166
1167                 p2u_nvhs_7: phy@3f20000 {
1168                         compatible = "nvidia,tegra194-p2u";
1169                         reg = <0x03f20000 0x10000>;
1170                         reg-names = "ctl";
1171
1172                         #phy-cells = <0>;
1173                 };
1174
1175                 p2u_hsio_10: phy@3f30000 {
1176                         compatible = "nvidia,tegra194-p2u";
1177                         reg = <0x03f30000 0x10000>;
1178                         reg-names = "ctl";
1179
1180                         #phy-cells = <0>;
1181                 };
1182
1183                 p2u_hsio_11: phy@3f40000 {
1184                         compatible = "nvidia,tegra194-p2u";
1185                         reg = <0x03f40000 0x10000>;
1186                         reg-names = "ctl";
1187
1188                         #phy-cells = <0>;
1189                 };
1190
1191                 hsp_aon: hsp@c150000 {
1192                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1193                         reg = <0x0c150000 0x90000>;
1194                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1198                         /*
1199                          * Shared interrupt 0 is routed only to AON/SPE, so
1200                          * we only have 4 shared interrupts for the CCPLEX.
1201                          */
1202                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
1203                         #mbox-cells = <2>;
1204                 };
1205
1206                 gen2_i2c: i2c@c240000 {
1207                         compatible = "nvidia,tegra194-i2c";
1208                         reg = <0x0c240000 0x10000>;
1209                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1210                         #address-cells = <1>;
1211                         #size-cells = <0>;
1212                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
1213                         clock-names = "div-clk";
1214                         resets = <&bpmp TEGRA194_RESET_I2C2>;
1215                         reset-names = "i2c";
1216                         status = "disabled";
1217                 };
1218
1219                 gen8_i2c: i2c@c250000 {
1220                         compatible = "nvidia,tegra194-i2c";
1221                         reg = <0x0c250000 0x10000>;
1222                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1223                         #address-cells = <1>;
1224                         #size-cells = <0>;
1225                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
1226                         clock-names = "div-clk";
1227                         resets = <&bpmp TEGRA194_RESET_I2C8>;
1228                         reset-names = "i2c";
1229                         status = "disabled";
1230                 };
1231
1232                 uartc: serial@c280000 {
1233                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1234                         reg = <0x0c280000 0x40>;
1235                         reg-shift = <2>;
1236                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1237                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
1238                         clock-names = "serial";
1239                         resets = <&bpmp TEGRA194_RESET_UARTC>;
1240                         reset-names = "serial";
1241                         status = "disabled";
1242                 };
1243
1244                 uartg: serial@c290000 {
1245                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1246                         reg = <0x0c290000 0x40>;
1247                         reg-shift = <2>;
1248                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1249                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
1250                         clock-names = "serial";
1251                         resets = <&bpmp TEGRA194_RESET_UARTG>;
1252                         reset-names = "serial";
1253                         status = "disabled";
1254                 };
1255
1256                 rtc: rtc@c2a0000 {
1257                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1258                         reg = <0x0c2a0000 0x10000>;
1259                         interrupt-parent = <&pmc>;
1260                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1261                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1262                         clock-names = "rtc";
1263                         status = "disabled";
1264                 };
1265
1266                 gpio_aon: gpio@c2f0000 {
1267                         compatible = "nvidia,tegra194-gpio-aon";
1268                         reg-names = "security", "gpio";
1269                         reg = <0xc2f0000 0x1000>,
1270                               <0xc2f1000 0x1000>;
1271                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1272                         gpio-controller;
1273                         #gpio-cells = <2>;
1274                         interrupt-controller;
1275                         #interrupt-cells = <2>;
1276                 };
1277
1278                 pwm4: pwm@c340000 {
1279                         compatible = "nvidia,tegra194-pwm",
1280                                      "nvidia,tegra186-pwm";
1281                         reg = <0xc340000 0x10000>;
1282                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
1283                         clock-names = "pwm";
1284                         resets = <&bpmp TEGRA194_RESET_PWM4>;
1285                         reset-names = "pwm";
1286                         status = "disabled";
1287                         #pwm-cells = <2>;
1288                 };
1289
1290                 pmc: pmc@c360000 {
1291                         compatible = "nvidia,tegra194-pmc";
1292                         reg = <0x0c360000 0x10000>,
1293                               <0x0c370000 0x10000>,
1294                               <0x0c380000 0x10000>,
1295                               <0x0c390000 0x10000>,
1296                               <0x0c3a0000 0x10000>;
1297                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1298
1299                         #interrupt-cells = <2>;
1300                         interrupt-controller;
1301                 };
1302
1303                 host1x@13e00000 {
1304                         compatible = "nvidia,tegra194-host1x";
1305                         reg = <0x13e00000 0x10000>,
1306                               <0x13e10000 0x10000>;
1307                         reg-names = "hypervisor", "vm";
1308                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1309                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1310                         interrupt-names = "syncpt", "host1x";
1311                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1312                         clock-names = "host1x";
1313                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
1314                         reset-names = "host1x";
1315
1316                         #address-cells = <1>;
1317                         #size-cells = <1>;
1318
1319                         ranges = <0x15000000 0x15000000 0x01000000>;
1320                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1321                         interconnect-names = "dma-mem";
1322
1323                         display-hub@15200000 {
1324                                 compatible = "nvidia,tegra194-display";
1325                                 reg = <0x15200000 0x00040000>;
1326                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1327                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1328                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1329                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1330                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1331                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1332                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1333                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1334                                               "wgrp3", "wgrp4", "wgrp5";
1335                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1336                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1337                                 clock-names = "disp", "hub";
1338                                 status = "disabled";
1339
1340                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1341
1342                                 #address-cells = <1>;
1343                                 #size-cells = <1>;
1344
1345                                 ranges = <0x15200000 0x15200000 0x40000>;
1346
1347                                 display@15200000 {
1348                                         compatible = "nvidia,tegra194-dc";
1349                                         reg = <0x15200000 0x10000>;
1350                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1351                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1352                                         clock-names = "dc";
1353                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1354                                         reset-names = "dc";
1355
1356                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1357                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1358                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1359                                         interconnect-names = "dma-mem", "read-1";
1360
1361                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1362                                         nvidia,head = <0>;
1363                                 };
1364
1365                                 display@15210000 {
1366                                         compatible = "nvidia,tegra194-dc";
1367                                         reg = <0x15210000 0x10000>;
1368                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1369                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1370                                         clock-names = "dc";
1371                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1372                                         reset-names = "dc";
1373
1374                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1375                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1376                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1377                                         interconnect-names = "dma-mem", "read-1";
1378
1379                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1380                                         nvidia,head = <1>;
1381                                 };
1382
1383                                 display@15220000 {
1384                                         compatible = "nvidia,tegra194-dc";
1385                                         reg = <0x15220000 0x10000>;
1386                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1387                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1388                                         clock-names = "dc";
1389                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1390                                         reset-names = "dc";
1391
1392                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1393                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1394                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1395                                         interconnect-names = "dma-mem", "read-1";
1396
1397                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1398                                         nvidia,head = <2>;
1399                                 };
1400
1401                                 display@15230000 {
1402                                         compatible = "nvidia,tegra194-dc";
1403                                         reg = <0x15230000 0x10000>;
1404                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1405                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1406                                         clock-names = "dc";
1407                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1408                                         reset-names = "dc";
1409
1410                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1411                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1412                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1413                                         interconnect-names = "dma-mem", "read-1";
1414
1415                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1416                                         nvidia,head = <3>;
1417                                 };
1418                         };
1419
1420                         vic@15340000 {
1421                                 compatible = "nvidia,tegra194-vic";
1422                                 reg = <0x15340000 0x00040000>;
1423                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1424                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
1425                                 clock-names = "vic";
1426                                 resets = <&bpmp TEGRA194_RESET_VIC>;
1427                                 reset-names = "vic";
1428
1429                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1430                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1431                                                 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1432                                 interconnect-names = "dma-mem", "write";
1433                         };
1434
1435                         dpaux0: dpaux@155c0000 {
1436                                 compatible = "nvidia,tegra194-dpaux";
1437                                 reg = <0x155c0000 0x10000>;
1438                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1439                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1440                                          <&bpmp TEGRA194_CLK_PLLDP>;
1441                                 clock-names = "dpaux", "parent";
1442                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
1443                                 reset-names = "dpaux";
1444                                 status = "disabled";
1445
1446                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1447
1448                                 state_dpaux0_aux: pinmux-aux {
1449                                         groups = "dpaux-io";
1450                                         function = "aux";
1451                                 };
1452
1453                                 state_dpaux0_i2c: pinmux-i2c {
1454                                         groups = "dpaux-io";
1455                                         function = "i2c";
1456                                 };
1457
1458                                 state_dpaux0_off: pinmux-off {
1459                                         groups = "dpaux-io";
1460                                         function = "off";
1461                                 };
1462
1463                                 i2c-bus {
1464                                         #address-cells = <1>;
1465                                         #size-cells = <0>;
1466                                 };
1467                         };
1468
1469                         dpaux1: dpaux@155d0000 {
1470                                 compatible = "nvidia,tegra194-dpaux";
1471                                 reg = <0x155d0000 0x10000>;
1472                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1473                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1474                                          <&bpmp TEGRA194_CLK_PLLDP>;
1475                                 clock-names = "dpaux", "parent";
1476                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1477                                 reset-names = "dpaux";
1478                                 status = "disabled";
1479
1480                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1481
1482                                 state_dpaux1_aux: pinmux-aux {
1483                                         groups = "dpaux-io";
1484                                         function = "aux";
1485                                 };
1486
1487                                 state_dpaux1_i2c: pinmux-i2c {
1488                                         groups = "dpaux-io";
1489                                         function = "i2c";
1490                                 };
1491
1492                                 state_dpaux1_off: pinmux-off {
1493                                         groups = "dpaux-io";
1494                                         function = "off";
1495                                 };
1496
1497                                 i2c-bus {
1498                                         #address-cells = <1>;
1499                                         #size-cells = <0>;
1500                                 };
1501                         };
1502
1503                         dpaux2: dpaux@155e0000 {
1504                                 compatible = "nvidia,tegra194-dpaux";
1505                                 reg = <0x155e0000 0x10000>;
1506                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1507                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1508                                          <&bpmp TEGRA194_CLK_PLLDP>;
1509                                 clock-names = "dpaux", "parent";
1510                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1511                                 reset-names = "dpaux";
1512                                 status = "disabled";
1513
1514                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1515
1516                                 state_dpaux2_aux: pinmux-aux {
1517                                         groups = "dpaux-io";
1518                                         function = "aux";
1519                                 };
1520
1521                                 state_dpaux2_i2c: pinmux-i2c {
1522                                         groups = "dpaux-io";
1523                                         function = "i2c";
1524                                 };
1525
1526                                 state_dpaux2_off: pinmux-off {
1527                                         groups = "dpaux-io";
1528                                         function = "off";
1529                                 };
1530
1531                                 i2c-bus {
1532                                         #address-cells = <1>;
1533                                         #size-cells = <0>;
1534                                 };
1535                         };
1536
1537                         dpaux3: dpaux@155f0000 {
1538                                 compatible = "nvidia,tegra194-dpaux";
1539                                 reg = <0x155f0000 0x10000>;
1540                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1541                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1542                                          <&bpmp TEGRA194_CLK_PLLDP>;
1543                                 clock-names = "dpaux", "parent";
1544                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1545                                 reset-names = "dpaux";
1546                                 status = "disabled";
1547
1548                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1549
1550                                 state_dpaux3_aux: pinmux-aux {
1551                                         groups = "dpaux-io";
1552                                         function = "aux";
1553                                 };
1554
1555                                 state_dpaux3_i2c: pinmux-i2c {
1556                                         groups = "dpaux-io";
1557                                         function = "i2c";
1558                                 };
1559
1560                                 state_dpaux3_off: pinmux-off {
1561                                         groups = "dpaux-io";
1562                                         function = "off";
1563                                 };
1564
1565                                 i2c-bus {
1566                                         #address-cells = <1>;
1567                                         #size-cells = <0>;
1568                                 };
1569                         };
1570
1571                         sor0: sor@15b00000 {
1572                                 compatible = "nvidia,tegra194-sor";
1573                                 reg = <0x15b00000 0x40000>;
1574                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1575                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1576                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
1577                                          <&bpmp TEGRA194_CLK_PLLD>,
1578                                          <&bpmp TEGRA194_CLK_PLLDP>,
1579                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1580                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1581                                 clock-names = "sor", "out", "parent", "dp", "safe",
1582                                               "pad";
1583                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
1584                                 reset-names = "sor";
1585                                 pinctrl-0 = <&state_dpaux0_aux>;
1586                                 pinctrl-1 = <&state_dpaux0_i2c>;
1587                                 pinctrl-2 = <&state_dpaux0_off>;
1588                                 pinctrl-names = "aux", "i2c", "off";
1589                                 status = "disabled";
1590
1591                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1592                                 nvidia,interface = <0>;
1593                         };
1594
1595                         sor1: sor@15b40000 {
1596                                 compatible = "nvidia,tegra194-sor";
1597                                 reg = <0x15b40000 0x40000>;
1598                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1599                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1600                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
1601                                          <&bpmp TEGRA194_CLK_PLLD2>,
1602                                          <&bpmp TEGRA194_CLK_PLLDP>,
1603                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1604                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1605                                 clock-names = "sor", "out", "parent", "dp", "safe",
1606                                               "pad";
1607                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
1608                                 reset-names = "sor";
1609                                 pinctrl-0 = <&state_dpaux1_aux>;
1610                                 pinctrl-1 = <&state_dpaux1_i2c>;
1611                                 pinctrl-2 = <&state_dpaux1_off>;
1612                                 pinctrl-names = "aux", "i2c", "off";
1613                                 status = "disabled";
1614
1615                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1616                                 nvidia,interface = <1>;
1617                         };
1618
1619                         sor2: sor@15b80000 {
1620                                 compatible = "nvidia,tegra194-sor";
1621                                 reg = <0x15b80000 0x40000>;
1622                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1623                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1624                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
1625                                          <&bpmp TEGRA194_CLK_PLLD3>,
1626                                          <&bpmp TEGRA194_CLK_PLLDP>,
1627                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1628                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1629                                 clock-names = "sor", "out", "parent", "dp", "safe",
1630                                               "pad";
1631                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
1632                                 reset-names = "sor";
1633                                 pinctrl-0 = <&state_dpaux2_aux>;
1634                                 pinctrl-1 = <&state_dpaux2_i2c>;
1635                                 pinctrl-2 = <&state_dpaux2_off>;
1636                                 pinctrl-names = "aux", "i2c", "off";
1637                                 status = "disabled";
1638
1639                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1640                                 nvidia,interface = <2>;
1641                         };
1642
1643                         sor3: sor@15bc0000 {
1644                                 compatible = "nvidia,tegra194-sor";
1645                                 reg = <0x15bc0000 0x40000>;
1646                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1647                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1648                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
1649                                          <&bpmp TEGRA194_CLK_PLLD4>,
1650                                          <&bpmp TEGRA194_CLK_PLLDP>,
1651                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1652                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1653                                 clock-names = "sor", "out", "parent", "dp", "safe",
1654                                               "pad";
1655                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
1656                                 reset-names = "sor";
1657                                 pinctrl-0 = <&state_dpaux3_aux>;
1658                                 pinctrl-1 = <&state_dpaux3_i2c>;
1659                                 pinctrl-2 = <&state_dpaux3_off>;
1660                                 pinctrl-names = "aux", "i2c", "off";
1661                                 status = "disabled";
1662
1663                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1664                                 nvidia,interface = <3>;
1665                         };
1666                 };
1667
1668                 gpu@17000000 {
1669                         compatible = "nvidia,gv11b";
1670                         reg = <0x17000000 0x1000000>,
1671                               <0x18000000 0x1000000>;
1672                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1673                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1674                         interrupt-names = "stall", "nonstall";
1675                         clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
1676                                  <&bpmp TEGRA194_CLK_GPU_PWR>,
1677                                  <&bpmp TEGRA194_CLK_FUSE>;
1678                         clock-names = "gpu", "pwr", "fuse";
1679                         resets = <&bpmp TEGRA194_RESET_GPU>;
1680                         reset-names = "gpu";
1681                         dma-coherent;
1682
1683                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1684                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
1685                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
1686                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
1687                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
1688                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
1689                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
1690                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
1691                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
1692                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
1693                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
1694                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
1695                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
1696                         interconnect-names = "dma-mem", "read-0-hp", "write-0",
1697                                              "read-1", "read-1-hp", "write-1",
1698                                              "read-2", "read-2-hp", "write-2",
1699                                              "read-3", "read-3-hp", "write-3";
1700                 };
1701         };
1702
1703         pcie@14100000 {
1704                 compatible = "nvidia,tegra194-pcie";
1705                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1706                 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
1707                       <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1708                       <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1709                       <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1710                 reg-names = "appl", "config", "atu_dma", "dbi";
1711
1712                 status = "disabled";
1713
1714                 #address-cells = <3>;
1715                 #size-cells = <2>;
1716                 device_type = "pci";
1717                 num-lanes = <1>;
1718                 num-viewport = <8>;
1719                 linux,pci-domain = <1>;
1720
1721                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1722                 clock-names = "core";
1723
1724                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1725                          <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1726                 reset-names = "apb", "core";
1727
1728                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1729                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1730                 interrupt-names = "intr", "msi";
1731
1732                 #interrupt-cells = <1>;
1733                 interrupt-map-mask = <0 0 0 0>;
1734                 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1735
1736                 nvidia,bpmp = <&bpmp 1>;
1737
1738                 nvidia,aspm-cmrt-us = <60>;
1739                 nvidia,aspm-pwr-on-t-us = <20>;
1740                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1741
1742                 bus-range = <0x0 0xff>;
1743
1744                 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1745                          <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1746                          <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1747
1748                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
1749                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
1750                 interconnect-names = "read", "write";
1751         };
1752
1753         pcie@14120000 {
1754                 compatible = "nvidia,tegra194-pcie";
1755                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1756                 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
1757                       <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1758                       <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1759                       <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1760                 reg-names = "appl", "config", "atu_dma", "dbi";
1761
1762                 status = "disabled";
1763
1764                 #address-cells = <3>;
1765                 #size-cells = <2>;
1766                 device_type = "pci";
1767                 num-lanes = <1>;
1768                 num-viewport = <8>;
1769                 linux,pci-domain = <2>;
1770
1771                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1772                 clock-names = "core";
1773
1774                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1775                          <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1776                 reset-names = "apb", "core";
1777
1778                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1779                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1780                 interrupt-names = "intr", "msi";
1781
1782                 #interrupt-cells = <1>;
1783                 interrupt-map-mask = <0 0 0 0>;
1784                 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1785
1786                 nvidia,bpmp = <&bpmp 2>;
1787
1788                 nvidia,aspm-cmrt-us = <60>;
1789                 nvidia,aspm-pwr-on-t-us = <20>;
1790                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1791
1792                 bus-range = <0x0 0xff>;
1793
1794                 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1795                          <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1796                          <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1797
1798                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
1799                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
1800                 interconnect-names = "read", "write";
1801         };
1802
1803         pcie@14140000 {
1804                 compatible = "nvidia,tegra194-pcie";
1805                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1806                 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
1807                       <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1808                       <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1809                       <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1810                 reg-names = "appl", "config", "atu_dma", "dbi";
1811
1812                 status = "disabled";
1813
1814                 #address-cells = <3>;
1815                 #size-cells = <2>;
1816                 device_type = "pci";
1817                 num-lanes = <1>;
1818                 num-viewport = <8>;
1819                 linux,pci-domain = <3>;
1820
1821                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1822                 clock-names = "core";
1823
1824                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1825                          <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1826                 reset-names = "apb", "core";
1827
1828                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1829                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1830                 interrupt-names = "intr", "msi";
1831
1832                 #interrupt-cells = <1>;
1833                 interrupt-map-mask = <0 0 0 0>;
1834                 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1835
1836                 nvidia,bpmp = <&bpmp 3>;
1837
1838                 nvidia,aspm-cmrt-us = <60>;
1839                 nvidia,aspm-pwr-on-t-us = <20>;
1840                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1841
1842                 bus-range = <0x0 0xff>;
1843
1844                 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1845                          <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
1846                          <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1847
1848                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
1849                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
1850                 interconnect-names = "read", "write";
1851         };
1852
1853         pcie@14160000 {
1854                 compatible = "nvidia,tegra194-pcie";
1855                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1856                 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
1857                       <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1858                       <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1859                       <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1860                 reg-names = "appl", "config", "atu_dma", "dbi";
1861
1862                 status = "disabled";
1863
1864                 #address-cells = <3>;
1865                 #size-cells = <2>;
1866                 device_type = "pci";
1867                 num-lanes = <4>;
1868                 num-viewport = <8>;
1869                 linux,pci-domain = <4>;
1870
1871                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1872                 clock-names = "core";
1873
1874                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1875                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1876                 reset-names = "apb", "core";
1877
1878                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1879                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1880                 interrupt-names = "intr", "msi";
1881
1882                 #interrupt-cells = <1>;
1883                 interrupt-map-mask = <0 0 0 0>;
1884                 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1885
1886                 nvidia,bpmp = <&bpmp 4>;
1887
1888                 nvidia,aspm-cmrt-us = <60>;
1889                 nvidia,aspm-pwr-on-t-us = <20>;
1890                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1891
1892                 bus-range = <0x0 0xff>;
1893
1894                 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1895                          <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1896                          <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1897
1898                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
1899                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
1900                 interconnect-names = "read", "write";
1901         };
1902
1903         pcie@14180000 {
1904                 compatible = "nvidia,tegra194-pcie";
1905                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1906                 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
1907                       <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
1908                       <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1909                       <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1910                 reg-names = "appl", "config", "atu_dma", "dbi";
1911
1912                 status = "disabled";
1913
1914                 #address-cells = <3>;
1915                 #size-cells = <2>;
1916                 device_type = "pci";
1917                 num-lanes = <8>;
1918                 num-viewport = <8>;
1919                 linux,pci-domain = <0>;
1920
1921                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1922                 clock-names = "core";
1923
1924                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1925                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1926                 reset-names = "apb", "core";
1927
1928                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1929                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1930                 interrupt-names = "intr", "msi";
1931
1932                 #interrupt-cells = <1>;
1933                 interrupt-map-mask = <0 0 0 0>;
1934                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1935
1936                 nvidia,bpmp = <&bpmp 0>;
1937
1938                 nvidia,aspm-cmrt-us = <60>;
1939                 nvidia,aspm-pwr-on-t-us = <20>;
1940                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1941
1942                 bus-range = <0x0 0xff>;
1943
1944                 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1945                          <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1946                          <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1947
1948                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
1949                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
1950                 interconnect-names = "read", "write";
1951         };
1952
1953         pcie@141a0000 {
1954                 compatible = "nvidia,tegra194-pcie";
1955                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1956                 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
1957                       <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
1958                       <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1959                       <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1960                 reg-names = "appl", "config", "atu_dma", "dbi";
1961
1962                 status = "disabled";
1963
1964                 #address-cells = <3>;
1965                 #size-cells = <2>;
1966                 device_type = "pci";
1967                 num-lanes = <8>;
1968                 num-viewport = <8>;
1969                 linux,pci-domain = <5>;
1970
1971                 pinctrl-names = "default";
1972                 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1973
1974                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1975                          <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1976                 clock-names = "core", "core_m";
1977
1978                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1979                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1980                 reset-names = "apb", "core";
1981
1982                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1983                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1984                 interrupt-names = "intr", "msi";
1985
1986                 nvidia,bpmp = <&bpmp 5>;
1987
1988                 #interrupt-cells = <1>;
1989                 interrupt-map-mask = <0 0 0 0>;
1990                 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1991
1992                 nvidia,aspm-cmrt-us = <60>;
1993                 nvidia,aspm-pwr-on-t-us = <20>;
1994                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1995
1996                 bus-range = <0x0 0xff>;
1997
1998                 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1999                          <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2000                          <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2001
2002                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2003                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2004                 interconnect-names = "read", "write";
2005         };
2006
2007         pcie_ep@14160000 {
2008                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2009                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2010                 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2011                       <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2012                       <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2013                       <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2014                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2015
2016                 status = "disabled";
2017
2018                 num-lanes = <4>;
2019                 num-ib-windows = <2>;
2020                 num-ob-windows = <8>;
2021
2022                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2023                 clock-names = "core";
2024
2025                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2026                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2027                 reset-names = "apb", "core";
2028
2029                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2030                 interrupt-names = "intr";
2031
2032                 nvidia,bpmp = <&bpmp 4>;
2033
2034                 nvidia,aspm-cmrt-us = <60>;
2035                 nvidia,aspm-pwr-on-t-us = <20>;
2036                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2037         };
2038
2039         pcie_ep@14180000 {
2040                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2041                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2042                 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2043                       <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2044                       <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2045                       <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2046                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2047
2048                 status = "disabled";
2049
2050                 num-lanes = <8>;
2051                 num-ib-windows = <2>;
2052                 num-ob-windows = <8>;
2053
2054                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2055                 clock-names = "core";
2056
2057                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2058                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2059                 reset-names = "apb", "core";
2060
2061                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2062                 interrupt-names = "intr";
2063
2064                 nvidia,bpmp = <&bpmp 0>;
2065
2066                 nvidia,aspm-cmrt-us = <60>;
2067                 nvidia,aspm-pwr-on-t-us = <20>;
2068                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2069         };
2070
2071         pcie_ep@141a0000 {
2072                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2073                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2074                 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2075                       <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2076                       <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2077                       <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2078                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2079
2080                 status = "disabled";
2081
2082                 num-lanes = <8>;
2083                 num-ib-windows = <2>;
2084                 num-ob-windows = <8>;
2085
2086                 pinctrl-names = "default";
2087                 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2088
2089                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2090                 clock-names = "core";
2091
2092                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2093                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2094                 reset-names = "apb", "core";
2095
2096                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2097                 interrupt-names = "intr";
2098
2099                 nvidia,bpmp = <&bpmp 5>;
2100
2101                 nvidia,aspm-cmrt-us = <60>;
2102                 nvidia,aspm-pwr-on-t-us = <20>;
2103                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2104         };
2105
2106         sram@40000000 {
2107                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2108                 reg = <0x0 0x40000000 0x0 0x50000>;
2109                 #address-cells = <1>;
2110                 #size-cells = <1>;
2111                 ranges = <0x0 0x0 0x40000000 0x50000>;
2112
2113                 cpu_bpmp_tx: sram@4e000 {
2114                         reg = <0x4e000 0x1000>;
2115                         label = "cpu-bpmp-tx";
2116                         pool;
2117                 };
2118
2119                 cpu_bpmp_rx: sram@4f000 {
2120                         reg = <0x4f000 0x1000>;
2121                         label = "cpu-bpmp-rx";
2122                         pool;
2123                 };
2124         };
2125
2126         bpmp: bpmp {
2127                 compatible = "nvidia,tegra186-bpmp";
2128                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2129                                     TEGRA_HSP_DB_MASTER_BPMP>;
2130                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2131                 #clock-cells = <1>;
2132                 #reset-cells = <1>;
2133                 #power-domain-cells = <1>;
2134                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2135                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2136                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2137                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2138                 interconnect-names = "read", "write", "dma-mem", "dma-write";
2139
2140                 bpmp_i2c: i2c {
2141                         compatible = "nvidia,tegra186-bpmp-i2c";
2142                         nvidia,bpmp-bus-id = <5>;
2143                         #address-cells = <1>;
2144                         #size-cells = <0>;
2145                 };
2146
2147                 bpmp_thermal: thermal {
2148                         compatible = "nvidia,tegra186-bpmp-thermal";
2149                         #thermal-sensor-cells = <1>;
2150                 };
2151         };
2152
2153         cpus {
2154                 compatible = "nvidia,tegra194-ccplex";
2155                 nvidia,bpmp = <&bpmp>;
2156                 #address-cells = <1>;
2157                 #size-cells = <0>;
2158
2159                 cpu0_0: cpu@0 {
2160                         compatible = "nvidia,tegra194-carmel";
2161                         device_type = "cpu";
2162                         reg = <0x000>;
2163                         enable-method = "psci";
2164                         i-cache-size = <131072>;
2165                         i-cache-line-size = <64>;
2166                         i-cache-sets = <512>;
2167                         d-cache-size = <65536>;
2168                         d-cache-line-size = <64>;
2169                         d-cache-sets = <256>;
2170                         next-level-cache = <&l2c_0>;
2171                 };
2172
2173                 cpu0_1: cpu@1 {
2174                         compatible = "nvidia,tegra194-carmel";
2175                         device_type = "cpu";
2176                         reg = <0x001>;
2177                         enable-method = "psci";
2178                         i-cache-size = <131072>;
2179                         i-cache-line-size = <64>;
2180                         i-cache-sets = <512>;
2181                         d-cache-size = <65536>;
2182                         d-cache-line-size = <64>;
2183                         d-cache-sets = <256>;
2184                         next-level-cache = <&l2c_0>;
2185                 };
2186
2187                 cpu1_0: cpu@100 {
2188                         compatible = "nvidia,tegra194-carmel";
2189                         device_type = "cpu";
2190                         reg = <0x100>;
2191                         enable-method = "psci";
2192                         i-cache-size = <131072>;
2193                         i-cache-line-size = <64>;
2194                         i-cache-sets = <512>;
2195                         d-cache-size = <65536>;
2196                         d-cache-line-size = <64>;
2197                         d-cache-sets = <256>;
2198                         next-level-cache = <&l2c_1>;
2199                 };
2200
2201                 cpu1_1: cpu@101 {
2202                         compatible = "nvidia,tegra194-carmel";
2203                         device_type = "cpu";
2204                         reg = <0x101>;
2205                         enable-method = "psci";
2206                         i-cache-size = <131072>;
2207                         i-cache-line-size = <64>;
2208                         i-cache-sets = <512>;
2209                         d-cache-size = <65536>;
2210                         d-cache-line-size = <64>;
2211                         d-cache-sets = <256>;
2212                         next-level-cache = <&l2c_1>;
2213                 };
2214
2215                 cpu2_0: cpu@200 {
2216                         compatible = "nvidia,tegra194-carmel";
2217                         device_type = "cpu";
2218                         reg = <0x200>;
2219                         enable-method = "psci";
2220                         i-cache-size = <131072>;
2221                         i-cache-line-size = <64>;
2222                         i-cache-sets = <512>;
2223                         d-cache-size = <65536>;
2224                         d-cache-line-size = <64>;
2225                         d-cache-sets = <256>;
2226                         next-level-cache = <&l2c_2>;
2227                 };
2228
2229                 cpu2_1: cpu@201 {
2230                         compatible = "nvidia,tegra194-carmel";
2231                         device_type = "cpu";
2232                         reg = <0x201>;
2233                         enable-method = "psci";
2234                         i-cache-size = <131072>;
2235                         i-cache-line-size = <64>;
2236                         i-cache-sets = <512>;
2237                         d-cache-size = <65536>;
2238                         d-cache-line-size = <64>;
2239                         d-cache-sets = <256>;
2240                         next-level-cache = <&l2c_2>;
2241                 };
2242
2243                 cpu3_0: cpu@300 {
2244                         compatible = "nvidia,tegra194-carmel";
2245                         device_type = "cpu";
2246                         reg = <0x300>;
2247                         enable-method = "psci";
2248                         i-cache-size = <131072>;
2249                         i-cache-line-size = <64>;
2250                         i-cache-sets = <512>;
2251                         d-cache-size = <65536>;
2252                         d-cache-line-size = <64>;
2253                         d-cache-sets = <256>;
2254                         next-level-cache = <&l2c_3>;
2255                 };
2256
2257                 cpu3_1: cpu@301 {
2258                         compatible = "nvidia,tegra194-carmel";
2259                         device_type = "cpu";
2260                         reg = <0x301>;
2261                         enable-method = "psci";
2262                         i-cache-size = <131072>;
2263                         i-cache-line-size = <64>;
2264                         i-cache-sets = <512>;
2265                         d-cache-size = <65536>;
2266                         d-cache-line-size = <64>;
2267                         d-cache-sets = <256>;
2268                         next-level-cache = <&l2c_3>;
2269                 };
2270
2271                 cpu-map {
2272                         cluster0 {
2273                                 core0 {
2274                                         cpu = <&cpu0_0>;
2275                                 };
2276
2277                                 core1 {
2278                                         cpu = <&cpu0_1>;
2279                                 };
2280                         };
2281
2282                         cluster1 {
2283                                 core0 {
2284                                         cpu = <&cpu1_0>;
2285                                 };
2286
2287                                 core1 {
2288                                         cpu = <&cpu1_1>;
2289                                 };
2290                         };
2291
2292                         cluster2 {
2293                                 core0 {
2294                                         cpu = <&cpu2_0>;
2295                                 };
2296
2297                                 core1 {
2298                                         cpu = <&cpu2_1>;
2299                                 };
2300                         };
2301
2302                         cluster3 {
2303                                 core0 {
2304                                         cpu = <&cpu3_0>;
2305                                 };
2306
2307                                 core1 {
2308                                         cpu = <&cpu3_1>;
2309                                 };
2310                         };
2311                 };
2312
2313                 l2c_0: l2-cache0 {
2314                         cache-size = <2097152>;
2315                         cache-line-size = <64>;
2316                         cache-sets = <2048>;
2317                         next-level-cache = <&l3c>;
2318                 };
2319
2320                 l2c_1: l2-cache1 {
2321                         cache-size = <2097152>;
2322                         cache-line-size = <64>;
2323                         cache-sets = <2048>;
2324                         next-level-cache = <&l3c>;
2325                 };
2326
2327                 l2c_2: l2-cache2 {
2328                         cache-size = <2097152>;
2329                         cache-line-size = <64>;
2330                         cache-sets = <2048>;
2331                         next-level-cache = <&l3c>;
2332                 };
2333
2334                 l2c_3: l2-cache3 {
2335                         cache-size = <2097152>;
2336                         cache-line-size = <64>;
2337                         cache-sets = <2048>;
2338                         next-level-cache = <&l3c>;
2339                 };
2340
2341                 l3c: l3-cache {
2342                         cache-size = <4194304>;
2343                         cache-line-size = <64>;
2344                         cache-sets = <4096>;
2345                 };
2346         };
2347
2348         psci {
2349                 compatible = "arm,psci-1.0";
2350                 status = "okay";
2351                 method = "smc";
2352         };
2353
2354         sound {
2355                 status = "disabled";
2356
2357                 clocks = <&bpmp TEGRA194_CLK_PLLA>,
2358                          <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2359                 clock-names = "pll_a", "plla_out0";
2360                 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2361                                   <&bpmp TEGRA194_CLK_PLLA_OUT0>,
2362                                   <&bpmp TEGRA194_CLK_AUD_MCLK>;
2363                 assigned-clock-parents = <0>,
2364                                          <&bpmp TEGRA194_CLK_PLLA>,
2365                                          <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2366                 /*
2367                  * PLLA supports dynamic ramp. Below initial rate is chosen
2368                  * for this to work and oscillate between base rates required
2369                  * for 8x and 11.025x sample rate streams.
2370                  */
2371                 assigned-clock-rates = <258000000>;
2372         };
2373
2374         tcu: tcu {
2375                 compatible = "nvidia,tegra194-tcu";
2376                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2377                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2378                 mbox-names = "rx", "tx";
2379         };
2380
2381         thermal-zones {
2382                 cpu {
2383                         thermal-sensors = <&{/bpmp/thermal}
2384                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2385                         status = "disabled";
2386                 };
2387
2388                 gpu {
2389                         thermal-sensors = <&{/bpmp/thermal}
2390                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2391                         status = "disabled";
2392                 };
2393
2394                 aux {
2395                         thermal-sensors = <&{/bpmp/thermal}
2396                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2397                         status = "disabled";
2398                 };
2399
2400                 pllx {
2401                         thermal-sensors = <&{/bpmp/thermal}
2402                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2403                         status = "disabled";
2404                 };
2405
2406                 ao {
2407                         thermal-sensors = <&{/bpmp/thermal}
2408                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
2409                         status = "disabled";
2410                 };
2411
2412                 tj {
2413                         thermal-sensors = <&{/bpmp/thermal}
2414                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2415                         status = "disabled";
2416                 };
2417         };
2418
2419         timer {
2420                 compatible = "arm,armv8-timer";
2421                 interrupts = <GIC_PPI 13
2422                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2423                              <GIC_PPI 14
2424                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2425                              <GIC_PPI 11
2426                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2427                              <GIC_PPI 10
2428                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2429                 interrupt-parent = <&gic>;
2430                 always-on;
2431         };
2432 };