arch/arm64/boot/dts/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/reset/tegra194-reset.h>
   9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
  10 #include <dt-bindings/memory/tegra194-mc.h>
  11
  12 / {
  13         compatible = "nvidia,tegra194";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         /* control backbone */
  19         bus@0 {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges = <0x0 0x0 0x0 0x40000000>;
  24
  25                 misc@100000 {
  26                         compatible = "nvidia,tegra194-misc";
  27                         reg = <0x00100000 0xf000>,
  28                               <0x0010f000 0x1000>;
  29                 };
  30
  31                 gpio: gpio@2200000 {
  32                         compatible = "nvidia,tegra194-gpio";
  33                         reg-names = "security", "gpio";
  34                         reg = <0x2200000 0x10000>,
  35                               <0x2210000 0x10000>;
  36                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  37                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  42                         #interrupt-cells = <2>;
  43                         interrupt-controller;
  44                         #gpio-cells = <2>;
  45                         gpio-controller;
  46                 };
  47
  48                 ethernet@2490000 {
  49                         compatible = "nvidia,tegra194-eqos",
  50                                      "nvidia,tegra186-eqos",
  51                                      "snps,dwc-qos-ethernet-4.10";
  52                         reg = <0x02490000 0x10000>;
  53                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  55                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  56                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  57                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  58                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  59                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  60                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  61                         reset-names = "eqos";
  62                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
  63                                         <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
  64                         interconnect-names = "dma-mem", "write";
  65                         iommus = <&smmu TEGRA194_SID_EQOS>;
  66                         status = "disabled";
  67
  68                         snps,write-requests = <1>;
  69                         snps,read-requests = <3>;
  70                         snps,burst-map = <0x7>;
  71                         snps,txpbl = <16>;
  72                         snps,rxpbl = <8>;
  73                 };
  74
  75                 aconnect@2900000 {
  76                         compatible = "nvidia,tegra194-aconnect",
  77                                      "nvidia,tegra210-aconnect";
  78                         clocks = <&bpmp TEGRA194_CLK_APE>,
  79                                  <&bpmp TEGRA194_CLK_APB2APE>;
  80                         clock-names = "ape", "apb2ape";
  81                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         ranges = <0x02900000 0x02900000 0x200000>;
  85                         status = "disabled";
  86
  87                         adma: dma-controller@2930000 {
  88                                 compatible = "nvidia,tegra194-adma",
  89                                              "nvidia,tegra186-adma";
  90                                 reg = <0x02930000 0x20000>;
  91                                 interrupt-parent = <&agic>;
  92                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  93                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  94                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  95                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  96                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  97                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  98                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  99                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 100                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 101                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 102                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 103                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 104                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 105                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 106                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 107                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 108                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 109                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 110                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 111                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 112                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 113                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 114                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 115                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 116                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 117                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 118                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 119                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 120                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 121                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 122                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 123                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 124                                 #dma-cells = <1>;
 125                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 126                                 clock-names = "d_audio";
 127                                 status = "disabled";
 128                         };
 129
 130                         agic: interrupt-controller@2a40000 {
 131                                 compatible = "nvidia,tegra194-agic",
 132                                              "nvidia,tegra210-agic";
 133                                 #interrupt-cells = <3>;
 134                                 interrupt-controller;
 135                                 reg = <0x02a41000 0x1000>,
 136                                       <0x02a42000 0x2000>;
 137                                 interrupts = <GIC_SPI 145
 138                                               (GIC_CPU_MASK_SIMPLE(4) |
 139                                                IRQ_TYPE_LEVEL_HIGH)>;
 140                                 clocks = <&bpmp TEGRA194_CLK_APE>;
 141                                 clock-names = "clk";
 142                                 status = "disabled";
 143                         };
 144
 145                         tegra_ahub: ahub@2900800 {
 146                                 compatible = "nvidia,tegra194-ahub",
 147                                              "nvidia,tegra186-ahub";
 148                                 reg = <0x02900800 0x800>;
 149                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 150                                 clock-names = "ahub";
 151                                 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
 152                                 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 153                                 #address-cells = <1>;
 154                                 #size-cells = <1>;
 155                                 ranges = <0x02900800 0x02900800 0x11800>;
 156                                 status = "disabled";
 157
 158                                 tegra_admaif: admaif@290f000 {
 159                                         compatible = "nvidia,tegra194-admaif",
 160                                                      "nvidia,tegra186-admaif";
 161                                         reg = <0x0290f000 0x1000>;
 162                                         dmas = <&adma 1>, <&adma 1>,
 163                                                <&adma 2>, <&adma 2>,
 164                                                <&adma 3>, <&adma 3>,
 165                                                <&adma 4>, <&adma 4>,
 166                                                <&adma 5>, <&adma 5>,
 167                                                <&adma 6>, <&adma 6>,
 168                                                <&adma 7>, <&adma 7>,
 169                                                <&adma 8>, <&adma 8>,
 170                                                <&adma 9>, <&adma 9>,
 171                                                <&adma 10>, <&adma 10>,
 172                                                <&adma 11>, <&adma 11>,
 173                                                <&adma 12>, <&adma 12>,
 174                                                <&adma 13>, <&adma 13>,
 175                                                <&adma 14>, <&adma 14>,
 176                                                <&adma 15>, <&adma 15>,
 177                                                <&adma 16>, <&adma 16>,
 178                                                <&adma 17>, <&adma 17>,
 179                                                <&adma 18>, <&adma 18>,
 180                                                <&adma 19>, <&adma 19>,
 181                                                <&adma 20>, <&adma 20>;
 182                                         dma-names = "rx1", "tx1",
 183                                                     "rx2", "tx2",
 184                                                     "rx3", "tx3",
 185                                                     "rx4", "tx4",
 186                                                     "rx5", "tx5",
 187                                                     "rx6", "tx6",
 188                                                     "rx7", "tx7",
 189                                                     "rx8", "tx8",
 190                                                     "rx9", "tx9",
 191                                                     "rx10", "tx10",
 192                                                     "rx11", "tx11",
 193                                                     "rx12", "tx12",
 194                                                     "rx13", "tx13",
 195                                                     "rx14", "tx14",
 196                                                     "rx15", "tx15",
 197                                                     "rx16", "tx16",
 198                                                     "rx17", "tx17",
 199                                                     "rx18", "tx18",
 200                                                     "rx19", "tx19",
 201                                                     "rx20", "tx20";
 202                                         status = "disabled";
 203                                 };
 204
 205                                 tegra_i2s1: i2s@2901000 {
 206                                         compatible = "nvidia,tegra194-i2s",
 207                                                      "nvidia,tegra210-i2s";
 208                                         reg = <0x2901000 0x100>;
 209                                         clocks = <&bpmp TEGRA194_CLK_I2S1>,
 210                                                  <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
 211                                         clock-names = "i2s", "sync_input";
 212                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
 213                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 214                                         assigned-clock-rates = <1536000>;
 215                                         sound-name-prefix = "I2S1";
 216                                         status = "disabled";
 217                                 };
 218
 219                                 tegra_i2s2: i2s@2901100 {
 220                                         compatible = "nvidia,tegra194-i2s",
 221                                                      "nvidia,tegra210-i2s";
 222                                         reg = <0x2901100 0x100>;
 223                                         clocks = <&bpmp TEGRA194_CLK_I2S2>,
 224                                                  <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
 225                                         clock-names = "i2s", "sync_input";
 226                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
 227                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 228                                         assigned-clock-rates = <1536000>;
 229                                         sound-name-prefix = "I2S2";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 tegra_i2s3: i2s@2901200 {
 234                                         compatible = "nvidia,tegra194-i2s",
 235                                                      "nvidia,tegra210-i2s";
 236                                         reg = <0x2901200 0x100>;
 237                                         clocks = <&bpmp TEGRA194_CLK_I2S3>,
 238                                                  <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
 239                                         clock-names = "i2s", "sync_input";
 240                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
 241                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 242                                         assigned-clock-rates = <1536000>;
 243                                         sound-name-prefix = "I2S3";
 244                                         status = "disabled";
 245                                 };
 246
 247                                 tegra_i2s4: i2s@2901300 {
 248                                         compatible = "nvidia,tegra194-i2s",
 249                                                      "nvidia,tegra210-i2s";
 250                                         reg = <0x2901300 0x100>;
 251                                         clocks = <&bpmp TEGRA194_CLK_I2S4>,
 252                                                  <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
 253                                         clock-names = "i2s", "sync_input";
 254                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
 255                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 256                                         assigned-clock-rates = <1536000>;
 257                                         sound-name-prefix = "I2S4";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 tegra_i2s5: i2s@2901400 {
 262                                         compatible = "nvidia,tegra194-i2s",
 263                                                      "nvidia,tegra210-i2s";
 264                                         reg = <0x2901400 0x100>;
 265                                         clocks = <&bpmp TEGRA194_CLK_I2S5>,
 266                                                  <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
 267                                         clock-names = "i2s", "sync_input";
 268                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
 269                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 270                                         assigned-clock-rates = <1536000>;
 271                                         sound-name-prefix = "I2S5";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 tegra_i2s6: i2s@2901500 {
 276                                         compatible = "nvidia,tegra194-i2s",
 277                                                      "nvidia,tegra210-i2s";
 278                                         reg = <0x2901500 0x100>;
 279                                         clocks = <&bpmp TEGRA194_CLK_I2S6>,
 280                                                  <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
 281                                         clock-names = "i2s", "sync_input";
 282                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
 283                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 284                                         assigned-clock-rates = <1536000>;
 285                                         sound-name-prefix = "I2S6";
 286                                         status = "disabled";
 287                                 };
 288
 289                                 tegra_dmic1: dmic@2904000 {
 290                                         compatible = "nvidia,tegra194-dmic",
 291                                                      "nvidia,tegra210-dmic";
 292                                         reg = <0x2904000 0x100>;
 293                                         clocks = <&bpmp TEGRA194_CLK_DMIC1>;
 294                                         clock-names = "dmic";
 295                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
 296                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 297                                         assigned-clock-rates = <3072000>;
 298                                         sound-name-prefix = "DMIC1";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 tegra_dmic2: dmic@2904100 {
 303                                         compatible = "nvidia,tegra194-dmic",
 304                                                      "nvidia,tegra210-dmic";
 305                                         reg = <0x2904100 0x100>;
 306                                         clocks = <&bpmp TEGRA194_CLK_DMIC2>;
 307                                         clock-names = "dmic";
 308                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
 309                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 310                                         assigned-clock-rates = <3072000>;
 311                                         sound-name-prefix = "DMIC2";
 312                                         status = "disabled";
 313                                 };
 314
 315                                 tegra_dmic3: dmic@2904200 {
 316                                         compatible = "nvidia,tegra194-dmic",
 317                                                      "nvidia,tegra210-dmic";
 318                                         reg = <0x2904200 0x100>;
 319                                         clocks = <&bpmp TEGRA194_CLK_DMIC3>;
 320                                         clock-names = "dmic";
 321                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
 322                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 323                                         assigned-clock-rates = <3072000>;
 324                                         sound-name-prefix = "DMIC3";
 325                                         status = "disabled";
 326                                 };
 327
 328                                 tegra_dmic4: dmic@2904300 {
 329                                         compatible = "nvidia,tegra194-dmic",
 330                                                      "nvidia,tegra210-dmic";
 331                                         reg = <0x2904300 0x100>;
 332                                         clocks = <&bpmp TEGRA194_CLK_DMIC4>;
 333                                         clock-names = "dmic";
 334                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
 335                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 336                                         assigned-clock-rates = <3072000>;
 337                                         sound-name-prefix = "DMIC4";
 338                                         status = "disabled";
 339                                 };
 340
 341                                 tegra_dspk1: dspk@2905000 {
 342                                         compatible = "nvidia,tegra194-dspk",
 343                                                      "nvidia,tegra186-dspk";
 344                                         reg = <0x2905000 0x100>;
 345                                         clocks = <&bpmp TEGRA194_CLK_DSPK1>;
 346                                         clock-names = "dspk";
 347                                         assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
 348                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 349                                         assigned-clock-rates = <12288000>;
 350                                         sound-name-prefix = "DSPK1";
 351                                         status = "disabled";
 352                                 };
 353
 354                                 tegra_dspk2: dspk@2905100 {
 355                                         compatible = "nvidia,tegra194-dspk",
 356                                                      "nvidia,tegra186-dspk";
 357                                         reg = <0x2905100 0x100>;
 358                                         clocks = <&bpmp TEGRA194_CLK_DSPK2>;
 359                                         clock-names = "dspk";
 360                                         assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
 361                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 362                                         assigned-clock-rates = <12288000>;
 363                                         sound-name-prefix = "DSPK2";
 364                                         status = "disabled";
 365                                 };
 366                         };
 367                 };
 368
 369                 pinmux: pinmux@2430000 {
 370                         compatible = "nvidia,tegra194-pinmux";
 371                         reg = <0x2430000 0x17000>,
 372                               <0xc300000 0x4000>;
 373
 374                         status = "okay";
 375
 376                         pex_rst_c5_out_state: pex_rst_c5_out {
 377                                 pex_rst {
 378                                         nvidia,pins = "pex_l5_rst_n_pgg1";
 379                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 380                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 381                                         nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 382                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 383                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 384                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 385                                 };
 386                         };
 387
 388                         clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
 389                                 clkreq {
 390                                         nvidia,pins = "pex_l5_clkreq_n_pgg0";
 391                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 392                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 393                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 394                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 395                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 396                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 397                                 };
 398                         };
 399                 };
 400
 401                 mc: memory-controller@2c00000 {
 402                         compatible = "nvidia,tegra194-mc";
 403                         reg = <0x02c00000 0x100000>,
 404                               <0x02b80000 0x040000>,
 405                               <0x01700000 0x100000>;
 406                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 407                         #interconnect-cells = <1>;
 408                         status = "disabled";
 409
 410                         #address-cells = <2>;
 411                         #size-cells = <2>;
 412
 413                         ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
 414                                  <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
 415                                  <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
 416
 417                         /*
 418                          * Bit 39 of addresses passing through the memory
 419                          * controller selects the XBAR format used when memory
 420                          * is accessed. This is used to transparently access
 421                          * memory in the XBAR format used by the discrete GPU
 422                          * (bit 39 set) or Tegra (bit 39 clear).
 423                          *
 424                          * As a consequence, the operating system must ensure
 425                          * that bit 39 is never used implicitly, for example
 426                          * via an I/O virtual address mapping of an IOMMU. If
 427                          * devices require access to the XBAR switch, their
 428                          * drivers must set this bit explicitly.
 429                          *
 430                          * Limit the DMA range for memory clients to [38:0].
 431                          */
 432                         dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
 433
 434                         emc: external-memory-controller@2c60000 {
 435                                 compatible = "nvidia,tegra194-emc";
 436                                 reg = <0x0 0x02c60000 0x0 0x90000>,
 437                                       <0x0 0x01780000 0x0 0x80000>;
 438                                 clocks = <&bpmp TEGRA194_CLK_EMC>;
 439                                 clock-names = "emc";
 440
 441                                 #interconnect-cells = <0>;
 442
 443                                 nvidia,bpmp = <&bpmp>;
 444                         };
 445                 };
 446
 447                 uarta: serial@3100000 {
 448                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 449                         reg = <0x03100000 0x40>;
 450                         reg-shift = <2>;
 451                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 452                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
 453                         clock-names = "serial";
 454                         resets = <&bpmp TEGRA194_RESET_UARTA>;
 455                         reset-names = "serial";
 456                         status = "disabled";
 457                 };
 458
 459                 uartb: serial@3110000 {
 460                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 461                         reg = <0x03110000 0x40>;
 462                         reg-shift = <2>;
 463                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
 465                         clock-names = "serial";
 466                         resets = <&bpmp TEGRA194_RESET_UARTB>;
 467                         reset-names = "serial";
 468                         status = "disabled";
 469                 };
 470
 471                 uartd: serial@3130000 {
 472                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 473                         reg = <0x03130000 0x40>;
 474                         reg-shift = <2>;
 475                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 476                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
 477                         clock-names = "serial";
 478                         resets = <&bpmp TEGRA194_RESET_UARTD>;
 479                         reset-names = "serial";
 480                         status = "disabled";
 481                 };
 482
 483                 uarte: serial@3140000 {
 484                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 485                         reg = <0x03140000 0x40>;
 486                         reg-shift = <2>;
 487                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 488                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 489                         clock-names = "serial";
 490                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 491                         reset-names = "serial";
 492                         status = "disabled";
 493                 };
 494
 495                 uartf: serial@3150000 {
 496                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 497                         reg = <0x03150000 0x40>;
 498                         reg-shift = <2>;
 499                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 501                         clock-names = "serial";
 502                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 503                         reset-names = "serial";
 504                         status = "disabled";
 505                 };
 506
 507                 gen1_i2c: i2c@3160000 {
 508                         compatible = "nvidia,tegra194-i2c";
 509                         reg = <0x03160000 0x10000>;
 510                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 514                         clock-names = "div-clk";
 515                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 516                         reset-names = "i2c";
 517                         status = "disabled";
 518                 };
 519
 520                 uarth: serial@3170000 {
 521                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 522                         reg = <0x03170000 0x40>;
 523                         reg-shift = <2>;
 524                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 526                         clock-names = "serial";
 527                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 528                         reset-names = "serial";
 529                         status = "disabled";
 530                 };
 531
 532                 cam_i2c: i2c@3180000 {
 533                         compatible = "nvidia,tegra194-i2c";
 534                         reg = <0x03180000 0x10000>;
 535                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 539                         clock-names = "div-clk";
 540                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 541                         reset-names = "i2c";
 542                         status = "disabled";
 543                 };
 544
 545                 /* shares pads with dpaux1 */
 546                 dp_aux_ch1_i2c: i2c@3190000 {
 547                         compatible = "nvidia,tegra194-i2c";
 548                         reg = <0x03190000 0x10000>;
 549                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 553                         clock-names = "div-clk";
 554                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 555                         reset-names = "i2c";
 556                         pinctrl-0 = <&state_dpaux1_i2c>;
 557                         pinctrl-1 = <&state_dpaux1_off>;
 558                         pinctrl-names = "default", "idle";
 559                         status = "disabled";
 560                 };
 561
 562                 /* shares pads with dpaux0 */
 563                 dp_aux_ch0_i2c: i2c@31b0000 {
 564                         compatible = "nvidia,tegra194-i2c";
 565                         reg = <0x031b0000 0x10000>;
 566                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 570                         clock-names = "div-clk";
 571                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 572                         reset-names = "i2c";
 573                         pinctrl-0 = <&state_dpaux0_i2c>;
 574                         pinctrl-1 = <&state_dpaux0_off>;
 575                         pinctrl-names = "default", "idle";
 576                         status = "disabled";
 577                 };
 578
 579                 /* shares pads with dpaux2 */
 580                 dp_aux_ch2_i2c: i2c@31c0000 {
 581                         compatible = "nvidia,tegra194-i2c";
 582                         reg = <0x031c0000 0x10000>;
 583                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 587                         clock-names = "div-clk";
 588                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 589                         reset-names = "i2c";
 590                         pinctrl-0 = <&state_dpaux2_i2c>;
 591                         pinctrl-1 = <&state_dpaux2_off>;
 592                         pinctrl-names = "default", "idle";
 593                         status = "disabled";
 594                 };
 595
 596                 /* shares pads with dpaux3 */
 597                 dp_aux_ch3_i2c: i2c@31e0000 {
 598                         compatible = "nvidia,tegra194-i2c";
 599                         reg = <0x031e0000 0x10000>;
 600                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 604                         clock-names = "div-clk";
 605                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 606                         reset-names = "i2c";
 607                         pinctrl-0 = <&state_dpaux3_i2c>;
 608                         pinctrl-1 = <&state_dpaux3_off>;
 609                         pinctrl-names = "default", "idle";
 610                         status = "disabled";
 611                 };
 612
 613                 spi@3270000 {
 614                         compatible = "nvidia,tegra194-qspi";
 615                         reg = <0x3270000 0x1000>;
 616                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                         clocks = <&bpmp TEGRA194_CLK_QSPI0>,
 620                                  <&bpmp TEGRA194_CLK_QSPI0_PM>;
 621                         clock-names = "qspi", "qspi_out";
 622                         resets = <&bpmp TEGRA194_RESET_QSPI0>;
 623                         reset-names = "qspi";
 624                         status = "disabled";
 625                 };
 626
 627                 spi@3300000 {
 628                         compatible = "nvidia,tegra194-qspi";
 629                         reg = <0x3300000 0x1000>;
 630                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         clocks = <&bpmp TEGRA194_CLK_QSPI1>,
 634                                  <&bpmp TEGRA194_CLK_QSPI1_PM>;
 635                         clock-names = "qspi", "qspi_out";
 636                         resets = <&bpmp TEGRA194_RESET_QSPI1>;
 637                         reset-names = "qspi";
 638                         status = "disabled";
 639                 };
 640
 641                 pwm1: pwm@3280000 {
 642                         compatible = "nvidia,tegra194-pwm",
 643                                      "nvidia,tegra186-pwm";
 644                         reg = <0x3280000 0x10000>;
 645                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 646                         clock-names = "pwm";
 647                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 648                         reset-names = "pwm";
 649                         status = "disabled";
 650                         #pwm-cells = <2>;
 651                 };
 652
 653                 pwm2: pwm@3290000 {
 654                         compatible = "nvidia,tegra194-pwm",
 655                                      "nvidia,tegra186-pwm";
 656                         reg = <0x3290000 0x10000>;
 657                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 658                         clock-names = "pwm";
 659                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 660                         reset-names = "pwm";
 661                         status = "disabled";
 662                         #pwm-cells = <2>;
 663                 };
 664
 665                 pwm3: pwm@32a0000 {
 666                         compatible = "nvidia,tegra194-pwm",
 667                                      "nvidia,tegra186-pwm";
 668                         reg = <0x32a0000 0x10000>;
 669                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 670                         clock-names = "pwm";
 671                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 672                         reset-names = "pwm";
 673                         status = "disabled";
 674                         #pwm-cells = <2>;
 675                 };
 676
 677                 pwm5: pwm@32c0000 {
 678                         compatible = "nvidia,tegra194-pwm",
 679                                      "nvidia,tegra186-pwm";
 680                         reg = <0x32c0000 0x10000>;
 681                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 682                         clock-names = "pwm";
 683                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 684                         reset-names = "pwm";
 685                         status = "disabled";
 686                         #pwm-cells = <2>;
 687                 };
 688
 689                 pwm6: pwm@32d0000 {
 690                         compatible = "nvidia,tegra194-pwm",
 691                                      "nvidia,tegra186-pwm";
 692                         reg = <0x32d0000 0x10000>;
 693                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 694                         clock-names = "pwm";
 695                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 696                         reset-names = "pwm";
 697                         status = "disabled";
 698                         #pwm-cells = <2>;
 699                 };
 700
 701                 pwm7: pwm@32e0000 {
 702                         compatible = "nvidia,tegra194-pwm",
 703                                      "nvidia,tegra186-pwm";
 704                         reg = <0x32e0000 0x10000>;
 705                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 706                         clock-names = "pwm";
 707                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 708                         reset-names = "pwm";
 709                         status = "disabled";
 710                         #pwm-cells = <2>;
 711                 };
 712
 713                 pwm8: pwm@32f0000 {
 714                         compatible = "nvidia,tegra194-pwm",
 715                                      "nvidia,tegra186-pwm";
 716                         reg = <0x32f0000 0x10000>;
 717                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 718                         clock-names = "pwm";
 719                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 720                         reset-names = "pwm";
 721                         status = "disabled";
 722                         #pwm-cells = <2>;
 723                 };
 724
 725                 sdmmc1: mmc@3400000 {
 726                         compatible = "nvidia,tegra194-sdhci";
 727                         reg = <0x03400000 0x10000>;
 728                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 729                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
 730                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 731                         clock-names = "sdhci", "tmclk";
 732                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 733                         reset-names = "sdhci";
 734                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
 735                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
 736                         interconnect-names = "dma-mem", "write";
 737                         iommus = <&smmu TEGRA194_SID_SDMMC1>;
 738                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 739                                                                         <0x07>;
 740                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 741                                                                         <0x07>;
 742                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 743                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 744                                                                         <0x07>;
 745                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 746                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 747                         nvidia,default-tap = <0x9>;
 748                         nvidia,default-trim = <0x5>;
 749                         status = "disabled";
 750                 };
 751
 752                 sdmmc3: mmc@3440000 {
 753                         compatible = "nvidia,tegra194-sdhci";
 754                         reg = <0x03440000 0x10000>;
 755                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 756                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
 757                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 758                         clock-names = "sdhci", "tmclk";
 759                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 760                         reset-names = "sdhci";
 761                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
 762                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
 763                         interconnect-names = "dma-mem", "write";
 764                         iommus = <&smmu TEGRA194_SID_SDMMC3>;
 765                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 766                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 767                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 768                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 769                                                                         <0x07>;
 770                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 771                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 772                                                                         <0x07>;
 773                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 774                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 775                         nvidia,default-tap = <0x9>;
 776                         nvidia,default-trim = <0x5>;
 777                         status = "disabled";
 778                 };
 779
 780                 sdmmc4: mmc@3460000 {
 781                         compatible = "nvidia,tegra194-sdhci";
 782                         reg = <0x03460000 0x10000>;
 783                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 784                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 785                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 786                         clock-names = "sdhci", "tmclk";
 787                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 788                                           <&bpmp TEGRA194_CLK_PLLC4>;
 789                         assigned-clock-parents =
 790                                           <&bpmp TEGRA194_CLK_PLLC4>;
 791                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 792                         reset-names = "sdhci";
 793                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
 794                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
 795                         interconnect-names = "dma-mem", "write";
 796                         iommus = <&smmu TEGRA194_SID_SDMMC4>;
 797                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 798                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 799                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 800                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 801                                                                         <0x0a>;
 802                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 803                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 804                                                                         <0x0a>;
 805                         nvidia,default-tap = <0x8>;
 806                         nvidia,default-trim = <0x14>;
 807                         nvidia,dqs-trim = <40>;
 808                         supports-cqe;
 809                         status = "disabled";
 810                 };
 811
 812                 hda@3510000 {
 813                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 814                         reg = <0x3510000 0x10000>;
 815                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 817                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
 818                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
 819                         clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 820                         resets = <&bpmp TEGRA194_RESET_HDA>,
 821                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
 822                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
 823                         reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 824                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 825                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
 826                                         <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
 827                         interconnect-names = "dma-mem", "write";
 828                         iommus = <&smmu TEGRA194_SID_HDA>;
 829                         status = "disabled";
 830                 };
 831
 832                 xusb_padctl: padctl@3520000 {
 833                         compatible = "nvidia,tegra194-xusb-padctl";
 834                         reg = <0x03520000 0x1000>,
 835                               <0x03540000 0x1000>;
 836                         reg-names = "padctl", "ao";
 837                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 838
 839                         resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
 840                         reset-names = "padctl";
 841
 842                         status = "disabled";
 843
 844                         pads {
 845                                 usb2 {
 846                                         clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
 847                                         clock-names = "trk";
 848
 849                                         lanes {
 850                                                 usb2-0 {
 851                                                         nvidia,function = "xusb";
 852                                                         status = "disabled";
 853                                                         #phy-cells = <0>;
 854                                                 };
 855
 856                                                 usb2-1 {
 857                                                         nvidia,function = "xusb";
 858                                                         status = "disabled";
 859                                                         #phy-cells = <0>;
 860                                                 };
 861
 862                                                 usb2-2 {
 863                                                         nvidia,function = "xusb";
 864                                                         status = "disabled";
 865                                                         #phy-cells = <0>;
 866                                                 };
 867
 868                                                 usb2-3 {
 869                                                         nvidia,function = "xusb";
 870                                                         status = "disabled";
 871                                                         #phy-cells = <0>;
 872                                                 };
 873                                         };
 874                                 };
 875
 876                                 usb3 {
 877                                         lanes {
 878                                                 usb3-0 {
 879                                                         nvidia,function = "xusb";
 880                                                         status = "disabled";
 881                                                         #phy-cells = <0>;
 882                                                 };
 883
 884                                                 usb3-1 {
 885                                                         nvidia,function = "xusb";
 886                                                         status = "disabled";
 887                                                         #phy-cells = <0>;
 888                                                 };
 889
 890                                                 usb3-2 {
 891                                                         nvidia,function = "xusb";
 892                                                         status = "disabled";
 893                                                         #phy-cells = <0>;
 894                                                 };
 895
 896                                                 usb3-3 {
 897                                                         nvidia,function = "xusb";
 898                                                         status = "disabled";
 899                                                         #phy-cells = <0>;
 900                                                 };
 901                                         };
 902                                 };
 903                         };
 904
 905                         ports {
 906                                 usb2-0 {
 907                                         status = "disabled";
 908                                 };
 909
 910                                 usb2-1 {
 911                                         status = "disabled";
 912                                 };
 913
 914                                 usb2-2 {
 915                                         status = "disabled";
 916                                 };
 917
 918                                 usb2-3 {
 919                                         status = "disabled";
 920                                 };
 921
 922                                 usb3-0 {
 923                                         status = "disabled";
 924                                 };
 925
 926                                 usb3-1 {
 927                                         status = "disabled";
 928                                 };
 929
 930                                 usb3-2 {
 931                                         status = "disabled";
 932                                 };
 933
 934                                 usb3-3 {
 935                                         status = "disabled";
 936                                 };
 937                         };
 938                 };
 939
 940                 usb@3550000 {
 941                         compatible = "nvidia,tegra194-xudc";
 942                         reg = <0x03550000 0x8000>,
 943                               <0x03558000 0x1000>;
 944                         reg-names = "base", "fpci";
 945                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 946                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
 947                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
 948                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
 949                                  <&bpmp TEGRA194_CLK_XUSB_FS>;
 950                         clock-names = "dev", "ss", "ss_src", "fs_src";
 951                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
 952                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
 953                         power-domain-names = "dev", "ss";
 954                         nvidia,xusb-padctl = <&xusb_padctl>;
 955                         status = "disabled";
 956                 };
 957
 958                 usb@3610000 {
 959                         compatible = "nvidia,tegra194-xusb";
 960                         reg = <0x03610000 0x40000>,
 961                               <0x03600000 0x10000>;
 962                         reg-names = "hcd", "fpci";
 963
 964                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 965                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 966
 967                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
 968                                  <&bpmp TEGRA194_CLK_XUSB_FALCON>,
 969                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
 970                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
 971                                  <&bpmp TEGRA194_CLK_CLK_M>,
 972                                  <&bpmp TEGRA194_CLK_XUSB_FS>,
 973                                  <&bpmp TEGRA194_CLK_UTMIPLL>,
 974                                  <&bpmp TEGRA194_CLK_CLK_M>,
 975                                  <&bpmp TEGRA194_CLK_PLLE>;
 976                         clock-names = "xusb_host", "xusb_falcon_src",
 977                                       "xusb_ss", "xusb_ss_src", "xusb_hs_src",
 978                                       "xusb_fs_src", "pll_u_480m", "clk_m",
 979                                       "pll_e";
 980
 981                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
 982                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
 983                         power-domain-names = "xusb_host", "xusb_ss";
 984
 985                         nvidia,xusb-padctl = <&xusb_padctl>;
 986                         status = "disabled";
 987                 };
 988
 989                 fuse@3820000 {
 990                         compatible = "nvidia,tegra194-efuse";
 991                         reg = <0x03820000 0x10000>;
 992                         clocks = <&bpmp TEGRA194_CLK_FUSE>;
 993                         clock-names = "fuse";
 994                 };
 995
 996                 gic: interrupt-controller@3881000 {
 997                         compatible = "arm,gic-400";
 998                         #interrupt-cells = <3>;
 999                         interrupt-controller;
1000                         reg = <0x03881000 0x1000>,
1001                               <0x03882000 0x2000>,
1002                               <0x03884000 0x2000>,
1003                               <0x03886000 0x2000>;
1004                         interrupts = <GIC_PPI 9
1005                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1006                         interrupt-parent = <&gic>;
1007                 };
1008
1009                 cec@3960000 {
1010                         compatible = "nvidia,tegra194-cec";
1011                         reg = <0x03960000 0x10000>;
1012                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1013                         clocks = <&bpmp TEGRA194_CLK_CEC>;
1014                         clock-names = "cec";
1015                         status = "disabled";
1016                 };
1017
1018                 hsp_top0: hsp@3c00000 {
1019                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1020                         reg = <0x03c00000 0xa0000>;
1021                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1022                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1023                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1024                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1025                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1027                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1028                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1029                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1030                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1031                                           "shared3", "shared4", "shared5", "shared6",
1032                                           "shared7";
1033                         #mbox-cells = <2>;
1034                 };
1035
1036                 p2u_hsio_0: phy@3e10000 {
1037                         compatible = "nvidia,tegra194-p2u";
1038                         reg = <0x03e10000 0x10000>;
1039                         reg-names = "ctl";
1040
1041                         #phy-cells = <0>;
1042                 };
1043
1044                 p2u_hsio_1: phy@3e20000 {
1045                         compatible = "nvidia,tegra194-p2u";
1046                         reg = <0x03e20000 0x10000>;
1047                         reg-names = "ctl";
1048
1049                         #phy-cells = <0>;
1050                 };
1051
1052                 p2u_hsio_2: phy@3e30000 {
1053                         compatible = "nvidia,tegra194-p2u";
1054                         reg = <0x03e30000 0x10000>;
1055                         reg-names = "ctl";
1056
1057                         #phy-cells = <0>;
1058                 };
1059
1060                 p2u_hsio_3: phy@3e40000 {
1061                         compatible = "nvidia,tegra194-p2u";
1062                         reg = <0x03e40000 0x10000>;
1063                         reg-names = "ctl";
1064
1065                         #phy-cells = <0>;
1066                 };
1067
1068                 p2u_hsio_4: phy@3e50000 {
1069                         compatible = "nvidia,tegra194-p2u";
1070                         reg = <0x03e50000 0x10000>;
1071                         reg-names = "ctl";
1072
1073                         #phy-cells = <0>;
1074                 };
1075
1076                 p2u_hsio_5: phy@3e60000 {
1077                         compatible = "nvidia,tegra194-p2u";
1078                         reg = <0x03e60000 0x10000>;
1079                         reg-names = "ctl";
1080
1081                         #phy-cells = <0>;
1082                 };
1083
1084                 p2u_hsio_6: phy@3e70000 {
1085                         compatible = "nvidia,tegra194-p2u";
1086                         reg = <0x03e70000 0x10000>;
1087                         reg-names = "ctl";
1088
1089                         #phy-cells = <0>;
1090                 };
1091
1092                 p2u_hsio_7: phy@3e80000 {
1093                         compatible = "nvidia,tegra194-p2u";
1094                         reg = <0x03e80000 0x10000>;
1095                         reg-names = "ctl";
1096
1097                         #phy-cells = <0>;
1098                 };
1099
1100                 p2u_hsio_8: phy@3e90000 {
1101                         compatible = "nvidia,tegra194-p2u";
1102                         reg = <0x03e90000 0x10000>;
1103                         reg-names = "ctl";
1104
1105                         #phy-cells = <0>;
1106                 };
1107
1108                 p2u_hsio_9: phy@3ea0000 {
1109                         compatible = "nvidia,tegra194-p2u";
1110                         reg = <0x03ea0000 0x10000>;
1111                         reg-names = "ctl";
1112
1113                         #phy-cells = <0>;
1114                 };
1115
1116                 p2u_nvhs_0: phy@3eb0000 {
1117                         compatible = "nvidia,tegra194-p2u";
1118                         reg = <0x03eb0000 0x10000>;
1119                         reg-names = "ctl";
1120
1121                         #phy-cells = <0>;
1122                 };
1123
1124                 p2u_nvhs_1: phy@3ec0000 {
1125                         compatible = "nvidia,tegra194-p2u";
1126                         reg = <0x03ec0000 0x10000>;
1127                         reg-names = "ctl";
1128
1129                         #phy-cells = <0>;
1130                 };
1131
1132                 p2u_nvhs_2: phy@3ed0000 {
1133                         compatible = "nvidia,tegra194-p2u";
1134                         reg = <0x03ed0000 0x10000>;
1135                         reg-names = "ctl";
1136
1137                         #phy-cells = <0>;
1138                 };
1139
1140                 p2u_nvhs_3: phy@3ee0000 {
1141                         compatible = "nvidia,tegra194-p2u";
1142                         reg = <0x03ee0000 0x10000>;
1143                         reg-names = "ctl";
1144
1145                         #phy-cells = <0>;
1146                 };
1147
1148                 p2u_nvhs_4: phy@3ef0000 {
1149                         compatible = "nvidia,tegra194-p2u";
1150                         reg = <0x03ef0000 0x10000>;
1151                         reg-names = "ctl";
1152
1153                         #phy-cells = <0>;
1154                 };
1155
1156                 p2u_nvhs_5: phy@3f00000 {
1157                         compatible = "nvidia,tegra194-p2u";
1158                         reg = <0x03f00000 0x10000>;
1159                         reg-names = "ctl";
1160
1161                         #phy-cells = <0>;
1162                 };
1163
1164                 p2u_nvhs_6: phy@3f10000 {
1165                         compatible = "nvidia,tegra194-p2u";
1166                         reg = <0x03f10000 0x10000>;
1167                         reg-names = "ctl";
1168
1169                         #phy-cells = <0>;
1170                 };
1171
1172                 p2u_nvhs_7: phy@3f20000 {
1173                         compatible = "nvidia,tegra194-p2u";
1174                         reg = <0x03f20000 0x10000>;
1175                         reg-names = "ctl";
1176
1177                         #phy-cells = <0>;
1178                 };
1179
1180                 p2u_hsio_10: phy@3f30000 {
1181                         compatible = "nvidia,tegra194-p2u";
1182                         reg = <0x03f30000 0x10000>;
1183                         reg-names = "ctl";
1184
1185                         #phy-cells = <0>;
1186                 };
1187
1188                 p2u_hsio_11: phy@3f40000 {
1189                         compatible = "nvidia,tegra194-p2u";
1190                         reg = <0x03f40000 0x10000>;
1191                         reg-names = "ctl";
1192
1193                         #phy-cells = <0>;
1194                 };
1195
1196                 hsp_aon: hsp@c150000 {
1197                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1198                         reg = <0x0c150000 0x90000>;
1199                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1203                         /*
1204                          * Shared interrupt 0 is routed only to AON/SPE, so
1205                          * we only have 4 shared interrupts for the CCPLEX.
1206                          */
1207                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
1208                         #mbox-cells = <2>;
1209                 };
1210
1211                 gen2_i2c: i2c@c240000 {
1212                         compatible = "nvidia,tegra194-i2c";
1213                         reg = <0x0c240000 0x10000>;
1214                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1215                         #address-cells = <1>;
1216                         #size-cells = <0>;
1217                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
1218                         clock-names = "div-clk";
1219                         resets = <&bpmp TEGRA194_RESET_I2C2>;
1220                         reset-names = "i2c";
1221                         status = "disabled";
1222                 };
1223
1224                 gen8_i2c: i2c@c250000 {
1225                         compatible = "nvidia,tegra194-i2c";
1226                         reg = <0x0c250000 0x10000>;
1227                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1228                         #address-cells = <1>;
1229                         #size-cells = <0>;
1230                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
1231                         clock-names = "div-clk";
1232                         resets = <&bpmp TEGRA194_RESET_I2C8>;
1233                         reset-names = "i2c";
1234                         status = "disabled";
1235                 };
1236
1237                 uartc: serial@c280000 {
1238                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1239                         reg = <0x0c280000 0x40>;
1240                         reg-shift = <2>;
1241                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1242                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
1243                         clock-names = "serial";
1244                         resets = <&bpmp TEGRA194_RESET_UARTC>;
1245                         reset-names = "serial";
1246                         status = "disabled";
1247                 };
1248
1249                 uartg: serial@c290000 {
1250                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1251                         reg = <0x0c290000 0x40>;
1252                         reg-shift = <2>;
1253                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1254                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
1255                         clock-names = "serial";
1256                         resets = <&bpmp TEGRA194_RESET_UARTG>;
1257                         reset-names = "serial";
1258                         status = "disabled";
1259                 };
1260
1261                 rtc: rtc@c2a0000 {
1262                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1263                         reg = <0x0c2a0000 0x10000>;
1264                         interrupt-parent = <&pmc>;
1265                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1266                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1267                         clock-names = "rtc";
1268                         status = "disabled";
1269                 };
1270
1271                 gpio_aon: gpio@c2f0000 {
1272                         compatible = "nvidia,tegra194-gpio-aon";
1273                         reg-names = "security", "gpio";
1274                         reg = <0xc2f0000 0x1000>,
1275                               <0xc2f1000 0x1000>;
1276                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1277                         gpio-controller;
1278                         #gpio-cells = <2>;
1279                         interrupt-controller;
1280                         #interrupt-cells = <2>;
1281                 };
1282
1283                 pwm4: pwm@c340000 {
1284                         compatible = "nvidia,tegra194-pwm",
1285                                      "nvidia,tegra186-pwm";
1286                         reg = <0xc340000 0x10000>;
1287                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
1288                         clock-names = "pwm";
1289                         resets = <&bpmp TEGRA194_RESET_PWM4>;
1290                         reset-names = "pwm";
1291                         status = "disabled";
1292                         #pwm-cells = <2>;
1293                 };
1294
1295                 pmc: pmc@c360000 {
1296                         compatible = "nvidia,tegra194-pmc";
1297                         reg = <0x0c360000 0x10000>,
1298                               <0x0c370000 0x10000>,
1299                               <0x0c380000 0x10000>,
1300                               <0x0c390000 0x10000>,
1301                               <0x0c3a0000 0x10000>;
1302                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1303
1304                         #interrupt-cells = <2>;
1305                         interrupt-controller;
1306                 };
1307
1308                 smmu: iommu@12000000 {
1309                         compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1310                         reg = <0x12000000 0x800000>,
1311                               <0x11000000 0x800000>;
1312                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1313                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1314                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1315                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1316                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1317                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1318                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1319                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1320                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1321                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1322                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1323                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1325                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1326                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1327                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1328                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1329                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1330                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1331                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1332                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1333                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1334                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1335                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1336                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1337                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1338                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1340                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1341                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1342                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1343                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1344                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1345                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1346                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1347                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1348                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1349                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1350                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1351                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1352                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1353                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1354                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1355                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1356                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1357                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1358                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1359                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1360                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1361                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1362                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1363                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1364                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1365                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1366                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1367                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1368                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1369                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1370                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1371                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1372                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1373                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1374                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1375                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1376                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1377                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1378                         stream-match-mask = <0x7f80>;
1379                         #global-interrupts = <2>;
1380                         #iommu-cells = <1>;
1381
1382                         nvidia,memory-controller = <&mc>;
1383                         status = "okay";
1384                 };
1385
1386                 host1x@13e00000 {
1387                         compatible = "nvidia,tegra194-host1x";
1388                         reg = <0x13e00000 0x10000>,
1389                               <0x13e10000 0x10000>;
1390                         reg-names = "hypervisor", "vm";
1391                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1392                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1393                         interrupt-names = "syncpt", "host1x";
1394                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1395                         clock-names = "host1x";
1396                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
1397                         reset-names = "host1x";
1398
1399                         #address-cells = <1>;
1400                         #size-cells = <1>;
1401
1402                         ranges = <0x15000000 0x15000000 0x01000000>;
1403                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1404                         interconnect-names = "dma-mem";
1405                         iommus = <&smmu TEGRA194_SID_HOST1X>;
1406
1407                         display-hub@15200000 {
1408                                 compatible = "nvidia,tegra194-display";
1409                                 reg = <0x15200000 0x00040000>;
1410                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1411                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1412                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1413                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1414                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1415                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1416                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1417                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1418                                               "wgrp3", "wgrp4", "wgrp5";
1419                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1420                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1421                                 clock-names = "disp", "hub";
1422                                 status = "disabled";
1423
1424                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1425
1426                                 #address-cells = <1>;
1427                                 #size-cells = <1>;
1428
1429                                 ranges = <0x15200000 0x15200000 0x40000>;
1430
1431                                 display@15200000 {
1432                                         compatible = "nvidia,tegra194-dc";
1433                                         reg = <0x15200000 0x10000>;
1434                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1435                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1436                                         clock-names = "dc";
1437                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1438                                         reset-names = "dc";
1439
1440                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1441                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1442                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1443                                         interconnect-names = "dma-mem", "read-1";
1444
1445                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1446                                         nvidia,head = <0>;
1447                                 };
1448
1449                                 display@15210000 {
1450                                         compatible = "nvidia,tegra194-dc";
1451                                         reg = <0x15210000 0x10000>;
1452                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1453                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1454                                         clock-names = "dc";
1455                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1456                                         reset-names = "dc";
1457
1458                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1459                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1460                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1461                                         interconnect-names = "dma-mem", "read-1";
1462
1463                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1464                                         nvidia,head = <1>;
1465                                 };
1466
1467                                 display@15220000 {
1468                                         compatible = "nvidia,tegra194-dc";
1469                                         reg = <0x15220000 0x10000>;
1470                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1471                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1472                                         clock-names = "dc";
1473                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1474                                         reset-names = "dc";
1475
1476                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1477                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1478                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1479                                         interconnect-names = "dma-mem", "read-1";
1480
1481                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1482                                         nvidia,head = <2>;
1483                                 };
1484
1485                                 display@15230000 {
1486                                         compatible = "nvidia,tegra194-dc";
1487                                         reg = <0x15230000 0x10000>;
1488                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1489                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1490                                         clock-names = "dc";
1491                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1492                                         reset-names = "dc";
1493
1494                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1495                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1496                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1497                                         interconnect-names = "dma-mem", "read-1";
1498
1499                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1500                                         nvidia,head = <3>;
1501                                 };
1502                         };
1503
1504                         vic@15340000 {
1505                                 compatible = "nvidia,tegra194-vic";
1506                                 reg = <0x15340000 0x00040000>;
1507                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1508                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
1509                                 clock-names = "vic";
1510                                 resets = <&bpmp TEGRA194_RESET_VIC>;
1511                                 reset-names = "vic";
1512
1513                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1514                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1515                                                 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1516                                 interconnect-names = "dma-mem", "write";
1517                                 iommus = <&smmu TEGRA194_SID_VIC>;
1518                         };
1519
1520                         dpaux0: dpaux@155c0000 {
1521                                 compatible = "nvidia,tegra194-dpaux";
1522                                 reg = <0x155c0000 0x10000>;
1523                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1524                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1525                                          <&bpmp TEGRA194_CLK_PLLDP>;
1526                                 clock-names = "dpaux", "parent";
1527                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
1528                                 reset-names = "dpaux";
1529                                 status = "disabled";
1530
1531                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1532
1533                                 state_dpaux0_aux: pinmux-aux {
1534                                         groups = "dpaux-io";
1535                                         function = "aux";
1536                                 };
1537
1538                                 state_dpaux0_i2c: pinmux-i2c {
1539                                         groups = "dpaux-io";
1540                                         function = "i2c";
1541                                 };
1542
1543                                 state_dpaux0_off: pinmux-off {
1544                                         groups = "dpaux-io";
1545                                         function = "off";
1546                                 };
1547
1548                                 i2c-bus {
1549                                         #address-cells = <1>;
1550                                         #size-cells = <0>;
1551                                 };
1552                         };
1553
1554                         dpaux1: dpaux@155d0000 {
1555                                 compatible = "nvidia,tegra194-dpaux";
1556                                 reg = <0x155d0000 0x10000>;
1557                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1558                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1559                                          <&bpmp TEGRA194_CLK_PLLDP>;
1560                                 clock-names = "dpaux", "parent";
1561                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1562                                 reset-names = "dpaux";
1563                                 status = "disabled";
1564
1565                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1566
1567                                 state_dpaux1_aux: pinmux-aux {
1568                                         groups = "dpaux-io";
1569                                         function = "aux";
1570                                 };
1571
1572                                 state_dpaux1_i2c: pinmux-i2c {
1573                                         groups = "dpaux-io";
1574                                         function = "i2c";
1575                                 };
1576
1577                                 state_dpaux1_off: pinmux-off {
1578                                         groups = "dpaux-io";
1579                                         function = "off";
1580                                 };
1581
1582                                 i2c-bus {
1583                                         #address-cells = <1>;
1584                                         #size-cells = <0>;
1585                                 };
1586                         };
1587
1588                         dpaux2: dpaux@155e0000 {
1589                                 compatible = "nvidia,tegra194-dpaux";
1590                                 reg = <0x155e0000 0x10000>;
1591                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1592                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1593                                          <&bpmp TEGRA194_CLK_PLLDP>;
1594                                 clock-names = "dpaux", "parent";
1595                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1596                                 reset-names = "dpaux";
1597                                 status = "disabled";
1598
1599                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1600
1601                                 state_dpaux2_aux: pinmux-aux {
1602                                         groups = "dpaux-io";
1603                                         function = "aux";
1604                                 };
1605
1606                                 state_dpaux2_i2c: pinmux-i2c {
1607                                         groups = "dpaux-io";
1608                                         function = "i2c";
1609                                 };
1610
1611                                 state_dpaux2_off: pinmux-off {
1612                                         groups = "dpaux-io";
1613                                         function = "off";
1614                                 };
1615
1616                                 i2c-bus {
1617                                         #address-cells = <1>;
1618                                         #size-cells = <0>;
1619                                 };
1620                         };
1621
1622                         dpaux3: dpaux@155f0000 {
1623                                 compatible = "nvidia,tegra194-dpaux";
1624                                 reg = <0x155f0000 0x10000>;
1625                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1626                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1627                                          <&bpmp TEGRA194_CLK_PLLDP>;
1628                                 clock-names = "dpaux", "parent";
1629                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1630                                 reset-names = "dpaux";
1631                                 status = "disabled";
1632
1633                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1634
1635                                 state_dpaux3_aux: pinmux-aux {
1636                                         groups = "dpaux-io";
1637                                         function = "aux";
1638                                 };
1639
1640                                 state_dpaux3_i2c: pinmux-i2c {
1641                                         groups = "dpaux-io";
1642                                         function = "i2c";
1643                                 };
1644
1645                                 state_dpaux3_off: pinmux-off {
1646                                         groups = "dpaux-io";
1647                                         function = "off";
1648                                 };
1649
1650                                 i2c-bus {
1651                                         #address-cells = <1>;
1652                                         #size-cells = <0>;
1653                                 };
1654                         };
1655
1656                         sor0: sor@15b00000 {
1657                                 compatible = "nvidia,tegra194-sor";
1658                                 reg = <0x15b00000 0x40000>;
1659                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1660                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1661                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
1662                                          <&bpmp TEGRA194_CLK_PLLD>,
1663                                          <&bpmp TEGRA194_CLK_PLLDP>,
1664                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1665                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1666                                 clock-names = "sor", "out", "parent", "dp", "safe",
1667                                               "pad";
1668                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
1669                                 reset-names = "sor";
1670                                 pinctrl-0 = <&state_dpaux0_aux>;
1671                                 pinctrl-1 = <&state_dpaux0_i2c>;
1672                                 pinctrl-2 = <&state_dpaux0_off>;
1673                                 pinctrl-names = "aux", "i2c", "off";
1674                                 status = "disabled";
1675
1676                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1677                                 nvidia,interface = <0>;
1678                         };
1679
1680                         sor1: sor@15b40000 {
1681                                 compatible = "nvidia,tegra194-sor";
1682                                 reg = <0x15b40000 0x40000>;
1683                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1684                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1685                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
1686                                          <&bpmp TEGRA194_CLK_PLLD2>,
1687                                          <&bpmp TEGRA194_CLK_PLLDP>,
1688                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1689                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1690                                 clock-names = "sor", "out", "parent", "dp", "safe",
1691                                               "pad";
1692                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
1693                                 reset-names = "sor";
1694                                 pinctrl-0 = <&state_dpaux1_aux>;
1695                                 pinctrl-1 = <&state_dpaux1_i2c>;
1696                                 pinctrl-2 = <&state_dpaux1_off>;
1697                                 pinctrl-names = "aux", "i2c", "off";
1698                                 status = "disabled";
1699
1700                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1701                                 nvidia,interface = <1>;
1702                         };
1703
1704                         sor2: sor@15b80000 {
1705                                 compatible = "nvidia,tegra194-sor";
1706                                 reg = <0x15b80000 0x40000>;
1707                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1708                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1709                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
1710                                          <&bpmp TEGRA194_CLK_PLLD3>,
1711                                          <&bpmp TEGRA194_CLK_PLLDP>,
1712                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1713                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1714                                 clock-names = "sor", "out", "parent", "dp", "safe",
1715                                               "pad";
1716                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
1717                                 reset-names = "sor";
1718                                 pinctrl-0 = <&state_dpaux2_aux>;
1719                                 pinctrl-1 = <&state_dpaux2_i2c>;
1720                                 pinctrl-2 = <&state_dpaux2_off>;
1721                                 pinctrl-names = "aux", "i2c", "off";
1722                                 status = "disabled";
1723
1724                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1725                                 nvidia,interface = <2>;
1726                         };
1727
1728                         sor3: sor@15bc0000 {
1729                                 compatible = "nvidia,tegra194-sor";
1730                                 reg = <0x15bc0000 0x40000>;
1731                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1732                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1733                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
1734                                          <&bpmp TEGRA194_CLK_PLLD4>,
1735                                          <&bpmp TEGRA194_CLK_PLLDP>,
1736                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1737                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1738                                 clock-names = "sor", "out", "parent", "dp", "safe",
1739                                               "pad";
1740                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
1741                                 reset-names = "sor";
1742                                 pinctrl-0 = <&state_dpaux3_aux>;
1743                                 pinctrl-1 = <&state_dpaux3_i2c>;
1744                                 pinctrl-2 = <&state_dpaux3_off>;
1745                                 pinctrl-names = "aux", "i2c", "off";
1746                                 status = "disabled";
1747
1748                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1749                                 nvidia,interface = <3>;
1750                         };
1751                 };
1752
1753                 gpu@17000000 {
1754                         compatible = "nvidia,gv11b";
1755                         reg = <0x17000000 0x1000000>,
1756                               <0x18000000 0x1000000>;
1757                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1758                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1759                         interrupt-names = "stall", "nonstall";
1760                         clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
1761                                  <&bpmp TEGRA194_CLK_GPU_PWR>,
1762                                  <&bpmp TEGRA194_CLK_FUSE>;
1763                         clock-names = "gpu", "pwr", "fuse";
1764                         resets = <&bpmp TEGRA194_RESET_GPU>;
1765                         reset-names = "gpu";
1766                         dma-coherent;
1767
1768                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1769                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
1770                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
1771                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
1772                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
1773                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
1774                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
1775                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
1776                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
1777                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
1778                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
1779                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
1780                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
1781                         interconnect-names = "dma-mem", "read-0-hp", "write-0",
1782                                              "read-1", "read-1-hp", "write-1",
1783                                              "read-2", "read-2-hp", "write-2",
1784                                              "read-3", "read-3-hp", "write-3";
1785                 };
1786         };
1787
1788         pcie@14100000 {
1789                 compatible = "nvidia,tegra194-pcie";
1790                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1791                 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
1792                       <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1793                       <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1794                       <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1795                 reg-names = "appl", "config", "atu_dma", "dbi";
1796
1797                 status = "disabled";
1798
1799                 #address-cells = <3>;
1800                 #size-cells = <2>;
1801                 device_type = "pci";
1802                 num-lanes = <1>;
1803                 num-viewport = <8>;
1804                 linux,pci-domain = <1>;
1805
1806                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1807                 clock-names = "core";
1808
1809                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1810                          <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1811                 reset-names = "apb", "core";
1812
1813                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1814                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1815                 interrupt-names = "intr", "msi";
1816
1817                 #interrupt-cells = <1>;
1818                 interrupt-map-mask = <0 0 0 0>;
1819                 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1820
1821                 nvidia,bpmp = <&bpmp 1>;
1822
1823                 nvidia,aspm-cmrt-us = <60>;
1824                 nvidia,aspm-pwr-on-t-us = <20>;
1825                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1826
1827                 bus-range = <0x0 0xff>;
1828
1829                 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1830                          <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1831                          <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1832
1833                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
1834                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
1835                 interconnect-names = "read", "write";
1836         };
1837
1838         pcie@14120000 {
1839                 compatible = "nvidia,tegra194-pcie";
1840                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1841                 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
1842                       <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1843                       <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1844                       <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1845                 reg-names = "appl", "config", "atu_dma", "dbi";
1846
1847                 status = "disabled";
1848
1849                 #address-cells = <3>;
1850                 #size-cells = <2>;
1851                 device_type = "pci";
1852                 num-lanes = <1>;
1853                 num-viewport = <8>;
1854                 linux,pci-domain = <2>;
1855
1856                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1857                 clock-names = "core";
1858
1859                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1860                          <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1861                 reset-names = "apb", "core";
1862
1863                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1864                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1865                 interrupt-names = "intr", "msi";
1866
1867                 #interrupt-cells = <1>;
1868                 interrupt-map-mask = <0 0 0 0>;
1869                 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1870
1871                 nvidia,bpmp = <&bpmp 2>;
1872
1873                 nvidia,aspm-cmrt-us = <60>;
1874                 nvidia,aspm-pwr-on-t-us = <20>;
1875                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1876
1877                 bus-range = <0x0 0xff>;
1878
1879                 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1880                          <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1881                          <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1882
1883                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
1884                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
1885                 interconnect-names = "read", "write";
1886         };
1887
1888         pcie@14140000 {
1889                 compatible = "nvidia,tegra194-pcie";
1890                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1891                 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
1892                       <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1893                       <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1894                       <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1895                 reg-names = "appl", "config", "atu_dma", "dbi";
1896
1897                 status = "disabled";
1898
1899                 #address-cells = <3>;
1900                 #size-cells = <2>;
1901                 device_type = "pci";
1902                 num-lanes = <1>;
1903                 num-viewport = <8>;
1904                 linux,pci-domain = <3>;
1905
1906                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1907                 clock-names = "core";
1908
1909                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1910                          <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1911                 reset-names = "apb", "core";
1912
1913                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1914                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1915                 interrupt-names = "intr", "msi";
1916
1917                 #interrupt-cells = <1>;
1918                 interrupt-map-mask = <0 0 0 0>;
1919                 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1920
1921                 nvidia,bpmp = <&bpmp 3>;
1922
1923                 nvidia,aspm-cmrt-us = <60>;
1924                 nvidia,aspm-pwr-on-t-us = <20>;
1925                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1926
1927                 bus-range = <0x0 0xff>;
1928
1929                 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1930                          <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
1931                          <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1932
1933                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
1934                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
1935                 interconnect-names = "read", "write";
1936         };
1937
1938         pcie@14160000 {
1939                 compatible = "nvidia,tegra194-pcie";
1940                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1941                 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
1942                       <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1943                       <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1944                       <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1945                 reg-names = "appl", "config", "atu_dma", "dbi";
1946
1947                 status = "disabled";
1948
1949                 #address-cells = <3>;
1950                 #size-cells = <2>;
1951                 device_type = "pci";
1952                 num-lanes = <4>;
1953                 num-viewport = <8>;
1954                 linux,pci-domain = <4>;
1955
1956                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1957                 clock-names = "core";
1958
1959                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1960                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1961                 reset-names = "apb", "core";
1962
1963                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1964                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1965                 interrupt-names = "intr", "msi";
1966
1967                 #interrupt-cells = <1>;
1968                 interrupt-map-mask = <0 0 0 0>;
1969                 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1970
1971                 nvidia,bpmp = <&bpmp 4>;
1972
1973                 nvidia,aspm-cmrt-us = <60>;
1974                 nvidia,aspm-pwr-on-t-us = <20>;
1975                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1976
1977                 bus-range = <0x0 0xff>;
1978
1979                 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1980                          <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1981                          <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1982
1983                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
1984                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
1985                 interconnect-names = "read", "write";
1986         };
1987
1988         pcie@14180000 {
1989                 compatible = "nvidia,tegra194-pcie";
1990                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1991                 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
1992                       <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
1993                       <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1994                       <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1995                 reg-names = "appl", "config", "atu_dma", "dbi";
1996
1997                 status = "disabled";
1998
1999                 #address-cells = <3>;
2000                 #size-cells = <2>;
2001                 device_type = "pci";
2002                 num-lanes = <8>;
2003                 num-viewport = <8>;
2004                 linux,pci-domain = <0>;
2005
2006                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2007                 clock-names = "core";
2008
2009                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2010                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2011                 reset-names = "apb", "core";
2012
2013                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2014                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2015                 interrupt-names = "intr", "msi";
2016
2017                 #interrupt-cells = <1>;
2018                 interrupt-map-mask = <0 0 0 0>;
2019                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2020
2021                 nvidia,bpmp = <&bpmp 0>;
2022
2023                 nvidia,aspm-cmrt-us = <60>;
2024                 nvidia,aspm-pwr-on-t-us = <20>;
2025                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2026
2027                 bus-range = <0x0 0xff>;
2028
2029                 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2030                          <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2031                          <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2032
2033                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2034                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2035                 interconnect-names = "read", "write";
2036         };
2037
2038         pcie@141a0000 {
2039                 compatible = "nvidia,tegra194-pcie";
2040                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2041                 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2042                       <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2043                       <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2044                       <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2045                 reg-names = "appl", "config", "atu_dma", "dbi";
2046
2047                 status = "disabled";
2048
2049                 #address-cells = <3>;
2050                 #size-cells = <2>;
2051                 device_type = "pci";
2052                 num-lanes = <8>;
2053                 num-viewport = <8>;
2054                 linux,pci-domain = <5>;
2055
2056                 pinctrl-names = "default";
2057                 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2058
2059                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
2060                          <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
2061                 clock-names = "core", "core_m";
2062
2063                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2064                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2065                 reset-names = "apb", "core";
2066
2067                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2068                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2069                 interrupt-names = "intr", "msi";
2070
2071                 nvidia,bpmp = <&bpmp 5>;
2072
2073                 #interrupt-cells = <1>;
2074                 interrupt-map-mask = <0 0 0 0>;
2075                 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2076
2077                 nvidia,aspm-cmrt-us = <60>;
2078                 nvidia,aspm-pwr-on-t-us = <20>;
2079                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2080
2081                 bus-range = <0x0 0xff>;
2082
2083                 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2084                          <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2085                          <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2086
2087                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2088                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2089                 interconnect-names = "read", "write";
2090         };
2091
2092         pcie_ep@14160000 {
2093                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2094                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2095                 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2096                       <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2097                       <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2098                       <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2099                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2100
2101                 status = "disabled";
2102
2103                 num-lanes = <4>;
2104                 num-ib-windows = <2>;
2105                 num-ob-windows = <8>;
2106
2107                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2108                 clock-names = "core";
2109
2110                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2111                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2112                 reset-names = "apb", "core";
2113
2114                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2115                 interrupt-names = "intr";
2116
2117                 nvidia,bpmp = <&bpmp 4>;
2118
2119                 nvidia,aspm-cmrt-us = <60>;
2120                 nvidia,aspm-pwr-on-t-us = <20>;
2121                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2122         };
2123
2124         pcie_ep@14180000 {
2125                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2126                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2127                 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2128                       <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2129                       <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2130                       <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2131                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2132
2133                 status = "disabled";
2134
2135                 num-lanes = <8>;
2136                 num-ib-windows = <2>;
2137                 num-ob-windows = <8>;
2138
2139                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2140                 clock-names = "core";
2141
2142                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2143                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2144                 reset-names = "apb", "core";
2145
2146                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2147                 interrupt-names = "intr";
2148
2149                 nvidia,bpmp = <&bpmp 0>;
2150
2151                 nvidia,aspm-cmrt-us = <60>;
2152                 nvidia,aspm-pwr-on-t-us = <20>;
2153                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2154         };
2155
2156         pcie_ep@141a0000 {
2157                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2158                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2159                 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2160                       <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2161                       <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2162                       <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2163                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2164
2165                 status = "disabled";
2166
2167                 num-lanes = <8>;
2168                 num-ib-windows = <2>;
2169                 num-ob-windows = <8>;
2170
2171                 pinctrl-names = "default";
2172                 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2173
2174                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2175                 clock-names = "core";
2176
2177                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2178                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2179                 reset-names = "apb", "core";
2180
2181                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2182                 interrupt-names = "intr";
2183
2184                 nvidia,bpmp = <&bpmp 5>;
2185
2186                 nvidia,aspm-cmrt-us = <60>;
2187                 nvidia,aspm-pwr-on-t-us = <20>;
2188                 nvidia,aspm-l0s-entrance-latency-us = <3>;
2189         };
2190
2191         sram@40000000 {
2192                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2193                 reg = <0x0 0x40000000 0x0 0x50000>;
2194                 #address-cells = <1>;
2195                 #size-cells = <1>;
2196                 ranges = <0x0 0x0 0x40000000 0x50000>;
2197
2198                 cpu_bpmp_tx: sram@4e000 {
2199                         reg = <0x4e000 0x1000>;
2200                         label = "cpu-bpmp-tx";
2201                         pool;
2202                 };
2203
2204                 cpu_bpmp_rx: sram@4f000 {
2205                         reg = <0x4f000 0x1000>;
2206                         label = "cpu-bpmp-rx";
2207                         pool;
2208                 };
2209         };
2210
2211         bpmp: bpmp {
2212                 compatible = "nvidia,tegra186-bpmp";
2213                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2214                                     TEGRA_HSP_DB_MASTER_BPMP>;
2215                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2216                 #clock-cells = <1>;
2217                 #reset-cells = <1>;
2218                 #power-domain-cells = <1>;
2219                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2220                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2221                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2222                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2223                 interconnect-names = "read", "write", "dma-mem", "dma-write";
2224                 iommus = <&smmu TEGRA194_SID_BPMP>;
2225
2226                 bpmp_i2c: i2c {
2227                         compatible = "nvidia,tegra186-bpmp-i2c";
2228                         nvidia,bpmp-bus-id = <5>;
2229                         #address-cells = <1>;
2230                         #size-cells = <0>;
2231                 };
2232
2233                 bpmp_thermal: thermal {
2234                         compatible = "nvidia,tegra186-bpmp-thermal";
2235                         #thermal-sensor-cells = <1>;
2236                 };
2237         };
2238
2239         cpus {
2240                 compatible = "nvidia,tegra194-ccplex";
2241                 nvidia,bpmp = <&bpmp>;
2242                 #address-cells = <1>;
2243                 #size-cells = <0>;
2244
2245                 cpu0_0: cpu@0 {
2246                         compatible = "nvidia,tegra194-carmel";
2247                         device_type = "cpu";
2248                         reg = <0x000>;
2249                         enable-method = "psci";
2250                         i-cache-size = <131072>;
2251                         i-cache-line-size = <64>;
2252                         i-cache-sets = <512>;
2253                         d-cache-size = <65536>;
2254                         d-cache-line-size = <64>;
2255                         d-cache-sets = <256>;
2256                         next-level-cache = <&l2c_0>;
2257                 };
2258
2259                 cpu0_1: cpu@1 {
2260                         compatible = "nvidia,tegra194-carmel";
2261                         device_type = "cpu";
2262                         reg = <0x001>;
2263                         enable-method = "psci";
2264                         i-cache-size = <131072>;
2265                         i-cache-line-size = <64>;
2266                         i-cache-sets = <512>;
2267                         d-cache-size = <65536>;
2268                         d-cache-line-size = <64>;
2269                         d-cache-sets = <256>;
2270                         next-level-cache = <&l2c_0>;
2271                 };
2272
2273                 cpu1_0: cpu@100 {
2274                         compatible = "nvidia,tegra194-carmel";
2275                         device_type = "cpu";
2276                         reg = <0x100>;
2277                         enable-method = "psci";
2278                         i-cache-size = <131072>;
2279                         i-cache-line-size = <64>;
2280                         i-cache-sets = <512>;
2281                         d-cache-size = <65536>;
2282                         d-cache-line-size = <64>;
2283                         d-cache-sets = <256>;
2284                         next-level-cache = <&l2c_1>;
2285                 };
2286
2287                 cpu1_1: cpu@101 {
2288                         compatible = "nvidia,tegra194-carmel";
2289                         device_type = "cpu";
2290                         reg = <0x101>;
2291                         enable-method = "psci";
2292                         i-cache-size = <131072>;
2293                         i-cache-line-size = <64>;
2294                         i-cache-sets = <512>;
2295                         d-cache-size = <65536>;
2296                         d-cache-line-size = <64>;
2297                         d-cache-sets = <256>;
2298                         next-level-cache = <&l2c_1>;
2299                 };
2300
2301                 cpu2_0: cpu@200 {
2302                         compatible = "nvidia,tegra194-carmel";
2303                         device_type = "cpu";
2304                         reg = <0x200>;
2305                         enable-method = "psci";
2306                         i-cache-size = <131072>;
2307                         i-cache-line-size = <64>;
2308                         i-cache-sets = <512>;
2309                         d-cache-size = <65536>;
2310                         d-cache-line-size = <64>;
2311                         d-cache-sets = <256>;
2312                         next-level-cache = <&l2c_2>;
2313                 };
2314
2315                 cpu2_1: cpu@201 {
2316                         compatible = "nvidia,tegra194-carmel";
2317                         device_type = "cpu";
2318                         reg = <0x201>;
2319                         enable-method = "psci";
2320                         i-cache-size = <131072>;
2321                         i-cache-line-size = <64>;
2322                         i-cache-sets = <512>;
2323                         d-cache-size = <65536>;
2324                         d-cache-line-size = <64>;
2325                         d-cache-sets = <256>;
2326                         next-level-cache = <&l2c_2>;
2327                 };
2328
2329                 cpu3_0: cpu@300 {
2330                         compatible = "nvidia,tegra194-carmel";
2331                         device_type = "cpu";
2332                         reg = <0x300>;
2333                         enable-method = "psci";
2334                         i-cache-size = <131072>;
2335                         i-cache-line-size = <64>;
2336                         i-cache-sets = <512>;
2337                         d-cache-size = <65536>;
2338                         d-cache-line-size = <64>;
2339                         d-cache-sets = <256>;
2340                         next-level-cache = <&l2c_3>;
2341                 };
2342
2343                 cpu3_1: cpu@301 {
2344                         compatible = "nvidia,tegra194-carmel";
2345                         device_type = "cpu";
2346                         reg = <0x301>;
2347                         enable-method = "psci";
2348                         i-cache-size = <131072>;
2349                         i-cache-line-size = <64>;
2350                         i-cache-sets = <512>;
2351                         d-cache-size = <65536>;
2352                         d-cache-line-size = <64>;
2353                         d-cache-sets = <256>;
2354                         next-level-cache = <&l2c_3>;
2355                 };
2356
2357                 cpu-map {
2358                         cluster0 {
2359                                 core0 {
2360                                         cpu = <&cpu0_0>;
2361                                 };
2362
2363                                 core1 {
2364                                         cpu = <&cpu0_1>;
2365                                 };
2366                         };
2367
2368                         cluster1 {
2369                                 core0 {
2370                                         cpu = <&cpu1_0>;
2371                                 };
2372
2373                                 core1 {
2374                                         cpu = <&cpu1_1>;
2375                                 };
2376                         };
2377
2378                         cluster2 {
2379                                 core0 {
2380                                         cpu = <&cpu2_0>;
2381                                 };
2382
2383                                 core1 {
2384                                         cpu = <&cpu2_1>;
2385                                 };
2386                         };
2387
2388                         cluster3 {
2389                                 core0 {
2390                                         cpu = <&cpu3_0>;
2391                                 };
2392
2393                                 core1 {
2394                                         cpu = <&cpu3_1>;
2395                                 };
2396                         };
2397                 };
2398
2399                 l2c_0: l2-cache0 {
2400                         cache-size = <2097152>;
2401                         cache-line-size = <64>;
2402                         cache-sets = <2048>;
2403                         next-level-cache = <&l3c>;
2404                 };
2405
2406                 l2c_1: l2-cache1 {
2407                         cache-size = <2097152>;
2408                         cache-line-size = <64>;
2409                         cache-sets = <2048>;
2410                         next-level-cache = <&l3c>;
2411                 };
2412
2413                 l2c_2: l2-cache2 {
2414                         cache-size = <2097152>;
2415                         cache-line-size = <64>;
2416                         cache-sets = <2048>;
2417                         next-level-cache = <&l3c>;
2418                 };
2419
2420                 l2c_3: l2-cache3 {
2421                         cache-size = <2097152>;
2422                         cache-line-size = <64>;
2423                         cache-sets = <2048>;
2424                         next-level-cache = <&l3c>;
2425                 };
2426
2427                 l3c: l3-cache {
2428                         cache-size = <4194304>;
2429                         cache-line-size = <64>;
2430                         cache-sets = <4096>;
2431                 };
2432         };
2433
2434         pmu {
2435                 compatible = "arm,armv8-pmuv3";
2436                 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2437                              <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2438                              <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2439                              <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2440                              <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
2441                              <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
2442                              <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
2443                              <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
2444                 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
2445                                       &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
2446         };
2447
2448         psci {
2449                 compatible = "arm,psci-1.0";
2450                 status = "okay";
2451                 method = "smc";
2452         };
2453
2454         sound {
2455                 status = "disabled";
2456
2457                 clocks = <&bpmp TEGRA194_CLK_PLLA>,
2458                          <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2459                 clock-names = "pll_a", "plla_out0";
2460                 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2461                                   <&bpmp TEGRA194_CLK_PLLA_OUT0>,
2462                                   <&bpmp TEGRA194_CLK_AUD_MCLK>;
2463                 assigned-clock-parents = <0>,
2464                                          <&bpmp TEGRA194_CLK_PLLA>,
2465                                          <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2466                 /*
2467                  * PLLA supports dynamic ramp. Below initial rate is chosen
2468                  * for this to work and oscillate between base rates required
2469                  * for 8x and 11.025x sample rate streams.
2470                  */
2471                 assigned-clock-rates = <258000000>;
2472         };
2473
2474         tcu: tcu {
2475                 compatible = "nvidia,tegra194-tcu";
2476                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2477                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2478                 mbox-names = "rx", "tx";
2479         };
2480
2481         thermal-zones {
2482                 cpu {
2483                         thermal-sensors = <&{/bpmp/thermal}
2484                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2485                         status = "disabled";
2486                 };
2487
2488                 gpu {
2489                         thermal-sensors = <&{/bpmp/thermal}
2490                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2491                         status = "disabled";
2492                 };
2493
2494                 aux {
2495                         thermal-sensors = <&{/bpmp/thermal}
2496                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2497                         status = "disabled";
2498                 };
2499
2500                 pllx {
2501                         thermal-sensors = <&{/bpmp/thermal}
2502                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2503                         status = "disabled";
2504                 };
2505
2506                 ao {
2507                         thermal-sensors = <&{/bpmp/thermal}
2508                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
2509                         status = "disabled";
2510                 };
2511
2512                 tj {
2513                         thermal-sensors = <&{/bpmp/thermal}
2514                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2515                         status = "disabled";
2516                 };
2517         };
2518
2519         timer {
2520                 compatible = "arm,armv8-timer";
2521                 interrupts = <GIC_PPI 13
2522                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2523                              <GIC_PPI 14
2524                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2525                              <GIC_PPI 11
2526                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2527                              <GIC_PPI 10
2528                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2529                 interrupt-parent = <&gic>;
2530                 always-on;
2531         };
2532 };