1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
13 compatible = "nvidia,tegra194";
14 interrupt-parent = <&gic>;
18 /* control backbone */
20 compatible = "simple-bus";
23 ranges = <0x0 0x0 0x0 0x40000000>;
26 compatible = "nvidia,tegra194-misc";
27 reg = <0x00100000 0xf000>,
32 compatible = "nvidia,tegra194-gpio";
33 reg-names = "security", "gpio";
34 reg = <0x2200000 0x10000>,
36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
42 #interrupt-cells = <2>;
49 compatible = "nvidia,tegra194-eqos",
50 "nvidia,tegra186-eqos",
51 "snps,dwc-qos-ethernet-4.10";
52 reg = <0x02490000 0x10000>;
53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
55 <&bpmp TEGRA194_CLK_EQOS_AXI>,
56 <&bpmp TEGRA194_CLK_EQOS_RX>,
57 <&bpmp TEGRA194_CLK_EQOS_TX>,
58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
60 resets = <&bpmp TEGRA194_RESET_EQOS>;
62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
64 interconnect-names = "dma-mem", "write";
65 iommus = <&smmu TEGRA194_SID_EQOS>;
68 snps,write-requests = <1>;
69 snps,read-requests = <3>;
70 snps,burst-map = <0x7>;
76 compatible = "nvidia,tegra194-aconnect",
77 "nvidia,tegra210-aconnect";
78 clocks = <&bpmp TEGRA194_CLK_APE>,
79 <&bpmp TEGRA194_CLK_APB2APE>;
80 clock-names = "ape", "apb2ape";
81 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
84 ranges = <0x02900000 0x02900000 0x200000>;
87 adma: dma-controller@2930000 {
88 compatible = "nvidia,tegra194-adma",
89 "nvidia,tegra186-adma";
90 reg = <0x02930000 0x20000>;
91 interrupt-parent = <&agic>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&bpmp TEGRA194_CLK_AHUB>;
126 clock-names = "d_audio";
130 agic: interrupt-controller@2a40000 {
131 compatible = "nvidia,tegra194-agic",
132 "nvidia,tegra210-agic";
133 #interrupt-cells = <3>;
134 interrupt-controller;
135 reg = <0x02a41000 0x1000>,
137 interrupts = <GIC_SPI 145
138 (GIC_CPU_MASK_SIMPLE(4) |
139 IRQ_TYPE_LEVEL_HIGH)>;
140 clocks = <&bpmp TEGRA194_CLK_APE>;
145 tegra_ahub: ahub@2900800 {
146 compatible = "nvidia,tegra194-ahub",
147 "nvidia,tegra186-ahub";
148 reg = <0x02900800 0x800>;
149 clocks = <&bpmp TEGRA194_CLK_AHUB>;
150 clock-names = "ahub";
151 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
152 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
153 #address-cells = <1>;
155 ranges = <0x02900800 0x02900800 0x11800>;
158 tegra_admaif: admaif@290f000 {
159 compatible = "nvidia,tegra194-admaif",
160 "nvidia,tegra186-admaif";
161 reg = <0x0290f000 0x1000>;
162 dmas = <&adma 1>, <&adma 1>,
163 <&adma 2>, <&adma 2>,
164 <&adma 3>, <&adma 3>,
165 <&adma 4>, <&adma 4>,
166 <&adma 5>, <&adma 5>,
167 <&adma 6>, <&adma 6>,
168 <&adma 7>, <&adma 7>,
169 <&adma 8>, <&adma 8>,
170 <&adma 9>, <&adma 9>,
171 <&adma 10>, <&adma 10>,
172 <&adma 11>, <&adma 11>,
173 <&adma 12>, <&adma 12>,
174 <&adma 13>, <&adma 13>,
175 <&adma 14>, <&adma 14>,
176 <&adma 15>, <&adma 15>,
177 <&adma 16>, <&adma 16>,
178 <&adma 17>, <&adma 17>,
179 <&adma 18>, <&adma 18>,
180 <&adma 19>, <&adma 19>,
181 <&adma 20>, <&adma 20>;
182 dma-names = "rx1", "tx1",
205 tegra_i2s1: i2s@2901000 {
206 compatible = "nvidia,tegra194-i2s",
207 "nvidia,tegra210-i2s";
208 reg = <0x2901000 0x100>;
209 clocks = <&bpmp TEGRA194_CLK_I2S1>,
210 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
213 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S1";
219 tegra_i2s2: i2s@2901100 {
220 compatible = "nvidia,tegra194-i2s",
221 "nvidia,tegra210-i2s";
222 reg = <0x2901100 0x100>;
223 clocks = <&bpmp TEGRA194_CLK_I2S2>,
224 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
227 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S2";
233 tegra_i2s3: i2s@2901200 {
234 compatible = "nvidia,tegra194-i2s",
235 "nvidia,tegra210-i2s";
236 reg = <0x2901200 0x100>;
237 clocks = <&bpmp TEGRA194_CLK_I2S3>,
238 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
241 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S3";
247 tegra_i2s4: i2s@2901300 {
248 compatible = "nvidia,tegra194-i2s",
249 "nvidia,tegra210-i2s";
250 reg = <0x2901300 0x100>;
251 clocks = <&bpmp TEGRA194_CLK_I2S4>,
252 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
255 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S4";
261 tegra_i2s5: i2s@2901400 {
262 compatible = "nvidia,tegra194-i2s",
263 "nvidia,tegra210-i2s";
264 reg = <0x2901400 0x100>;
265 clocks = <&bpmp TEGRA194_CLK_I2S5>,
266 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
269 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S5";
275 tegra_i2s6: i2s@2901500 {
276 compatible = "nvidia,tegra194-i2s",
277 "nvidia,tegra210-i2s";
278 reg = <0x2901500 0x100>;
279 clocks = <&bpmp TEGRA194_CLK_I2S6>,
280 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
281 clock-names = "i2s", "sync_input";
282 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
283 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
284 assigned-clock-rates = <1536000>;
285 sound-name-prefix = "I2S6";
289 tegra_dmic1: dmic@2904000 {
290 compatible = "nvidia,tegra194-dmic",
291 "nvidia,tegra210-dmic";
292 reg = <0x2904000 0x100>;
293 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
294 clock-names = "dmic";
295 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
296 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
297 assigned-clock-rates = <3072000>;
298 sound-name-prefix = "DMIC1";
302 tegra_dmic2: dmic@2904100 {
303 compatible = "nvidia,tegra194-dmic",
304 "nvidia,tegra210-dmic";
305 reg = <0x2904100 0x100>;
306 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
307 clock-names = "dmic";
308 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
309 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
310 assigned-clock-rates = <3072000>;
311 sound-name-prefix = "DMIC2";
315 tegra_dmic3: dmic@2904200 {
316 compatible = "nvidia,tegra194-dmic",
317 "nvidia,tegra210-dmic";
318 reg = <0x2904200 0x100>;
319 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
320 clock-names = "dmic";
321 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
322 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
323 assigned-clock-rates = <3072000>;
324 sound-name-prefix = "DMIC3";
328 tegra_dmic4: dmic@2904300 {
329 compatible = "nvidia,tegra194-dmic",
330 "nvidia,tegra210-dmic";
331 reg = <0x2904300 0x100>;
332 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
333 clock-names = "dmic";
334 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
335 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
336 assigned-clock-rates = <3072000>;
337 sound-name-prefix = "DMIC4";
341 tegra_dspk1: dspk@2905000 {
342 compatible = "nvidia,tegra194-dspk",
343 "nvidia,tegra186-dspk";
344 reg = <0x2905000 0x100>;
345 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
346 clock-names = "dspk";
347 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
348 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
349 assigned-clock-rates = <12288000>;
350 sound-name-prefix = "DSPK1";
354 tegra_dspk2: dspk@2905100 {
355 compatible = "nvidia,tegra194-dspk",
356 "nvidia,tegra186-dspk";
357 reg = <0x2905100 0x100>;
358 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
359 clock-names = "dspk";
360 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
361 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
362 assigned-clock-rates = <12288000>;
363 sound-name-prefix = "DSPK2";
369 pinmux: pinmux@2430000 {
370 compatible = "nvidia,tegra194-pinmux";
371 reg = <0x2430000 0x17000>,
376 pex_rst_c5_out_state: pex_rst_c5_out {
378 nvidia,pins = "pex_l5_rst_n_pgg1";
379 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
380 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
383 nvidia,tristate = <TEGRA_PIN_DISABLE>;
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
388 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
390 nvidia,pins = "pex_l5_clkreq_n_pgg0";
391 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
392 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
396 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
401 mc: memory-controller@2c00000 {
402 compatible = "nvidia,tegra194-mc";
403 reg = <0x02c00000 0x100000>,
404 <0x02b80000 0x040000>,
405 <0x01700000 0x100000>;
406 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
407 #interconnect-cells = <1>;
410 #address-cells = <2>;
413 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
414 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
415 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
418 * Bit 39 of addresses passing through the memory
419 * controller selects the XBAR format used when memory
420 * is accessed. This is used to transparently access
421 * memory in the XBAR format used by the discrete GPU
422 * (bit 39 set) or Tegra (bit 39 clear).
424 * As a consequence, the operating system must ensure
425 * that bit 39 is never used implicitly, for example
426 * via an I/O virtual address mapping of an IOMMU. If
427 * devices require access to the XBAR switch, their
428 * drivers must set this bit explicitly.
430 * Limit the DMA range for memory clients to [38:0].
432 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
434 emc: external-memory-controller@2c60000 {
435 compatible = "nvidia,tegra194-emc";
436 reg = <0x0 0x02c60000 0x0 0x90000>,
437 <0x0 0x01780000 0x0 0x80000>;
438 clocks = <&bpmp TEGRA194_CLK_EMC>;
441 #interconnect-cells = <0>;
443 nvidia,bpmp = <&bpmp>;
447 uarta: serial@3100000 {
448 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
449 reg = <0x03100000 0x40>;
451 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&bpmp TEGRA194_CLK_UARTA>;
453 clock-names = "serial";
454 resets = <&bpmp TEGRA194_RESET_UARTA>;
455 reset-names = "serial";
459 uartb: serial@3110000 {
460 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
461 reg = <0x03110000 0x40>;
463 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&bpmp TEGRA194_CLK_UARTB>;
465 clock-names = "serial";
466 resets = <&bpmp TEGRA194_RESET_UARTB>;
467 reset-names = "serial";
471 uartd: serial@3130000 {
472 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
473 reg = <0x03130000 0x40>;
475 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&bpmp TEGRA194_CLK_UARTD>;
477 clock-names = "serial";
478 resets = <&bpmp TEGRA194_RESET_UARTD>;
479 reset-names = "serial";
483 uarte: serial@3140000 {
484 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
485 reg = <0x03140000 0x40>;
487 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&bpmp TEGRA194_CLK_UARTE>;
489 clock-names = "serial";
490 resets = <&bpmp TEGRA194_RESET_UARTE>;
491 reset-names = "serial";
495 uartf: serial@3150000 {
496 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
497 reg = <0x03150000 0x40>;
499 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&bpmp TEGRA194_CLK_UARTF>;
501 clock-names = "serial";
502 resets = <&bpmp TEGRA194_RESET_UARTF>;
503 reset-names = "serial";
507 gen1_i2c: i2c@3160000 {
508 compatible = "nvidia,tegra194-i2c";
509 reg = <0x03160000 0x10000>;
510 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
511 #address-cells = <1>;
513 clocks = <&bpmp TEGRA194_CLK_I2C1>;
514 clock-names = "div-clk";
515 resets = <&bpmp TEGRA194_RESET_I2C1>;
520 uarth: serial@3170000 {
521 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
522 reg = <0x03170000 0x40>;
524 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&bpmp TEGRA194_CLK_UARTH>;
526 clock-names = "serial";
527 resets = <&bpmp TEGRA194_RESET_UARTH>;
528 reset-names = "serial";
532 cam_i2c: i2c@3180000 {
533 compatible = "nvidia,tegra194-i2c";
534 reg = <0x03180000 0x10000>;
535 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
536 #address-cells = <1>;
538 clocks = <&bpmp TEGRA194_CLK_I2C3>;
539 clock-names = "div-clk";
540 resets = <&bpmp TEGRA194_RESET_I2C3>;
545 /* shares pads with dpaux1 */
546 dp_aux_ch1_i2c: i2c@3190000 {
547 compatible = "nvidia,tegra194-i2c";
548 reg = <0x03190000 0x10000>;
549 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
550 #address-cells = <1>;
552 clocks = <&bpmp TEGRA194_CLK_I2C4>;
553 clock-names = "div-clk";
554 resets = <&bpmp TEGRA194_RESET_I2C4>;
556 pinctrl-0 = <&state_dpaux1_i2c>;
557 pinctrl-1 = <&state_dpaux1_off>;
558 pinctrl-names = "default", "idle";
562 /* shares pads with dpaux0 */
563 dp_aux_ch0_i2c: i2c@31b0000 {
564 compatible = "nvidia,tegra194-i2c";
565 reg = <0x031b0000 0x10000>;
566 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
567 #address-cells = <1>;
569 clocks = <&bpmp TEGRA194_CLK_I2C6>;
570 clock-names = "div-clk";
571 resets = <&bpmp TEGRA194_RESET_I2C6>;
573 pinctrl-0 = <&state_dpaux0_i2c>;
574 pinctrl-1 = <&state_dpaux0_off>;
575 pinctrl-names = "default", "idle";
579 /* shares pads with dpaux2 */
580 dp_aux_ch2_i2c: i2c@31c0000 {
581 compatible = "nvidia,tegra194-i2c";
582 reg = <0x031c0000 0x10000>;
583 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
584 #address-cells = <1>;
586 clocks = <&bpmp TEGRA194_CLK_I2C7>;
587 clock-names = "div-clk";
588 resets = <&bpmp TEGRA194_RESET_I2C7>;
590 pinctrl-0 = <&state_dpaux2_i2c>;
591 pinctrl-1 = <&state_dpaux2_off>;
592 pinctrl-names = "default", "idle";
596 /* shares pads with dpaux3 */
597 dp_aux_ch3_i2c: i2c@31e0000 {
598 compatible = "nvidia,tegra194-i2c";
599 reg = <0x031e0000 0x10000>;
600 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
601 #address-cells = <1>;
603 clocks = <&bpmp TEGRA194_CLK_I2C9>;
604 clock-names = "div-clk";
605 resets = <&bpmp TEGRA194_RESET_I2C9>;
607 pinctrl-0 = <&state_dpaux3_i2c>;
608 pinctrl-1 = <&state_dpaux3_off>;
609 pinctrl-names = "default", "idle";
614 compatible = "nvidia,tegra194-qspi";
615 reg = <0x3270000 0x1000>;
616 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
617 #address-cells = <1>;
619 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
620 <&bpmp TEGRA194_CLK_QSPI0_PM>;
621 clock-names = "qspi", "qspi_out";
622 resets = <&bpmp TEGRA194_RESET_QSPI0>;
623 reset-names = "qspi";
628 compatible = "nvidia,tegra194-qspi";
629 reg = <0x3300000 0x1000>;
630 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
631 #address-cells = <1>;
633 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
634 <&bpmp TEGRA194_CLK_QSPI1_PM>;
635 clock-names = "qspi", "qspi_out";
636 resets = <&bpmp TEGRA194_RESET_QSPI1>;
637 reset-names = "qspi";
642 compatible = "nvidia,tegra194-pwm",
643 "nvidia,tegra186-pwm";
644 reg = <0x3280000 0x10000>;
645 clocks = <&bpmp TEGRA194_CLK_PWM1>;
647 resets = <&bpmp TEGRA194_RESET_PWM1>;
654 compatible = "nvidia,tegra194-pwm",
655 "nvidia,tegra186-pwm";
656 reg = <0x3290000 0x10000>;
657 clocks = <&bpmp TEGRA194_CLK_PWM2>;
659 resets = <&bpmp TEGRA194_RESET_PWM2>;
666 compatible = "nvidia,tegra194-pwm",
667 "nvidia,tegra186-pwm";
668 reg = <0x32a0000 0x10000>;
669 clocks = <&bpmp TEGRA194_CLK_PWM3>;
671 resets = <&bpmp TEGRA194_RESET_PWM3>;
678 compatible = "nvidia,tegra194-pwm",
679 "nvidia,tegra186-pwm";
680 reg = <0x32c0000 0x10000>;
681 clocks = <&bpmp TEGRA194_CLK_PWM5>;
683 resets = <&bpmp TEGRA194_RESET_PWM5>;
690 compatible = "nvidia,tegra194-pwm",
691 "nvidia,tegra186-pwm";
692 reg = <0x32d0000 0x10000>;
693 clocks = <&bpmp TEGRA194_CLK_PWM6>;
695 resets = <&bpmp TEGRA194_RESET_PWM6>;
702 compatible = "nvidia,tegra194-pwm",
703 "nvidia,tegra186-pwm";
704 reg = <0x32e0000 0x10000>;
705 clocks = <&bpmp TEGRA194_CLK_PWM7>;
707 resets = <&bpmp TEGRA194_RESET_PWM7>;
714 compatible = "nvidia,tegra194-pwm",
715 "nvidia,tegra186-pwm";
716 reg = <0x32f0000 0x10000>;
717 clocks = <&bpmp TEGRA194_CLK_PWM8>;
719 resets = <&bpmp TEGRA194_RESET_PWM8>;
725 sdmmc1: mmc@3400000 {
726 compatible = "nvidia,tegra194-sdhci";
727 reg = <0x03400000 0x10000>;
728 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
730 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
731 clock-names = "sdhci", "tmclk";
732 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
733 reset-names = "sdhci";
734 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
735 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
736 interconnect-names = "dma-mem", "write";
737 iommus = <&smmu TEGRA194_SID_SDMMC1>;
738 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
740 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
742 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
743 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
745 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
746 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
747 nvidia,default-tap = <0x9>;
748 nvidia,default-trim = <0x5>;
752 sdmmc3: mmc@3440000 {
753 compatible = "nvidia,tegra194-sdhci";
754 reg = <0x03440000 0x10000>;
755 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
757 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
758 clock-names = "sdhci", "tmclk";
759 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
760 reset-names = "sdhci";
761 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
762 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
763 interconnect-names = "dma-mem", "write";
764 iommus = <&smmu TEGRA194_SID_SDMMC3>;
765 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
766 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
767 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
768 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
770 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
771 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
773 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
774 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
775 nvidia,default-tap = <0x9>;
776 nvidia,default-trim = <0x5>;
780 sdmmc4: mmc@3460000 {
781 compatible = "nvidia,tegra194-sdhci";
782 reg = <0x03460000 0x10000>;
783 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
785 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
786 clock-names = "sdhci", "tmclk";
787 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
788 <&bpmp TEGRA194_CLK_PLLC4>;
789 assigned-clock-parents =
790 <&bpmp TEGRA194_CLK_PLLC4>;
791 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
792 reset-names = "sdhci";
793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
794 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
795 interconnect-names = "dma-mem", "write";
796 iommus = <&smmu TEGRA194_SID_SDMMC4>;
797 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
798 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
799 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
800 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
802 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
803 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
805 nvidia,default-tap = <0x8>;
806 nvidia,default-trim = <0x14>;
807 nvidia,dqs-trim = <40>;
813 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
814 reg = <0x3510000 0x10000>;
815 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&bpmp TEGRA194_CLK_HDA>,
817 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
818 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
819 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
820 resets = <&bpmp TEGRA194_RESET_HDA>,
821 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
822 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
823 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
826 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
827 interconnect-names = "dma-mem", "write";
828 iommus = <&smmu TEGRA194_SID_HDA>;
832 xusb_padctl: padctl@3520000 {
833 compatible = "nvidia,tegra194-xusb-padctl";
834 reg = <0x03520000 0x1000>,
836 reg-names = "padctl", "ao";
837 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
839 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
840 reset-names = "padctl";
846 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
851 nvidia,function = "xusb";
857 nvidia,function = "xusb";
863 nvidia,function = "xusb";
869 nvidia,function = "xusb";
879 nvidia,function = "xusb";
885 nvidia,function = "xusb";
891 nvidia,function = "xusb";
897 nvidia,function = "xusb";
941 compatible = "nvidia,tegra194-xudc";
942 reg = <0x03550000 0x8000>,
944 reg-names = "base", "fpci";
945 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
947 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
948 <&bpmp TEGRA194_CLK_XUSB_SS>,
949 <&bpmp TEGRA194_CLK_XUSB_FS>;
950 clock-names = "dev", "ss", "ss_src", "fs_src";
951 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
952 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
953 interconnect-names = "dma-mem", "write";
954 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
955 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
956 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
957 power-domain-names = "dev", "ss";
958 nvidia,xusb-padctl = <&xusb_padctl>;
963 compatible = "nvidia,tegra194-xusb";
964 reg = <0x03610000 0x40000>,
965 <0x03600000 0x10000>;
966 reg-names = "hcd", "fpci";
968 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
972 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
973 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
974 <&bpmp TEGRA194_CLK_XUSB_SS>,
975 <&bpmp TEGRA194_CLK_CLK_M>,
976 <&bpmp TEGRA194_CLK_XUSB_FS>,
977 <&bpmp TEGRA194_CLK_UTMIPLL>,
978 <&bpmp TEGRA194_CLK_CLK_M>,
979 <&bpmp TEGRA194_CLK_PLLE>;
980 clock-names = "xusb_host", "xusb_falcon_src",
981 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
982 "xusb_fs_src", "pll_u_480m", "clk_m",
984 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
985 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
986 interconnect-names = "dma-mem", "write";
987 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
989 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
990 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
991 power-domain-names = "xusb_host", "xusb_ss";
993 nvidia,xusb-padctl = <&xusb_padctl>;
998 compatible = "nvidia,tegra194-efuse";
999 reg = <0x03820000 0x10000>;
1000 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1001 clock-names = "fuse";
1004 gic: interrupt-controller@3881000 {
1005 compatible = "arm,gic-400";
1006 #interrupt-cells = <3>;
1007 interrupt-controller;
1008 reg = <0x03881000 0x1000>,
1009 <0x03882000 0x2000>,
1010 <0x03884000 0x2000>,
1011 <0x03886000 0x2000>;
1012 interrupts = <GIC_PPI 9
1013 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1014 interrupt-parent = <&gic>;
1018 compatible = "nvidia,tegra194-cec";
1019 reg = <0x03960000 0x10000>;
1020 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&bpmp TEGRA194_CLK_CEC>;
1022 clock-names = "cec";
1023 status = "disabled";
1026 hsp_top0: hsp@3c00000 {
1027 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1028 reg = <0x03c00000 0xa0000>;
1029 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1039 "shared3", "shared4", "shared5", "shared6",
1044 p2u_hsio_0: phy@3e10000 {
1045 compatible = "nvidia,tegra194-p2u";
1046 reg = <0x03e10000 0x10000>;
1052 p2u_hsio_1: phy@3e20000 {
1053 compatible = "nvidia,tegra194-p2u";
1054 reg = <0x03e20000 0x10000>;
1060 p2u_hsio_2: phy@3e30000 {
1061 compatible = "nvidia,tegra194-p2u";
1062 reg = <0x03e30000 0x10000>;
1068 p2u_hsio_3: phy@3e40000 {
1069 compatible = "nvidia,tegra194-p2u";
1070 reg = <0x03e40000 0x10000>;
1076 p2u_hsio_4: phy@3e50000 {
1077 compatible = "nvidia,tegra194-p2u";
1078 reg = <0x03e50000 0x10000>;
1084 p2u_hsio_5: phy@3e60000 {
1085 compatible = "nvidia,tegra194-p2u";
1086 reg = <0x03e60000 0x10000>;
1092 p2u_hsio_6: phy@3e70000 {
1093 compatible = "nvidia,tegra194-p2u";
1094 reg = <0x03e70000 0x10000>;
1100 p2u_hsio_7: phy@3e80000 {
1101 compatible = "nvidia,tegra194-p2u";
1102 reg = <0x03e80000 0x10000>;
1108 p2u_hsio_8: phy@3e90000 {
1109 compatible = "nvidia,tegra194-p2u";
1110 reg = <0x03e90000 0x10000>;
1116 p2u_hsio_9: phy@3ea0000 {
1117 compatible = "nvidia,tegra194-p2u";
1118 reg = <0x03ea0000 0x10000>;
1124 p2u_nvhs_0: phy@3eb0000 {
1125 compatible = "nvidia,tegra194-p2u";
1126 reg = <0x03eb0000 0x10000>;
1132 p2u_nvhs_1: phy@3ec0000 {
1133 compatible = "nvidia,tegra194-p2u";
1134 reg = <0x03ec0000 0x10000>;
1140 p2u_nvhs_2: phy@3ed0000 {
1141 compatible = "nvidia,tegra194-p2u";
1142 reg = <0x03ed0000 0x10000>;
1148 p2u_nvhs_3: phy@3ee0000 {
1149 compatible = "nvidia,tegra194-p2u";
1150 reg = <0x03ee0000 0x10000>;
1156 p2u_nvhs_4: phy@3ef0000 {
1157 compatible = "nvidia,tegra194-p2u";
1158 reg = <0x03ef0000 0x10000>;
1164 p2u_nvhs_5: phy@3f00000 {
1165 compatible = "nvidia,tegra194-p2u";
1166 reg = <0x03f00000 0x10000>;
1172 p2u_nvhs_6: phy@3f10000 {
1173 compatible = "nvidia,tegra194-p2u";
1174 reg = <0x03f10000 0x10000>;
1180 p2u_nvhs_7: phy@3f20000 {
1181 compatible = "nvidia,tegra194-p2u";
1182 reg = <0x03f20000 0x10000>;
1188 p2u_hsio_10: phy@3f30000 {
1189 compatible = "nvidia,tegra194-p2u";
1190 reg = <0x03f30000 0x10000>;
1196 p2u_hsio_11: phy@3f40000 {
1197 compatible = "nvidia,tegra194-p2u";
1198 reg = <0x03f40000 0x10000>;
1204 hsp_aon: hsp@c150000 {
1205 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1206 reg = <0x0c150000 0x90000>;
1207 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1212 * Shared interrupt 0 is routed only to AON/SPE, so
1213 * we only have 4 shared interrupts for the CCPLEX.
1215 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1219 gen2_i2c: i2c@c240000 {
1220 compatible = "nvidia,tegra194-i2c";
1221 reg = <0x0c240000 0x10000>;
1222 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1223 #address-cells = <1>;
1225 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1226 clock-names = "div-clk";
1227 resets = <&bpmp TEGRA194_RESET_I2C2>;
1228 reset-names = "i2c";
1229 status = "disabled";
1232 gen8_i2c: i2c@c250000 {
1233 compatible = "nvidia,tegra194-i2c";
1234 reg = <0x0c250000 0x10000>;
1235 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1236 #address-cells = <1>;
1238 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1239 clock-names = "div-clk";
1240 resets = <&bpmp TEGRA194_RESET_I2C8>;
1241 reset-names = "i2c";
1242 status = "disabled";
1245 uartc: serial@c280000 {
1246 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1247 reg = <0x0c280000 0x40>;
1249 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1251 clock-names = "serial";
1252 resets = <&bpmp TEGRA194_RESET_UARTC>;
1253 reset-names = "serial";
1254 status = "disabled";
1257 uartg: serial@c290000 {
1258 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1259 reg = <0x0c290000 0x40>;
1261 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1263 clock-names = "serial";
1264 resets = <&bpmp TEGRA194_RESET_UARTG>;
1265 reset-names = "serial";
1266 status = "disabled";
1270 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1271 reg = <0x0c2a0000 0x10000>;
1272 interrupt-parent = <&pmc>;
1273 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1274 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1275 clock-names = "rtc";
1276 status = "disabled";
1279 gpio_aon: gpio@c2f0000 {
1280 compatible = "nvidia,tegra194-gpio-aon";
1281 reg-names = "security", "gpio";
1282 reg = <0xc2f0000 0x1000>,
1284 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1287 interrupt-controller;
1288 #interrupt-cells = <2>;
1292 compatible = "nvidia,tegra194-pwm",
1293 "nvidia,tegra186-pwm";
1294 reg = <0xc340000 0x10000>;
1295 clocks = <&bpmp TEGRA194_CLK_PWM4>;
1296 clock-names = "pwm";
1297 resets = <&bpmp TEGRA194_RESET_PWM4>;
1298 reset-names = "pwm";
1299 status = "disabled";
1304 compatible = "nvidia,tegra194-pmc";
1305 reg = <0x0c360000 0x10000>,
1306 <0x0c370000 0x10000>,
1307 <0x0c380000 0x10000>,
1308 <0x0c390000 0x10000>,
1309 <0x0c3a0000 0x10000>;
1310 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1312 #interrupt-cells = <2>;
1313 interrupt-controller;
1316 smmu: iommu@12000000 {
1317 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1318 reg = <0x12000000 0x800000>,
1319 <0x11000000 0x800000>;
1320 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1386 stream-match-mask = <0x7f80>;
1387 #global-interrupts = <2>;
1390 nvidia,memory-controller = <&mc>;
1395 compatible = "nvidia,tegra194-host1x";
1396 reg = <0x13e00000 0x10000>,
1397 <0x13e10000 0x10000>;
1398 reg-names = "hypervisor", "vm";
1399 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1401 interrupt-names = "syncpt", "host1x";
1402 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1403 clock-names = "host1x";
1404 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1405 reset-names = "host1x";
1407 #address-cells = <1>;
1410 ranges = <0x15000000 0x15000000 0x01000000>;
1411 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1412 interconnect-names = "dma-mem";
1413 iommus = <&smmu TEGRA194_SID_HOST1X>;
1415 display-hub@15200000 {
1416 compatible = "nvidia,tegra194-display";
1417 reg = <0x15200000 0x00040000>;
1418 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1419 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1420 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1421 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1422 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1423 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1424 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1425 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1426 "wgrp3", "wgrp4", "wgrp5";
1427 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1428 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1429 clock-names = "disp", "hub";
1430 status = "disabled";
1432 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1434 #address-cells = <1>;
1437 ranges = <0x15200000 0x15200000 0x40000>;
1440 compatible = "nvidia,tegra194-dc";
1441 reg = <0x15200000 0x10000>;
1442 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1445 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1448 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1449 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1450 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1451 interconnect-names = "dma-mem", "read-1";
1453 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1458 compatible = "nvidia,tegra194-dc";
1459 reg = <0x15210000 0x10000>;
1460 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1463 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1466 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1467 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1468 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1469 interconnect-names = "dma-mem", "read-1";
1471 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1476 compatible = "nvidia,tegra194-dc";
1477 reg = <0x15220000 0x10000>;
1478 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1481 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1484 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1485 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1486 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1487 interconnect-names = "dma-mem", "read-1";
1489 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1494 compatible = "nvidia,tegra194-dc";
1495 reg = <0x15230000 0x10000>;
1496 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1499 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1502 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1503 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1504 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1505 interconnect-names = "dma-mem", "read-1";
1507 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1513 compatible = "nvidia,tegra194-vic";
1514 reg = <0x15340000 0x00040000>;
1515 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1516 clocks = <&bpmp TEGRA194_CLK_VIC>;
1517 clock-names = "vic";
1518 resets = <&bpmp TEGRA194_RESET_VIC>;
1519 reset-names = "vic";
1521 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1522 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1523 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1524 interconnect-names = "dma-mem", "write";
1525 iommus = <&smmu TEGRA194_SID_VIC>;
1528 dpaux0: dpaux@155c0000 {
1529 compatible = "nvidia,tegra194-dpaux";
1530 reg = <0x155c0000 0x10000>;
1531 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1532 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1533 <&bpmp TEGRA194_CLK_PLLDP>;
1534 clock-names = "dpaux", "parent";
1535 resets = <&bpmp TEGRA194_RESET_DPAUX>;
1536 reset-names = "dpaux";
1537 status = "disabled";
1539 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1541 state_dpaux0_aux: pinmux-aux {
1542 groups = "dpaux-io";
1546 state_dpaux0_i2c: pinmux-i2c {
1547 groups = "dpaux-io";
1551 state_dpaux0_off: pinmux-off {
1552 groups = "dpaux-io";
1557 #address-cells = <1>;
1562 dpaux1: dpaux@155d0000 {
1563 compatible = "nvidia,tegra194-dpaux";
1564 reg = <0x155d0000 0x10000>;
1565 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1567 <&bpmp TEGRA194_CLK_PLLDP>;
1568 clock-names = "dpaux", "parent";
1569 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1570 reset-names = "dpaux";
1571 status = "disabled";
1573 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1575 state_dpaux1_aux: pinmux-aux {
1576 groups = "dpaux-io";
1580 state_dpaux1_i2c: pinmux-i2c {
1581 groups = "dpaux-io";
1585 state_dpaux1_off: pinmux-off {
1586 groups = "dpaux-io";
1591 #address-cells = <1>;
1596 dpaux2: dpaux@155e0000 {
1597 compatible = "nvidia,tegra194-dpaux";
1598 reg = <0x155e0000 0x10000>;
1599 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1600 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1601 <&bpmp TEGRA194_CLK_PLLDP>;
1602 clock-names = "dpaux", "parent";
1603 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1604 reset-names = "dpaux";
1605 status = "disabled";
1607 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1609 state_dpaux2_aux: pinmux-aux {
1610 groups = "dpaux-io";
1614 state_dpaux2_i2c: pinmux-i2c {
1615 groups = "dpaux-io";
1619 state_dpaux2_off: pinmux-off {
1620 groups = "dpaux-io";
1625 #address-cells = <1>;
1630 dpaux3: dpaux@155f0000 {
1631 compatible = "nvidia,tegra194-dpaux";
1632 reg = <0x155f0000 0x10000>;
1633 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1634 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1635 <&bpmp TEGRA194_CLK_PLLDP>;
1636 clock-names = "dpaux", "parent";
1637 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1638 reset-names = "dpaux";
1639 status = "disabled";
1641 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1643 state_dpaux3_aux: pinmux-aux {
1644 groups = "dpaux-io";
1648 state_dpaux3_i2c: pinmux-i2c {
1649 groups = "dpaux-io";
1653 state_dpaux3_off: pinmux-off {
1654 groups = "dpaux-io";
1659 #address-cells = <1>;
1664 sor0: sor@15b00000 {
1665 compatible = "nvidia,tegra194-sor";
1666 reg = <0x15b00000 0x40000>;
1667 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1668 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1669 <&bpmp TEGRA194_CLK_SOR0_OUT>,
1670 <&bpmp TEGRA194_CLK_PLLD>,
1671 <&bpmp TEGRA194_CLK_PLLDP>,
1672 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1673 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1674 clock-names = "sor", "out", "parent", "dp", "safe",
1676 resets = <&bpmp TEGRA194_RESET_SOR0>;
1677 reset-names = "sor";
1678 pinctrl-0 = <&state_dpaux0_aux>;
1679 pinctrl-1 = <&state_dpaux0_i2c>;
1680 pinctrl-2 = <&state_dpaux0_off>;
1681 pinctrl-names = "aux", "i2c", "off";
1682 status = "disabled";
1684 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1685 nvidia,interface = <0>;
1688 sor1: sor@15b40000 {
1689 compatible = "nvidia,tegra194-sor";
1690 reg = <0x15b40000 0x40000>;
1691 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1692 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1693 <&bpmp TEGRA194_CLK_SOR1_OUT>,
1694 <&bpmp TEGRA194_CLK_PLLD2>,
1695 <&bpmp TEGRA194_CLK_PLLDP>,
1696 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1697 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1698 clock-names = "sor", "out", "parent", "dp", "safe",
1700 resets = <&bpmp TEGRA194_RESET_SOR1>;
1701 reset-names = "sor";
1702 pinctrl-0 = <&state_dpaux1_aux>;
1703 pinctrl-1 = <&state_dpaux1_i2c>;
1704 pinctrl-2 = <&state_dpaux1_off>;
1705 pinctrl-names = "aux", "i2c", "off";
1706 status = "disabled";
1708 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1709 nvidia,interface = <1>;
1712 sor2: sor@15b80000 {
1713 compatible = "nvidia,tegra194-sor";
1714 reg = <0x15b80000 0x40000>;
1715 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1716 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1717 <&bpmp TEGRA194_CLK_SOR2_OUT>,
1718 <&bpmp TEGRA194_CLK_PLLD3>,
1719 <&bpmp TEGRA194_CLK_PLLDP>,
1720 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1721 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1722 clock-names = "sor", "out", "parent", "dp", "safe",
1724 resets = <&bpmp TEGRA194_RESET_SOR2>;
1725 reset-names = "sor";
1726 pinctrl-0 = <&state_dpaux2_aux>;
1727 pinctrl-1 = <&state_dpaux2_i2c>;
1728 pinctrl-2 = <&state_dpaux2_off>;
1729 pinctrl-names = "aux", "i2c", "off";
1730 status = "disabled";
1732 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1733 nvidia,interface = <2>;
1736 sor3: sor@15bc0000 {
1737 compatible = "nvidia,tegra194-sor";
1738 reg = <0x15bc0000 0x40000>;
1739 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1740 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1741 <&bpmp TEGRA194_CLK_SOR3_OUT>,
1742 <&bpmp TEGRA194_CLK_PLLD4>,
1743 <&bpmp TEGRA194_CLK_PLLDP>,
1744 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1745 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1746 clock-names = "sor", "out", "parent", "dp", "safe",
1748 resets = <&bpmp TEGRA194_RESET_SOR3>;
1749 reset-names = "sor";
1750 pinctrl-0 = <&state_dpaux3_aux>;
1751 pinctrl-1 = <&state_dpaux3_i2c>;
1752 pinctrl-2 = <&state_dpaux3_off>;
1753 pinctrl-names = "aux", "i2c", "off";
1754 status = "disabled";
1756 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1757 nvidia,interface = <3>;
1762 compatible = "nvidia,gv11b";
1763 reg = <0x17000000 0x1000000>,
1764 <0x18000000 0x1000000>;
1765 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1767 interrupt-names = "stall", "nonstall";
1768 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
1769 <&bpmp TEGRA194_CLK_GPU_PWR>,
1770 <&bpmp TEGRA194_CLK_FUSE>;
1771 clock-names = "gpu", "pwr", "fuse";
1772 resets = <&bpmp TEGRA194_RESET_GPU>;
1773 reset-names = "gpu";
1776 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1777 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
1778 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
1779 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
1780 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
1781 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
1782 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
1783 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
1784 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
1785 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
1786 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
1787 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
1788 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
1789 interconnect-names = "dma-mem", "read-0-hp", "write-0",
1790 "read-1", "read-1-hp", "write-1",
1791 "read-2", "read-2-hp", "write-2",
1792 "read-3", "read-3-hp", "write-3";
1797 compatible = "nvidia,tegra194-pcie";
1798 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1799 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
1800 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1801 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1802 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
1803 reg-names = "appl", "config", "atu_dma", "dbi";
1805 status = "disabled";
1807 #address-cells = <3>;
1809 device_type = "pci";
1812 linux,pci-domain = <1>;
1814 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1815 clock-names = "core";
1817 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1818 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1819 reset-names = "apb", "core";
1821 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1822 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1823 interrupt-names = "intr", "msi";
1825 #interrupt-cells = <1>;
1826 interrupt-map-mask = <0 0 0 0>;
1827 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1829 nvidia,bpmp = <&bpmp 1>;
1831 nvidia,aspm-cmrt-us = <60>;
1832 nvidia,aspm-pwr-on-t-us = <20>;
1833 nvidia,aspm-l0s-entrance-latency-us = <3>;
1835 bus-range = <0x0 0xff>;
1837 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1838 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1839 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1841 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
1842 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
1843 interconnect-names = "read", "write";
1847 compatible = "nvidia,tegra194-pcie";
1848 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1849 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
1850 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1851 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1852 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
1853 reg-names = "appl", "config", "atu_dma", "dbi";
1855 status = "disabled";
1857 #address-cells = <3>;
1859 device_type = "pci";
1862 linux,pci-domain = <2>;
1864 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1865 clock-names = "core";
1867 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1868 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1869 reset-names = "apb", "core";
1871 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1872 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1873 interrupt-names = "intr", "msi";
1875 #interrupt-cells = <1>;
1876 interrupt-map-mask = <0 0 0 0>;
1877 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1879 nvidia,bpmp = <&bpmp 2>;
1881 nvidia,aspm-cmrt-us = <60>;
1882 nvidia,aspm-pwr-on-t-us = <20>;
1883 nvidia,aspm-l0s-entrance-latency-us = <3>;
1885 bus-range = <0x0 0xff>;
1887 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1888 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1889 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1891 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
1892 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
1893 interconnect-names = "read", "write";
1897 compatible = "nvidia,tegra194-pcie";
1898 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1899 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
1900 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1901 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1902 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
1903 reg-names = "appl", "config", "atu_dma", "dbi";
1905 status = "disabled";
1907 #address-cells = <3>;
1909 device_type = "pci";
1912 linux,pci-domain = <3>;
1914 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1915 clock-names = "core";
1917 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1918 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1919 reset-names = "apb", "core";
1921 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1922 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1923 interrupt-names = "intr", "msi";
1925 #interrupt-cells = <1>;
1926 interrupt-map-mask = <0 0 0 0>;
1927 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1929 nvidia,bpmp = <&bpmp 3>;
1931 nvidia,aspm-cmrt-us = <60>;
1932 nvidia,aspm-pwr-on-t-us = <20>;
1933 nvidia,aspm-l0s-entrance-latency-us = <3>;
1935 bus-range = <0x0 0xff>;
1937 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1938 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
1939 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1941 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
1942 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
1943 interconnect-names = "read", "write";
1947 compatible = "nvidia,tegra194-pcie";
1948 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1949 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
1950 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1951 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1952 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
1953 reg-names = "appl", "config", "atu_dma", "dbi";
1955 status = "disabled";
1957 #address-cells = <3>;
1959 device_type = "pci";
1962 linux,pci-domain = <4>;
1964 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1965 clock-names = "core";
1967 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1968 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1969 reset-names = "apb", "core";
1971 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1972 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1973 interrupt-names = "intr", "msi";
1975 #interrupt-cells = <1>;
1976 interrupt-map-mask = <0 0 0 0>;
1977 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1979 nvidia,bpmp = <&bpmp 4>;
1981 nvidia,aspm-cmrt-us = <60>;
1982 nvidia,aspm-pwr-on-t-us = <20>;
1983 nvidia,aspm-l0s-entrance-latency-us = <3>;
1985 bus-range = <0x0 0xff>;
1987 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1988 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1989 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1991 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
1992 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
1993 interconnect-names = "read", "write";
1997 compatible = "nvidia,tegra194-pcie";
1998 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1999 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2000 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2001 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2002 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2003 reg-names = "appl", "config", "atu_dma", "dbi";
2005 status = "disabled";
2007 #address-cells = <3>;
2009 device_type = "pci";
2012 linux,pci-domain = <0>;
2014 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2015 clock-names = "core";
2017 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2018 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2019 reset-names = "apb", "core";
2021 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2022 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2023 interrupt-names = "intr", "msi";
2025 #interrupt-cells = <1>;
2026 interrupt-map-mask = <0 0 0 0>;
2027 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2029 nvidia,bpmp = <&bpmp 0>;
2031 nvidia,aspm-cmrt-us = <60>;
2032 nvidia,aspm-pwr-on-t-us = <20>;
2033 nvidia,aspm-l0s-entrance-latency-us = <3>;
2035 bus-range = <0x0 0xff>;
2037 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2038 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2039 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2041 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2042 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2043 interconnect-names = "read", "write";
2047 compatible = "nvidia,tegra194-pcie";
2048 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2049 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2050 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2051 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2052 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2053 reg-names = "appl", "config", "atu_dma", "dbi";
2055 status = "disabled";
2057 #address-cells = <3>;
2059 device_type = "pci";
2062 linux,pci-domain = <5>;
2064 pinctrl-names = "default";
2065 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2067 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
2068 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
2069 clock-names = "core", "core_m";
2071 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2072 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2073 reset-names = "apb", "core";
2075 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2076 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2077 interrupt-names = "intr", "msi";
2079 nvidia,bpmp = <&bpmp 5>;
2081 #interrupt-cells = <1>;
2082 interrupt-map-mask = <0 0 0 0>;
2083 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2085 nvidia,aspm-cmrt-us = <60>;
2086 nvidia,aspm-pwr-on-t-us = <20>;
2087 nvidia,aspm-l0s-entrance-latency-us = <3>;
2089 bus-range = <0x0 0xff>;
2091 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2092 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2093 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2095 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2096 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2097 interconnect-names = "read", "write";
2101 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2102 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2103 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2104 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2105 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2106 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2107 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2109 status = "disabled";
2112 num-ib-windows = <2>;
2113 num-ob-windows = <8>;
2115 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2116 clock-names = "core";
2118 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2119 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2120 reset-names = "apb", "core";
2122 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2123 interrupt-names = "intr";
2125 nvidia,bpmp = <&bpmp 4>;
2127 nvidia,aspm-cmrt-us = <60>;
2128 nvidia,aspm-pwr-on-t-us = <20>;
2129 nvidia,aspm-l0s-entrance-latency-us = <3>;
2133 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2134 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2135 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2136 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2137 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2138 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2139 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2141 status = "disabled";
2144 num-ib-windows = <2>;
2145 num-ob-windows = <8>;
2147 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2148 clock-names = "core";
2150 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2151 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2152 reset-names = "apb", "core";
2154 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2155 interrupt-names = "intr";
2157 nvidia,bpmp = <&bpmp 0>;
2159 nvidia,aspm-cmrt-us = <60>;
2160 nvidia,aspm-pwr-on-t-us = <20>;
2161 nvidia,aspm-l0s-entrance-latency-us = <3>;
2165 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2167 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2168 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2169 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2170 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2171 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2173 status = "disabled";
2176 num-ib-windows = <2>;
2177 num-ob-windows = <8>;
2179 pinctrl-names = "default";
2180 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2182 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2183 clock-names = "core";
2185 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2186 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2187 reset-names = "apb", "core";
2189 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2190 interrupt-names = "intr";
2192 nvidia,bpmp = <&bpmp 5>;
2194 nvidia,aspm-cmrt-us = <60>;
2195 nvidia,aspm-pwr-on-t-us = <20>;
2196 nvidia,aspm-l0s-entrance-latency-us = <3>;
2200 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2201 reg = <0x0 0x40000000 0x0 0x50000>;
2202 #address-cells = <1>;
2204 ranges = <0x0 0x0 0x40000000 0x50000>;
2206 cpu_bpmp_tx: sram@4e000 {
2207 reg = <0x4e000 0x1000>;
2208 label = "cpu-bpmp-tx";
2212 cpu_bpmp_rx: sram@4f000 {
2213 reg = <0x4f000 0x1000>;
2214 label = "cpu-bpmp-rx";
2220 compatible = "nvidia,tegra186-bpmp";
2221 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2222 TEGRA_HSP_DB_MASTER_BPMP>;
2223 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
2226 #power-domain-cells = <1>;
2227 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2228 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2229 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2230 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2231 interconnect-names = "read", "write", "dma-mem", "dma-write";
2232 iommus = <&smmu TEGRA194_SID_BPMP>;
2235 compatible = "nvidia,tegra186-bpmp-i2c";
2236 nvidia,bpmp-bus-id = <5>;
2237 #address-cells = <1>;
2241 bpmp_thermal: thermal {
2242 compatible = "nvidia,tegra186-bpmp-thermal";
2243 #thermal-sensor-cells = <1>;
2248 compatible = "nvidia,tegra194-ccplex";
2249 nvidia,bpmp = <&bpmp>;
2250 #address-cells = <1>;
2254 compatible = "nvidia,tegra194-carmel";
2255 device_type = "cpu";
2257 enable-method = "psci";
2258 i-cache-size = <131072>;
2259 i-cache-line-size = <64>;
2260 i-cache-sets = <512>;
2261 d-cache-size = <65536>;
2262 d-cache-line-size = <64>;
2263 d-cache-sets = <256>;
2264 next-level-cache = <&l2c_0>;
2268 compatible = "nvidia,tegra194-carmel";
2269 device_type = "cpu";
2271 enable-method = "psci";
2272 i-cache-size = <131072>;
2273 i-cache-line-size = <64>;
2274 i-cache-sets = <512>;
2275 d-cache-size = <65536>;
2276 d-cache-line-size = <64>;
2277 d-cache-sets = <256>;
2278 next-level-cache = <&l2c_0>;
2282 compatible = "nvidia,tegra194-carmel";
2283 device_type = "cpu";
2285 enable-method = "psci";
2286 i-cache-size = <131072>;
2287 i-cache-line-size = <64>;
2288 i-cache-sets = <512>;
2289 d-cache-size = <65536>;
2290 d-cache-line-size = <64>;
2291 d-cache-sets = <256>;
2292 next-level-cache = <&l2c_1>;
2296 compatible = "nvidia,tegra194-carmel";
2297 device_type = "cpu";
2299 enable-method = "psci";
2300 i-cache-size = <131072>;
2301 i-cache-line-size = <64>;
2302 i-cache-sets = <512>;
2303 d-cache-size = <65536>;
2304 d-cache-line-size = <64>;
2305 d-cache-sets = <256>;
2306 next-level-cache = <&l2c_1>;
2310 compatible = "nvidia,tegra194-carmel";
2311 device_type = "cpu";
2313 enable-method = "psci";
2314 i-cache-size = <131072>;
2315 i-cache-line-size = <64>;
2316 i-cache-sets = <512>;
2317 d-cache-size = <65536>;
2318 d-cache-line-size = <64>;
2319 d-cache-sets = <256>;
2320 next-level-cache = <&l2c_2>;
2324 compatible = "nvidia,tegra194-carmel";
2325 device_type = "cpu";
2327 enable-method = "psci";
2328 i-cache-size = <131072>;
2329 i-cache-line-size = <64>;
2330 i-cache-sets = <512>;
2331 d-cache-size = <65536>;
2332 d-cache-line-size = <64>;
2333 d-cache-sets = <256>;
2334 next-level-cache = <&l2c_2>;
2338 compatible = "nvidia,tegra194-carmel";
2339 device_type = "cpu";
2341 enable-method = "psci";
2342 i-cache-size = <131072>;
2343 i-cache-line-size = <64>;
2344 i-cache-sets = <512>;
2345 d-cache-size = <65536>;
2346 d-cache-line-size = <64>;
2347 d-cache-sets = <256>;
2348 next-level-cache = <&l2c_3>;
2352 compatible = "nvidia,tegra194-carmel";
2353 device_type = "cpu";
2355 enable-method = "psci";
2356 i-cache-size = <131072>;
2357 i-cache-line-size = <64>;
2358 i-cache-sets = <512>;
2359 d-cache-size = <65536>;
2360 d-cache-line-size = <64>;
2361 d-cache-sets = <256>;
2362 next-level-cache = <&l2c_3>;
2408 cache-size = <2097152>;
2409 cache-line-size = <64>;
2410 cache-sets = <2048>;
2411 next-level-cache = <&l3c>;
2415 cache-size = <2097152>;
2416 cache-line-size = <64>;
2417 cache-sets = <2048>;
2418 next-level-cache = <&l3c>;
2422 cache-size = <2097152>;
2423 cache-line-size = <64>;
2424 cache-sets = <2048>;
2425 next-level-cache = <&l3c>;
2429 cache-size = <2097152>;
2430 cache-line-size = <64>;
2431 cache-sets = <2048>;
2432 next-level-cache = <&l3c>;
2436 cache-size = <4194304>;
2437 cache-line-size = <64>;
2438 cache-sets = <4096>;
2443 compatible = "arm,armv8-pmuv3";
2444 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2448 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
2449 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
2450 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
2452 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
2453 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
2457 compatible = "arm,psci-1.0";
2463 status = "disabled";
2465 clocks = <&bpmp TEGRA194_CLK_PLLA>,
2466 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2467 clock-names = "pll_a", "plla_out0";
2468 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2469 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
2470 <&bpmp TEGRA194_CLK_AUD_MCLK>;
2471 assigned-clock-parents = <0>,
2472 <&bpmp TEGRA194_CLK_PLLA>,
2473 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
2475 * PLLA supports dynamic ramp. Below initial rate is chosen
2476 * for this to work and oscillate between base rates required
2477 * for 8x and 11.025x sample rate streams.
2479 assigned-clock-rates = <258000000>;
2481 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
2482 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
2483 interconnect-names = "dma-mem", "write";
2484 iommus = <&smmu TEGRA194_SID_APE>;
2488 compatible = "nvidia,tegra194-tcu";
2489 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2490 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2491 mbox-names = "rx", "tx";
2496 thermal-sensors = <&{/bpmp/thermal}
2497 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2498 status = "disabled";
2502 thermal-sensors = <&{/bpmp/thermal}
2503 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2504 status = "disabled";
2508 thermal-sensors = <&{/bpmp/thermal}
2509 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2510 status = "disabled";
2514 thermal-sensors = <&{/bpmp/thermal}
2515 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2516 status = "disabled";
2520 thermal-sensors = <&{/bpmp/thermal}
2521 TEGRA194_BPMP_THERMAL_ZONE_AO>;
2522 status = "disabled";
2526 thermal-sensors = <&{/bpmp/thermal}
2527 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2528 status = "disabled";
2533 compatible = "arm,armv8-timer";
2534 interrupts = <GIC_PPI 13
2535 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2537 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2539 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2541 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2542 interrupt-parent = <&gic>;