1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
63 iommus = <&smmu TEGRA186_SID_EQOS>;
66 snps,write-requests = <1>;
67 snps,read-requests = <3>;
68 snps,burst-map = <0x7>;
73 memory-controller@2c00000 {
74 compatible = "nvidia,tegra186-mc";
75 reg = <0x0 0x02c00000 0x0 0xb0000>;
79 uarta: serial@3100000 {
80 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
81 reg = <0x0 0x03100000 0x0 0x40>;
83 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&bpmp TEGRA186_CLK_UARTA>;
85 clock-names = "serial";
86 resets = <&bpmp TEGRA186_RESET_UARTA>;
87 reset-names = "serial";
91 uartb: serial@3110000 {
92 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
93 reg = <0x0 0x03110000 0x0 0x40>;
95 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&bpmp TEGRA186_CLK_UARTB>;
97 clock-names = "serial";
98 resets = <&bpmp TEGRA186_RESET_UARTB>;
99 reset-names = "serial";
103 uartd: serial@3130000 {
104 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
105 reg = <0x0 0x03130000 0x0 0x40>;
107 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&bpmp TEGRA186_CLK_UARTD>;
109 clock-names = "serial";
110 resets = <&bpmp TEGRA186_RESET_UARTD>;
111 reset-names = "serial";
115 uarte: serial@3140000 {
116 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
117 reg = <0x0 0x03140000 0x0 0x40>;
119 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&bpmp TEGRA186_CLK_UARTE>;
121 clock-names = "serial";
122 resets = <&bpmp TEGRA186_RESET_UARTE>;
123 reset-names = "serial";
127 uartf: serial@3150000 {
128 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
129 reg = <0x0 0x03150000 0x0 0x40>;
131 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&bpmp TEGRA186_CLK_UARTF>;
133 clock-names = "serial";
134 resets = <&bpmp TEGRA186_RESET_UARTF>;
135 reset-names = "serial";
139 gen1_i2c: i2c@3160000 {
140 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
141 reg = <0x0 0x03160000 0x0 0x10000>;
142 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
143 #address-cells = <1>;
145 clocks = <&bpmp TEGRA186_CLK_I2C1>;
146 clock-names = "div-clk";
147 resets = <&bpmp TEGRA186_RESET_I2C1>;
152 cam_i2c: i2c@3180000 {
153 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
154 reg = <0x0 0x03180000 0x0 0x10000>;
155 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
156 #address-cells = <1>;
158 clocks = <&bpmp TEGRA186_CLK_I2C3>;
159 clock-names = "div-clk";
160 resets = <&bpmp TEGRA186_RESET_I2C3>;
165 /* shares pads with dpaux1 */
166 dp_aux_ch1_i2c: i2c@3190000 {
167 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
168 reg = <0x0 0x03190000 0x0 0x10000>;
169 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
170 #address-cells = <1>;
172 clocks = <&bpmp TEGRA186_CLK_I2C4>;
173 clock-names = "div-clk";
174 resets = <&bpmp TEGRA186_RESET_I2C4>;
179 /* controlled by BPMP, should not be enabled */
180 pwr_i2c: i2c@31a0000 {
181 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
182 reg = <0x0 0x031a0000 0x0 0x10000>;
183 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>;
186 clocks = <&bpmp TEGRA186_CLK_I2C5>;
187 clock-names = "div-clk";
188 resets = <&bpmp TEGRA186_RESET_I2C5>;
193 /* shares pads with dpaux0 */
194 dp_aux_ch0_i2c: i2c@31b0000 {
195 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
196 reg = <0x0 0x031b0000 0x0 0x10000>;
197 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
198 #address-cells = <1>;
200 clocks = <&bpmp TEGRA186_CLK_I2C6>;
201 clock-names = "div-clk";
202 resets = <&bpmp TEGRA186_RESET_I2C6>;
207 gen7_i2c: i2c@31c0000 {
208 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
209 reg = <0x0 0x031c0000 0x0 0x10000>;
210 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
213 clocks = <&bpmp TEGRA186_CLK_I2C7>;
214 clock-names = "div-clk";
215 resets = <&bpmp TEGRA186_RESET_I2C7>;
220 gen9_i2c: i2c@31e0000 {
221 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
222 reg = <0x0 0x031e0000 0x0 0x10000>;
223 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>;
226 clocks = <&bpmp TEGRA186_CLK_I2C9>;
227 clock-names = "div-clk";
228 resets = <&bpmp TEGRA186_RESET_I2C9>;
233 sdmmc1: sdhci@3400000 {
234 compatible = "nvidia,tegra186-sdhci";
235 reg = <0x0 0x03400000 0x0 0x10000>;
236 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
238 clock-names = "sdhci";
239 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
240 reset-names = "sdhci";
241 iommus = <&smmu TEGRA186_SID_SDMMC1>;
242 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
243 pinctrl-0 = <&sdmmc1_3v3>;
244 pinctrl-1 = <&sdmmc1_1v8>;
245 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
246 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
247 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
248 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
249 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
250 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
251 nvidia,default-tap = <0x5>;
252 nvidia,default-trim = <0xb>;
253 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
254 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
255 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
259 sdmmc2: sdhci@3420000 {
260 compatible = "nvidia,tegra186-sdhci";
261 reg = <0x0 0x03420000 0x0 0x10000>;
262 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
264 clock-names = "sdhci";
265 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
266 reset-names = "sdhci";
267 iommus = <&smmu TEGRA186_SID_SDMMC2>;
268 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
269 pinctrl-0 = <&sdmmc2_3v3>;
270 pinctrl-1 = <&sdmmc2_1v8>;
271 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
272 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
273 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
274 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
275 nvidia,default-tap = <0x5>;
276 nvidia,default-trim = <0xb>;
280 sdmmc3: sdhci@3440000 {
281 compatible = "nvidia,tegra186-sdhci";
282 reg = <0x0 0x03440000 0x0 0x10000>;
283 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
285 clock-names = "sdhci";
286 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
287 reset-names = "sdhci";
288 iommus = <&smmu TEGRA186_SID_SDMMC3>;
289 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
290 pinctrl-0 = <&sdmmc3_3v3>;
291 pinctrl-1 = <&sdmmc3_1v8>;
292 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
293 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
294 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
295 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
296 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
297 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
298 nvidia,default-tap = <0x5>;
299 nvidia,default-trim = <0xb>;
303 sdmmc4: sdhci@3460000 {
304 compatible = "nvidia,tegra186-sdhci";
305 reg = <0x0 0x03460000 0x0 0x10000>;
306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
308 clock-names = "sdhci";
309 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
310 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
311 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
312 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
313 reset-names = "sdhci";
314 iommus = <&smmu TEGRA186_SID_SDMMC4>;
315 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
316 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
317 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
318 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
319 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
320 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
321 nvidia,default-tap = <0x9>;
322 nvidia,default-trim = <0x5>;
323 nvidia,dqs-trim = <63>;
330 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
331 reg = <0x0 0x03510000 0x0 0x10000>;
332 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&bpmp TEGRA186_CLK_HDA>,
334 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
335 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
336 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
337 resets = <&bpmp TEGRA186_RESET_HDA>,
338 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
339 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
340 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
341 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
342 iommus = <&smmu TEGRA186_SID_HDA>;
346 padctl: padctl@3520000 {
347 compatible = "nvidia,tegra186-xusb-padctl";
348 reg = <0x0 0x03520000 0x0 0x1000>,
349 <0x0 0x03540000 0x0 0x1000>;
350 reg-names = "padctl", "ao";
352 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
353 reset-names = "padctl";
359 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
382 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
448 compatible = "nvidia,tegra186-xusb";
449 reg = <0x0 0x03530000 0x0 0x8000>,
450 <0x0 0x03538000 0x0 0x1000>;
451 reg-names = "hcd", "fpci";
453 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
458 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
459 <&bpmp TEGRA186_CLK_XUSB_SS>,
460 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
461 <&bpmp TEGRA186_CLK_CLK_M>,
462 <&bpmp TEGRA186_CLK_XUSB_FS>,
463 <&bpmp TEGRA186_CLK_PLLU>,
464 <&bpmp TEGRA186_CLK_CLK_M>,
465 <&bpmp TEGRA186_CLK_PLLE>;
466 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
467 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
468 "pll_u_480m", "clk_m", "pll_e";
470 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
471 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
472 power-domain-names = "xusb_host", "xusb_ss";
473 nvidia,xusb-padctl = <&padctl>;
477 #address-cells = <1>;
482 compatible = "nvidia,tegra186-efuse";
483 reg = <0x0 0x03820000 0x0 0x10000>;
484 clocks = <&bpmp TEGRA186_CLK_FUSE>;
485 clock-names = "fuse";
488 gic: interrupt-controller@3881000 {
489 compatible = "arm,gic-400";
490 #interrupt-cells = <3>;
491 interrupt-controller;
492 reg = <0x0 0x03881000 0x0 0x1000>,
493 <0x0 0x03882000 0x0 0x2000>;
494 interrupts = <GIC_PPI 9
495 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
496 interrupt-parent = <&gic>;
500 compatible = "nvidia,tegra186-cec";
501 reg = <0x0 0x03960000 0x0 0x10000>;
502 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&bpmp TEGRA186_CLK_CEC>;
508 hsp_top0: hsp@3c00000 {
509 compatible = "nvidia,tegra186-hsp";
510 reg = <0x0 0x03c00000 0x0 0xa0000>;
511 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
512 interrupt-names = "doorbell";
517 gen2_i2c: i2c@c240000 {
518 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
519 reg = <0x0 0x0c240000 0x0 0x10000>;
520 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
523 clocks = <&bpmp TEGRA186_CLK_I2C2>;
524 clock-names = "div-clk";
525 resets = <&bpmp TEGRA186_RESET_I2C2>;
530 gen8_i2c: i2c@c250000 {
531 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
532 reg = <0x0 0x0c250000 0x0 0x10000>;
533 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
536 clocks = <&bpmp TEGRA186_CLK_I2C8>;
537 clock-names = "div-clk";
538 resets = <&bpmp TEGRA186_RESET_I2C8>;
543 uartc: serial@c280000 {
544 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
545 reg = <0x0 0x0c280000 0x0 0x40>;
547 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&bpmp TEGRA186_CLK_UARTC>;
549 clock-names = "serial";
550 resets = <&bpmp TEGRA186_RESET_UARTC>;
551 reset-names = "serial";
555 uartg: serial@c290000 {
556 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
557 reg = <0x0 0x0c290000 0x0 0x40>;
559 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&bpmp TEGRA186_CLK_UARTG>;
561 clock-names = "serial";
562 resets = <&bpmp TEGRA186_RESET_UARTG>;
563 reset-names = "serial";
568 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
569 reg = <0 0x0c2a0000 0 0x10000>;
570 interrupt-parent = <&pmc>;
571 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
577 gpio_aon: gpio@c2f0000 {
578 compatible = "nvidia,tegra186-gpio-aon";
579 reg-names = "security", "gpio";
580 reg = <0x0 0xc2f0000 0x0 0x1000>,
581 <0x0 0xc2f1000 0x0 0x1000>;
582 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
585 interrupt-controller;
586 #interrupt-cells = <2>;
590 compatible = "nvidia,tegra186-pmc";
591 reg = <0 0x0c360000 0 0x10000>,
592 <0 0x0c370000 0 0x10000>,
593 <0 0x0c380000 0 0x10000>,
594 <0 0x0c390000 0 0x10000>;
595 reg-names = "pmc", "wake", "aotag", "scratch";
597 #interrupt-cells = <2>;
598 interrupt-controller;
600 sdmmc1_3v3: sdmmc1-3v3 {
602 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
605 sdmmc1_1v8: sdmmc1-1v8 {
607 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
610 sdmmc2_3v3: sdmmc2-3v3 {
612 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
615 sdmmc2_1v8: sdmmc2-1v8 {
617 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
620 sdmmc3_3v3: sdmmc3-3v3 {
622 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
625 sdmmc3_1v8: sdmmc3-1v8 {
627 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
632 compatible = "nvidia,tegra186-ccplex-cluster";
633 reg = <0x0 0x0e000000 0x0 0x3fffff>;
635 nvidia,bpmp = <&bpmp>;
639 compatible = "nvidia,tegra186-pcie";
640 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
642 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
643 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
644 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
645 reg-names = "pads", "afi", "cs";
647 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
648 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
649 interrupt-names = "intr", "msi";
651 #interrupt-cells = <1>;
652 interrupt-map-mask = <0 0 0 0>;
653 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
655 bus-range = <0x00 0xff>;
656 #address-cells = <3>;
659 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
660 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
661 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
662 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
663 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
664 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
666 clocks = <&bpmp TEGRA186_CLK_AFI>,
667 <&bpmp TEGRA186_CLK_PCIE>,
668 <&bpmp TEGRA186_CLK_PLLE>;
669 clock-names = "afi", "pex", "pll_e";
671 resets = <&bpmp TEGRA186_RESET_AFI>,
672 <&bpmp TEGRA186_RESET_PCIE>,
673 <&bpmp TEGRA186_RESET_PCIEXCLK>;
674 reset-names = "afi", "pex", "pcie_x";
676 iommus = <&smmu TEGRA186_SID_AFI>;
677 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
678 iommu-map-mask = <0x0>;
684 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
685 reg = <0x000800 0 0 0 0>;
688 #address-cells = <3>;
692 nvidia,num-lanes = <2>;
697 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
698 reg = <0x001000 0 0 0 0>;
701 #address-cells = <3>;
705 nvidia,num-lanes = <1>;
710 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
711 reg = <0x001800 0 0 0 0>;
714 #address-cells = <3>;
718 nvidia,num-lanes = <1>;
722 smmu: iommu@12000000 {
723 compatible = "arm,mmu-500";
724 reg = <0 0x12000000 0 0x800000>;
725 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
790 stream-match-mask = <0x7f80>;
791 #global-interrupts = <1>;
796 compatible = "nvidia,tegra186-host1x", "simple-bus";
797 reg = <0x0 0x13e00000 0x0 0x10000>,
798 <0x0 0x13e10000 0x0 0x10000>;
799 reg-names = "hypervisor", "vm";
800 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
803 clock-names = "host1x";
804 resets = <&bpmp TEGRA186_RESET_HOST1X>;
805 reset-names = "host1x";
807 #address-cells = <1>;
810 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
811 iommus = <&smmu TEGRA186_SID_HOST1X>;
813 dpaux1: dpaux@15040000 {
814 compatible = "nvidia,tegra186-dpaux";
815 reg = <0x15040000 0x10000>;
816 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
818 <&bpmp TEGRA186_CLK_PLLDP>;
819 clock-names = "dpaux", "parent";
820 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
821 reset-names = "dpaux";
824 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
826 state_dpaux1_aux: pinmux-aux {
831 state_dpaux1_i2c: pinmux-i2c {
836 state_dpaux1_off: pinmux-off {
842 #address-cells = <1>;
847 display-hub@15200000 {
848 compatible = "nvidia,tegra186-display", "simple-bus";
849 reg = <0x15200000 0x00040000>;
850 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
851 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
852 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
853 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
854 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
855 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
856 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
857 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
858 "wgrp3", "wgrp4", "wgrp5";
859 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
860 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
861 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
862 clock-names = "disp", "dsc", "hub";
865 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
867 #address-cells = <1>;
870 ranges = <0x15200000 0x15200000 0x40000>;
873 compatible = "nvidia,tegra186-dc";
874 reg = <0x15200000 0x10000>;
875 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
878 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
882 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
884 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
889 compatible = "nvidia,tegra186-dc";
890 reg = <0x15210000 0x10000>;
891 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
894 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
897 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
898 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
900 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
905 compatible = "nvidia,tegra186-dc";
906 reg = <0x15220000 0x10000>;
907 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
910 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
913 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
914 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
916 nvidia,outputs = <&sor0 &sor1>;
922 compatible = "nvidia,tegra186-dsi";
923 reg = <0x15300000 0x10000>;
924 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&bpmp TEGRA186_CLK_DSI>,
926 <&bpmp TEGRA186_CLK_DSIA_LP>,
927 <&bpmp TEGRA186_CLK_PLLD>;
928 clock-names = "dsi", "lp", "parent";
929 resets = <&bpmp TEGRA186_RESET_DSI>;
933 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
937 compatible = "nvidia,tegra186-vic";
938 reg = <0x15340000 0x40000>;
939 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&bpmp TEGRA186_CLK_VIC>;
942 resets = <&bpmp TEGRA186_RESET_VIC>;
945 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
949 compatible = "nvidia,tegra186-dsi";
950 reg = <0x15400000 0x10000>;
951 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&bpmp TEGRA186_CLK_DSIB>,
953 <&bpmp TEGRA186_CLK_DSIB_LP>,
954 <&bpmp TEGRA186_CLK_PLLD>;
955 clock-names = "dsi", "lp", "parent";
956 resets = <&bpmp TEGRA186_RESET_DSIB>;
960 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
964 compatible = "nvidia,tegra186-sor";
965 reg = <0x15540000 0x10000>;
966 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&bpmp TEGRA186_CLK_SOR0>,
968 <&bpmp TEGRA186_CLK_SOR0_OUT>,
969 <&bpmp TEGRA186_CLK_PLLD2>,
970 <&bpmp TEGRA186_CLK_PLLDP>,
971 <&bpmp TEGRA186_CLK_SOR_SAFE>,
972 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
973 clock-names = "sor", "out", "parent", "dp", "safe",
975 resets = <&bpmp TEGRA186_RESET_SOR0>;
977 pinctrl-0 = <&state_dpaux_aux>;
978 pinctrl-1 = <&state_dpaux_i2c>;
979 pinctrl-2 = <&state_dpaux_off>;
980 pinctrl-names = "aux", "i2c", "off";
983 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
984 nvidia,interface = <0>;
988 compatible = "nvidia,tegra186-sor1";
989 reg = <0x15580000 0x10000>;
990 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&bpmp TEGRA186_CLK_SOR1>,
992 <&bpmp TEGRA186_CLK_SOR1_OUT>,
993 <&bpmp TEGRA186_CLK_PLLD3>,
994 <&bpmp TEGRA186_CLK_PLLDP>,
995 <&bpmp TEGRA186_CLK_SOR_SAFE>,
996 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
997 clock-names = "sor", "out", "parent", "dp", "safe",
999 resets = <&bpmp TEGRA186_RESET_SOR1>;
1000 reset-names = "sor";
1001 pinctrl-0 = <&state_dpaux1_aux>;
1002 pinctrl-1 = <&state_dpaux1_i2c>;
1003 pinctrl-2 = <&state_dpaux1_off>;
1004 pinctrl-names = "aux", "i2c", "off";
1005 status = "disabled";
1007 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1008 nvidia,interface = <1>;
1011 dpaux: dpaux@155c0000 {
1012 compatible = "nvidia,tegra186-dpaux";
1013 reg = <0x155c0000 0x10000>;
1014 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1016 <&bpmp TEGRA186_CLK_PLLDP>;
1017 clock-names = "dpaux", "parent";
1018 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1019 reset-names = "dpaux";
1020 status = "disabled";
1022 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1024 state_dpaux_aux: pinmux-aux {
1025 groups = "dpaux-io";
1029 state_dpaux_i2c: pinmux-i2c {
1030 groups = "dpaux-io";
1034 state_dpaux_off: pinmux-off {
1035 groups = "dpaux-io";
1040 #address-cells = <1>;
1046 compatible = "nvidia,tegra186-dsi-padctl";
1047 reg = <0x15880000 0x10000>;
1048 resets = <&bpmp TEGRA186_RESET_DSI>;
1049 reset-names = "dsi";
1050 status = "disabled";
1053 dsic: dsi@15900000 {
1054 compatible = "nvidia,tegra186-dsi";
1055 reg = <0x15900000 0x10000>;
1056 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1058 <&bpmp TEGRA186_CLK_DSIC_LP>,
1059 <&bpmp TEGRA186_CLK_PLLD>;
1060 clock-names = "dsi", "lp", "parent";
1061 resets = <&bpmp TEGRA186_RESET_DSIC>;
1062 reset-names = "dsi";
1063 status = "disabled";
1065 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1068 dsid: dsi@15940000 {
1069 compatible = "nvidia,tegra186-dsi";
1070 reg = <0x15940000 0x10000>;
1071 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&bpmp TEGRA186_CLK_DSID>,
1073 <&bpmp TEGRA186_CLK_DSID_LP>,
1074 <&bpmp TEGRA186_CLK_PLLD>;
1075 clock-names = "dsi", "lp", "parent";
1076 resets = <&bpmp TEGRA186_RESET_DSID>;
1077 reset-names = "dsi";
1078 status = "disabled";
1080 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1085 compatible = "nvidia,gp10b";
1086 reg = <0x0 0x17000000 0x0 0x1000000>,
1087 <0x0 0x18000000 0x0 0x1000000>;
1088 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
1089 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "stall", "nonstall";
1092 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1093 <&bpmp TEGRA186_CLK_GPU>;
1094 clock-names = "gpu", "pwr";
1095 resets = <&bpmp TEGRA186_RESET_GPU>;
1096 reset-names = "gpu";
1097 status = "disabled";
1099 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1103 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1104 reg = <0x0 0x30000000 0x0 0x50000>;
1105 #address-cells = <2>;
1107 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
1109 cpu_bpmp_tx: shmem@4e000 {
1110 compatible = "nvidia,tegra186-bpmp-shmem";
1111 reg = <0x0 0x4e000 0x0 0x1000>;
1112 label = "cpu-bpmp-tx";
1116 cpu_bpmp_rx: shmem@4f000 {
1117 compatible = "nvidia,tegra186-bpmp-shmem";
1118 reg = <0x0 0x4f000 0x0 0x1000>;
1119 label = "cpu-bpmp-rx";
1125 #address-cells = <1>;
1129 compatible = "nvidia,tegra186-denver";
1130 device_type = "cpu";
1135 compatible = "nvidia,tegra186-denver";
1136 device_type = "cpu";
1141 compatible = "arm,cortex-a57";
1142 device_type = "cpu";
1147 compatible = "arm,cortex-a57";
1148 device_type = "cpu";
1153 compatible = "arm,cortex-a57";
1154 device_type = "cpu";
1159 compatible = "arm,cortex-a57";
1160 device_type = "cpu";
1166 compatible = "nvidia,tegra186-bpmp";
1167 iommus = <&smmu TEGRA186_SID_BPMP>;
1168 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1169 TEGRA_HSP_DB_MASTER_BPMP>;
1170 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1173 #power-domain-cells = <1>;
1176 compatible = "nvidia,tegra186-bpmp-i2c";
1177 nvidia,bpmp-bus-id = <5>;
1178 #address-cells = <1>;
1180 status = "disabled";
1183 bpmp_thermal: thermal {
1184 compatible = "nvidia,tegra186-bpmp-thermal";
1185 #thermal-sensor-cells = <1>;
1191 polling-delay = <0>;
1192 polling-delay-passive = <1000>;
1195 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1199 temperature = <101000>;
1210 polling-delay = <0>;
1211 polling-delay-passive = <1000>;
1214 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1218 temperature = <101000>;
1229 polling-delay = <0>;
1230 polling-delay-passive = <1000>;
1233 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1237 temperature = <101000>;
1248 polling-delay = <0>;
1249 polling-delay-passive = <1000>;
1252 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1256 temperature = <101000>;
1267 polling-delay = <0>;
1268 polling-delay-passive = <1000>;
1271 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1275 temperature = <101000>;
1287 compatible = "arm,armv8-timer";
1288 interrupts = <GIC_PPI 13
1289 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1291 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1293 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1295 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1296 interrupt-parent = <&gic>;