arch/arm64/boot/dts/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/memory/tegra186-mc.h>
   7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   8 #include <dt-bindings/power/tegra186-powergate.h>
   9 #include <dt-bindings/reset/tegra186-reset.h>
  10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
  11
  12 / {
  13         compatible = "nvidia,tegra186";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         misc@100000 {
  19                 compatible = "nvidia,tegra186-misc";
  20                 reg = <0x0 0x00100000 0x0 0xf000>,
  21                       <0x0 0x0010f000 0x0 0x1000>;
  22         };
  23
  24         gpio: gpio@2200000 {
  25                 compatible = "nvidia,tegra186-gpio";
  26                 reg-names = "security", "gpio";
  27                 reg = <0x0 0x2200000 0x0 0x10000>,
  28                       <0x0 0x2210000 0x0 0x10000>;
  29                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  34                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  35                 #interrupt-cells = <2>;
  36                 interrupt-controller;
  37                 #gpio-cells = <2>;
  38                 gpio-controller;
  39         };
  40
  41         ethernet@2490000 {
  42                 compatible = "nvidia,tegra186-eqos",
  43                              "snps,dwc-qos-ethernet-4.10";
  44                 reg = <0x0 0x02490000 0x0 0x10000>;
  45                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  46                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  47                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  48                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  49                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  50                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  51                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  52                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  53                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  54                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  55                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  56                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  57                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  58                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  59                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  60                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  61                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  62                 reset-names = "eqos";
  63                 status = "disabled";
  64
  65                 snps,write-requests = <1>;
  66                 snps,read-requests = <3>;
  67                 snps,burst-map = <0x7>;
  68                 snps,txpbl = <32>;
  69                 snps,rxpbl = <8>;
  70         };
  71
  72         memory-controller@2c00000 {
  73                 compatible = "nvidia,tegra186-mc";
  74                 reg = <0x0 0x02c00000 0x0 0xb0000>;
  75                 status = "disabled";
  76         };
  77
  78         uarta: serial@3100000 {
  79                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  80                 reg = <0x0 0x03100000 0x0 0x40>;
  81                 reg-shift = <2>;
  82                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  83                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
  84                 clock-names = "serial";
  85                 resets = <&bpmp TEGRA186_RESET_UARTA>;
  86                 reset-names = "serial";
  87                 status = "disabled";
  88         };
  89
  90         uartb: serial@3110000 {
  91                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  92                 reg = <0x0 0x03110000 0x0 0x40>;
  93                 reg-shift = <2>;
  94                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  95                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
  96                 clock-names = "serial";
  97                 resets = <&bpmp TEGRA186_RESET_UARTB>;
  98                 reset-names = "serial";
  99                 status = "disabled";
 100         };
 101
 102         uartd: serial@3130000 {
 103                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 104                 reg = <0x0 0x03130000 0x0 0x40>;
 105                 reg-shift = <2>;
 106                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 107                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
 108                 clock-names = "serial";
 109                 resets = <&bpmp TEGRA186_RESET_UARTD>;
 110                 reset-names = "serial";
 111                 status = "disabled";
 112         };
 113
 114         uarte: serial@3140000 {
 115                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 116                 reg = <0x0 0x03140000 0x0 0x40>;
 117                 reg-shift = <2>;
 118                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 119                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 120                 clock-names = "serial";
 121                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 122                 reset-names = "serial";
 123                 status = "disabled";
 124         };
 125
 126         uartf: serial@3150000 {
 127                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 128                 reg = <0x0 0x03150000 0x0 0x40>;
 129                 reg-shift = <2>;
 130                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 131                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 132                 clock-names = "serial";
 133                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 134                 reset-names = "serial";
 135                 status = "disabled";
 136         };
 137
 138         gen1_i2c: i2c@3160000 {
 139                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 140                 reg = <0x0 0x03160000 0x0 0x10000>;
 141                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 145                 clock-names = "div-clk";
 146                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 147                 reset-names = "i2c";
 148                 status = "disabled";
 149         };
 150
 151         cam_i2c: i2c@3180000 {
 152                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 153                 reg = <0x0 0x03180000 0x0 0x10000>;
 154                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 158                 clock-names = "div-clk";
 159                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 160                 reset-names = "i2c";
 161                 status = "disabled";
 162         };
 163
 164         /* shares pads with dpaux1 */
 165         dp_aux_ch1_i2c: i2c@3190000 {
 166                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 167                 reg = <0x0 0x03190000 0x0 0x10000>;
 168                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 172                 clock-names = "div-clk";
 173                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 174                 reset-names = "i2c";
 175                 status = "disabled";
 176         };
 177
 178         /* controlled by BPMP, should not be enabled */
 179         pwr_i2c: i2c@31a0000 {
 180                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 181                 reg = <0x0 0x031a0000 0x0 0x10000>;
 182                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 186                 clock-names = "div-clk";
 187                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 188                 reset-names = "i2c";
 189                 status = "disabled";
 190         };
 191
 192         /* shares pads with dpaux0 */
 193         dp_aux_ch0_i2c: i2c@31b0000 {
 194                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 195                 reg = <0x0 0x031b0000 0x0 0x10000>;
 196                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 200                 clock-names = "div-clk";
 201                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 202                 reset-names = "i2c";
 203                 status = "disabled";
 204         };
 205
 206         gen7_i2c: i2c@31c0000 {
 207                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 208                 reg = <0x0 0x031c0000 0x0 0x10000>;
 209                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 213                 clock-names = "div-clk";
 214                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 215                 reset-names = "i2c";
 216                 status = "disabled";
 217         };
 218
 219         gen9_i2c: i2c@31e0000 {
 220                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 221                 reg = <0x0 0x031e0000 0x0 0x10000>;
 222                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 226                 clock-names = "div-clk";
 227                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 228                 reset-names = "i2c";
 229                 status = "disabled";
 230         };
 231
 232         sdmmc1: sdhci@3400000 {
 233                 compatible = "nvidia,tegra186-sdhci";
 234                 reg = <0x0 0x03400000 0x0 0x10000>;
 235                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 237                 clock-names = "sdhci";
 238                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 239                 reset-names = "sdhci";
 240                 iommus = <&smmu TEGRA186_SID_SDMMC1>;
 241                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 242                 pinctrl-0 = <&sdmmc1_3v3>;
 243                 pinctrl-1 = <&sdmmc1_1v8>;
 244                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 245                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 246                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 247                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 248                 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
 249                 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
 250                 nvidia,default-tap = <0x5>;
 251                 nvidia,default-trim = <0xb>;
 252                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
 253                                   <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 254                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 255                 status = "disabled";
 256         };
 257
 258         sdmmc2: sdhci@3420000 {
 259                 compatible = "nvidia,tegra186-sdhci";
 260                 reg = <0x0 0x03420000 0x0 0x10000>;
 261                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 262                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 263                 clock-names = "sdhci";
 264                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 265                 reset-names = "sdhci";
 266                 iommus = <&smmu TEGRA186_SID_SDMMC2>;
 267                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 268                 pinctrl-0 = <&sdmmc2_3v3>;
 269                 pinctrl-1 = <&sdmmc2_1v8>;
 270                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 271                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 272                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 273                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 274                 nvidia,default-tap = <0x5>;
 275                 nvidia,default-trim = <0xb>;
 276                 status = "disabled";
 277         };
 278
 279         sdmmc3: sdhci@3440000 {
 280                 compatible = "nvidia,tegra186-sdhci";
 281                 reg = <0x0 0x03440000 0x0 0x10000>;
 282                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 284                 clock-names = "sdhci";
 285                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 286                 reset-names = "sdhci";
 287                 iommus = <&smmu TEGRA186_SID_SDMMC3>;
 288                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 289                 pinctrl-0 = <&sdmmc3_3v3>;
 290                 pinctrl-1 = <&sdmmc3_1v8>;
 291                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 292                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 293                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 294                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 295                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 296                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 297                 nvidia,default-tap = <0x5>;
 298                 nvidia,default-trim = <0xb>;
 299                 status = "disabled";
 300         };
 301
 302         sdmmc4: sdhci@3460000 {
 303                 compatible = "nvidia,tegra186-sdhci";
 304                 reg = <0x0 0x03460000 0x0 0x10000>;
 305                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 307                 clock-names = "sdhci";
 308                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
 309                                   <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 310                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 311                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 312                 reset-names = "sdhci";
 313                 iommus = <&smmu TEGRA186_SID_SDMMC4>;
 314                 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
 315                 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
 316                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 317                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
 318                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 319                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
 320                 nvidia,default-tap = <0x9>;
 321                 nvidia,default-trim = <0x5>;
 322                 nvidia,dqs-trim = <63>;
 323                 mmc-hs400-1_8v;
 324                 supports-cqe;
 325                 status = "disabled";
 326         };
 327
 328         hda@3510000 {
 329                 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
 330                 reg = <0x0 0x03510000 0x0 0x10000>;
 331                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&bpmp TEGRA186_CLK_HDA>,
 333                          <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
 334                          <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
 335                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 336                 resets = <&bpmp TEGRA186_RESET_HDA>,
 337                          <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
 338                          <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
 339                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 340                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 341                 status = "disabled";
 342         };
 343
 344         padctl: padctl@3520000 {
 345                 compatible = "nvidia,tegra186-xusb-padctl";
 346                 reg = <0x0 0x03520000 0x0 0x1000>,
 347                       <0x0 0x03540000 0x0 0x1000>;
 348                 reg-names = "padctl", "ao";
 349
 350                 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
 351                 reset-names = "padctl";
 352
 353                 status = "disabled";
 354
 355                 pads {
 356                         usb2 {
 357                                 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
 358                                 clock-names = "trk";
 359                                 status = "disabled";
 360
 361                                 lanes {
 362                                         usb2-0 {
 363                                                 status = "disabled";
 364                                                 #phy-cells = <0>;
 365                                         };
 366
 367                                         usb2-1 {
 368                                                 status = "disabled";
 369                                                 #phy-cells = <0>;
 370                                         };
 371
 372                                         usb2-2 {
 373                                                 status = "disabled";
 374                                                 #phy-cells = <0>;
 375                                         };
 376                                 };
 377                         };
 378
 379                         hsic {
 380                                 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
 381                                 clock-names = "trk";
 382                                 status = "disabled";
 383
 384                                 lanes {
 385                                         hsic-0 {
 386                                                 status = "disabled";
 387                                                 #phy-cells = <0>;
 388                                         };
 389                                 };
 390                         };
 391
 392                         usb3 {
 393                                 status = "disabled";
 394
 395                                 lanes {
 396                                         usb3-0 {
 397                                                 status = "disabled";
 398                                                 #phy-cells = <0>;
 399                                         };
 400
 401                                         usb3-1 {
 402                                                 status = "disabled";
 403                                                 #phy-cells = <0>;
 404                                         };
 405
 406                                         usb3-2 {
 407                                                 status = "disabled";
 408                                                 #phy-cells = <0>;
 409                                         };
 410                                 };
 411                         };
 412                 };
 413
 414                 ports {
 415                         usb2-0 {
 416                                 status = "disabled";
 417                         };
 418
 419                         usb2-1 {
 420                                 status = "disabled";
 421                         };
 422
 423                         usb2-2 {
 424                                 status = "disabled";
 425                         };
 426
 427                         hsic-0 {
 428                                 status = "disabled";
 429                         };
 430
 431                         usb3-0 {
 432                                 status = "disabled";
 433                         };
 434
 435                         usb3-1 {
 436                                 status = "disabled";
 437                         };
 438
 439                         usb3-2 {
 440                                 status = "disabled";
 441                         };
 442                 };
 443         };
 444
 445         usb@3530000 {
 446                 compatible = "nvidia,tegra186-xusb";
 447                 reg = <0x0 0x03530000 0x0 0x8000>,
 448                       <0x0 0x03538000 0x0 0x1000>;
 449                 reg-names = "hcd", "fpci";
 450
 451                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 452                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 454
 455                 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
 456                          <&bpmp TEGRA186_CLK_XUSB_FALCON>,
 457                          <&bpmp TEGRA186_CLK_XUSB_SS>,
 458                          <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
 459                          <&bpmp TEGRA186_CLK_CLK_M>,
 460                          <&bpmp TEGRA186_CLK_XUSB_FS>,
 461                          <&bpmp TEGRA186_CLK_PLLU>,
 462                          <&bpmp TEGRA186_CLK_CLK_M>,
 463                          <&bpmp TEGRA186_CLK_PLLE>;
 464                 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
 465                               "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
 466                               "pll_u_480m", "clk_m", "pll_e";
 467
 468                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
 469                                 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
 470                 power-domain-names = "xusb_host", "xusb_ss";
 471                 nvidia,xusb-padctl = <&padctl>;
 472
 473                 status = "disabled";
 474
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477         };
 478
 479         fuse@3820000 {
 480                 compatible = "nvidia,tegra186-efuse";
 481                 reg = <0x0 0x03820000 0x0 0x10000>;
 482                 clocks = <&bpmp TEGRA186_CLK_FUSE>;
 483                 clock-names = "fuse";
 484         };
 485
 486         gic: interrupt-controller@3881000 {
 487                 compatible = "arm,gic-400";
 488                 #interrupt-cells = <3>;
 489                 interrupt-controller;
 490                 reg = <0x0 0x03881000 0x0 0x1000>,
 491                       <0x0 0x03882000 0x0 0x2000>;
 492                 interrupts = <GIC_PPI 9
 493                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 494                 interrupt-parent = <&gic>;
 495         };
 496
 497         cec@3960000 {
 498                 compatible = "nvidia,tegra186-cec";
 499                 reg = <0x0 0x03960000 0x0 0x10000>;
 500                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 501                 clocks = <&bpmp TEGRA186_CLK_CEC>;
 502                 clock-names = "cec";
 503                 status = "disabled";
 504         };
 505
 506         hsp_top0: hsp@3c00000 {
 507                 compatible = "nvidia,tegra186-hsp";
 508                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 509                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 510                 interrupt-names = "doorbell";
 511                 #mbox-cells = <2>;
 512                 status = "disabled";
 513         };
 514
 515         gen2_i2c: i2c@c240000 {
 516                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 517                 reg = <0x0 0x0c240000 0x0 0x10000>;
 518                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 522                 clock-names = "div-clk";
 523                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 524                 reset-names = "i2c";
 525                 status = "disabled";
 526         };
 527
 528         gen8_i2c: i2c@c250000 {
 529                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 530                 reg = <0x0 0x0c250000 0x0 0x10000>;
 531                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 535                 clock-names = "div-clk";
 536                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 537                 reset-names = "i2c";
 538                 status = "disabled";
 539         };
 540
 541         uartc: serial@c280000 {
 542                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 543                 reg = <0x0 0x0c280000 0x0 0x40>;
 544                 reg-shift = <2>;
 545                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 546                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 547                 clock-names = "serial";
 548                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 549                 reset-names = "serial";
 550                 status = "disabled";
 551         };
 552
 553         uartg: serial@c290000 {
 554                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 555                 reg = <0x0 0x0c290000 0x0 0x40>;
 556                 reg-shift = <2>;
 557                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 559                 clock-names = "serial";
 560                 resets = <&bpmp TEGRA186_RESET_UARTG>;
 561                 reset-names = "serial";
 562                 status = "disabled";
 563         };
 564
 565         rtc: rtc@c2a0000 {
 566                 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
 567                 reg = <0 0x0c2a0000 0 0x10000>;
 568                 interrupt-parent = <&pmc>;
 569                 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 570                 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
 571                 clock-names = "rtc";
 572                 status = "disabled";
 573         };
 574
 575         gpio_aon: gpio@c2f0000 {
 576                 compatible = "nvidia,tegra186-gpio-aon";
 577                 reg-names = "security", "gpio";
 578                 reg = <0x0 0xc2f0000 0x0 0x1000>,
 579                       <0x0 0xc2f1000 0x0 0x1000>;
 580                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 581                 gpio-controller;
 582                 #gpio-cells = <2>;
 583                 interrupt-controller;
 584                 #interrupt-cells = <2>;
 585         };
 586
 587         pmc: pmc@c360000 {
 588                 compatible = "nvidia,tegra186-pmc";
 589                 reg = <0 0x0c360000 0 0x10000>,
 590                       <0 0x0c370000 0 0x10000>,
 591                       <0 0x0c380000 0 0x10000>,
 592                       <0 0x0c390000 0 0x10000>;
 593                 reg-names = "pmc", "wake", "aotag", "scratch";
 594
 595                 #interrupt-cells = <2>;
 596                 interrupt-controller;
 597
 598                 sdmmc1_3v3: sdmmc1-3v3 {
 599                         pins = "sdmmc1-hv";
 600                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 601                 };
 602
 603                 sdmmc1_1v8: sdmmc1-1v8 {
 604                         pins = "sdmmc1-hv";
 605                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 606                 };
 607
 608                 sdmmc2_3v3: sdmmc2-3v3 {
 609                         pins = "sdmmc2-hv";
 610                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 611                 };
 612
 613                 sdmmc2_1v8: sdmmc2-1v8 {
 614                         pins = "sdmmc2-hv";
 615                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 616                 };
 617
 618                 sdmmc3_3v3: sdmmc3-3v3 {
 619                         pins = "sdmmc3-hv";
 620                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 621                 };
 622
 623                 sdmmc3_1v8: sdmmc3-1v8 {
 624                         pins = "sdmmc3-hv";
 625                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 626                 };
 627         };
 628
 629         ccplex@e000000 {
 630                 compatible = "nvidia,tegra186-ccplex-cluster";
 631                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
 632
 633                 nvidia,bpmp = <&bpmp>;
 634         };
 635
 636         pcie@10003000 {
 637                 compatible = "nvidia,tegra186-pcie";
 638                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
 639                 device_type = "pci";
 640                 reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
 641                        0x0 0x10003800 0x0 0x00000800   /* AFI registers */
 642                        0x0 0x40000000 0x0 0x10000000>; /* configuration space */
 643                 reg-names = "pads", "afi", "cs";
 644
 645                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 646                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 647                 interrupt-names = "intr", "msi";
 648
 649                 #interrupt-cells = <1>;
 650                 interrupt-map-mask = <0 0 0 0>;
 651                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 652
 653                 bus-range = <0x00 0xff>;
 654                 #address-cells = <3>;
 655                 #size-cells = <2>;
 656
 657                 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
 658                           0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
 659                           0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
 660                           0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
 661                           0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
 662                           0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
 663
 664                 clocks = <&bpmp TEGRA186_CLK_AFI>,
 665                          <&bpmp TEGRA186_CLK_PCIE>,
 666                          <&bpmp TEGRA186_CLK_PLLE>;
 667                 clock-names = "afi", "pex", "pll_e";
 668
 669                 resets = <&bpmp TEGRA186_RESET_AFI>,
 670                          <&bpmp TEGRA186_RESET_PCIE>,
 671                          <&bpmp TEGRA186_RESET_PCIEXCLK>;
 672                 reset-names = "afi", "pex", "pcie_x";
 673
 674                 status = "disabled";
 675
 676                 pci@1,0 {
 677                         device_type = "pci";
 678                         assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
 679                         reg = <0x000800 0 0 0 0>;
 680                         status = "disabled";
 681
 682                         #address-cells = <3>;
 683                         #size-cells = <2>;
 684                         ranges;
 685
 686                         nvidia,num-lanes = <2>;
 687                 };
 688
 689                 pci@2,0 {
 690                         device_type = "pci";
 691                         assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
 692                         reg = <0x001000 0 0 0 0>;
 693                         status = "disabled";
 694
 695                         #address-cells = <3>;
 696                         #size-cells = <2>;
 697                         ranges;
 698
 699                         nvidia,num-lanes = <1>;
 700                 };
 701
 702                 pci@3,0 {
 703                         device_type = "pci";
 704                         assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
 705                         reg = <0x001800 0 0 0 0>;
 706                         status = "disabled";
 707
 708                         #address-cells = <3>;
 709                         #size-cells = <2>;
 710                         ranges;
 711
 712                         nvidia,num-lanes = <1>;
 713                 };
 714         };
 715
 716         smmu: iommu@12000000 {
 717                 compatible = "arm,mmu-500";
 718                 reg = <0 0x12000000 0 0x800000>;
 719                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 720                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 721                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 722                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 723                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 724                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 725                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 726                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 727                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 728                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 729                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 730                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 731                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 732                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 733                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 734                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 735                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 736                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 737                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 738                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 739                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 740                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 741                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 742                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 743                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 744                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 745                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 746                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 747                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 748                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 749                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 750                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 751                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 752                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 753                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 754                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 755                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 756                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 757                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 758                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 759                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 760                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 761                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 762                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 763                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 764                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 765                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 766                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 767                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 768                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 769                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 770                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 771                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 772                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 773                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 774                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 775                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 776                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 777                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 778                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 779                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 780                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 781                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 782                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 783                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 784                 stream-match-mask = <0x7f80>;
 785                 #global-interrupts = <1>;
 786                 #iommu-cells = <1>;
 787         };
 788
 789         host1x@13e00000 {
 790                 compatible = "nvidia,tegra186-host1x", "simple-bus";
 791                 reg = <0x0 0x13e00000 0x0 0x10000>,
 792                       <0x0 0x13e10000 0x0 0x10000>;
 793                 reg-names = "hypervisor", "vm";
 794                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 795                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
 797                 clock-names = "host1x";
 798                 resets = <&bpmp TEGRA186_RESET_HOST1X>;
 799                 reset-names = "host1x";
 800
 801                 #address-cells = <1>;
 802                 #size-cells = <1>;
 803
 804                 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
 805                 iommus = <&smmu TEGRA186_SID_HOST1X>;
 806
 807                 dpaux1: dpaux@15040000 {
 808                         compatible = "nvidia,tegra186-dpaux";
 809                         reg = <0x15040000 0x10000>;
 810                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 811                         clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
 812                                  <&bpmp TEGRA186_CLK_PLLDP>;
 813                         clock-names = "dpaux", "parent";
 814                         resets = <&bpmp TEGRA186_RESET_DPAUX1>;
 815                         reset-names = "dpaux";
 816                         status = "disabled";
 817
 818                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 819
 820                         state_dpaux1_aux: pinmux-aux {
 821                                 groups = "dpaux-io";
 822                                 function = "aux";
 823                         };
 824
 825                         state_dpaux1_i2c: pinmux-i2c {
 826                                 groups = "dpaux-io";
 827                                 function = "i2c";
 828                         };
 829
 830                         state_dpaux1_off: pinmux-off {
 831                                 groups = "dpaux-io";
 832                                 function = "off";
 833                         };
 834
 835                         i2c-bus {
 836                                 #address-cells = <1>;
 837                                 #size-cells = <0>;
 838                         };
 839                 };
 840
 841                 display-hub@15200000 {
 842                         compatible = "nvidia,tegra186-display", "simple-bus";
 843                         reg = <0x15200000 0x00040000>;
 844                         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
 845                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
 846                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
 847                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
 848                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
 849                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
 850                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
 851                         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 852                                       "wgrp3", "wgrp4", "wgrp5";
 853                         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
 854                                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
 855                                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
 856                         clock-names = "disp", "dsc", "hub";
 857                         status = "disabled";
 858
 859                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 860
 861                         #address-cells = <1>;
 862                         #size-cells = <1>;
 863
 864                         ranges = <0x15200000 0x15200000 0x40000>;
 865
 866                         display@15200000 {
 867                                 compatible = "nvidia,tegra186-dc";
 868                                 reg = <0x15200000 0x10000>;
 869                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 870                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
 871                                 clock-names = "dc";
 872                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
 873                                 reset-names = "dc";
 874
 875                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 876                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 877
 878                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 879                                 nvidia,head = <0>;
 880                         };
 881
 882                         display@15210000 {
 883                                 compatible = "nvidia,tegra186-dc";
 884                                 reg = <0x15210000 0x10000>;
 885                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
 887                                 clock-names = "dc";
 888                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
 889                                 reset-names = "dc";
 890
 891                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
 892                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 893
 894                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 895                                 nvidia,head = <1>;
 896                         };
 897
 898                         display@15220000 {
 899                                 compatible = "nvidia,tegra186-dc";
 900                                 reg = <0x15220000 0x10000>;
 901                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 902                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
 903                                 clock-names = "dc";
 904                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
 905                                 reset-names = "dc";
 906
 907                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
 908                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 909
 910                                 nvidia,outputs = <&sor0 &sor1>;
 911                                 nvidia,head = <2>;
 912                         };
 913                 };
 914
 915                 dsia: dsi@15300000 {
 916                         compatible = "nvidia,tegra186-dsi";
 917                         reg = <0x15300000 0x10000>;
 918                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 919                         clocks = <&bpmp TEGRA186_CLK_DSI>,
 920                                  <&bpmp TEGRA186_CLK_DSIA_LP>,
 921                                  <&bpmp TEGRA186_CLK_PLLD>;
 922                         clock-names = "dsi", "lp", "parent";
 923                         resets = <&bpmp TEGRA186_RESET_DSI>;
 924                         reset-names = "dsi";
 925                         status = "disabled";
 926
 927                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 928                 };
 929
 930                 vic@15340000 {
 931                         compatible = "nvidia,tegra186-vic";
 932                         reg = <0x15340000 0x40000>;
 933                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 934                         clocks = <&bpmp TEGRA186_CLK_VIC>;
 935                         clock-names = "vic";
 936                         resets = <&bpmp TEGRA186_RESET_VIC>;
 937                         reset-names = "vic";
 938
 939                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
 940                 };
 941
 942                 dsib: dsi@15400000 {
 943                         compatible = "nvidia,tegra186-dsi";
 944                         reg = <0x15400000 0x10000>;
 945                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 946                         clocks = <&bpmp TEGRA186_CLK_DSIB>,
 947                                  <&bpmp TEGRA186_CLK_DSIB_LP>,
 948                                  <&bpmp TEGRA186_CLK_PLLD>;
 949                         clock-names = "dsi", "lp", "parent";
 950                         resets = <&bpmp TEGRA186_RESET_DSIB>;
 951                         reset-names = "dsi";
 952                         status = "disabled";
 953
 954                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 955                 };
 956
 957                 sor0: sor@15540000 {
 958                         compatible = "nvidia,tegra186-sor";
 959                         reg = <0x15540000 0x10000>;
 960                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&bpmp TEGRA186_CLK_SOR0>,
 962                                  <&bpmp TEGRA186_CLK_SOR0_OUT>,
 963                                  <&bpmp TEGRA186_CLK_PLLD2>,
 964                                  <&bpmp TEGRA186_CLK_PLLDP>,
 965                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
 966                                  <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
 967                         clock-names = "sor", "out", "parent", "dp", "safe",
 968                                       "pad";
 969                         resets = <&bpmp TEGRA186_RESET_SOR0>;
 970                         reset-names = "sor";
 971                         pinctrl-0 = <&state_dpaux_aux>;
 972                         pinctrl-1 = <&state_dpaux_i2c>;
 973                         pinctrl-2 = <&state_dpaux_off>;
 974                         pinctrl-names = "aux", "i2c", "off";
 975                         status = "disabled";
 976
 977                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 978                         nvidia,interface = <0>;
 979                 };
 980
 981                 sor1: sor@15580000 {
 982                         compatible = "nvidia,tegra186-sor1";
 983                         reg = <0x15580000 0x10000>;
 984                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 985                         clocks = <&bpmp TEGRA186_CLK_SOR1>,
 986                                  <&bpmp TEGRA186_CLK_SOR1_OUT>,
 987                                  <&bpmp TEGRA186_CLK_PLLD3>,
 988                                  <&bpmp TEGRA186_CLK_PLLDP>,
 989                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
 990                                  <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
 991                         clock-names = "sor", "out", "parent", "dp", "safe",
 992                                       "pad";
 993                         resets = <&bpmp TEGRA186_RESET_SOR1>;
 994                         reset-names = "sor";
 995                         pinctrl-0 = <&state_dpaux1_aux>;
 996                         pinctrl-1 = <&state_dpaux1_i2c>;
 997                         pinctrl-2 = <&state_dpaux1_off>;
 998                         pinctrl-names = "aux", "i2c", "off";
 999                         status = "disabled";
1000
1001                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1002                         nvidia,interface = <1>;
1003                 };
1004
1005                 dpaux: dpaux@155c0000 {
1006                         compatible = "nvidia,tegra186-dpaux";
1007                         reg = <0x155c0000 0x10000>;
1008                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1010                                  <&bpmp TEGRA186_CLK_PLLDP>;
1011                         clock-names = "dpaux", "parent";
1012                         resets = <&bpmp TEGRA186_RESET_DPAUX>;
1013                         reset-names = "dpaux";
1014                         status = "disabled";
1015
1016                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1017
1018                         state_dpaux_aux: pinmux-aux {
1019                                 groups = "dpaux-io";
1020                                 function = "aux";
1021                         };
1022
1023                         state_dpaux_i2c: pinmux-i2c {
1024                                 groups = "dpaux-io";
1025                                 function = "i2c";
1026                         };
1027
1028                         state_dpaux_off: pinmux-off {
1029                                 groups = "dpaux-io";
1030                                 function = "off";
1031                         };
1032
1033                         i2c-bus {
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036                         };
1037                 };
1038
1039                 padctl@15880000 {
1040                         compatible = "nvidia,tegra186-dsi-padctl";
1041                         reg = <0x15880000 0x10000>;
1042                         resets = <&bpmp TEGRA186_RESET_DSI>;
1043                         reset-names = "dsi";
1044                         status = "disabled";
1045                 };
1046
1047                 dsic: dsi@15900000 {
1048                         compatible = "nvidia,tegra186-dsi";
1049                         reg = <0x15900000 0x10000>;
1050                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1051                         clocks = <&bpmp TEGRA186_CLK_DSIC>,
1052                                  <&bpmp TEGRA186_CLK_DSIC_LP>,
1053                                  <&bpmp TEGRA186_CLK_PLLD>;
1054                         clock-names = "dsi", "lp", "parent";
1055                         resets = <&bpmp TEGRA186_RESET_DSIC>;
1056                         reset-names = "dsi";
1057                         status = "disabled";
1058
1059                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1060                 };
1061
1062                 dsid: dsi@15940000 {
1063                         compatible = "nvidia,tegra186-dsi";
1064                         reg = <0x15940000 0x10000>;
1065                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1066                         clocks = <&bpmp TEGRA186_CLK_DSID>,
1067                                  <&bpmp TEGRA186_CLK_DSID_LP>,
1068                                  <&bpmp TEGRA186_CLK_PLLD>;
1069                         clock-names = "dsi", "lp", "parent";
1070                         resets = <&bpmp TEGRA186_RESET_DSID>;
1071                         reset-names = "dsi";
1072                         status = "disabled";
1073
1074                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1075                 };
1076         };
1077
1078         gpu@17000000 {
1079                 compatible = "nvidia,gp10b";
1080                 reg = <0x0 0x17000000 0x0 0x1000000>,
1081                       <0x0 0x18000000 0x0 0x1000000>;
1082                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
1083                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1084                 interrupt-names = "stall", "nonstall";
1085
1086                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1087                          <&bpmp TEGRA186_CLK_GPU>;
1088                 clock-names = "gpu", "pwr";
1089                 resets = <&bpmp TEGRA186_RESET_GPU>;
1090                 reset-names = "gpu";
1091                 status = "disabled";
1092
1093                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1094         };
1095
1096         sysram@30000000 {
1097                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1098                 reg = <0x0 0x30000000 0x0 0x50000>;
1099                 #address-cells = <2>;
1100                 #size-cells = <2>;
1101                 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
1102
1103                 cpu_bpmp_tx: shmem@4e000 {
1104                         compatible = "nvidia,tegra186-bpmp-shmem";
1105                         reg = <0x0 0x4e000 0x0 0x1000>;
1106                         label = "cpu-bpmp-tx";
1107                         pool;
1108                 };
1109
1110                 cpu_bpmp_rx: shmem@4f000 {
1111                         compatible = "nvidia,tegra186-bpmp-shmem";
1112                         reg = <0x0 0x4f000 0x0 0x1000>;
1113                         label = "cpu-bpmp-rx";
1114                         pool;
1115                 };
1116         };
1117
1118         cpus {
1119                 #address-cells = <1>;
1120                 #size-cells = <0>;
1121
1122                 cpu@0 {
1123                         compatible = "nvidia,tegra186-denver";
1124                         device_type = "cpu";
1125                         reg = <0x000>;
1126                 };
1127
1128                 cpu@1 {
1129                         compatible = "nvidia,tegra186-denver";
1130                         device_type = "cpu";
1131                         reg = <0x001>;
1132                 };
1133
1134                 cpu@2 {
1135                         compatible = "arm,cortex-a57";
1136                         device_type = "cpu";
1137                         reg = <0x100>;
1138                 };
1139
1140                 cpu@3 {
1141                         compatible = "arm,cortex-a57";
1142                         device_type = "cpu";
1143                         reg = <0x101>;
1144                 };
1145
1146                 cpu@4 {
1147                         compatible = "arm,cortex-a57";
1148                         device_type = "cpu";
1149                         reg = <0x102>;
1150                 };
1151
1152                 cpu@5 {
1153                         compatible = "arm,cortex-a57";
1154                         device_type = "cpu";
1155                         reg = <0x103>;
1156                 };
1157         };
1158
1159         bpmp: bpmp {
1160                 compatible = "nvidia,tegra186-bpmp";
1161                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1162                                     TEGRA_HSP_DB_MASTER_BPMP>;
1163                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1164                 #clock-cells = <1>;
1165                 #reset-cells = <1>;
1166                 #power-domain-cells = <1>;
1167
1168                 bpmp_i2c: i2c {
1169                         compatible = "nvidia,tegra186-bpmp-i2c";
1170                         nvidia,bpmp-bus-id = <5>;
1171                         #address-cells = <1>;
1172                         #size-cells = <0>;
1173                         status = "disabled";
1174                 };
1175
1176                 bpmp_thermal: thermal {
1177                         compatible = "nvidia,tegra186-bpmp-thermal";
1178                         #thermal-sensor-cells = <1>;
1179                 };
1180         };
1181
1182         thermal-zones {
1183                 a57 {
1184                         polling-delay = <0>;
1185                         polling-delay-passive = <1000>;
1186
1187                         thermal-sensors =
1188                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1189
1190                         trips {
1191                                 critical {
1192                                         temperature = <101000>;
1193                                         hysteresis = <0>;
1194                                         type = "critical";
1195                                 };
1196                         };
1197
1198                         cooling-maps {
1199                         };
1200                 };
1201
1202                 denver {
1203                         polling-delay = <0>;
1204                         polling-delay-passive = <1000>;
1205
1206                         thermal-sensors =
1207                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1208
1209                         trips {
1210                                 critical {
1211                                         temperature = <101000>;
1212                                         hysteresis = <0>;
1213                                         type = "critical";
1214                                 };
1215                         };
1216
1217                         cooling-maps {
1218                         };
1219                 };
1220
1221                 gpu {
1222                         polling-delay = <0>;
1223                         polling-delay-passive = <1000>;
1224
1225                         thermal-sensors =
1226                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1227
1228                         trips {
1229                                 critical {
1230                                         temperature = <101000>;
1231                                         hysteresis = <0>;
1232                                         type = "critical";
1233                                 };
1234                         };
1235
1236                         cooling-maps {
1237                         };
1238                 };
1239
1240                 pll {
1241                         polling-delay = <0>;
1242                         polling-delay-passive = <1000>;
1243
1244                         thermal-sensors =
1245                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1246
1247                         trips {
1248                                 critical {
1249                                         temperature = <101000>;
1250                                         hysteresis = <0>;
1251                                         type = "critical";
1252                                 };
1253                         };
1254
1255                         cooling-maps {
1256                         };
1257                 };
1258
1259                 always_on {
1260                         polling-delay = <0>;
1261                         polling-delay-passive = <1000>;
1262
1263                         thermal-sensors =
1264                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1265
1266                         trips {
1267                                 critical {
1268                                         temperature = <101000>;
1269                                         hysteresis = <0>;
1270                                         type = "critical";
1271                                 };
1272                         };
1273
1274                         cooling-maps {
1275                         };
1276                 };
1277         };
1278
1279         timer {
1280                 compatible = "arm,armv8-timer";
1281                 interrupts = <GIC_PPI 13
1282                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1283                              <GIC_PPI 14
1284                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1285                              <GIC_PPI 11
1286                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1287                              <GIC_PPI 10
1288                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1289                 interrupt-parent = <&gic>;
1290         };
1291 };