1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019 MediaTek Inc.
4 * Copyright (c) 2019 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "mt8516-pinfunc.h"
16 compatible = "mediatek,mt8516";
17 interrupt-parent = <&sysirq>;
21 cluster0_opp: opp-table-0 {
22 compatible = "operating-points-v2";
25 opp-hz = /bits/ 64 <598000000>;
26 opp-microvolt = <1150000>;
29 opp-hz = /bits/ 64 <747500000>;
30 opp-microvolt = <1150000>;
33 opp-hz = /bits/ 64 <1040000000>;
34 opp-microvolt = <1200000>;
37 opp-hz = /bits/ 64 <1196000000>;
38 opp-microvolt = <1250000>;
41 opp-hz = /bits/ 64 <1300000000>;
42 opp-microvolt = <1300000>;
52 compatible = "arm,cortex-a35";
54 enable-method = "psci";
55 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
56 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
58 <&topckgen CLK_TOP_MAINPLL_D2>;
59 clock-names = "cpu", "intermediate";
60 operating-points-v2 = <&cluster0_opp>;
65 compatible = "arm,cortex-a35";
67 enable-method = "psci";
68 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
69 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
71 <&topckgen CLK_TOP_MAINPLL_D2>;
72 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cluster0_opp>;
78 compatible = "arm,cortex-a35";
80 enable-method = "psci";
81 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
82 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
84 <&topckgen CLK_TOP_MAINPLL_D2>;
85 clock-names = "cpu", "intermediate";
86 operating-points-v2 = <&cluster0_opp>;
91 compatible = "arm,cortex-a35";
93 enable-method = "psci";
94 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
95 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
97 <&topckgen CLK_TOP_MAINPLL_D2>;
98 clock-names = "cpu", "intermediate", "armpll";
99 operating-points-v2 = <&cluster0_opp>;
103 entry-method = "psci";
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
106 compatible = "arm,idle-state";
107 entry-latency-us = <600>;
108 exit-latency-us = <600>;
109 min-residency-us = <1200>;
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
114 compatible = "arm,idle-state";
115 entry-latency-us = <800>;
116 exit-latency-us = <1000>;
117 min-residency-us = <2000>;
118 arm,psci-suspend-param = <0x2010000>;
124 compatible = "arm,psci-1.0";
129 compatible = "fixed-clock";
131 clock-frequency = <26000000>;
132 clock-output-names = "clk26m";
136 compatible = "fixed-clock";
138 clock-frequency = <32000>;
139 clock-output-names = "clk32k";
143 #address-cells = <2>;
147 /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
148 bl31_secmon_reserved: secmon@43000000 {
150 reg = <0 0x43000000 0 0x20000>;
155 compatible = "arm,armv8-timer";
156 interrupt-parent = <&gic>;
157 interrupts = <GIC_PPI 13
158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
168 compatible = "arm,armv8-pmuv3";
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
170 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
171 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
172 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
177 #address-cells = <2>;
179 compatible = "simple-bus";
182 topckgen: topckgen@10000000 {
183 compatible = "mediatek,mt8516-topckgen", "syscon";
184 reg = <0 0x10000000 0 0x1000>;
188 infracfg: infracfg@10001000 {
189 compatible = "mediatek,mt8516-infracfg", "syscon";
190 reg = <0 0x10001000 0 0x1000>;
194 pericfg: pericfg@10003050 {
195 compatible = "mediatek,mt8516-pericfg", "syscon";
196 reg = <0 0x10003050 0 0x1000>;
199 apmixedsys: apmixedsys@10018000 {
200 compatible = "mediatek,mt8516-apmixedsys", "syscon";
201 reg = <0 0x10018000 0 0x710>;
205 toprgu: toprgu@10007000 {
206 compatible = "mediatek,mt8516-wdt",
207 "mediatek,mt6589-wdt";
208 reg = <0 0x10007000 0 0x1000>;
209 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
213 timer: timer@10008000 {
214 compatible = "mediatek,mt8516-timer",
215 "mediatek,mt6577-timer";
216 reg = <0 0x10008000 0 0x1000>;
217 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
220 clock-names = "clk13m", "bus";
223 syscfg_pctl: syscfg-pctl@10005000 {
224 compatible = "syscon";
225 reg = <0 0x10005000 0 0x1000>;
228 pio: pinctrl@1000b000 {
229 compatible = "mediatek,mt8516-pinctrl";
230 reg = <0 0x1000b000 0 0x1000>;
231 mediatek,pctl-regmap = <&syscfg_pctl>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
240 efuse: efuse@10009000 {
241 compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
242 reg = <0 0x10009000 0 0x1000>;
243 #address-cells = <1>;
247 pwrap: pwrap@1000f000 {
248 compatible = "mediatek,mt8516-pwrap";
249 reg = <0 0x1000f000 0 0x1000>;
251 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
253 <&topckgen CLK_TOP_PMICWRAP_AP>;
254 clock-names = "spi", "wrap";
257 sysirq: interrupt-controller@10200620 {
258 compatible = "mediatek,mt8516-sysirq",
259 "mediatek,mt6577-sysirq";
260 interrupt-controller;
261 #interrupt-cells = <3>;
262 interrupt-parent = <&gic>;
263 reg = <0 0x10200620 0 0x20>;
266 gic: interrupt-controller@10310000 {
267 compatible = "arm,gic-400";
268 #interrupt-cells = <3>;
269 interrupt-parent = <&gic>;
270 interrupt-controller;
271 reg = <0 0x10310000 0 0x1000>,
272 <0 0x10320000 0 0x1000>,
273 <0 0x10340000 0 0x2000>,
274 <0 0x10360000 0 0x2000>;
275 interrupts = <GIC_PPI 9
276 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
279 apdma: dma-controller@11000480 {
280 compatible = "mediatek,mt8516-uart-dma",
281 "mediatek,mt6577-uart-dma";
282 reg = <0 0x11000480 0 0x80>,
283 <0 0x11000500 0 0x80>,
284 <0 0x11000580 0 0x80>,
285 <0 0x11000600 0 0x80>,
286 <0 0x11000980 0 0x80>,
287 <0 0x11000a00 0 0x80>;
288 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
289 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
290 <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
291 <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
292 <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
293 <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
295 clocks = <&topckgen CLK_TOP_APDMA>;
296 clock-names = "apdma";
300 uart0: serial@11005000 {
301 compatible = "mediatek,mt8516-uart",
302 "mediatek,mt6577-uart";
303 reg = <0 0x11005000 0 0x1000>;
304 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
305 clocks = <&topckgen CLK_TOP_UART0_SEL>,
306 <&topckgen CLK_TOP_UART0>;
307 clock-names = "baud", "bus";
310 dma-names = "tx", "rx";
314 uart1: serial@11006000 {
315 compatible = "mediatek,mt8516-uart",
316 "mediatek,mt6577-uart";
317 reg = <0 0x11006000 0 0x1000>;
318 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
319 clocks = <&topckgen CLK_TOP_UART1_SEL>,
320 <&topckgen CLK_TOP_UART1>;
321 clock-names = "baud", "bus";
324 dma-names = "tx", "rx";
328 uart2: serial@11007000 {
329 compatible = "mediatek,mt8516-uart",
330 "mediatek,mt6577-uart";
331 reg = <0 0x11007000 0 0x1000>;
332 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
333 clocks = <&topckgen CLK_TOP_UART2_SEL>,
334 <&topckgen CLK_TOP_UART2>;
335 clock-names = "baud", "bus";
338 dma-names = "tx", "rx";
343 compatible = "mediatek,mt8516-i2c",
344 "mediatek,mt2712-i2c";
345 reg = <0 0x11009000 0 0x90>,
346 <0 0x11000180 0 0x80>;
347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
348 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
349 <&infracfg CLK_IFR_I2C0_SEL>,
350 <&topckgen CLK_TOP_I2C0>,
351 <&topckgen CLK_TOP_APDMA>;
352 clock-names = "main-source",
356 #address-cells = <1>;
362 compatible = "mediatek,mt8516-i2c",
363 "mediatek,mt2712-i2c";
364 reg = <0 0x1100a000 0 0x90>,
365 <0 0x11000200 0 0x80>;
366 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
367 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
368 <&infracfg CLK_IFR_I2C1_SEL>,
369 <&topckgen CLK_TOP_I2C1>,
370 <&topckgen CLK_TOP_APDMA>;
371 clock-names = "main-source",
375 #address-cells = <1>;
381 compatible = "mediatek,mt8516-i2c",
382 "mediatek,mt2712-i2c";
383 reg = <0 0x1100b000 0 0x90>,
384 <0 0x11000280 0 0x80>;
385 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
386 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
387 <&infracfg CLK_IFR_I2C2_SEL>,
388 <&topckgen CLK_TOP_I2C2>,
389 <&topckgen CLK_TOP_APDMA>;
390 clock-names = "main-source",
394 #address-cells = <1>;
400 compatible = "mediatek,mt8516-spi",
401 "mediatek,mt2712-spi";
402 #address-cells = <1>;
404 reg = <0 0x1100c000 0 0x1000>;
405 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
406 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
407 <&topckgen CLK_TOP_SPI_SEL>,
408 <&topckgen CLK_TOP_SPI>;
409 clock-names = "parent-clk", "sel-clk", "spi-clk";
414 compatible = "mediatek,mt8516-mmc";
415 reg = <0 0x11120000 0 0x1000>;
416 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
417 clocks = <&topckgen CLK_TOP_MSDC0>,
418 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
419 <&topckgen CLK_TOP_MSDC0_INFRA>;
420 clock-names = "source", "hclk", "source_cg";
425 compatible = "mediatek,mt8516-mmc";
426 reg = <0 0x11130000 0 0x1000>;
427 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
428 clocks = <&topckgen CLK_TOP_MSDC1>,
429 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
430 <&topckgen CLK_TOP_MSDC1_INFRA>;
431 clock-names = "source", "hclk", "source_cg";
436 compatible = "mediatek,mt8516-mmc";
437 reg = <0 0x11170000 0 0x1000>;
438 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_MSDC2>,
440 <&topckgen CLK_TOP_RG_MSDC2>,
441 <&topckgen CLK_TOP_MSDC2_INFRA>;
442 clock-names = "source", "hclk", "source_cg";
446 ethernet: ethernet@11180000 {
447 compatible = "mediatek,mt8516-eth";
448 reg = <0 0x11180000 0 0x1000>;
449 mediatek,pericfg = <&pericfg>;
450 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
451 clocks = <&topckgen CLK_TOP_RG_ETH>,
452 <&topckgen CLK_TOP_66M_ETH>,
453 <&topckgen CLK_TOP_133M_ETH>;
454 clock-names = "core", "reg", "trans";
459 compatible = "mediatek,mt8516-rng",
460 "mediatek,mt7623-rng";
461 reg = <0 0x1020c000 0 0x100>;
462 clocks = <&topckgen CLK_TOP_TRNG>;
467 compatible = "mediatek,mt8516-pwm";
468 reg = <0 0x11008000 0 0x1000>;
470 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
471 clocks = <&topckgen CLK_TOP_PWM>,
472 <&topckgen CLK_TOP_PWM_B>,
473 <&topckgen CLK_TOP_PWM1_FB>,
474 <&topckgen CLK_TOP_PWM2_FB>,
475 <&topckgen CLK_TOP_PWM3_FB>,
476 <&topckgen CLK_TOP_PWM4_FB>,
477 <&topckgen CLK_TOP_PWM5_FB>;
478 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
483 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
484 reg = <0 0x11100000 0 0x1000>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
486 interrupt-names = "mc";
487 phys = <&usb0_port PHY_TYPE_USB2>;
488 clocks = <&topckgen CLK_TOP_USB>,
489 <&topckgen CLK_TOP_USBIF>,
490 <&topckgen CLK_TOP_USB_1P>;
491 clock-names = "main","mcu","univpll";
496 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
497 reg = <0 0x11190000 0 0x1000>;
498 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
499 interrupt-names = "mc";
500 phys = <&usb1_port PHY_TYPE_USB2>;
501 clocks = <&topckgen CLK_TOP_USB>,
502 <&topckgen CLK_TOP_USBIF>,
503 <&topckgen CLK_TOP_USB_1P>;
504 clock-names = "main","mcu","univpll";
509 usb_phy: t-phy@11110000 {
510 compatible = "mediatek,mt8516-tphy",
511 "mediatek,generic-tphy-v1";
512 reg = <0 0x11110000 0 0x800>;
513 #address-cells = <2>;
518 usb0_port: usb-phy@11110800 {
519 reg = <0 0x11110800 0 0x100>;
520 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
525 usb1_port: usb-phy@11110900 {
526 reg = <0 0x11110900 0 0x100>;
527 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
533 auxadc: adc@11003000 {
534 compatible = "mediatek,mt8516-auxadc",
535 "mediatek,mt8173-auxadc";
536 reg = <0 0x11003000 0 0x1000>;
537 clocks = <&topckgen CLK_TOP_AUX_ADC>;
538 clock-names = "main";
539 #io-channel-cells = <1>;