1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
13 compatible = "mediatek,mt8192";
14 interrupt-parent = <&gic>;
19 compatible = "fixed-clock";
21 clock-frequency = <26000000>;
22 clock-output-names = "clk26m";
26 compatible = "fixed-clock";
28 clock-frequency = <32768>;
29 clock-output-names = "clk32k";
38 compatible = "arm,cortex-a55";
40 enable-method = "psci";
41 clock-frequency = <1701000000>;
42 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
43 next-level-cache = <&l2_0>;
44 capacity-dmips-mhz = <530>;
49 compatible = "arm,cortex-a55";
51 enable-method = "psci";
52 clock-frequency = <1701000000>;
53 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
54 next-level-cache = <&l2_0>;
55 capacity-dmips-mhz = <530>;
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 clock-frequency = <1701000000>;
64 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
65 next-level-cache = <&l2_0>;
66 capacity-dmips-mhz = <530>;
71 compatible = "arm,cortex-a55";
73 enable-method = "psci";
74 clock-frequency = <1701000000>;
75 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
76 next-level-cache = <&l2_0>;
77 capacity-dmips-mhz = <530>;
82 compatible = "arm,cortex-a76";
84 enable-method = "psci";
85 clock-frequency = <2171000000>;
86 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
87 next-level-cache = <&l2_1>;
88 capacity-dmips-mhz = <1024>;
93 compatible = "arm,cortex-a76";
95 enable-method = "psci";
96 clock-frequency = <2171000000>;
97 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
98 next-level-cache = <&l2_1>;
99 capacity-dmips-mhz = <1024>;
104 compatible = "arm,cortex-a76";
106 enable-method = "psci";
107 clock-frequency = <2171000000>;
108 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
109 next-level-cache = <&l2_1>;
110 capacity-dmips-mhz = <1024>;
115 compatible = "arm,cortex-a76";
117 enable-method = "psci";
118 clock-frequency = <2171000000>;
119 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
120 next-level-cache = <&l2_1>;
121 capacity-dmips-mhz = <1024>;
157 compatible = "cache";
158 next-level-cache = <&l3_0>;
162 compatible = "cache";
163 next-level-cache = <&l3_0>;
167 compatible = "cache";
171 entry-method = "arm,psci";
173 compatible = "arm,idle-state";
174 arm,psci-suspend-param = <0x00010001>;
176 entry-latency-us = <55>;
177 exit-latency-us = <140>;
178 min-residency-us = <780>;
181 compatible = "arm,idle-state";
182 arm,psci-suspend-param = <0x00010001>;
184 entry-latency-us = <35>;
185 exit-latency-us = <145>;
186 min-residency-us = <720>;
188 clusteroff_l: clusteroff_l {
189 compatible = "arm,idle-state";
190 arm,psci-suspend-param = <0x01010002>;
192 entry-latency-us = <60>;
193 exit-latency-us = <155>;
194 min-residency-us = <860>;
196 clusteroff_b: clusteroff_b {
197 compatible = "arm,idle-state";
198 arm,psci-suspend-param = <0x01010002>;
200 entry-latency-us = <40>;
201 exit-latency-us = <155>;
202 min-residency-us = <780>;
208 compatible = "arm,cortex-a55-pmu";
209 interrupt-parent = <&gic>;
210 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
214 compatible = "arm,cortex-a76-pmu";
215 interrupt-parent = <&gic>;
216 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
220 compatible = "arm,psci-1.0";
225 compatible = "arm,armv8-timer";
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
228 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
229 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
230 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
231 clock-frequency = <13000000>;
235 #address-cells = <2>;
237 compatible = "simple-bus";
240 gic: interrupt-controller@c000000 {
241 compatible = "arm,gic-v3";
242 #interrupt-cells = <4>;
243 #redistributor-regions = <1>;
244 interrupt-parent = <&gic>;
245 interrupt-controller;
246 reg = <0 0x0c000000 0 0x40000>,
247 <0 0x0c040000 0 0x200000>;
248 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
251 ppi_cluster0: interrupt-partition-0 {
252 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
254 ppi_cluster1: interrupt-partition-1 {
255 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
260 pio: pinctrl@10005000 {
261 compatible = "mediatek,mt8192-pinctrl";
262 reg = <0 0x10005000 0 0x1000>,
263 <0 0x11c20000 0 0x1000>,
264 <0 0x11d10000 0 0x1000>,
265 <0 0x11d30000 0 0x1000>,
266 <0 0x11d40000 0 0x1000>,
267 <0 0x11e20000 0 0x1000>,
268 <0 0x11e70000 0 0x1000>,
269 <0 0x11ea0000 0 0x1000>,
270 <0 0x11f20000 0 0x1000>,
271 <0 0x11f30000 0 0x1000>,
272 <0 0x1000b000 0 0x1000>;
273 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
274 "iocfg_bl", "iocfg_br", "iocfg_lm",
275 "iocfg_lb", "iocfg_rt", "iocfg_lt",
279 gpio-ranges = <&pio 0 0 220>;
280 interrupt-controller;
281 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
282 #interrupt-cells = <2>;
285 systimer: timer@10017000 {
286 compatible = "mediatek,mt8192-timer",
287 "mediatek,mt6765-timer";
288 reg = <0 0x10017000 0 0x1000>;
289 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
291 clock-names = "clk13m";
294 uart0: serial@11002000 {
295 compatible = "mediatek,mt8192-uart",
296 "mediatek,mt6577-uart";
297 reg = <0 0x11002000 0 0x1000>;
298 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
299 clocks = <&clk26m>, <&clk26m>;
300 clock-names = "baud", "bus";
304 uart1: serial@11003000 {
305 compatible = "mediatek,mt8192-uart",
306 "mediatek,mt6577-uart";
307 reg = <0 0x11003000 0 0x1000>;
308 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
309 clocks = <&clk26m>, <&clk26m>;
310 clock-names = "baud", "bus";
315 compatible = "mediatek,mt8192-spi",
316 "mediatek,mt6765-spi";
317 #address-cells = <1>;
319 reg = <0 0x1100a000 0 0x1000>;
320 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
324 clock-names = "parent-clk", "sel-clk", "spi-clk";
329 compatible = "mediatek,mt8192-spi",
330 "mediatek,mt6765-spi";
331 #address-cells = <1>;
333 reg = <0 0x11010000 0 0x1000>;
334 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
338 clock-names = "parent-clk", "sel-clk", "spi-clk";
343 compatible = "mediatek,mt8192-spi",
344 "mediatek,mt6765-spi";
345 #address-cells = <1>;
347 reg = <0 0x11012000 0 0x1000>;
348 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
352 clock-names = "parent-clk", "sel-clk", "spi-clk";
357 compatible = "mediatek,mt8192-spi",
358 "mediatek,mt6765-spi";
359 #address-cells = <1>;
361 reg = <0 0x11013000 0 0x1000>;
362 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
366 clock-names = "parent-clk", "sel-clk", "spi-clk";
371 compatible = "mediatek,mt8192-spi",
372 "mediatek,mt6765-spi";
373 #address-cells = <1>;
375 reg = <0 0x11018000 0 0x1000>;
376 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
380 clock-names = "parent-clk", "sel-clk", "spi-clk";
385 compatible = "mediatek,mt8192-spi",
386 "mediatek,mt6765-spi";
387 #address-cells = <1>;
389 reg = <0 0x11019000 0 0x1000>;
390 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
394 clock-names = "parent-clk", "sel-clk", "spi-clk";
399 compatible = "mediatek,mt8192-spi",
400 "mediatek,mt6765-spi";
401 #address-cells = <1>;
403 reg = <0 0x1101d000 0 0x1000>;
404 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
408 clock-names = "parent-clk", "sel-clk", "spi-clk";
413 compatible = "mediatek,mt8192-spi",
414 "mediatek,mt6765-spi";
415 #address-cells = <1>;
417 reg = <0 0x1101e000 0 0x1000>;
418 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
422 clock-names = "parent-clk", "sel-clk", "spi-clk";
426 nor_flash: spi@11234000 {
427 compatible = "mediatek,mt8192-nor";
428 reg = <0 0x11234000 0 0xe0>;
429 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
433 clock-names = "spi", "sf", "axi";
434 #address-cells = <1>;
439 i2c3: i2c3@11cb0000 {
440 compatible = "mediatek,mt8192-i2c";
441 reg = <0 0x11cb0000 0 0x1000>,
442 <0 0x10217300 0 0x80>;
443 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
444 clocks = <&clk26m>, <&clk26m>;
445 clock-names = "main", "dma";
447 #address-cells = <1>;
452 i2c7: i2c7@11d00000 {
453 compatible = "mediatek,mt8192-i2c";
454 reg = <0 0x11d00000 0 0x1000>,
455 <0 0x10217600 0 0x180>;
456 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
457 clocks = <&clk26m>, <&clk26m>;
458 clock-names = "main", "dma";
460 #address-cells = <1>;
465 i2c8: i2c8@11d01000 {
466 compatible = "mediatek,mt8192-i2c";
467 reg = <0 0x11d01000 0 0x1000>,
468 <0 0x10217780 0 0x180>;
469 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
470 clocks = <&clk26m>, <&clk26m>;
471 clock-names = "main", "dma";
473 #address-cells = <1>;
478 i2c9: i2c9@11d02000 {
479 compatible = "mediatek,mt8192-i2c";
480 reg = <0 0x11d02000 0 0x1000>,
481 <0 0x10217900 0 0x180>;
482 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
483 clocks = <&clk26m>, <&clk26m>;
484 clock-names = "main", "dma";
486 #address-cells = <1>;
491 i2c1: i2c1@11d20000 {
492 compatible = "mediatek,mt8192-i2c";
493 reg = <0 0x11d20000 0 0x1000>,
494 <0 0x10217100 0 0x80>;
495 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
496 clocks = <&clk26m>, <&clk26m>;
497 clock-names = "main", "dma";
499 #address-cells = <1>;
504 i2c2: i2c2@11d21000 {
505 compatible = "mediatek,mt8192-i2c";
506 reg = <0 0x11d21000 0 0x1000>,
507 <0 0x10217180 0 0x180>;
508 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
509 clocks = <&clk26m>, <&clk26m>;
510 clock-names = "main", "dma";
512 #address-cells = <1>;
517 i2c4: i2c4@11d22000 {
518 compatible = "mediatek,mt8192-i2c";
519 reg = <0 0x11d22000 0 0x1000>,
520 <0 0x10217380 0 0x180>;
521 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
522 clocks = <&clk26m>, <&clk26m>;
523 clock-names = "main", "dma";
525 #address-cells = <1>;
530 i2c5: i2c5@11e00000 {
531 compatible = "mediatek,mt8192-i2c";
532 reg = <0 0x11e00000 0 0x1000>,
533 <0 0x10217500 0 0x80>;
534 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
535 clocks = <&clk26m>, <&clk26m>;
536 clock-names = "main", "dma";
538 #address-cells = <1>;
543 i2c0: i2c0@11f00000 {
544 compatible = "mediatek,mt8192-i2c";
545 reg = <0 0x11f00000 0 0x1000>,
546 <0 0x10217080 0 0x80>;
547 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
548 clocks = <&clk26m>, <&clk26m>;
549 clock-names = "main", "dma";
551 #address-cells = <1>;
556 i2c6: i2c6@11f01000 {
557 compatible = "mediatek,mt8192-i2c";
558 reg = <0 0x11f01000 0 0x1000>,
559 <0 0x10217580 0 0x80>;
560 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
561 clocks = <&clk26m>, <&clk26m>;
562 clock-names = "main", "dma";
564 #address-cells = <1>;