1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
13 compatible = "mediatek,mt8192";
14 interrupt-parent = <&gic>;
19 compatible = "fixed-clock";
21 clock-frequency = <26000000>;
22 clock-output-names = "clk26m";
26 compatible = "fixed-clock";
28 clock-frequency = <32768>;
29 clock-output-names = "clk32k";
38 compatible = "arm,cortex-a55";
40 enable-method = "psci";
41 clock-frequency = <1701000000>;
42 next-level-cache = <&l2_0>;
43 capacity-dmips-mhz = <530>;
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 clock-frequency = <1701000000>;
52 next-level-cache = <&l2_0>;
53 capacity-dmips-mhz = <530>;
58 compatible = "arm,cortex-a55";
60 enable-method = "psci";
61 clock-frequency = <1701000000>;
62 next-level-cache = <&l2_0>;
63 capacity-dmips-mhz = <530>;
68 compatible = "arm,cortex-a55";
70 enable-method = "psci";
71 clock-frequency = <1701000000>;
72 next-level-cache = <&l2_0>;
73 capacity-dmips-mhz = <530>;
78 compatible = "arm,cortex-a76";
80 enable-method = "psci";
81 clock-frequency = <2171000000>;
82 next-level-cache = <&l2_1>;
83 capacity-dmips-mhz = <1024>;
88 compatible = "arm,cortex-a76";
90 enable-method = "psci";
91 clock-frequency = <2171000000>;
92 next-level-cache = <&l2_1>;
93 capacity-dmips-mhz = <1024>;
98 compatible = "arm,cortex-a76";
100 enable-method = "psci";
101 clock-frequency = <2171000000>;
102 next-level-cache = <&l2_1>;
103 capacity-dmips-mhz = <1024>;
108 compatible = "arm,cortex-a76";
110 enable-method = "psci";
111 clock-frequency = <2171000000>;
112 next-level-cache = <&l2_1>;
113 capacity-dmips-mhz = <1024>;
149 compatible = "cache";
150 next-level-cache = <&l3_0>;
154 compatible = "cache";
155 next-level-cache = <&l3_0>;
159 compatible = "cache";
164 compatible = "arm,cortex-a55-pmu";
165 interrupt-parent = <&gic>;
166 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
170 compatible = "arm,cortex-a76-pmu";
171 interrupt-parent = <&gic>;
172 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
176 compatible = "arm,psci-1.0";
181 compatible = "arm,armv8-timer";
182 interrupt-parent = <&gic>;
183 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
184 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
185 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
186 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
187 clock-frequency = <13000000>;
191 #address-cells = <2>;
193 compatible = "simple-bus";
196 gic: interrupt-controller@c000000 {
197 compatible = "arm,gic-v3";
198 #interrupt-cells = <4>;
199 #redistributor-regions = <1>;
200 interrupt-parent = <&gic>;
201 interrupt-controller;
202 reg = <0 0x0c000000 0 0x40000>,
203 <0 0x0c040000 0 0x200000>;
204 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
207 ppi_cluster0: interrupt-partition-0 {
208 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
210 ppi_cluster1: interrupt-partition-1 {
211 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
216 pio: pinctrl@10005000 {
217 compatible = "mediatek,mt8192-pinctrl";
218 reg = <0 0x10005000 0 0x1000>,
219 <0 0x11c20000 0 0x1000>,
220 <0 0x11d10000 0 0x1000>,
221 <0 0x11d30000 0 0x1000>,
222 <0 0x11d40000 0 0x1000>,
223 <0 0x11e20000 0 0x1000>,
224 <0 0x11e70000 0 0x1000>,
225 <0 0x11ea0000 0 0x1000>,
226 <0 0x11f20000 0 0x1000>,
227 <0 0x11f30000 0 0x1000>,
228 <0 0x1000b000 0 0x1000>;
229 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
230 "iocfg_bl", "iocfg_br", "iocfg_lm",
231 "iocfg_lb", "iocfg_rt", "iocfg_lt",
235 gpio-ranges = <&pio 0 0 220>;
236 interrupt-controller;
237 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
238 #interrupt-cells = <2>;
241 systimer: timer@10017000 {
242 compatible = "mediatek,mt8192-timer",
243 "mediatek,mt6765-timer";
244 reg = <0 0x10017000 0 0x1000>;
245 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
247 clock-names = "clk13m";
250 uart0: serial@11002000 {
251 compatible = "mediatek,mt8192-uart",
252 "mediatek,mt6577-uart";
253 reg = <0 0x11002000 0 0x1000>;
254 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
255 clocks = <&clk26m>, <&clk26m>;
256 clock-names = "baud", "bus";
260 uart1: serial@11003000 {
261 compatible = "mediatek,mt8192-uart",
262 "mediatek,mt6577-uart";
263 reg = <0 0x11003000 0 0x1000>;
264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
265 clocks = <&clk26m>, <&clk26m>;
266 clock-names = "baud", "bus";
271 compatible = "mediatek,mt8192-spi",
272 "mediatek,mt6765-spi";
273 #address-cells = <1>;
275 reg = <0 0x1100a000 0 0x1000>;
276 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
280 clock-names = "parent-clk", "sel-clk", "spi-clk";
285 compatible = "mediatek,mt8192-spi",
286 "mediatek,mt6765-spi";
287 #address-cells = <1>;
289 reg = <0 0x11010000 0 0x1000>;
290 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
294 clock-names = "parent-clk", "sel-clk", "spi-clk";
299 compatible = "mediatek,mt8192-spi",
300 "mediatek,mt6765-spi";
301 #address-cells = <1>;
303 reg = <0 0x11012000 0 0x1000>;
304 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
308 clock-names = "parent-clk", "sel-clk", "spi-clk";
313 compatible = "mediatek,mt8192-spi",
314 "mediatek,mt6765-spi";
315 #address-cells = <1>;
317 reg = <0 0x11013000 0 0x1000>;
318 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk";
327 compatible = "mediatek,mt8192-spi",
328 "mediatek,mt6765-spi";
329 #address-cells = <1>;
331 reg = <0 0x11018000 0 0x1000>;
332 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
336 clock-names = "parent-clk", "sel-clk", "spi-clk";
341 compatible = "mediatek,mt8192-spi",
342 "mediatek,mt6765-spi";
343 #address-cells = <1>;
345 reg = <0 0x11019000 0 0x1000>;
346 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
350 clock-names = "parent-clk", "sel-clk", "spi-clk";
355 compatible = "mediatek,mt8192-spi",
356 "mediatek,mt6765-spi";
357 #address-cells = <1>;
359 reg = <0 0x1101d000 0 0x1000>;
360 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
364 clock-names = "parent-clk", "sel-clk", "spi-clk";
369 compatible = "mediatek,mt8192-spi",
370 "mediatek,mt6765-spi";
371 #address-cells = <1>;
373 reg = <0 0x1101e000 0 0x1000>;
374 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
378 clock-names = "parent-clk", "sel-clk", "spi-clk";
382 i2c3: i2c3@11cb0000 {
383 compatible = "mediatek,mt8192-i2c";
384 reg = <0 0x11cb0000 0 0x1000>,
385 <0 0x10217300 0 0x80>;
386 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
387 clocks = <&clk26m>, <&clk26m>;
388 clock-names = "main", "dma";
390 #address-cells = <1>;
395 i2c7: i2c7@11d00000 {
396 compatible = "mediatek,mt8192-i2c";
397 reg = <0 0x11d00000 0 0x1000>,
398 <0 0x10217600 0 0x180>;
399 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
400 clocks = <&clk26m>, <&clk26m>;
401 clock-names = "main", "dma";
403 #address-cells = <1>;
408 i2c8: i2c8@11d01000 {
409 compatible = "mediatek,mt8192-i2c";
410 reg = <0 0x11d01000 0 0x1000>,
411 <0 0x10217780 0 0x180>;
412 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
413 clocks = <&clk26m>, <&clk26m>;
414 clock-names = "main", "dma";
416 #address-cells = <1>;
421 i2c9: i2c9@11d02000 {
422 compatible = "mediatek,mt8192-i2c";
423 reg = <0 0x11d02000 0 0x1000>,
424 <0 0x10217900 0 0x180>;
425 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
426 clocks = <&clk26m>, <&clk26m>;
427 clock-names = "main", "dma";
429 #address-cells = <1>;
434 i2c1: i2c1@11d20000 {
435 compatible = "mediatek,mt8192-i2c";
436 reg = <0 0x11d20000 0 0x1000>,
437 <0 0x10217100 0 0x80>;
438 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
439 clocks = <&clk26m>, <&clk26m>;
440 clock-names = "main", "dma";
442 #address-cells = <1>;
447 i2c2: i2c2@11d21000 {
448 compatible = "mediatek,mt8192-i2c";
449 reg = <0 0x11d21000 0 0x1000>,
450 <0 0x10217180 0 0x180>;
451 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
452 clocks = <&clk26m>, <&clk26m>;
453 clock-names = "main", "dma";
455 #address-cells = <1>;
460 i2c4: i2c4@11d22000 {
461 compatible = "mediatek,mt8192-i2c";
462 reg = <0 0x11d22000 0 0x1000>,
463 <0 0x10217380 0 0x180>;
464 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
465 clocks = <&clk26m>, <&clk26m>;
466 clock-names = "main", "dma";
468 #address-cells = <1>;
473 i2c5: i2c5@11e00000 {
474 compatible = "mediatek,mt8192-i2c";
475 reg = <0 0x11e00000 0 0x1000>,
476 <0 0x10217500 0 0x80>;
477 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
478 clocks = <&clk26m>, <&clk26m>;
479 clock-names = "main", "dma";
481 #address-cells = <1>;
486 i2c0: i2c0@11f00000 {
487 compatible = "mediatek,mt8192-i2c";
488 reg = <0 0x11f00000 0 0x1000>,
489 <0 0x10217080 0 0x80>;
490 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
491 clocks = <&clk26m>, <&clk26m>;
492 clock-names = "main", "dma";
494 #address-cells = <1>;
499 i2c6: i2c6@11f01000 {
500 compatible = "mediatek,mt8192-i2c";
501 reg = <0 0x11f01000 0 0x1000>,
502 <0 0x10217580 0 0x80>;
503 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
504 clocks = <&clk26m>, <&clk26m>;
505 clock-names = "main", "dma";
507 #address-cells = <1>;