1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "mt8183.dtsi"
11 #include "mt6358.dtsi"
21 stdout-path = "serial0:115200n8";
24 backlight_lcd0: backlight_lcd0 {
25 compatible = "pwm-backlight";
26 pwms = <&pwm0 0 500000>;
27 power-supply = <&bl_pp5000>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
36 device_type = "memory";
37 reg = <0 0x40000000 0 0x80000000>;
41 compatible = "fixed-clock";
43 clock-frequency = <32768>;
44 clock-output-names = "clk32k";
47 it6505_pp18_reg: regulator0 {
48 compatible = "regulator-fixed";
49 regulator-name = "it6505_pp18";
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
56 lcd_pp3300: regulator1 {
57 compatible = "regulator-fixed";
58 regulator-name = "lcd_pp3300";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
65 bl_pp5000: regulator2 {
66 compatible = "regulator-fixed";
67 regulator-name = "bl_pp5000";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
74 mmc1_fixed_power: regulator3 {
75 compatible = "regulator-fixed";
76 regulator-name = "mmc1_power";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
81 mmc1_fixed_io: regulator4 {
82 compatible = "regulator-fixed";
83 regulator-name = "mmc1_io";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
88 pp1800_alw: regulator5 {
89 compatible = "regulator-fixed";
90 regulator-name = "pp1800_alw";
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
97 pp3300_alw: regulator6 {
98 compatible = "regulator-fixed";
99 regulator-name = "pp3300_alw";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
106 reserved_memory: reserved-memory {
107 #address-cells = <2>;
111 scp_mem_reserved: scp_mem_region {
112 compatible = "shared-dma-pool";
113 reg = <0 0x50000000 0 0x2900000>;
119 compatible = "maxim,max98357a";
120 sdmode-gpios = <&pio 175 0>;
124 compatible = "linux,bt-sco";
127 wifi_pwrseq: wifi-pwrseq {
128 compatible = "mmc-pwrseq-simple";
129 pinctrl-names = "default";
130 pinctrl-0 = <&wifi_pins_pwrseq>;
132 /* Toggle WIFI_ENABLE to reset the chip. */
133 reset-gpios = <&pio 119 1>;
136 wifi_wakeup: wifi-wakeup {
137 compatible = "gpio-keys";
138 pinctrl-names = "default";
139 pinctrl-0 = <&wifi_pins_wakeup>;
142 label = "Wake on WiFi";
143 gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
144 linux,code = <KEY_WAKEUP>;
149 tboard_thermistor1: thermal-sensor1 {
150 compatible = "generic-adc-thermal";
151 #thermal-sensor-cells = <0>;
152 io-channels = <&auxadc 0>;
153 io-channel-names = "sensor-channel";
154 temperature-lookup-table = < (-5000) 4241
183 tboard_thermistor2: thermal-sensor2 {
184 compatible = "generic-adc-thermal";
185 #thermal-sensor-cells = <0>;
186 io-channels = <&auxadc 1>;
187 io-channel-names = "sensor-channel";
188 temperature-lookup-table = < (-5000) 4241
223 proc-supply = <&mt6358_vproc12_reg>;
227 proc-supply = <&mt6358_vproc12_reg>;
231 proc-supply = <&mt6358_vproc12_reg>;
235 proc-supply = <&mt6358_vproc12_reg>;
239 proc-supply = <&mt6358_vproc11_reg>;
243 proc-supply = <&mt6358_vproc11_reg>;
247 proc-supply = <&mt6358_vproc11_reg>;
251 proc-supply = <&mt6358_vproc11_reg>;
256 #address-cells = <1>;
259 /* compatible will be set in board dts */
261 enable-gpios = <&pio 45 0>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&panel_pins_default>;
264 avdd-supply = <&ppvarn_lcd>;
265 avee-supply = <&ppvarp_lcd>;
266 pp1800-supply = <&pp1800_lcd>;
267 backlight = <&backlight_lcd0>;
270 remote-endpoint = <&dsi_out>;
278 remote-endpoint = <&panel_in>;
285 mali-supply = <&mt6358_vgpu_reg>;
286 sram-supply = <&mt6358_vsram_gpu_reg>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c0_pins>;
293 clock-frequency = <400000>;
294 #address-cells = <1>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c1_pins>;
302 clock-frequency = <100000>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c3_pins>;
309 clock-frequency = <100000>;
310 #address-cells = <1>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c5_pins>;
318 clock-frequency = <100000>;
319 #address-cells = <1>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c6_pins>;
327 clock-frequency = <100000>;
336 pinctrl-names = "default", "state_uhs";
337 pinctrl-0 = <&mmc0_pins_default>;
338 pinctrl-1 = <&mmc0_pins_uhs>;
340 max-frequency = <200000000>;
347 hs400-ds-delay = <0x12814>;
348 vmmc-supply = <&mt6358_vemc_reg>;
349 vqmmc-supply = <&mt6358_vio18_reg>;
350 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
351 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
357 pinctrl-names = "default", "state_uhs";
358 pinctrl-0 = <&mmc1_pins_default>;
359 pinctrl-1 = <&mmc1_pins_uhs>;
360 vmmc-supply = <&mmc1_fixed_power>;
361 vqmmc-supply = <&mmc1_fixed_io>;
362 mmc-pwrseq = <&wifi_pwrseq>;
364 max-frequency = <200000000>;
369 keep-power-in-suspend;
375 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
376 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
377 #address-cells = <1>;
380 qca_wifi: qca-wifi@1 {
381 compatible = "qcom,ath10k";
391 Avdd-supply = <&mt6358_vaud28_reg>;
395 regulator-min-microvolt = <2700000>;
396 regulator-max-microvolt = <2700000>;
400 regulator-min-microvolt = <2700000>;
401 regulator-max-microvolt = <2700000>;
407 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
412 ec_ap_int_odl: ec_ap_int_odl {
414 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
420 h1_int_od_l: h1_int_od_l {
422 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
429 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
430 <PINMUX_GPIO83__FUNC_SCL0>;
431 mediatek,pull-up-adv = <3>;
432 mediatek,drive-strength-adv = <00>;
438 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
439 <PINMUX_GPIO84__FUNC_SCL1>;
440 mediatek,pull-up-adv = <3>;
441 mediatek,drive-strength-adv = <00>;
447 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
448 <PINMUX_GPIO104__FUNC_SDA2>;
450 mediatek,drive-strength-adv = <00>;
456 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
457 <PINMUX_GPIO51__FUNC_SDA3>;
458 mediatek,pull-up-adv = <3>;
459 mediatek,drive-strength-adv = <00>;
465 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
466 <PINMUX_GPIO106__FUNC_SDA4>;
468 mediatek,drive-strength-adv = <00>;
474 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
475 <PINMUX_GPIO49__FUNC_SDA5>;
476 mediatek,pull-up-adv = <3>;
477 mediatek,drive-strength-adv = <00>;
483 pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
484 <PINMUX_GPIO12__FUNC_SDA6>;
489 mmc0_pins_default: mmc0-pins-default {
491 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
492 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
493 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
494 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
495 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
496 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
497 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
498 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
499 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
501 drive-strength = <MTK_DRIVE_14mA>;
502 mediatek,pull-up-adv = <01>;
506 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
507 drive-strength = <MTK_DRIVE_14mA>;
508 mediatek,pull-down-adv = <10>;
512 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
513 drive-strength = <MTK_DRIVE_14mA>;
514 mediatek,pull-down-adv = <01>;
518 mmc0_pins_uhs: mmc0-pins-uhs {
520 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
521 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
522 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
523 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
524 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
525 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
526 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
527 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
528 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
530 drive-strength = <MTK_DRIVE_14mA>;
531 mediatek,pull-up-adv = <01>;
535 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
536 drive-strength = <MTK_DRIVE_14mA>;
537 mediatek,pull-down-adv = <10>;
541 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
542 drive-strength = <MTK_DRIVE_14mA>;
543 mediatek,pull-down-adv = <10>;
547 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
548 drive-strength = <MTK_DRIVE_14mA>;
549 mediatek,pull-up-adv = <01>;
553 mmc1_pins_default: mmc1-pins-default {
555 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
556 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
557 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
558 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
559 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
561 mediatek,pull-up-adv = <10>;
565 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
567 mediatek,pull-down-adv = <10>;
571 mmc1_pins_uhs: mmc1-pins-uhs {
573 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
574 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
575 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
576 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
577 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
578 drive-strength = <MTK_DRIVE_6mA>;
580 mediatek,pull-up-adv = <10>;
584 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
585 drive-strength = <MTK_DRIVE_8mA>;
586 mediatek,pull-down-adv = <10>;
591 panel_pins_default: panel_pins_default {
593 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
599 pwm0_pin_default: pwm0_pin_default {
601 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
606 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
612 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
613 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
619 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
620 <PINMUX_GPIO86__FUNC_GPIO86>,
621 <PINMUX_GPIO87__FUNC_SPI0_MO>,
622 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
629 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
630 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
631 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
632 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
639 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
640 <PINMUX_GPIO1__FUNC_SPI2_MO>,
641 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
645 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
646 mediatek,pull-down-adv = <00>;
652 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
653 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
654 <PINMUX_GPIO23__FUNC_SPI3_MO>,
655 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
662 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
663 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
664 <PINMUX_GPIO19__FUNC_SPI4_MO>,
665 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
672 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
673 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
674 <PINMUX_GPIO15__FUNC_SPI5_MO>,
675 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
680 uart0_pins_default: uart0-pins-default {
682 pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
687 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
691 uart1_pins_default: uart1-pins-default {
693 pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
698 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
701 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
705 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
710 uart1_pins_sleep: uart1-pins-sleep {
712 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
717 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
720 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
724 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
729 wifi_pins_pwrseq: wifi-pins-pwrseq {
731 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
736 wifi_pins_wakeup: wifi-pins-wakeup {
738 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&pwm0_pin_default>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&scp_pins>;
756 compatible = "google,cros-ec-rpmsg";
757 mtk,rpmsg-name = "cros-ec-rpmsg";
762 domain-supply = <&mt6358_vgpu_reg>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&spi0_pins>;
772 mediatek,pad-select = <0>;
774 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
777 compatible = "google,cr50";
779 spi-max-frequency = <1000000>;
780 pinctrl-names = "default";
781 pinctrl-0 = <&h1_int_od_l>;
782 interrupt-parent = <&pio>;
783 interrupts = <153 IRQ_TYPE_EDGE_RISING>;
788 pinctrl-names = "default";
789 pinctrl-0 = <&spi1_pins>;
790 mediatek,pad-select = <0>;
793 w25q64dw: spi-flash@0 {
794 compatible = "winbond,w25q64dw", "jedec,spi-nor";
796 spi-max-frequency = <25000000>;
801 pinctrl-names = "default";
802 pinctrl-0 = <&spi2_pins>;
803 mediatek,pad-select = <0>;
807 compatible = "google,cros-ec-spi";
809 spi-max-frequency = <3000000>;
810 interrupt-parent = <&pio>;
811 interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
812 pinctrl-names = "default";
813 pinctrl-0 = <&ec_ap_int_odl>;
815 i2c_tunnel: i2c-tunnel {
816 compatible = "google,cros-ec-i2c-tunnel";
817 google,remote-bus = <1>;
818 #address-cells = <1>;
822 usbc_extcon: extcon0 {
823 compatible = "google,extcon-usbc-cros-ec";
824 google,usb-port-id = <0>;
828 compatible = "google,cros-cbas";
834 pinctrl-names = "default";
835 pinctrl-0 = <&spi3_pins>;
836 mediatek,pad-select = <0>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&spi4_pins>;
843 mediatek,pad-select = <0>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&spi5_pins>;
850 mediatek,pad-select = <0>;
857 vusb33-supply = <&mt6358_vusb_reg>;
863 polling-delay = <1000>; /* milliseconds */
864 polling-delay-passive = <0>; /* milliseconds */
865 thermal-sensors = <&tboard_thermistor1>;
869 polling-delay = <1000>; /* milliseconds */
870 polling-delay-passive = <0>; /* milliseconds */
871 thermal-sensors = <&tboard_thermistor2>;
880 pinctrl-names = "default";
881 pinctrl-0 = <&uart0_pins_default>;
886 pinctrl-names = "default", "sleep";
887 pinctrl-0 = <&uart1_pins_default>;
888 pinctrl-1 = <&uart1_pins_sleep>;
890 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
891 <&pio 121 IRQ_TYPE_EDGE_FALLING>;
893 bluetooth: bluetooth {
894 pinctrl-names = "default";
895 pinctrl-0 = <&bt_pins>;
897 compatible = "qcom,qca6174-bt";
898 enable-gpios = <&pio 120 0>;
900 firmware-name = "nvm_00440302_i2s.bin";
905 #address-cells = <1>;
907 vusb33-supply = <&mt6358_vusb_reg>;
911 compatible = "usb5e3,610";
916 #include <arm/cros-ec-keyboard.dtsi>
917 #include <arm/cros-ec-sbs.dtsi>