1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
10 #include "mt6358.dtsi"
13 model = "MediaTek MT8183 evaluation board";
14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
21 device_type = "memory";
22 reg = <0 0x40000000 0 0x80000000>;
26 stdout-path = "serial0:921600n8";
33 scp_mem_reserved: scp_mem_region {
34 compatible = "shared-dma-pool";
35 reg = <0 0x50000000 0 0x2900000>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&i2c_pins_0>;
49 clock-frequency = <100000>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&i2c_pins_1>;
56 clock-frequency = <100000>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c_pins_2>;
63 clock-frequency = <100000>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&i2c_pins_3>;
70 clock-frequency = <100000>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&i2c_pins_4>;
77 clock-frequency = <1000000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&i2c_pins_5>;
84 clock-frequency = <1000000>;
89 pinctrl-names = "default", "state_uhs";
90 pinctrl-0 = <&mmc0_pins_default>;
91 pinctrl-1 = <&mmc0_pins_uhs>;
93 max-frequency = <200000000>;
100 hs400-ds-delay = <0x12814>;
101 vmmc-supply = <&mt6358_vemc_reg>;
102 vqmmc-supply = <&mt6358_vio18_reg>;
103 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
104 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
110 pinctrl-names = "default", "state_uhs";
111 pinctrl-0 = <&mmc1_pins_default>;
112 pinctrl-1 = <&mmc1_pins_uhs>;
114 max-frequency = <200000000>;
121 vmmc-supply = <&mt6358_vmch_reg>;
122 vqmmc-supply = <&mt6358_vmc_reg>;
123 keep-power-in-suspend;
131 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
132 <PINMUX_GPIO83__FUNC_SCL0>;
133 mediatek,pull-up-adv = <3>;
134 mediatek,drive-strength-adv = <00>;
140 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
141 <PINMUX_GPIO84__FUNC_SCL1>;
142 mediatek,pull-up-adv = <3>;
143 mediatek,drive-strength-adv = <00>;
149 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
150 <PINMUX_GPIO104__FUNC_SDA2>;
151 mediatek,pull-up-adv = <3>;
152 mediatek,drive-strength-adv = <00>;
158 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
159 <PINMUX_GPIO51__FUNC_SDA3>;
160 mediatek,pull-up-adv = <3>;
161 mediatek,drive-strength-adv = <00>;
167 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
168 <PINMUX_GPIO106__FUNC_SDA4>;
169 mediatek,pull-up-adv = <3>;
170 mediatek,drive-strength-adv = <00>;
176 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
177 <PINMUX_GPIO49__FUNC_SDA5>;
178 mediatek,pull-up-adv = <3>;
179 mediatek,drive-strength-adv = <00>;
185 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
186 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
187 <PINMUX_GPIO87__FUNC_SPI0_MO>,
188 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
193 mmc0_pins_default: mmc0default {
195 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
196 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
197 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
198 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
199 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
200 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
201 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
202 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
203 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
209 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
214 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
219 mmc0_pins_uhs: mmc0 {
221 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
222 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
223 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
224 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
225 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
226 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
227 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
228 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
229 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
231 drive-strength = <MTK_DRIVE_10mA>;
232 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
236 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
237 drive-strength = <MTK_DRIVE_10mA>;
238 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
242 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
243 drive-strength = <MTK_DRIVE_10mA>;
244 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
248 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
249 drive-strength = <MTK_DRIVE_10mA>;
254 mmc1_pins_default: mmc1default {
256 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
257 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
258 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
259 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
260 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
266 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
272 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
273 <PINMUX_GPIO166__FUNC_GPIO166>;
278 mmc1_pins_uhs: mmc1 {
280 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
281 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
282 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
283 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
284 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
285 drive-strength = <MTK_DRIVE_6mA>;
287 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
291 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
292 drive-strength = <MTK_DRIVE_6mA>;
293 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
300 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
301 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
302 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
303 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
310 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
311 <PINMUX_GPIO1__FUNC_SPI2_MO>,
312 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
313 <PINMUX_GPIO94__FUNC_SPI2_MI>;
320 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
321 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
322 <PINMUX_GPIO23__FUNC_SPI3_MO>,
323 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
330 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
331 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
332 <PINMUX_GPIO19__FUNC_SPI4_MO>,
333 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
340 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
341 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
342 <PINMUX_GPIO15__FUNC_SPI5_MO>,
343 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
350 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
356 domain-supply = <&mt6358_vgpu_reg>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&spi_pins_0>;
362 mediatek,pad-select = <0>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&spi_pins_1>;
369 mediatek,pad-select = <0>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&spi_pins_2>;
376 mediatek,pad-select = <0>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&spi_pins_3>;
383 mediatek,pad-select = <0>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&spi_pins_4>;
390 mediatek,pad-select = <0>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&spi_pins_5>;
397 mediatek,pad-select = <0>;
408 pinctrl-0 = <&pwm_pins_1>;
409 pinctrl-names = "default";