1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
10 #include "mt6358.dtsi"
13 model = "MediaTek MT8183 evaluation board";
14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
21 device_type = "memory";
22 reg = <0 0x40000000 0 0x80000000>;
26 stdout-path = "serial0:921600n8";
33 scp_mem_reserved: scp_mem_region {
34 compatible = "shared-dma-pool";
35 reg = <0 0x50000000 0 0x2900000>;
46 mali-supply = <&mt6358_vgpu_reg>;
47 sram-supply = <&mt6358_vsram_gpu_reg>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&i2c_pins_0>;
54 clock-frequency = <100000>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c_pins_1>;
61 clock-frequency = <100000>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c_pins_2>;
68 clock-frequency = <100000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&i2c_pins_3>;
75 clock-frequency = <100000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&i2c_pins_4>;
82 clock-frequency = <1000000>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c_pins_5>;
89 clock-frequency = <1000000>;
94 pinctrl-names = "default", "state_uhs";
95 pinctrl-0 = <&mmc0_pins_default>;
96 pinctrl-1 = <&mmc0_pins_uhs>;
98 max-frequency = <200000000>;
105 hs400-ds-delay = <0x12814>;
106 vmmc-supply = <&mt6358_vemc_reg>;
107 vqmmc-supply = <&mt6358_vio18_reg>;
108 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
109 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
115 pinctrl-names = "default", "state_uhs";
116 pinctrl-0 = <&mmc1_pins_default>;
117 pinctrl-1 = <&mmc1_pins_uhs>;
119 max-frequency = <200000000>;
126 vmmc-supply = <&mt6358_vmch_reg>;
127 vqmmc-supply = <&mt6358_vmc_reg>;
128 keep-power-in-suspend;
136 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
137 <PINMUX_GPIO83__FUNC_SCL0>;
138 mediatek,pull-up-adv = <3>;
139 mediatek,drive-strength-adv = <00>;
145 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
146 <PINMUX_GPIO84__FUNC_SCL1>;
147 mediatek,pull-up-adv = <3>;
148 mediatek,drive-strength-adv = <00>;
154 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
155 <PINMUX_GPIO104__FUNC_SDA2>;
156 mediatek,pull-up-adv = <3>;
157 mediatek,drive-strength-adv = <00>;
163 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
164 <PINMUX_GPIO51__FUNC_SDA3>;
165 mediatek,pull-up-adv = <3>;
166 mediatek,drive-strength-adv = <00>;
172 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
173 <PINMUX_GPIO106__FUNC_SDA4>;
174 mediatek,pull-up-adv = <3>;
175 mediatek,drive-strength-adv = <00>;
181 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
182 <PINMUX_GPIO49__FUNC_SDA5>;
183 mediatek,pull-up-adv = <3>;
184 mediatek,drive-strength-adv = <00>;
190 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
191 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
192 <PINMUX_GPIO87__FUNC_SPI0_MO>,
193 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
198 mmc0_pins_default: mmc0default {
200 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
201 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
202 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
203 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
204 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
205 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
206 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
207 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
208 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
214 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
219 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
224 mmc0_pins_uhs: mmc0 {
226 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
227 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
228 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
229 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
230 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
231 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
232 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
233 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
234 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
236 drive-strength = <MTK_DRIVE_10mA>;
237 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
241 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
242 drive-strength = <MTK_DRIVE_10mA>;
243 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
247 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
248 drive-strength = <MTK_DRIVE_10mA>;
249 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
253 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
254 drive-strength = <MTK_DRIVE_10mA>;
259 mmc1_pins_default: mmc1default {
261 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
262 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
263 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
264 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
265 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
271 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
277 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
278 <PINMUX_GPIO166__FUNC_GPIO166>;
283 mmc1_pins_uhs: mmc1 {
285 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
286 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
287 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
288 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
289 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
290 drive-strength = <MTK_DRIVE_6mA>;
292 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
296 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
297 drive-strength = <MTK_DRIVE_6mA>;
298 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
305 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
306 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
307 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
308 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
315 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
316 <PINMUX_GPIO1__FUNC_SPI2_MO>,
317 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
318 <PINMUX_GPIO94__FUNC_SPI2_MI>;
325 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
326 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
327 <PINMUX_GPIO23__FUNC_SPI3_MO>,
328 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
335 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
336 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
337 <PINMUX_GPIO19__FUNC_SPI4_MO>,
338 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
345 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
346 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
347 <PINMUX_GPIO15__FUNC_SPI5_MO>,
348 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
355 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
361 domain-supply = <&mt6358_vgpu_reg>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&spi_pins_0>;
367 mediatek,pad-select = <0>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi_pins_1>;
374 mediatek,pad-select = <0>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi_pins_2>;
381 mediatek,pad-select = <0>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi_pins_3>;
388 mediatek,pad-select = <0>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi_pins_4>;
395 mediatek,pad-select = <0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&spi_pins_5>;
402 mediatek,pad-select = <0>;
413 pinctrl-0 = <&pwm_pins_1>;
414 pinctrl-names = "default";