arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Eddie Huang <eddie.huang@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/clock/mt8173-clk.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/memory/mt8173-larb-port.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/power/mt8173-power.h>
  13 #include <dt-bindings/reset/mt8173-resets.h>
  14 #include <dt-bindings/gce/mt8173-gce.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16 #include "mt8173-pinfunc.h"
  17
  18 / {
  19         compatible = "mediatek,mt8173";
  20         interrupt-parent = <&sysirq>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 ovl0 = &ovl0;
  26                 ovl1 = &ovl1;
  27                 rdma0 = &rdma0;
  28                 rdma1 = &rdma1;
  29                 rdma2 = &rdma2;
  30                 wdma0 = &wdma0;
  31                 wdma1 = &wdma1;
  32                 color0 = &color0;
  33                 color1 = &color1;
  34                 split0 = &split0;
  35                 split1 = &split1;
  36                 dpi0 = &dpi0;
  37                 dsi0 = &dsi0;
  38                 dsi1 = &dsi1;
  39                 mdp-rdma0 = &mdp_rdma0;
  40                 mdp-rdma1 = &mdp_rdma1;
  41                 mdp-rsz0 = &mdp_rsz0;
  42                 mdp-rsz1 = &mdp_rsz1;
  43                 mdp-rsz2 = &mdp_rsz2;
  44                 mdp-wdma0 = &mdp_wdma0;
  45                 mdp-wrot0 = &mdp_wrot0;
  46                 mdp-wrot1 = &mdp_wrot1;
  47                 serial0 = &uart0;
  48                 serial1 = &uart1;
  49                 serial2 = &uart2;
  50                 serial3 = &uart3;
  51         };
  52
  53         cluster0_opp: opp-table-0 {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56                 opp-507000000 {
  57                         opp-hz = /bits/ 64 <507000000>;
  58                         opp-microvolt = <859000>;
  59                 };
  60                 opp-702000000 {
  61                         opp-hz = /bits/ 64 <702000000>;
  62                         opp-microvolt = <908000>;
  63                 };
  64                 opp-1001000000 {
  65                         opp-hz = /bits/ 64 <1001000000>;
  66                         opp-microvolt = <983000>;
  67                 };
  68                 opp-1105000000 {
  69                         opp-hz = /bits/ 64 <1105000000>;
  70                         opp-microvolt = <1009000>;
  71                 };
  72                 opp-1209000000 {
  73                         opp-hz = /bits/ 64 <1209000000>;
  74                         opp-microvolt = <1034000>;
  75                 };
  76                 opp-1300000000 {
  77                         opp-hz = /bits/ 64 <1300000000>;
  78                         opp-microvolt = <1057000>;
  79                 };
  80                 opp-1508000000 {
  81                         opp-hz = /bits/ 64 <1508000000>;
  82                         opp-microvolt = <1109000>;
  83                 };
  84                 opp-1703000000 {
  85                         opp-hz = /bits/ 64 <1703000000>;
  86                         opp-microvolt = <1125000>;
  87                 };
  88         };
  89
  90         cluster1_opp: opp-table-1 {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93                 opp-507000000 {
  94                         opp-hz = /bits/ 64 <507000000>;
  95                         opp-microvolt = <828000>;
  96                 };
  97                 opp-702000000 {
  98                         opp-hz = /bits/ 64 <702000000>;
  99                         opp-microvolt = <867000>;
 100                 };
 101                 opp-1001000000 {
 102                         opp-hz = /bits/ 64 <1001000000>;
 103                         opp-microvolt = <927000>;
 104                 };
 105                 opp-1209000000 {
 106                         opp-hz = /bits/ 64 <1209000000>;
 107                         opp-microvolt = <968000>;
 108                 };
 109                 opp-1404000000 {
 110                         opp-hz = /bits/ 64 <1404000000>;
 111                         opp-microvolt = <1007000>;
 112                 };
 113                 opp-1612000000 {
 114                         opp-hz = /bits/ 64 <1612000000>;
 115                         opp-microvolt = <1049000>;
 116                 };
 117                 opp-1807000000 {
 118                         opp-hz = /bits/ 64 <1807000000>;
 119                         opp-microvolt = <1089000>;
 120                 };
 121                 opp-2106000000 {
 122                         opp-hz = /bits/ 64 <2106000000>;
 123                         opp-microvolt = <1125000>;
 124                 };
 125         };
 126
 127         cpus {
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130
 131                 cpu-map {
 132                         cluster0 {
 133                                 core0 {
 134                                         cpu = <&cpu0>;
 135                                 };
 136                                 core1 {
 137                                         cpu = <&cpu1>;
 138                                 };
 139                         };
 140
 141                         cluster1 {
 142                                 core0 {
 143                                         cpu = <&cpu2>;
 144                                 };
 145                                 core1 {
 146                                         cpu = <&cpu3>;
 147                                 };
 148                         };
 149                 };
 150
 151                 cpu0: cpu@0 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53";
 154                         reg = <0x000>;
 155                         enable-method = "psci";
 156                         cpu-idle-states = <&CPU_SLEEP_0>;
 157                         #cooling-cells = <2>;
 158                         dynamic-power-coefficient = <263>;
 159                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 160                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 161                         clock-names = "cpu", "intermediate";
 162                         operating-points-v2 = <&cluster0_opp>;
 163                         capacity-dmips-mhz = <740>;
 164                 };
 165
 166                 cpu1: cpu@1 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53";
 169                         reg = <0x001>;
 170                         enable-method = "psci";
 171                         cpu-idle-states = <&CPU_SLEEP_0>;
 172                         #cooling-cells = <2>;
 173                         dynamic-power-coefficient = <263>;
 174                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 175                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 176                         clock-names = "cpu", "intermediate";
 177                         operating-points-v2 = <&cluster0_opp>;
 178                         capacity-dmips-mhz = <740>;
 179                 };
 180
 181                 cpu2: cpu@100 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a72";
 184                         reg = <0x100>;
 185                         enable-method = "psci";
 186                         cpu-idle-states = <&CPU_SLEEP_0>;
 187                         #cooling-cells = <2>;
 188                         dynamic-power-coefficient = <530>;
 189                         clocks = <&infracfg CLK_INFRA_CA72SEL>,
 190                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 191                         clock-names = "cpu", "intermediate";
 192                         operating-points-v2 = <&cluster1_opp>;
 193                         capacity-dmips-mhz = <1024>;
 194                 };
 195
 196                 cpu3: cpu@101 {
 197                         device_type = "cpu";
 198                         compatible = "arm,cortex-a72";
 199                         reg = <0x101>;
 200                         enable-method = "psci";
 201                         cpu-idle-states = <&CPU_SLEEP_0>;
 202                         #cooling-cells = <2>;
 203                         dynamic-power-coefficient = <530>;
 204                         clocks = <&infracfg CLK_INFRA_CA72SEL>,
 205                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 206                         clock-names = "cpu", "intermediate";
 207                         operating-points-v2 = <&cluster1_opp>;
 208                         capacity-dmips-mhz = <1024>;
 209                 };
 210
 211                 idle-states {
 212                         entry-method = "psci";
 213
 214                         CPU_SLEEP_0: cpu-sleep-0 {
 215                                 compatible = "arm,idle-state";
 216                                 local-timer-stop;
 217                                 entry-latency-us = <639>;
 218                                 exit-latency-us = <680>;
 219                                 min-residency-us = <1088>;
 220                                 arm,psci-suspend-param = <0x0010000>;
 221                         };
 222                 };
 223         };
 224
 225         pmu-a53 {
 226                 compatible = "arm,cortex-a53-pmu";
 227                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 228                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 229                 interrupt-affinity = <&cpu0>, <&cpu1>;
 230         };
 231
 232         pmu-a72 {
 233                 compatible = "arm,cortex-a72-pmu";
 234                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
 235                              <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu2>, <&cpu3>;
 237         };
 238
 239         psci {
 240                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 241                 method = "smc";
 242                 cpu_suspend = <0x84000001>;
 243                 cpu_off  = <0x84000002>;
 244                 cpu_on   = <0x84000003>;
 245         };
 246
 247         clk26m: oscillator0 {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <26000000>;
 251                 clock-output-names = "clk26m";
 252         };
 253
 254         clk32k: oscillator1 {
 255                 compatible = "fixed-clock";
 256                 #clock-cells = <0>;
 257                 clock-frequency = <32000>;
 258                 clock-output-names = "clk32k";
 259         };
 260
 261         cpum_ck: oscillator2 {
 262                 compatible = "fixed-clock";
 263                 #clock-cells = <0>;
 264                 clock-frequency = <0>;
 265                 clock-output-names = "cpum_ck";
 266         };
 267
 268         thermal-zones {
 269                 cpu_thermal: cpu-thermal {
 270                         polling-delay-passive = <1000>; /* milliseconds */
 271                         polling-delay = <1000>; /* milliseconds */
 272
 273                         thermal-sensors = <&thermal>;
 274                         sustainable-power = <1500>; /* milliwatts */
 275
 276                         trips {
 277                                 threshold: trip-point0 {
 278                                         temperature = <68000>;
 279                                         hysteresis = <2000>;
 280                                         type = "passive";
 281                                 };
 282
 283                                 target: trip-point1 {
 284                                         temperature = <85000>;
 285                                         hysteresis = <2000>;
 286                                         type = "passive";
 287                                 };
 288
 289                                 cpu_crit: cpu-crit0 {
 290                                         temperature = <115000>;
 291                                         hysteresis = <2000>;
 292                                         type = "critical";
 293                                 };
 294                         };
 295
 296                         cooling-maps {
 297                                 map0 {
 298                                         trip = <&target>;
 299                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT
 300                                                           THERMAL_NO_LIMIT>,
 301                                                          <&cpu1 THERMAL_NO_LIMIT
 302                                                           THERMAL_NO_LIMIT>;
 303                                         contribution = <3072>;
 304                                 };
 305                                 map1 {
 306                                         trip = <&target>;
 307                                         cooling-device = <&cpu2 THERMAL_NO_LIMIT
 308                                                           THERMAL_NO_LIMIT>,
 309                                                          <&cpu3 THERMAL_NO_LIMIT
 310                                                           THERMAL_NO_LIMIT>;
 311                                         contribution = <1024>;
 312                                 };
 313                         };
 314                 };
 315         };
 316
 317         reserved-memory {
 318                 #address-cells = <2>;
 319                 #size-cells = <2>;
 320                 ranges;
 321                 vpu_dma_reserved: vpu-dma-mem@b7000000 {
 322                         compatible = "shared-dma-pool";
 323                         reg = <0 0xb7000000 0 0x500000>;
 324                         alignment = <0x1000>;
 325                         no-map;
 326                 };
 327         };
 328
 329         timer {
 330                 compatible = "arm,armv8-timer";
 331                 interrupt-parent = <&gic>;
 332                 interrupts = <GIC_PPI 13
 333                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 334                              <GIC_PPI 14
 335                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 336                              <GIC_PPI 11
 337                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 338                              <GIC_PPI 10
 339                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 340                 arm,no-tick-in-suspend;
 341         };
 342
 343         soc {
 344                 #address-cells = <2>;
 345                 #size-cells = <2>;
 346                 compatible = "simple-bus";
 347                 ranges;
 348
 349                 topckgen: clock-controller@10000000 {
 350                         compatible = "mediatek,mt8173-topckgen";
 351                         reg = <0 0x10000000 0 0x1000>;
 352                         #clock-cells = <1>;
 353                 };
 354
 355                 infracfg: power-controller@10001000 {
 356                         compatible = "mediatek,mt8173-infracfg", "syscon";
 357                         reg = <0 0x10001000 0 0x1000>;
 358                         #clock-cells = <1>;
 359                         #reset-cells = <1>;
 360                 };
 361
 362                 pericfg: power-controller@10003000 {
 363                         compatible = "mediatek,mt8173-pericfg", "syscon";
 364                         reg = <0 0x10003000 0 0x1000>;
 365                         #clock-cells = <1>;
 366                         #reset-cells = <1>;
 367                 };
 368
 369                 syscfg_pctl_a: syscon@10005000 {
 370                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 371                         reg = <0 0x10005000 0 0x1000>;
 372                 };
 373
 374                 pio: pinctrl@1000b000 {
 375                         compatible = "mediatek,mt8173-pinctrl";
 376                         reg = <0 0x1000b000 0 0x1000>;
 377                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 378                         gpio-controller;
 379                         #gpio-cells = <2>;
 380                         interrupt-controller;
 381                         #interrupt-cells = <2>;
 382                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 383                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 384                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 385
 386                         hdmi_pin: xxx {
 387
 388                                 /*hdmi htplg pin*/
 389                                 pins1 {
 390                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 391                                         input-enable;
 392                                         bias-pull-down;
 393                                 };
 394                         };
 395
 396                         i2c0_pins_a: i2c0 {
 397                                 pins1 {
 398                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 399                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 400                                         bias-disable;
 401                                 };
 402                         };
 403
 404                         i2c1_pins_a: i2c1 {
 405                                 pins1 {
 406                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 407                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 408                                         bias-disable;
 409                                 };
 410                         };
 411
 412                         i2c2_pins_a: i2c2 {
 413                                 pins1 {
 414                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 415                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 416                                         bias-disable;
 417                                 };
 418                         };
 419
 420                         i2c3_pins_a: i2c3 {
 421                                 pins1 {
 422                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 423                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 424                                         bias-disable;
 425                                 };
 426                         };
 427
 428                         i2c4_pins_a: i2c4 {
 429                                 pins1 {
 430                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 431                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 432                                         bias-disable;
 433                                 };
 434                         };
 435
 436                         i2c6_pins_a: i2c6 {
 437                                 pins1 {
 438                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 439                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 440                                         bias-disable;
 441                                 };
 442                         };
 443                 };
 444
 445                 scpsys: syscon@10006000 {
 446                         compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
 447                         reg = <0 0x10006000 0 0x1000>;
 448
 449                         /* System Power Manager */
 450                         spm: power-controller {
 451                                 compatible = "mediatek,mt8173-power-controller";
 452                                 #address-cells = <1>;
 453                                 #size-cells = <0>;
 454                                 #power-domain-cells = <1>;
 455
 456                                 /* power domains of the SoC */
 457                                 power-domain@MT8173_POWER_DOMAIN_VDEC {
 458                                         reg = <MT8173_POWER_DOMAIN_VDEC>;
 459                                         clocks = <&topckgen CLK_TOP_MM_SEL>;
 460                                         clock-names = "mm";
 461                                         #power-domain-cells = <0>;
 462                                 };
 463                                 power-domain@MT8173_POWER_DOMAIN_VENC {
 464                                         reg = <MT8173_POWER_DOMAIN_VENC>;
 465                                         clocks = <&topckgen CLK_TOP_MM_SEL>,
 466                                                  <&topckgen CLK_TOP_VENC_SEL>;
 467                                         clock-names = "mm", "venc";
 468                                         #power-domain-cells = <0>;
 469                                 };
 470                                 power-domain@MT8173_POWER_DOMAIN_ISP {
 471                                         reg = <MT8173_POWER_DOMAIN_ISP>;
 472                                         clocks = <&topckgen CLK_TOP_MM_SEL>;
 473                                         clock-names = "mm";
 474                                         #power-domain-cells = <0>;
 475                                 };
 476                                 power-domain@MT8173_POWER_DOMAIN_MM {
 477                                         reg = <MT8173_POWER_DOMAIN_MM>;
 478                                         clocks = <&topckgen CLK_TOP_MM_SEL>;
 479                                         clock-names = "mm";
 480                                         #power-domain-cells = <0>;
 481                                         mediatek,infracfg = <&infracfg>;
 482                                 };
 483                                 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
 484                                         reg = <MT8173_POWER_DOMAIN_VENC_LT>;
 485                                         clocks = <&topckgen CLK_TOP_MM_SEL>,
 486                                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 487                                         clock-names = "mm", "venclt";
 488                                         #power-domain-cells = <0>;
 489                                 };
 490                                 power-domain@MT8173_POWER_DOMAIN_AUDIO {
 491                                         reg = <MT8173_POWER_DOMAIN_AUDIO>;
 492                                         #power-domain-cells = <0>;
 493                                 };
 494                                 power-domain@MT8173_POWER_DOMAIN_USB {
 495                                         reg = <MT8173_POWER_DOMAIN_USB>;
 496                                         #power-domain-cells = <0>;
 497                                 };
 498                                 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
 499                                         reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
 500                                         clocks = <&clk26m>;
 501                                         clock-names = "mfg";
 502                                         #address-cells = <1>;
 503                                         #size-cells = <0>;
 504                                         #power-domain-cells = <1>;
 505
 506                                         power-domain@MT8173_POWER_DOMAIN_MFG_2D {
 507                                                 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
 508                                                 #address-cells = <1>;
 509                                                 #size-cells = <0>;
 510                                                 #power-domain-cells = <1>;
 511
 512                                                 power-domain@MT8173_POWER_DOMAIN_MFG {
 513                                                         reg = <MT8173_POWER_DOMAIN_MFG>;
 514                                                         #power-domain-cells = <0>;
 515                                                         mediatek,infracfg = <&infracfg>;
 516                                                 };
 517                                         };
 518                                 };
 519                         };
 520                 };
 521
 522                 watchdog: watchdog@10007000 {
 523                         compatible = "mediatek,mt8173-wdt",
 524                                      "mediatek,mt6589-wdt";
 525                         reg = <0 0x10007000 0 0x100>;
 526                 };
 527
 528                 timer: timer@10008000 {
 529                         compatible = "mediatek,mt8173-timer",
 530                                      "mediatek,mt6577-timer";
 531                         reg = <0 0x10008000 0 0x1000>;
 532                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 533                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 534                                  <&topckgen CLK_TOP_RTC_SEL>;
 535                 };
 536
 537                 pwrap: pwrap@1000d000 {
 538                         compatible = "mediatek,mt8173-pwrap";
 539                         reg = <0 0x1000d000 0 0x1000>;
 540                         reg-names = "pwrap";
 541                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 542                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 543                         reset-names = "pwrap";
 544                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 545                         clock-names = "spi", "wrap";
 546                 };
 547
 548                 cec: cec@10013000 {
 549                         compatible = "mediatek,mt8173-cec";
 550                         reg = <0 0x10013000 0 0xbc>;
 551                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 552                         clocks = <&infracfg CLK_INFRA_CEC>;
 553                         status = "disabled";
 554                 };
 555
 556                 vpu: vpu@10020000 {
 557                         compatible = "mediatek,mt8173-vpu";
 558                         reg = <0 0x10020000 0 0x30000>,
 559                               <0 0x10050000 0 0x100>;
 560                         reg-names = "tcm", "cfg_reg";
 561                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 563                         clock-names = "main";
 564                         memory-region = <&vpu_dma_reserved>;
 565                 };
 566
 567                 sysirq: intpol-controller@10200620 {
 568                         compatible = "mediatek,mt8173-sysirq",
 569                                      "mediatek,mt6577-sysirq";
 570                         interrupt-controller;
 571                         #interrupt-cells = <3>;
 572                         interrupt-parent = <&gic>;
 573                         reg = <0 0x10200620 0 0x20>;
 574                 };
 575
 576                 iommu: iommu@10205000 {
 577                         compatible = "mediatek,mt8173-m4u";
 578                         reg = <0 0x10205000 0 0x1000>;
 579                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 580                         clocks = <&infracfg CLK_INFRA_M4U>;
 581                         clock-names = "bclk";
 582                         mediatek,infracfg = <&infracfg>;
 583                         mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
 584                                          <&larb3>, <&larb4>, <&larb5>;
 585                         #iommu-cells = <1>;
 586                 };
 587
 588                 efuse: efuse@10206000 {
 589                         compatible = "mediatek,mt8173-efuse";
 590                         reg = <0 0x10206000 0 0x1000>;
 591                         #address-cells = <1>;
 592                         #size-cells = <1>;
 593
 594                         socinfo-data1@40 {
 595                                 reg = <0x040 0x4>;
 596                         };
 597
 598                         socinfo-data2@44 {
 599                                 reg = <0x044 0x4>;
 600                         };
 601
 602                         thermal_calibration: calib@528 {
 603                                 reg = <0x528 0xc>;
 604                         };
 605                 };
 606
 607                 apmixedsys: clock-controller@10209000 {
 608                         compatible = "mediatek,mt8173-apmixedsys";
 609                         reg = <0 0x10209000 0 0x1000>;
 610                         #clock-cells = <1>;
 611                 };
 612
 613                 hdmi_phy: hdmi-phy@10209100 {
 614                         compatible = "mediatek,mt8173-hdmi-phy";
 615                         reg = <0 0x10209100 0 0x24>;
 616                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 617                         clock-names = "pll_ref";
 618                         clock-output-names = "hdmitx_dig_cts";
 619                         mediatek,ibias = <0xa>;
 620                         mediatek,ibias_up = <0x1c>;
 621                         #clock-cells = <0>;
 622                         #phy-cells = <0>;
 623                         status = "disabled";
 624                 };
 625
 626                 gce: mailbox@10212000 {
 627                         compatible = "mediatek,mt8173-gce";
 628                         reg = <0 0x10212000 0 0x1000>;
 629                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 630                         clocks = <&infracfg CLK_INFRA_GCE>;
 631                         clock-names = "gce";
 632                         #mbox-cells = <2>;
 633                 };
 634
 635                 mipi_tx0: dsi-phy@10215000 {
 636                         compatible = "mediatek,mt8173-mipi-tx";
 637                         reg = <0 0x10215000 0 0x1000>;
 638                         clocks = <&clk26m>;
 639                         clock-output-names = "mipi_tx0_pll";
 640                         #clock-cells = <0>;
 641                         #phy-cells = <0>;
 642                         status = "disabled";
 643                 };
 644
 645                 mipi_tx1: dsi-phy@10216000 {
 646                         compatible = "mediatek,mt8173-mipi-tx";
 647                         reg = <0 0x10216000 0 0x1000>;
 648                         clocks = <&clk26m>;
 649                         clock-output-names = "mipi_tx1_pll";
 650                         #clock-cells = <0>;
 651                         #phy-cells = <0>;
 652                         status = "disabled";
 653                 };
 654
 655                 gic: interrupt-controller@10221000 {
 656                         compatible = "arm,gic-400";
 657                         #interrupt-cells = <3>;
 658                         interrupt-parent = <&gic>;
 659                         interrupt-controller;
 660                         reg = <0 0x10221000 0 0x1000>,
 661                               <0 0x10222000 0 0x2000>,
 662                               <0 0x10224000 0 0x2000>,
 663                               <0 0x10226000 0 0x2000>;
 664                         interrupts = <GIC_PPI 9
 665                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 666                 };
 667
 668                 auxadc: auxadc@11001000 {
 669                         compatible = "mediatek,mt8173-auxadc";
 670                         reg = <0 0x11001000 0 0x1000>;
 671                         clocks = <&pericfg CLK_PERI_AUXADC>;
 672                         clock-names = "main";
 673                         #io-channel-cells = <1>;
 674                 };
 675
 676                 uart0: serial@11002000 {
 677                         compatible = "mediatek,mt8173-uart",
 678                                      "mediatek,mt6577-uart";
 679                         reg = <0 0x11002000 0 0x400>;
 680                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 681                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 682                         clock-names = "baud", "bus";
 683                         status = "disabled";
 684                 };
 685
 686                 uart1: serial@11003000 {
 687                         compatible = "mediatek,mt8173-uart",
 688                                      "mediatek,mt6577-uart";
 689                         reg = <0 0x11003000 0 0x400>;
 690                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 691                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 692                         clock-names = "baud", "bus";
 693                         status = "disabled";
 694                 };
 695
 696                 uart2: serial@11004000 {
 697                         compatible = "mediatek,mt8173-uart",
 698                                      "mediatek,mt6577-uart";
 699                         reg = <0 0x11004000 0 0x400>;
 700                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 701                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 702                         clock-names = "baud", "bus";
 703                         status = "disabled";
 704                 };
 705
 706                 uart3: serial@11005000 {
 707                         compatible = "mediatek,mt8173-uart",
 708                                      "mediatek,mt6577-uart";
 709                         reg = <0 0x11005000 0 0x400>;
 710                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 711                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 712                         clock-names = "baud", "bus";
 713                         status = "disabled";
 714                 };
 715
 716                 i2c0: i2c@11007000 {
 717                         compatible = "mediatek,mt8173-i2c";
 718                         reg = <0 0x11007000 0 0x70>,
 719                               <0 0x11000100 0 0x80>;
 720                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 721                         clock-div = <16>;
 722                         clocks = <&pericfg CLK_PERI_I2C0>,
 723                                  <&pericfg CLK_PERI_AP_DMA>;
 724                         clock-names = "main", "dma";
 725                         pinctrl-names = "default";
 726                         pinctrl-0 = <&i2c0_pins_a>;
 727                         #address-cells = <1>;
 728                         #size-cells = <0>;
 729                         status = "disabled";
 730                 };
 731
 732                 i2c1: i2c@11008000 {
 733                         compatible = "mediatek,mt8173-i2c";
 734                         reg = <0 0x11008000 0 0x70>,
 735                               <0 0x11000180 0 0x80>;
 736                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 737                         clock-div = <16>;
 738                         clocks = <&pericfg CLK_PERI_I2C1>,
 739                                  <&pericfg CLK_PERI_AP_DMA>;
 740                         clock-names = "main", "dma";
 741                         pinctrl-names = "default";
 742                         pinctrl-0 = <&i2c1_pins_a>;
 743                         #address-cells = <1>;
 744                         #size-cells = <0>;
 745                         status = "disabled";
 746                 };
 747
 748                 i2c2: i2c@11009000 {
 749                         compatible = "mediatek,mt8173-i2c";
 750                         reg = <0 0x11009000 0 0x70>,
 751                               <0 0x11000200 0 0x80>;
 752                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 753                         clock-div = <16>;
 754                         clocks = <&pericfg CLK_PERI_I2C2>,
 755                                  <&pericfg CLK_PERI_AP_DMA>;
 756                         clock-names = "main", "dma";
 757                         pinctrl-names = "default";
 758                         pinctrl-0 = <&i2c2_pins_a>;
 759                         #address-cells = <1>;
 760                         #size-cells = <0>;
 761                         status = "disabled";
 762                 };
 763
 764                 spi: spi@1100a000 {
 765                         compatible = "mediatek,mt8173-spi";
 766                         #address-cells = <1>;
 767                         #size-cells = <0>;
 768                         reg = <0 0x1100a000 0 0x1000>;
 769                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 770                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 771                                  <&topckgen CLK_TOP_SPI_SEL>,
 772                                  <&pericfg CLK_PERI_SPI0>;
 773                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 774                         status = "disabled";
 775                 };
 776
 777                 thermal: thermal@1100b000 {
 778                         #thermal-sensor-cells = <0>;
 779                         compatible = "mediatek,mt8173-thermal";
 780                         reg = <0 0x1100b000 0 0x1000>;
 781                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 782                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 783                         clock-names = "therm", "auxadc";
 784                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 785                         mediatek,auxadc = <&auxadc>;
 786                         mediatek,apmixedsys = <&apmixedsys>;
 787                         nvmem-cells = <&thermal_calibration>;
 788                         nvmem-cell-names = "calibration-data";
 789                 };
 790
 791                 nor_flash: spi@1100d000 {
 792                         compatible = "mediatek,mt8173-nor";
 793                         reg = <0 0x1100d000 0 0xe0>;
 794                         assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
 795                         assigned-clock-parents = <&clk26m>;
 796                         clocks = <&pericfg CLK_PERI_SPI>,
 797                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
 798                                  <&pericfg CLK_PERI_NFI>;
 799                         clock-names = "spi", "sf", "axi";
 800                         #address-cells = <1>;
 801                         #size-cells = <0>;
 802                         status = "disabled";
 803                 };
 804
 805                 i2c3: i2c@11010000 {
 806                         compatible = "mediatek,mt8173-i2c";
 807                         reg = <0 0x11010000 0 0x70>,
 808                               <0 0x11000280 0 0x80>;
 809                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 810                         clock-div = <16>;
 811                         clocks = <&pericfg CLK_PERI_I2C3>,
 812                                  <&pericfg CLK_PERI_AP_DMA>;
 813                         clock-names = "main", "dma";
 814                         pinctrl-names = "default";
 815                         pinctrl-0 = <&i2c3_pins_a>;
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818                         status = "disabled";
 819                 };
 820
 821                 i2c4: i2c@11011000 {
 822                         compatible = "mediatek,mt8173-i2c";
 823                         reg = <0 0x11011000 0 0x70>,
 824                               <0 0x11000300 0 0x80>;
 825                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 826                         clock-div = <16>;
 827                         clocks = <&pericfg CLK_PERI_I2C4>,
 828                                  <&pericfg CLK_PERI_AP_DMA>;
 829                         clock-names = "main", "dma";
 830                         pinctrl-names = "default";
 831                         pinctrl-0 = <&i2c4_pins_a>;
 832                         #address-cells = <1>;
 833                         #size-cells = <0>;
 834                         status = "disabled";
 835                 };
 836
 837                 hdmiddc0: i2c@11012000 {
 838                         compatible = "mediatek,mt8173-hdmi-ddc";
 839                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 840                         reg = <0 0x11012000 0 0x1C>;
 841                         clocks = <&pericfg CLK_PERI_I2C5>;
 842                         clock-names = "ddc-i2c";
 843                 };
 844
 845                 i2c6: i2c@11013000 {
 846                         compatible = "mediatek,mt8173-i2c";
 847                         reg = <0 0x11013000 0 0x70>,
 848                               <0 0x11000080 0 0x80>;
 849                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 850                         clock-div = <16>;
 851                         clocks = <&pericfg CLK_PERI_I2C6>,
 852                                  <&pericfg CLK_PERI_AP_DMA>;
 853                         clock-names = "main", "dma";
 854                         pinctrl-names = "default";
 855                         pinctrl-0 = <&i2c6_pins_a>;
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         status = "disabled";
 859                 };
 860
 861                 afe: audio-controller@11220000  {
 862                         compatible = "mediatek,mt8173-afe-pcm";
 863                         reg = <0 0x11220000 0 0x1000>;
 864                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 865                         power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
 866                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 867                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 868                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 869                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 870                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 871                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 872                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 873                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 874                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 875                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 876                         clock-names = "infra_sys_audio_clk",
 877                                       "top_pdn_audio",
 878                                       "top_pdn_aud_intbus",
 879                                       "bck0",
 880                                       "bck1",
 881                                       "i2s0_m",
 882                                       "i2s1_m",
 883                                       "i2s2_m",
 884                                       "i2s3_m",
 885                                       "i2s3_b";
 886                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 887                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 888                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 889                                                  <&topckgen CLK_TOP_APLL2>;
 890                 };
 891
 892                 mmc0: mmc@11230000 {
 893                         compatible = "mediatek,mt8173-mmc";
 894                         reg = <0 0x11230000 0 0x1000>;
 895                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 896                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 897                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 898                         clock-names = "source", "hclk";
 899                         status = "disabled";
 900                 };
 901
 902                 mmc1: mmc@11240000 {
 903                         compatible = "mediatek,mt8173-mmc";
 904                         reg = <0 0x11240000 0 0x1000>;
 905                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 906                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 907                                  <&topckgen CLK_TOP_AXI_SEL>;
 908                         clock-names = "source", "hclk";
 909                         status = "disabled";
 910                 };
 911
 912                 mmc2: mmc@11250000 {
 913                         compatible = "mediatek,mt8173-mmc";
 914                         reg = <0 0x11250000 0 0x1000>;
 915                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 916                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 917                                  <&topckgen CLK_TOP_AXI_SEL>;
 918                         clock-names = "source", "hclk";
 919                         status = "disabled";
 920                 };
 921
 922                 mmc3: mmc@11260000 {
 923                         compatible = "mediatek,mt8173-mmc";
 924                         reg = <0 0x11260000 0 0x1000>;
 925                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 926                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 927                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 928                         clock-names = "source", "hclk";
 929                         status = "disabled";
 930                 };
 931
 932                 ssusb: usb@11271000 {
 933                         compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
 934                         reg = <0 0x11271000 0 0x3000>,
 935                               <0 0x11280700 0 0x0100>;
 936                         reg-names = "mac", "ippc";
 937                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 938                         phys = <&u2port0 PHY_TYPE_USB2>,
 939                                <&u3port0 PHY_TYPE_USB3>,
 940                                <&u2port1 PHY_TYPE_USB2>;
 941                         power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
 942                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 943                         clock-names = "sys_ck", "ref_ck";
 944                         mediatek,syscon-wakeup = <&pericfg 0x400 1>;
 945                         #address-cells = <2>;
 946                         #size-cells = <2>;
 947                         ranges;
 948                         status = "disabled";
 949
 950                         usb_host: usb@11270000 {
 951                                 compatible = "mediatek,mt8173-xhci",
 952                                              "mediatek,mtk-xhci";
 953                                 reg = <0 0x11270000 0 0x1000>;
 954                                 reg-names = "mac";
 955                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 956                                 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
 957                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 958                                 clock-names = "sys_ck", "ref_ck";
 959                                 status = "disabled";
 960                         };
 961                 };
 962
 963                 u3phy: t-phy@11290000 {
 964                         compatible = "mediatek,mt8173-u3phy";
 965                         reg = <0 0x11290000 0 0x800>;
 966                         #address-cells = <2>;
 967                         #size-cells = <2>;
 968                         ranges;
 969                         status = "okay";
 970
 971                         u2port0: usb-phy@11290800 {
 972                                 reg = <0 0x11290800 0 0x100>;
 973                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 974                                 clock-names = "ref";
 975                                 #phy-cells = <1>;
 976                                 status = "okay";
 977                         };
 978
 979                         u3port0: usb-phy@11290900 {
 980                                 reg = <0 0x11290900 0 0x700>;
 981                                 clocks = <&clk26m>;
 982                                 clock-names = "ref";
 983                                 #phy-cells = <1>;
 984                                 status = "okay";
 985                         };
 986
 987                         u2port1: usb-phy@11291000 {
 988                                 reg = <0 0x11291000 0 0x100>;
 989                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 990                                 clock-names = "ref";
 991                                 #phy-cells = <1>;
 992                                 status = "okay";
 993                         };
 994                 };
 995
 996                 mmsys: syscon@14000000 {
 997                         compatible = "mediatek,mt8173-mmsys", "syscon";
 998                         reg = <0 0x14000000 0 0x1000>;
 999                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1000                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1001                         assigned-clock-rates = <400000000>;
1002                         #clock-cells = <1>;
1003                         #reset-cells = <1>;
1004                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1005                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1006                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1007                 };
1008
1009                 mdp_rdma0: rdma@14001000 {
1010                         compatible = "mediatek,mt8173-mdp-rdma",
1011                                      "mediatek,mt8173-mdp";
1012                         reg = <0 0x14001000 0 0x1000>;
1013                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1014                                  <&mmsys CLK_MM_MUTEX_32K>;
1015                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1016                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1017                         mediatek,vpu = <&vpu>;
1018                 };
1019
1020                 mdp_rdma1: rdma@14002000 {
1021                         compatible = "mediatek,mt8173-mdp-rdma";
1022                         reg = <0 0x14002000 0 0x1000>;
1023                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1024                                  <&mmsys CLK_MM_MUTEX_32K>;
1025                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1026                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1027                 };
1028
1029                 mdp_rsz0: rsz@14003000 {
1030                         compatible = "mediatek,mt8173-mdp-rsz";
1031                         reg = <0 0x14003000 0 0x1000>;
1032                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1033                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1034                 };
1035
1036                 mdp_rsz1: rsz@14004000 {
1037                         compatible = "mediatek,mt8173-mdp-rsz";
1038                         reg = <0 0x14004000 0 0x1000>;
1039                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1040                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1041                 };
1042
1043                 mdp_rsz2: rsz@14005000 {
1044                         compatible = "mediatek,mt8173-mdp-rsz";
1045                         reg = <0 0x14005000 0 0x1000>;
1046                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1047                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1048                 };
1049
1050                 mdp_wdma0: wdma@14006000 {
1051                         compatible = "mediatek,mt8173-mdp-wdma";
1052                         reg = <0 0x14006000 0 0x1000>;
1053                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
1054                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1055                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
1056                 };
1057
1058                 mdp_wrot0: wrot@14007000 {
1059                         compatible = "mediatek,mt8173-mdp-wrot";
1060                         reg = <0 0x14007000 0 0x1000>;
1061                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
1062                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1063                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
1064                 };
1065
1066                 mdp_wrot1: wrot@14008000 {
1067                         compatible = "mediatek,mt8173-mdp-wrot";
1068                         reg = <0 0x14008000 0 0x1000>;
1069                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
1070                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1071                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
1072                 };
1073
1074                 ovl0: ovl@1400c000 {
1075                         compatible = "mediatek,mt8173-disp-ovl";
1076                         reg = <0 0x1400c000 0 0x1000>;
1077                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1078                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1079                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1080                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
1081                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1082                 };
1083
1084                 ovl1: ovl@1400d000 {
1085                         compatible = "mediatek,mt8173-disp-ovl";
1086                         reg = <0 0x1400d000 0 0x1000>;
1087                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1088                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1089                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
1090                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
1091                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1092                 };
1093
1094                 rdma0: rdma@1400e000 {
1095                         compatible = "mediatek,mt8173-disp-rdma";
1096                         reg = <0 0x1400e000 0 0x1000>;
1097                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1098                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1099                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1100                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1101                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1102                 };
1103
1104                 rdma1: rdma@1400f000 {
1105                         compatible = "mediatek,mt8173-disp-rdma";
1106                         reg = <0 0x1400f000 0 0x1000>;
1107                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1108                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1109                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1110                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1111                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1112                 };
1113
1114                 rdma2: rdma@14010000 {
1115                         compatible = "mediatek,mt8173-disp-rdma";
1116                         reg = <0 0x14010000 0 0x1000>;
1117                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1118                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1119                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1120                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1121                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1122                 };
1123
1124                 wdma0: wdma@14011000 {
1125                         compatible = "mediatek,mt8173-disp-wdma";
1126                         reg = <0 0x14011000 0 0x1000>;
1127                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1128                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1129                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1130                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1131                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1132                 };
1133
1134                 wdma1: wdma@14012000 {
1135                         compatible = "mediatek,mt8173-disp-wdma";
1136                         reg = <0 0x14012000 0 0x1000>;
1137                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1138                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1139                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1140                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1141                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1142                 };
1143
1144                 color0: color@14013000 {
1145                         compatible = "mediatek,mt8173-disp-color";
1146                         reg = <0 0x14013000 0 0x1000>;
1147                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1148                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1149                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1150                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1151                 };
1152
1153                 color1: color@14014000 {
1154                         compatible = "mediatek,mt8173-disp-color";
1155                         reg = <0 0x14014000 0 0x1000>;
1156                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1157                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1158                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1159                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1160                 };
1161
1162                 aal@14015000 {
1163                         compatible = "mediatek,mt8173-disp-aal";
1164                         reg = <0 0x14015000 0 0x1000>;
1165                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1166                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1167                         clocks = <&mmsys CLK_MM_DISP_AAL>;
1168                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1169                 };
1170
1171                 gamma@14016000 {
1172                         compatible = "mediatek,mt8173-disp-gamma";
1173                         reg = <0 0x14016000 0 0x1000>;
1174                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1175                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1176                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1177                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1178                 };
1179
1180                 merge@14017000 {
1181                         compatible = "mediatek,mt8173-disp-merge";
1182                         reg = <0 0x14017000 0 0x1000>;
1183                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1184                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
1185                 };
1186
1187                 split0: split@14018000 {
1188                         compatible = "mediatek,mt8173-disp-split";
1189                         reg = <0 0x14018000 0 0x1000>;
1190                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1191                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1192                 };
1193
1194                 split1: split@14019000 {
1195                         compatible = "mediatek,mt8173-disp-split";
1196                         reg = <0 0x14019000 0 0x1000>;
1197                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1198                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1199                 };
1200
1201                 ufoe@1401a000 {
1202                         compatible = "mediatek,mt8173-disp-ufoe";
1203                         reg = <0 0x1401a000 0 0x1000>;
1204                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1205                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1206                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1207                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1208                 };
1209
1210                 dsi0: dsi@1401b000 {
1211                         compatible = "mediatek,mt8173-dsi";
1212                         reg = <0 0x1401b000 0 0x1000>;
1213                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1214                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1215                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1216                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1217                                  <&mipi_tx0>;
1218                         clock-names = "engine", "digital", "hs";
1219                         resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1220                         phys = <&mipi_tx0>;
1221                         phy-names = "dphy";
1222                         status = "disabled";
1223                 };
1224
1225                 dsi1: dsi@1401c000 {
1226                         compatible = "mediatek,mt8173-dsi";
1227                         reg = <0 0x1401c000 0 0x1000>;
1228                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1229                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1230                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1231                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1232                                  <&mipi_tx1>;
1233                         clock-names = "engine", "digital", "hs";
1234                         phys = <&mipi_tx1>;
1235                         phy-names = "dphy";
1236                         status = "disabled";
1237                 };
1238
1239                 dpi0: dpi@1401d000 {
1240                         compatible = "mediatek,mt8173-dpi";
1241                         reg = <0 0x1401d000 0 0x1000>;
1242                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1243                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1244                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1245                                  <&mmsys CLK_MM_DPI_ENGINE>,
1246                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1247                         clock-names = "pixel", "engine", "pll";
1248                         status = "disabled";
1249
1250                         port {
1251                                 dpi0_out: endpoint {
1252                                         remote-endpoint = <&hdmi0_in>;
1253                                 };
1254                         };
1255                 };
1256
1257                 pwm0: pwm@1401e000 {
1258                         compatible = "mediatek,mt8173-disp-pwm",
1259                                      "mediatek,mt6595-disp-pwm";
1260                         reg = <0 0x1401e000 0 0x1000>;
1261                         #pwm-cells = <2>;
1262                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1263                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1264                         clock-names = "main", "mm";
1265                         status = "disabled";
1266                 };
1267
1268                 pwm1: pwm@1401f000 {
1269                         compatible = "mediatek,mt8173-disp-pwm",
1270                                      "mediatek,mt6595-disp-pwm";
1271                         reg = <0 0x1401f000 0 0x1000>;
1272                         #pwm-cells = <2>;
1273                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1274                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1275                         clock-names = "main", "mm";
1276                         status = "disabled";
1277                 };
1278
1279                 mutex: mutex@14020000 {
1280                         compatible = "mediatek,mt8173-disp-mutex";
1281                         reg = <0 0x14020000 0 0x1000>;
1282                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1283                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1284                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1285                         mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1286                         mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1287                                               <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
1288                 };
1289
1290                 larb0: larb@14021000 {
1291                         compatible = "mediatek,mt8173-smi-larb";
1292                         reg = <0 0x14021000 0 0x1000>;
1293                         mediatek,smi = <&smi_common>;
1294                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1295                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1296                                  <&mmsys CLK_MM_SMI_LARB0>;
1297                         clock-names = "apb", "smi";
1298                 };
1299
1300                 smi_common: smi@14022000 {
1301                         compatible = "mediatek,mt8173-smi-common";
1302                         reg = <0 0x14022000 0 0x1000>;
1303                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1304                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1305                                  <&mmsys CLK_MM_SMI_COMMON>;
1306                         clock-names = "apb", "smi";
1307                 };
1308
1309                 od@14023000 {
1310                         compatible = "mediatek,mt8173-disp-od";
1311                         reg = <0 0x14023000 0 0x1000>;
1312                         clocks = <&mmsys CLK_MM_DISP_OD>;
1313                         mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1314                 };
1315
1316                 hdmi0: hdmi@14025000 {
1317                         compatible = "mediatek,mt8173-hdmi";
1318                         reg = <0 0x14025000 0 0x400>;
1319                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1320                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1321                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1322                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1323                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1324                         clock-names = "pixel", "pll", "bclk", "spdif";
1325                         pinctrl-names = "default";
1326                         pinctrl-0 = <&hdmi_pin>;
1327                         phys = <&hdmi_phy>;
1328                         phy-names = "hdmi";
1329                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1330                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1331                         assigned-clock-parents = <&hdmi_phy>;
1332                         status = "disabled";
1333
1334                         ports {
1335                                 #address-cells = <1>;
1336                                 #size-cells = <0>;
1337
1338                                 port@0 {
1339                                         reg = <0>;
1340
1341                                         hdmi0_in: endpoint {
1342                                                 remote-endpoint = <&dpi0_out>;
1343                                         };
1344                                 };
1345                         };
1346                 };
1347
1348                 larb4: larb@14027000 {
1349                         compatible = "mediatek,mt8173-smi-larb";
1350                         reg = <0 0x14027000 0 0x1000>;
1351                         mediatek,smi = <&smi_common>;
1352                         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1353                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1354                                  <&mmsys CLK_MM_SMI_LARB4>;
1355                         clock-names = "apb", "smi";
1356                 };
1357
1358                 imgsys: clock-controller@15000000 {
1359                         compatible = "mediatek,mt8173-imgsys", "syscon";
1360                         reg = <0 0x15000000 0 0x1000>;
1361                         #clock-cells = <1>;
1362                 };
1363
1364                 larb2: larb@15001000 {
1365                         compatible = "mediatek,mt8173-smi-larb";
1366                         reg = <0 0x15001000 0 0x1000>;
1367                         mediatek,smi = <&smi_common>;
1368                         power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1369                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1370                                  <&imgsys CLK_IMG_LARB2_SMI>;
1371                         clock-names = "apb", "smi";
1372                 };
1373
1374                 vdecsys: clock-controller@16000000 {
1375                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1376                         reg = <0 0x16000000 0 0x1000>;
1377                         #clock-cells = <1>;
1378                 };
1379
1380                 vcodec_dec: vcodec@16020000 {
1381                         compatible = "mediatek,mt8173-vcodec-dec";
1382                         reg = <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1383                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1384                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1385                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1386                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1387                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1388                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1389                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1390                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1391                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1392                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1393                         reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
1394                                     "hwd", "hwq", "hwb", "hwg";
1395                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1396                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1397                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1398                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1399                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1400                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1401                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1402                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1403                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1404                         mediatek,vpu = <&vpu>;
1405                         mediatek,vdecsys = <&vdecsys>;
1406                         power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1407                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1408                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1409                                  <&topckgen CLK_TOP_CCI400_SEL>,
1410                                  <&topckgen CLK_TOP_VDEC_SEL>,
1411                                  <&topckgen CLK_TOP_VCODECPLL>,
1412                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1413                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1414                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1415                         clock-names = "vcodecpll",
1416                                       "univpll_d2",
1417                                       "clk_cci400_sel",
1418                                       "vdec_sel",
1419                                       "vdecpll",
1420                                       "vencpll",
1421                                       "venc_lt_sel",
1422                                       "vdec_bus_clk_src";
1423                         assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1424                                           <&topckgen CLK_TOP_CCI400_SEL>,
1425                                           <&topckgen CLK_TOP_VDEC_SEL>,
1426                                           <&apmixedsys CLK_APMIXED_VCODECPLL>,
1427                                           <&apmixedsys CLK_APMIXED_VENCPLL>;
1428                         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1429                                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1430                                                  <&topckgen CLK_TOP_VCODECPLL>;
1431                         assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1432                 };
1433
1434                 larb1: larb@16010000 {
1435                         compatible = "mediatek,mt8173-smi-larb";
1436                         reg = <0 0x16010000 0 0x1000>;
1437                         mediatek,smi = <&smi_common>;
1438                         power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1439                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1440                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1441                         clock-names = "apb", "smi";
1442                 };
1443
1444                 vencsys: clock-controller@18000000 {
1445                         compatible = "mediatek,mt8173-vencsys", "syscon";
1446                         reg = <0 0x18000000 0 0x1000>;
1447                         #clock-cells = <1>;
1448                 };
1449
1450                 larb3: larb@18001000 {
1451                         compatible = "mediatek,mt8173-smi-larb";
1452                         reg = <0 0x18001000 0 0x1000>;
1453                         mediatek,smi = <&smi_common>;
1454                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1455                         clocks = <&vencsys CLK_VENC_CKE1>,
1456                                  <&vencsys CLK_VENC_CKE0>;
1457                         clock-names = "apb", "smi";
1458                 };
1459
1460                 vcodec_enc_avc: vcodec@18002000 {
1461                         compatible = "mediatek,mt8173-vcodec-enc";
1462                         reg = <0 0x18002000 0 0x1000>;  /* VENC_SYS */
1463                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1464                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1465                                  <&iommu M4U_PORT_VENC_REC>,
1466                                  <&iommu M4U_PORT_VENC_BSDMA>,
1467                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1468                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1469                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1470                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1471                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1472                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1473                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1474                                  <&iommu M4U_PORT_VENC_NBM_WDMA>;
1475                         mediatek,vpu = <&vpu>;
1476                         clocks = <&topckgen CLK_TOP_VENC_SEL>;
1477                         clock-names = "venc_sel";
1478                         assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1479                         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1480                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1481                 };
1482
1483                 jpegdec: jpegdec@18004000 {
1484                         compatible = "mediatek,mt8173-jpgdec";
1485                         reg = <0 0x18004000 0 0x1000>;
1486                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1487                         clocks = <&vencsys CLK_VENC_CKE0>,
1488                                  <&vencsys CLK_VENC_CKE3>;
1489                         clock-names = "jpgdec-smi",
1490                                       "jpgdec";
1491                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1492                         iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1493                                  <&iommu M4U_PORT_JPGDEC_BSDMA>;
1494                 };
1495
1496                 vencltsys: clock-controller@19000000 {
1497                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1498                         reg = <0 0x19000000 0 0x1000>;
1499                         #clock-cells = <1>;
1500                 };
1501
1502                 larb5: larb@19001000 {
1503                         compatible = "mediatek,mt8173-smi-larb";
1504                         reg = <0 0x19001000 0 0x1000>;
1505                         mediatek,smi = <&smi_common>;
1506                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1507                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1508                                  <&vencltsys CLK_VENCLT_CKE0>;
1509                         clock-names = "apb", "smi";
1510                 };
1511
1512                 vcodec_enc_vp8: vcodec@19002000 {
1513                         compatible = "mediatek,mt8173-vcodec-enc-vp8";
1514                         reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1515                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1516                         iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
1517                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1518                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1519                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1520                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1521                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1522                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1523                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1524                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1525                         mediatek,vpu = <&vpu>;
1526                         clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1527                         clock-names = "venc_lt_sel";
1528                         assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1529                         assigned-clock-parents =
1530                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1531                         power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1532                 };
1533         };
1534 };