arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include <dt-bindings/gce/mt8173-gce.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23 #include "mt8173-pinfunc.h"
  24
  25 / {
  26         compatible = "mediatek,mt8173";
  27         interrupt-parent = <&sysirq>;
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         aliases {
  32                 ovl0 = &ovl0;
  33                 ovl1 = &ovl1;
  34                 rdma0 = &rdma0;
  35                 rdma1 = &rdma1;
  36                 rdma2 = &rdma2;
  37                 wdma0 = &wdma0;
  38                 wdma1 = &wdma1;
  39                 color0 = &color0;
  40                 color1 = &color1;
  41                 split0 = &split0;
  42                 split1 = &split1;
  43                 dpi0 = &dpi0;
  44                 dsi0 = &dsi0;
  45                 dsi1 = &dsi1;
  46                 mdp-rdma0 = &mdp_rdma0;
  47                 mdp-rdma1 = &mdp_rdma1;
  48                 mdp-rsz0 = &mdp_rsz0;
  49                 mdp-rsz1 = &mdp_rsz1;
  50                 mdp-rsz2 = &mdp_rsz2;
  51                 mdp-wdma0 = &mdp_wdma0;
  52                 mdp-wrot0 = &mdp_wrot0;
  53                 mdp-wrot1 = &mdp_wrot1;
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57                 serial3 = &uart3;
  58         };
  59
  60         cluster0_opp: opp_table0 {
  61                 compatible = "operating-points-v2";
  62                 opp-shared;
  63                 opp-507000000 {
  64                         opp-hz = /bits/ 64 <507000000>;
  65                         opp-microvolt = <859000>;
  66                 };
  67                 opp-702000000 {
  68                         opp-hz = /bits/ 64 <702000000>;
  69                         opp-microvolt = <908000>;
  70                 };
  71                 opp-1001000000 {
  72                         opp-hz = /bits/ 64 <1001000000>;
  73                         opp-microvolt = <983000>;
  74                 };
  75                 opp-1105000000 {
  76                         opp-hz = /bits/ 64 <1105000000>;
  77                         opp-microvolt = <1009000>;
  78                 };
  79                 opp-1209000000 {
  80                         opp-hz = /bits/ 64 <1209000000>;
  81                         opp-microvolt = <1034000>;
  82                 };
  83                 opp-1300000000 {
  84                         opp-hz = /bits/ 64 <1300000000>;
  85                         opp-microvolt = <1057000>;
  86                 };
  87                 opp-1508000000 {
  88                         opp-hz = /bits/ 64 <1508000000>;
  89                         opp-microvolt = <1109000>;
  90                 };
  91                 opp-1703000000 {
  92                         opp-hz = /bits/ 64 <1703000000>;
  93                         opp-microvolt = <1125000>;
  94                 };
  95         };
  96
  97         cluster1_opp: opp_table1 {
  98                 compatible = "operating-points-v2";
  99                 opp-shared;
 100                 opp-507000000 {
 101                         opp-hz = /bits/ 64 <507000000>;
 102                         opp-microvolt = <828000>;
 103                 };
 104                 opp-702000000 {
 105                         opp-hz = /bits/ 64 <702000000>;
 106                         opp-microvolt = <867000>;
 107                 };
 108                 opp-1001000000 {
 109                         opp-hz = /bits/ 64 <1001000000>;
 110                         opp-microvolt = <927000>;
 111                 };
 112                 opp-1209000000 {
 113                         opp-hz = /bits/ 64 <1209000000>;
 114                         opp-microvolt = <968000>;
 115                 };
 116                 opp-1404000000 {
 117                         opp-hz = /bits/ 64 <1404000000>;
 118                         opp-microvolt = <1007000>;
 119                 };
 120                 opp-1612000000 {
 121                         opp-hz = /bits/ 64 <1612000000>;
 122                         opp-microvolt = <1049000>;
 123                 };
 124                 opp-1807000000 {
 125                         opp-hz = /bits/ 64 <1807000000>;
 126                         opp-microvolt = <1089000>;
 127                 };
 128                 opp-2106000000 {
 129                         opp-hz = /bits/ 64 <2106000000>;
 130                         opp-microvolt = <1125000>;
 131                 };
 132         };
 133
 134         cpus {
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137
 138                 cpu-map {
 139                         cluster0 {
 140                                 core0 {
 141                                         cpu = <&cpu0>;
 142                                 };
 143                                 core1 {
 144                                         cpu = <&cpu1>;
 145                                 };
 146                         };
 147
 148                         cluster1 {
 149                                 core0 {
 150                                         cpu = <&cpu2>;
 151                                 };
 152                                 core1 {
 153                                         cpu = <&cpu3>;
 154                                 };
 155                         };
 156                 };
 157
 158                 cpu0: cpu@0 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a53";
 161                         reg = <0x000>;
 162                         enable-method = "psci";
 163                         cpu-idle-states = <&CPU_SLEEP_0>;
 164                         #cooling-cells = <2>;
 165                         dynamic-power-coefficient = <263>;
 166                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 167                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 168                         clock-names = "cpu", "intermediate";
 169                         operating-points-v2 = <&cluster0_opp>;
 170                         capacity-dmips-mhz = <740>;
 171                 };
 172
 173                 cpu1: cpu@1 {
 174                         device_type = "cpu";
 175                         compatible = "arm,cortex-a53";
 176                         reg = <0x001>;
 177                         enable-method = "psci";
 178                         cpu-idle-states = <&CPU_SLEEP_0>;
 179                         #cooling-cells = <2>;
 180                         dynamic-power-coefficient = <263>;
 181                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 182                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 183                         clock-names = "cpu", "intermediate";
 184                         operating-points-v2 = <&cluster0_opp>;
 185                         capacity-dmips-mhz = <740>;
 186                 };
 187
 188                 cpu2: cpu@100 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a72";
 191                         reg = <0x100>;
 192                         enable-method = "psci";
 193                         cpu-idle-states = <&CPU_SLEEP_0>;
 194                         #cooling-cells = <2>;
 195                         dynamic-power-coefficient = <530>;
 196                         clocks = <&infracfg CLK_INFRA_CA72SEL>,
 197                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 198                         clock-names = "cpu", "intermediate";
 199                         operating-points-v2 = <&cluster1_opp>;
 200                         capacity-dmips-mhz = <1024>;
 201                 };
 202
 203                 cpu3: cpu@101 {
 204                         device_type = "cpu";
 205                         compatible = "arm,cortex-a72";
 206                         reg = <0x101>;
 207                         enable-method = "psci";
 208                         cpu-idle-states = <&CPU_SLEEP_0>;
 209                         #cooling-cells = <2>;
 210                         dynamic-power-coefficient = <530>;
 211                         clocks = <&infracfg CLK_INFRA_CA72SEL>,
 212                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 213                         clock-names = "cpu", "intermediate";
 214                         operating-points-v2 = <&cluster1_opp>;
 215                         capacity-dmips-mhz = <1024>;
 216                 };
 217
 218                 idle-states {
 219                         entry-method = "psci";
 220
 221                         CPU_SLEEP_0: cpu-sleep-0 {
 222                                 compatible = "arm,idle-state";
 223                                 local-timer-stop;
 224                                 entry-latency-us = <639>;
 225                                 exit-latency-us = <680>;
 226                                 min-residency-us = <1088>;
 227                                 arm,psci-suspend-param = <0x0010000>;
 228                         };
 229                 };
 230         };
 231
 232         pmu_a53 {
 233                 compatible = "arm,cortex-a53-pmu";
 234                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 235                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu0>, <&cpu1>;
 237         };
 238
 239         pmu_a72 {
 240                 compatible = "arm,cortex-a72-pmu";
 241                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
 242                              <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
 243                 interrupt-affinity = <&cpu2>, <&cpu3>;
 244         };
 245
 246         psci {
 247                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 248                 method = "smc";
 249                 cpu_suspend   = <0x84000001>;
 250                 cpu_off       = <0x84000002>;
 251                 cpu_on        = <0x84000003>;
 252         };
 253
 254         clk26m: oscillator0 {
 255                 compatible = "fixed-clock";
 256                 #clock-cells = <0>;
 257                 clock-frequency = <26000000>;
 258                 clock-output-names = "clk26m";
 259         };
 260
 261         clk32k: oscillator1 {
 262                 compatible = "fixed-clock";
 263                 #clock-cells = <0>;
 264                 clock-frequency = <32000>;
 265                 clock-output-names = "clk32k";
 266         };
 267
 268         cpum_ck: oscillator2 {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <0>;
 272                 clock-output-names = "cpum_ck";
 273         };
 274
 275         thermal-zones {
 276                 cpu_thermal: cpu_thermal {
 277                         polling-delay-passive = <1000>; /* milliseconds */
 278                         polling-delay = <1000>; /* milliseconds */
 279
 280                         thermal-sensors = <&thermal>;
 281                         sustainable-power = <1500>; /* milliwatts */
 282
 283                         trips {
 284                                 threshold: trip-point0 {
 285                                         temperature = <68000>;
 286                                         hysteresis = <2000>;
 287                                         type = "passive";
 288                                 };
 289
 290                                 target: trip-point1 {
 291                                         temperature = <85000>;
 292                                         hysteresis = <2000>;
 293                                         type = "passive";
 294                                 };
 295
 296                                 cpu_crit: cpu_crit0 {
 297                                         temperature = <115000>;
 298                                         hysteresis = <2000>;
 299                                         type = "critical";
 300                                 };
 301                         };
 302
 303                         cooling-maps {
 304                                 map0 {
 305                                         trip = <&target>;
 306                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT
 307                                                           THERMAL_NO_LIMIT>,
 308                                                          <&cpu1 THERMAL_NO_LIMIT
 309                                                           THERMAL_NO_LIMIT>;
 310                                         contribution = <3072>;
 311                                 };
 312                                 map1 {
 313                                         trip = <&target>;
 314                                         cooling-device = <&cpu2 THERMAL_NO_LIMIT
 315                                                           THERMAL_NO_LIMIT>,
 316                                                          <&cpu3 THERMAL_NO_LIMIT
 317                                                           THERMAL_NO_LIMIT>;
 318                                         contribution = <1024>;
 319                                 };
 320                         };
 321                 };
 322         };
 323
 324         reserved-memory {
 325                 #address-cells = <2>;
 326                 #size-cells = <2>;
 327                 ranges;
 328                 vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
 329                         compatible = "shared-dma-pool";
 330                         reg = <0 0xb7000000 0 0x500000>;
 331                         alignment = <0x1000>;
 332                         no-map;
 333                 };
 334         };
 335
 336         timer {
 337                 compatible = "arm,armv8-timer";
 338                 interrupt-parent = <&gic>;
 339                 interrupts = <GIC_PPI 13
 340                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 341                              <GIC_PPI 14
 342                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 343                              <GIC_PPI 11
 344                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 345                              <GIC_PPI 10
 346                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 347                 arm,no-tick-in-suspend;
 348         };
 349
 350         soc {
 351                 #address-cells = <2>;
 352                 #size-cells = <2>;
 353                 compatible = "simple-bus";
 354                 ranges;
 355
 356                 topckgen: clock-controller@10000000 {
 357                         compatible = "mediatek,mt8173-topckgen";
 358                         reg = <0 0x10000000 0 0x1000>;
 359                         #clock-cells = <1>;
 360                 };
 361
 362                 infracfg: power-controller@10001000 {
 363                         compatible = "mediatek,mt8173-infracfg", "syscon";
 364                         reg = <0 0x10001000 0 0x1000>;
 365                         #clock-cells = <1>;
 366                         #reset-cells = <1>;
 367                 };
 368
 369                 pericfg: power-controller@10003000 {
 370                         compatible = "mediatek,mt8173-pericfg", "syscon";
 371                         reg = <0 0x10003000 0 0x1000>;
 372                         #clock-cells = <1>;
 373                         #reset-cells = <1>;
 374                 };
 375
 376                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 377                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 378                         reg = <0 0x10005000 0 0x1000>;
 379                 };
 380
 381                 pio: pinctrl@1000b000 {
 382                         compatible = "mediatek,mt8173-pinctrl";
 383                         reg = <0 0x1000b000 0 0x1000>;
 384                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 385                         pins-are-numbered;
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <2>;
 390                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 391                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 392                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 393
 394                         hdmi_pin: xxx {
 395
 396                                 /*hdmi htplg pin*/
 397                                 pins1 {
 398                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 399                                         input-enable;
 400                                         bias-pull-down;
 401                                 };
 402                         };
 403
 404                         i2c0_pins_a: i2c0 {
 405                                 pins1 {
 406                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 407                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 408                                         bias-disable;
 409                                 };
 410                         };
 411
 412                         i2c1_pins_a: i2c1 {
 413                                 pins1 {
 414                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 415                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 416                                         bias-disable;
 417                                 };
 418                         };
 419
 420                         i2c2_pins_a: i2c2 {
 421                                 pins1 {
 422                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 423                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 424                                         bias-disable;
 425                                 };
 426                         };
 427
 428                         i2c3_pins_a: i2c3 {
 429                                 pins1 {
 430                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 431                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 432                                         bias-disable;
 433                                 };
 434                         };
 435
 436                         i2c4_pins_a: i2c4 {
 437                                 pins1 {
 438                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 439                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 440                                         bias-disable;
 441                                 };
 442                         };
 443
 444                         i2c6_pins_a: i2c6 {
 445                                 pins1 {
 446                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 447                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 448                                         bias-disable;
 449                                 };
 450                         };
 451                 };
 452
 453                 scpsys: power-controller@10006000 {
 454                         compatible = "mediatek,mt8173-scpsys";
 455                         #power-domain-cells = <1>;
 456                         reg = <0 0x10006000 0 0x1000>;
 457                         clocks = <&clk26m>,
 458                                  <&topckgen CLK_TOP_MM_SEL>,
 459                                  <&topckgen CLK_TOP_VENC_SEL>,
 460                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 461                         clock-names = "mfg", "mm", "venc", "venc_lt";
 462                         infracfg = <&infracfg>;
 463                 };
 464
 465                 watchdog: watchdog@10007000 {
 466                         compatible = "mediatek,mt8173-wdt",
 467                                      "mediatek,mt6589-wdt";
 468                         reg = <0 0x10007000 0 0x100>;
 469                 };
 470
 471                 timer: timer@10008000 {
 472                         compatible = "mediatek,mt8173-timer",
 473                                      "mediatek,mt6577-timer";
 474                         reg = <0 0x10008000 0 0x1000>;
 475                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 476                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 477                                  <&topckgen CLK_TOP_RTC_SEL>;
 478                 };
 479
 480                 pwrap: pwrap@1000d000 {
 481                         compatible = "mediatek,mt8173-pwrap";
 482                         reg = <0 0x1000d000 0 0x1000>;
 483                         reg-names = "pwrap";
 484                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 485                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 486                         reset-names = "pwrap";
 487                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 488                         clock-names = "spi", "wrap";
 489                 };
 490
 491                 cec: cec@10013000 {
 492                         compatible = "mediatek,mt8173-cec";
 493                         reg = <0 0x10013000 0 0xbc>;
 494                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 495                         clocks = <&infracfg CLK_INFRA_CEC>;
 496                         status = "disabled";
 497                 };
 498
 499                 vpu: vpu@10020000 {
 500                         compatible = "mediatek,mt8173-vpu";
 501                         reg = <0 0x10020000 0 0x30000>,
 502                               <0 0x10050000 0 0x100>;
 503                         reg-names = "tcm", "cfg_reg";
 504                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 506                         clock-names = "main";
 507                         memory-region = <&vpu_dma_reserved>;
 508                 };
 509
 510                 sysirq: intpol-controller@10200620 {
 511                         compatible = "mediatek,mt8173-sysirq",
 512                                      "mediatek,mt6577-sysirq";
 513                         interrupt-controller;
 514                         #interrupt-cells = <3>;
 515                         interrupt-parent = <&gic>;
 516                         reg = <0 0x10200620 0 0x20>;
 517                 };
 518
 519                 iommu: iommu@10205000 {
 520                         compatible = "mediatek,mt8173-m4u";
 521                         reg = <0 0x10205000 0 0x1000>;
 522                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 523                         clocks = <&infracfg CLK_INFRA_M4U>;
 524                         clock-names = "bclk";
 525                         mediatek,larbs = <&larb0 &larb1 &larb2
 526                                           &larb3 &larb4 &larb5>;
 527                         #iommu-cells = <1>;
 528                 };
 529
 530                 efuse: efuse@10206000 {
 531                         compatible = "mediatek,mt8173-efuse";
 532                         reg = <0 0x10206000 0 0x1000>;
 533                         #address-cells = <1>;
 534                         #size-cells = <1>;
 535                         thermal_calibration: calib@528 {
 536                                 reg = <0x528 0xc>;
 537                         };
 538                 };
 539
 540                 apmixedsys: clock-controller@10209000 {
 541                         compatible = "mediatek,mt8173-apmixedsys";
 542                         reg = <0 0x10209000 0 0x1000>;
 543                         #clock-cells = <1>;
 544                 };
 545
 546                 hdmi_phy: hdmi-phy@10209100 {
 547                         compatible = "mediatek,mt8173-hdmi-phy";
 548                         reg = <0 0x10209100 0 0x24>;
 549                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 550                         clock-names = "pll_ref";
 551                         clock-output-names = "hdmitx_dig_cts";
 552                         mediatek,ibias = <0xa>;
 553                         mediatek,ibias_up = <0x1c>;
 554                         #clock-cells = <0>;
 555                         #phy-cells = <0>;
 556                         status = "disabled";
 557                 };
 558
 559                 gce: mailbox@10212000 {
 560                         compatible = "mediatek,mt8173-gce";
 561                         reg = <0 0x10212000 0 0x1000>;
 562                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 563                         clocks = <&infracfg CLK_INFRA_GCE>;
 564                         clock-names = "gce";
 565                         #mbox-cells = <2>;
 566                 };
 567
 568                 mipi_tx0: mipi-dphy@10215000 {
 569                         compatible = "mediatek,mt8173-mipi-tx";
 570                         reg = <0 0x10215000 0 0x1000>;
 571                         clocks = <&clk26m>;
 572                         clock-output-names = "mipi_tx0_pll";
 573                         #clock-cells = <0>;
 574                         #phy-cells = <0>;
 575                         status = "disabled";
 576                 };
 577
 578                 mipi_tx1: mipi-dphy@10216000 {
 579                         compatible = "mediatek,mt8173-mipi-tx";
 580                         reg = <0 0x10216000 0 0x1000>;
 581                         clocks = <&clk26m>;
 582                         clock-output-names = "mipi_tx1_pll";
 583                         #clock-cells = <0>;
 584                         #phy-cells = <0>;
 585                         status = "disabled";
 586                 };
 587
 588                 gic: interrupt-controller@10221000 {
 589                         compatible = "arm,gic-400";
 590                         #interrupt-cells = <3>;
 591                         interrupt-parent = <&gic>;
 592                         interrupt-controller;
 593                         reg = <0 0x10221000 0 0x1000>,
 594                               <0 0x10222000 0 0x2000>,
 595                               <0 0x10224000 0 0x2000>,
 596                               <0 0x10226000 0 0x2000>;
 597                         interrupts = <GIC_PPI 9
 598                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 599                 };
 600
 601                 auxadc: auxadc@11001000 {
 602                         compatible = "mediatek,mt8173-auxadc";
 603                         reg = <0 0x11001000 0 0x1000>;
 604                         clocks = <&pericfg CLK_PERI_AUXADC>;
 605                         clock-names = "main";
 606                         #io-channel-cells = <1>;
 607                 };
 608
 609                 uart0: serial@11002000 {
 610                         compatible = "mediatek,mt8173-uart",
 611                                      "mediatek,mt6577-uart";
 612                         reg = <0 0x11002000 0 0x400>;
 613                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 614                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 615                         clock-names = "baud", "bus";
 616                         status = "disabled";
 617                 };
 618
 619                 uart1: serial@11003000 {
 620                         compatible = "mediatek,mt8173-uart",
 621                                      "mediatek,mt6577-uart";
 622                         reg = <0 0x11003000 0 0x400>;
 623                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 624                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 625                         clock-names = "baud", "bus";
 626                         status = "disabled";
 627                 };
 628
 629                 uart2: serial@11004000 {
 630                         compatible = "mediatek,mt8173-uart",
 631                                      "mediatek,mt6577-uart";
 632                         reg = <0 0x11004000 0 0x400>;
 633                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 634                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 635                         clock-names = "baud", "bus";
 636                         status = "disabled";
 637                 };
 638
 639                 uart3: serial@11005000 {
 640                         compatible = "mediatek,mt8173-uart",
 641                                      "mediatek,mt6577-uart";
 642                         reg = <0 0x11005000 0 0x400>;
 643                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 644                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 645                         clock-names = "baud", "bus";
 646                         status = "disabled";
 647                 };
 648
 649                 i2c0: i2c@11007000 {
 650                         compatible = "mediatek,mt8173-i2c";
 651                         reg = <0 0x11007000 0 0x70>,
 652                               <0 0x11000100 0 0x80>;
 653                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 654                         clock-div = <16>;
 655                         clocks = <&pericfg CLK_PERI_I2C0>,
 656                                  <&pericfg CLK_PERI_AP_DMA>;
 657                         clock-names = "main", "dma";
 658                         pinctrl-names = "default";
 659                         pinctrl-0 = <&i2c0_pins_a>;
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         status = "disabled";
 663                 };
 664
 665                 i2c1: i2c@11008000 {
 666                         compatible = "mediatek,mt8173-i2c";
 667                         reg = <0 0x11008000 0 0x70>,
 668                               <0 0x11000180 0 0x80>;
 669                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 670                         clock-div = <16>;
 671                         clocks = <&pericfg CLK_PERI_I2C1>,
 672                                  <&pericfg CLK_PERI_AP_DMA>;
 673                         clock-names = "main", "dma";
 674                         pinctrl-names = "default";
 675                         pinctrl-0 = <&i2c1_pins_a>;
 676                         #address-cells = <1>;
 677                         #size-cells = <0>;
 678                         status = "disabled";
 679                 };
 680
 681                 i2c2: i2c@11009000 {
 682                         compatible = "mediatek,mt8173-i2c";
 683                         reg = <0 0x11009000 0 0x70>,
 684                               <0 0x11000200 0 0x80>;
 685                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 686                         clock-div = <16>;
 687                         clocks = <&pericfg CLK_PERI_I2C2>,
 688                                  <&pericfg CLK_PERI_AP_DMA>;
 689                         clock-names = "main", "dma";
 690                         pinctrl-names = "default";
 691                         pinctrl-0 = <&i2c2_pins_a>;
 692                         #address-cells = <1>;
 693                         #size-cells = <0>;
 694                         status = "disabled";
 695                 };
 696
 697                 spi: spi@1100a000 {
 698                         compatible = "mediatek,mt8173-spi";
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         reg = <0 0x1100a000 0 0x1000>;
 702                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 703                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 704                                  <&topckgen CLK_TOP_SPI_SEL>,
 705                                  <&pericfg CLK_PERI_SPI0>;
 706                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 707                         status = "disabled";
 708                 };
 709
 710                 thermal: thermal@1100b000 {
 711                         #thermal-sensor-cells = <0>;
 712                         compatible = "mediatek,mt8173-thermal";
 713                         reg = <0 0x1100b000 0 0x1000>;
 714                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 715                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 716                         clock-names = "therm", "auxadc";
 717                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 718                         mediatek,auxadc = <&auxadc>;
 719                         mediatek,apmixedsys = <&apmixedsys>;
 720                         nvmem-cells = <&thermal_calibration>;
 721                         nvmem-cell-names = "calibration-data";
 722                 };
 723
 724                 nor_flash: spi@1100d000 {
 725                         compatible = "mediatek,mt8173-nor";
 726                         reg = <0 0x1100d000 0 0xe0>;
 727                         clocks = <&pericfg CLK_PERI_SPI>,
 728                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 729                         clock-names = "spi", "sf";
 730                         #address-cells = <1>;
 731                         #size-cells = <0>;
 732                         status = "disabled";
 733                 };
 734
 735                 i2c3: i2c@11010000 {
 736                         compatible = "mediatek,mt8173-i2c";
 737                         reg = <0 0x11010000 0 0x70>,
 738                               <0 0x11000280 0 0x80>;
 739                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 740                         clock-div = <16>;
 741                         clocks = <&pericfg CLK_PERI_I2C3>,
 742                                  <&pericfg CLK_PERI_AP_DMA>;
 743                         clock-names = "main", "dma";
 744                         pinctrl-names = "default";
 745                         pinctrl-0 = <&i2c3_pins_a>;
 746                         #address-cells = <1>;
 747                         #size-cells = <0>;
 748                         status = "disabled";
 749                 };
 750
 751                 i2c4: i2c@11011000 {
 752                         compatible = "mediatek,mt8173-i2c";
 753                         reg = <0 0x11011000 0 0x70>,
 754                               <0 0x11000300 0 0x80>;
 755                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 756                         clock-div = <16>;
 757                         clocks = <&pericfg CLK_PERI_I2C4>,
 758                                  <&pericfg CLK_PERI_AP_DMA>;
 759                         clock-names = "main", "dma";
 760                         pinctrl-names = "default";
 761                         pinctrl-0 = <&i2c4_pins_a>;
 762                         #address-cells = <1>;
 763                         #size-cells = <0>;
 764                         status = "disabled";
 765                 };
 766
 767                 hdmiddc0: i2c@11012000 {
 768                         compatible = "mediatek,mt8173-hdmi-ddc";
 769                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 770                         reg = <0 0x11012000 0 0x1C>;
 771                         clocks = <&pericfg CLK_PERI_I2C5>;
 772                         clock-names = "ddc-i2c";
 773                 };
 774
 775                 i2c6: i2c@11013000 {
 776                         compatible = "mediatek,mt8173-i2c";
 777                         reg = <0 0x11013000 0 0x70>,
 778                               <0 0x11000080 0 0x80>;
 779                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 780                         clock-div = <16>;
 781                         clocks = <&pericfg CLK_PERI_I2C6>,
 782                                  <&pericfg CLK_PERI_AP_DMA>;
 783                         clock-names = "main", "dma";
 784                         pinctrl-names = "default";
 785                         pinctrl-0 = <&i2c6_pins_a>;
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788                         status = "disabled";
 789                 };
 790
 791                 afe: audio-controller@11220000  {
 792                         compatible = "mediatek,mt8173-afe-pcm";
 793                         reg = <0 0x11220000 0 0x1000>;
 794                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 795                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 796                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 797                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 798                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 799                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 800                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 801                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 802                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 803                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 804                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 805                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 806                         clock-names = "infra_sys_audio_clk",
 807                                       "top_pdn_audio",
 808                                       "top_pdn_aud_intbus",
 809                                       "bck0",
 810                                       "bck1",
 811                                       "i2s0_m",
 812                                       "i2s1_m",
 813                                       "i2s2_m",
 814                                       "i2s3_m",
 815                                       "i2s3_b";
 816                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 817                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 818                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 819                                                  <&topckgen CLK_TOP_APLL2>;
 820                 };
 821
 822                 mmc0: mmc@11230000 {
 823                         compatible = "mediatek,mt8173-mmc";
 824                         reg = <0 0x11230000 0 0x1000>;
 825                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 826                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 827                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 828                         clock-names = "source", "hclk";
 829                         status = "disabled";
 830                 };
 831
 832                 mmc1: mmc@11240000 {
 833                         compatible = "mediatek,mt8173-mmc";
 834                         reg = <0 0x11240000 0 0x1000>;
 835                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 836                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 837                                  <&topckgen CLK_TOP_AXI_SEL>;
 838                         clock-names = "source", "hclk";
 839                         status = "disabled";
 840                 };
 841
 842                 mmc2: mmc@11250000 {
 843                         compatible = "mediatek,mt8173-mmc";
 844                         reg = <0 0x11250000 0 0x1000>;
 845                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 846                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 847                                  <&topckgen CLK_TOP_AXI_SEL>;
 848                         clock-names = "source", "hclk";
 849                         status = "disabled";
 850                 };
 851
 852                 mmc3: mmc@11260000 {
 853                         compatible = "mediatek,mt8173-mmc";
 854                         reg = <0 0x11260000 0 0x1000>;
 855                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 856                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 857                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 858                         clock-names = "source", "hclk";
 859                         status = "disabled";
 860                 };
 861
 862                 ssusb: usb@11271000 {
 863                         compatible = "mediatek,mt8173-mtu3";
 864                         reg = <0 0x11271000 0 0x3000>,
 865                               <0 0x11280700 0 0x0100>;
 866                         reg-names = "mac", "ippc";
 867                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 868                         phys = <&u2port0 PHY_TYPE_USB2>,
 869                                <&u3port0 PHY_TYPE_USB3>,
 870                                <&u2port1 PHY_TYPE_USB2>;
 871                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 872                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 873                         clock-names = "sys_ck", "ref_ck";
 874                         mediatek,syscon-wakeup = <&pericfg 0x400 1>;
 875                         #address-cells = <2>;
 876                         #size-cells = <2>;
 877                         ranges;
 878                         status = "disabled";
 879
 880                         usb_host: xhci@11270000 {
 881                                 compatible = "mediatek,mt8173-xhci";
 882                                 reg = <0 0x11270000 0 0x1000>;
 883                                 reg-names = "mac";
 884                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 885                                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 886                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 887                                 clock-names = "sys_ck", "ref_ck";
 888                                 status = "disabled";
 889                         };
 890                 };
 891
 892                 u3phy: usb-phy@11290000 {
 893                         compatible = "mediatek,mt8173-u3phy";
 894                         reg = <0 0x11290000 0 0x800>;
 895                         #address-cells = <2>;
 896                         #size-cells = <2>;
 897                         ranges;
 898                         status = "okay";
 899
 900                         u2port0: usb-phy@11290800 {
 901                                 reg = <0 0x11290800 0 0x100>;
 902                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 903                                 clock-names = "ref";
 904                                 #phy-cells = <1>;
 905                                 status = "okay";
 906                         };
 907
 908                         u3port0: usb-phy@11290900 {
 909                                 reg = <0 0x11290900 0 0x700>;
 910                                 clocks = <&clk26m>;
 911                                 clock-names = "ref";
 912                                 #phy-cells = <1>;
 913                                 status = "okay";
 914                         };
 915
 916                         u2port1: usb-phy@11291000 {
 917                                 reg = <0 0x11291000 0 0x100>;
 918                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 919                                 clock-names = "ref";
 920                                 #phy-cells = <1>;
 921                                 status = "okay";
 922                         };
 923                 };
 924
 925                 mmsys: syscon@14000000 {
 926                         compatible = "mediatek,mt8173-mmsys", "syscon";
 927                         reg = <0 0x14000000 0 0x1000>;
 928                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 929                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
 930                         assigned-clock-rates = <400000000>;
 931                         #clock-cells = <1>;
 932                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
 933                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
 934                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 935                 };
 936
 937                 mdp_rdma0: rdma@14001000 {
 938                         compatible = "mediatek,mt8173-mdp-rdma",
 939                                      "mediatek,mt8173-mdp";
 940                         reg = <0 0x14001000 0 0x1000>;
 941                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
 942                                  <&mmsys CLK_MM_MUTEX_32K>;
 943                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 944                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
 945                         mediatek,larb = <&larb0>;
 946                         mediatek,vpu = <&vpu>;
 947                 };
 948
 949                 mdp_rdma1: rdma@14002000 {
 950                         compatible = "mediatek,mt8173-mdp-rdma";
 951                         reg = <0 0x14002000 0 0x1000>;
 952                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
 953                                  <&mmsys CLK_MM_MUTEX_32K>;
 954                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 955                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
 956                         mediatek,larb = <&larb4>;
 957                 };
 958
 959                 mdp_rsz0: rsz@14003000 {
 960                         compatible = "mediatek,mt8173-mdp-rsz";
 961                         reg = <0 0x14003000 0 0x1000>;
 962                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
 963                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 964                 };
 965
 966                 mdp_rsz1: rsz@14004000 {
 967                         compatible = "mediatek,mt8173-mdp-rsz";
 968                         reg = <0 0x14004000 0 0x1000>;
 969                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
 970                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 971                 };
 972
 973                 mdp_rsz2: rsz@14005000 {
 974                         compatible = "mediatek,mt8173-mdp-rsz";
 975                         reg = <0 0x14005000 0 0x1000>;
 976                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
 977                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 978                 };
 979
 980                 mdp_wdma0: wdma@14006000 {
 981                         compatible = "mediatek,mt8173-mdp-wdma";
 982                         reg = <0 0x14006000 0 0x1000>;
 983                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
 984                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 985                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
 986                         mediatek,larb = <&larb0>;
 987                 };
 988
 989                 mdp_wrot0: wrot@14007000 {
 990                         compatible = "mediatek,mt8173-mdp-wrot";
 991                         reg = <0 0x14007000 0 0x1000>;
 992                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
 993                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 994                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
 995                         mediatek,larb = <&larb0>;
 996                 };
 997
 998                 mdp_wrot1: wrot@14008000 {
 999                         compatible = "mediatek,mt8173-mdp-wrot";
1000                         reg = <0 0x14008000 0 0x1000>;
1001                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
1002                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1003                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
1004                         mediatek,larb = <&larb4>;
1005                 };
1006
1007                 ovl0: ovl@1400c000 {
1008                         compatible = "mediatek,mt8173-disp-ovl";
1009                         reg = <0 0x1400c000 0 0x1000>;
1010                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1011                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1012                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1013                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
1014                         mediatek,larb = <&larb0>;
1015                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1016                 };
1017
1018                 ovl1: ovl@1400d000 {
1019                         compatible = "mediatek,mt8173-disp-ovl";
1020                         reg = <0 0x1400d000 0 0x1000>;
1021                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1022                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1023                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
1024                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
1025                         mediatek,larb = <&larb4>;
1026                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1027                 };
1028
1029                 rdma0: rdma@1400e000 {
1030                         compatible = "mediatek,mt8173-disp-rdma";
1031                         reg = <0 0x1400e000 0 0x1000>;
1032                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1033                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1034                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1035                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1036                         mediatek,larb = <&larb0>;
1037                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1038                 };
1039
1040                 rdma1: rdma@1400f000 {
1041                         compatible = "mediatek,mt8173-disp-rdma";
1042                         reg = <0 0x1400f000 0 0x1000>;
1043                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1044                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1045                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1046                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1047                         mediatek,larb = <&larb4>;
1048                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1049                 };
1050
1051                 rdma2: rdma@14010000 {
1052                         compatible = "mediatek,mt8173-disp-rdma";
1053                         reg = <0 0x14010000 0 0x1000>;
1054                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1055                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1056                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1057                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1058                         mediatek,larb = <&larb4>;
1059                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1060                 };
1061
1062                 wdma0: wdma@14011000 {
1063                         compatible = "mediatek,mt8173-disp-wdma";
1064                         reg = <0 0x14011000 0 0x1000>;
1065                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1066                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1067                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1068                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1069                         mediatek,larb = <&larb0>;
1070                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1071                 };
1072
1073                 wdma1: wdma@14012000 {
1074                         compatible = "mediatek,mt8173-disp-wdma";
1075                         reg = <0 0x14012000 0 0x1000>;
1076                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1077                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1078                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1079                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1080                         mediatek,larb = <&larb4>;
1081                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1082                 };
1083
1084                 color0: color@14013000 {
1085                         compatible = "mediatek,mt8173-disp-color";
1086                         reg = <0 0x14013000 0 0x1000>;
1087                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1088                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1089                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1090                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1091                 };
1092
1093                 color1: color@14014000 {
1094                         compatible = "mediatek,mt8173-disp-color";
1095                         reg = <0 0x14014000 0 0x1000>;
1096                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1097                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1098                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1099                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1100                 };
1101
1102                 aal@14015000 {
1103                         compatible = "mediatek,mt8173-disp-aal";
1104                         reg = <0 0x14015000 0 0x1000>;
1105                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1106                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1107                         clocks = <&mmsys CLK_MM_DISP_AAL>;
1108                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1109                 };
1110
1111                 gamma@14016000 {
1112                         compatible = "mediatek,mt8173-disp-gamma";
1113                         reg = <0 0x14016000 0 0x1000>;
1114                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1115                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1116                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1117                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1118                 };
1119
1120                 merge@14017000 {
1121                         compatible = "mediatek,mt8173-disp-merge";
1122                         reg = <0 0x14017000 0 0x1000>;
1123                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1124                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
1125                 };
1126
1127                 split0: split@14018000 {
1128                         compatible = "mediatek,mt8173-disp-split";
1129                         reg = <0 0x14018000 0 0x1000>;
1130                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1131                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1132                 };
1133
1134                 split1: split@14019000 {
1135                         compatible = "mediatek,mt8173-disp-split";
1136                         reg = <0 0x14019000 0 0x1000>;
1137                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1138                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1139                 };
1140
1141                 ufoe@1401a000 {
1142                         compatible = "mediatek,mt8173-disp-ufoe";
1143                         reg = <0 0x1401a000 0 0x1000>;
1144                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1145                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1146                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1147                 };
1148
1149                 dsi0: dsi@1401b000 {
1150                         compatible = "mediatek,mt8173-dsi";
1151                         reg = <0 0x1401b000 0 0x1000>;
1152                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1153                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1154                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1155                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1156                                  <&mipi_tx0>;
1157                         clock-names = "engine", "digital", "hs";
1158                         phys = <&mipi_tx0>;
1159                         phy-names = "dphy";
1160                         status = "disabled";
1161                 };
1162
1163                 dsi1: dsi@1401c000 {
1164                         compatible = "mediatek,mt8173-dsi";
1165                         reg = <0 0x1401c000 0 0x1000>;
1166                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1167                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1168                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1169                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1170                                  <&mipi_tx1>;
1171                         clock-names = "engine", "digital", "hs";
1172                         phy = <&mipi_tx1>;
1173                         phy-names = "dphy";
1174                         status = "disabled";
1175                 };
1176
1177                 dpi0: dpi@1401d000 {
1178                         compatible = "mediatek,mt8173-dpi";
1179                         reg = <0 0x1401d000 0 0x1000>;
1180                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1181                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1182                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1183                                  <&mmsys CLK_MM_DPI_ENGINE>,
1184                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1185                         clock-names = "pixel", "engine", "pll";
1186                         status = "disabled";
1187
1188                         port {
1189                                 dpi0_out: endpoint {
1190                                         remote-endpoint = <&hdmi0_in>;
1191                                 };
1192                         };
1193                 };
1194
1195                 pwm0: pwm@1401e000 {
1196                         compatible = "mediatek,mt8173-disp-pwm",
1197                                      "mediatek,mt6595-disp-pwm";
1198                         reg = <0 0x1401e000 0 0x1000>;
1199                         #pwm-cells = <2>;
1200                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1201                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1202                         clock-names = "main", "mm";
1203                         status = "disabled";
1204                 };
1205
1206                 pwm1: pwm@1401f000 {
1207                         compatible = "mediatek,mt8173-disp-pwm",
1208                                      "mediatek,mt6595-disp-pwm";
1209                         reg = <0 0x1401f000 0 0x1000>;
1210                         #pwm-cells = <2>;
1211                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1212                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1213                         clock-names = "main", "mm";
1214                         status = "disabled";
1215                 };
1216
1217                 mutex: mutex@14020000 {
1218                         compatible = "mediatek,mt8173-disp-mutex";
1219                         reg = <0 0x14020000 0 0x1000>;
1220                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1221                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1222                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1223                         mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1224                                               <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
1225                 };
1226
1227                 larb0: larb@14021000 {
1228                         compatible = "mediatek,mt8173-smi-larb";
1229                         reg = <0 0x14021000 0 0x1000>;
1230                         mediatek,smi = <&smi_common>;
1231                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1232                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1233                                  <&mmsys CLK_MM_SMI_LARB0>;
1234                         clock-names = "apb", "smi";
1235                 };
1236
1237                 smi_common: smi@14022000 {
1238                         compatible = "mediatek,mt8173-smi-common";
1239                         reg = <0 0x14022000 0 0x1000>;
1240                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1241                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1242                                  <&mmsys CLK_MM_SMI_COMMON>;
1243                         clock-names = "apb", "smi";
1244                 };
1245
1246                 od@14023000 {
1247                         compatible = "mediatek,mt8173-disp-od";
1248                         reg = <0 0x14023000 0 0x1000>;
1249                         clocks = <&mmsys CLK_MM_DISP_OD>;
1250                 };
1251
1252                 hdmi0: hdmi@14025000 {
1253                         compatible = "mediatek,mt8173-hdmi";
1254                         reg = <0 0x14025000 0 0x400>;
1255                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1256                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1257                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1258                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1259                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1260                         clock-names = "pixel", "pll", "bclk", "spdif";
1261                         pinctrl-names = "default";
1262                         pinctrl-0 = <&hdmi_pin>;
1263                         phys = <&hdmi_phy>;
1264                         phy-names = "hdmi";
1265                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1266                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1267                         assigned-clock-parents = <&hdmi_phy>;
1268                         status = "disabled";
1269
1270                         ports {
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273
1274                                 port@0 {
1275                                         reg = <0>;
1276
1277                                         hdmi0_in: endpoint {
1278                                                 remote-endpoint = <&dpi0_out>;
1279                                         };
1280                                 };
1281                         };
1282                 };
1283
1284                 larb4: larb@14027000 {
1285                         compatible = "mediatek,mt8173-smi-larb";
1286                         reg = <0 0x14027000 0 0x1000>;
1287                         mediatek,smi = <&smi_common>;
1288                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1289                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1290                                  <&mmsys CLK_MM_SMI_LARB4>;
1291                         clock-names = "apb", "smi";
1292                 };
1293
1294                 imgsys: clock-controller@15000000 {
1295                         compatible = "mediatek,mt8173-imgsys", "syscon";
1296                         reg = <0 0x15000000 0 0x1000>;
1297                         #clock-cells = <1>;
1298                 };
1299
1300                 larb2: larb@15001000 {
1301                         compatible = "mediatek,mt8173-smi-larb";
1302                         reg = <0 0x15001000 0 0x1000>;
1303                         mediatek,smi = <&smi_common>;
1304                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1305                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1306                                  <&imgsys CLK_IMG_LARB2_SMI>;
1307                         clock-names = "apb", "smi";
1308                 };
1309
1310                 vdecsys: clock-controller@16000000 {
1311                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1312                         reg = <0 0x16000000 0 0x1000>;
1313                         #clock-cells = <1>;
1314                 };
1315
1316                 vcodec_dec: vcodec@16000000 {
1317                         compatible = "mediatek,mt8173-vcodec-dec";
1318                         reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
1319                               <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1320                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1321                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1322                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1323                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1324                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1325                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1326                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1327                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1328                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1329                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1330                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1331                         mediatek,larb = <&larb1>;
1332                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1333                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1334                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1335                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1336                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1337                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1338                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1339                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1340                         mediatek,vpu = <&vpu>;
1341                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1342                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1343                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1344                                  <&topckgen CLK_TOP_CCI400_SEL>,
1345                                  <&topckgen CLK_TOP_VDEC_SEL>,
1346                                  <&topckgen CLK_TOP_VCODECPLL>,
1347                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1348                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1349                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1350                         clock-names = "vcodecpll",
1351                                       "univpll_d2",
1352                                       "clk_cci400_sel",
1353                                       "vdec_sel",
1354                                       "vdecpll",
1355                                       "vencpll",
1356                                       "venc_lt_sel",
1357                                       "vdec_bus_clk_src";
1358                         assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1359                                           <&topckgen CLK_TOP_CCI400_SEL>,
1360                                           <&topckgen CLK_TOP_VDEC_SEL>,
1361                                           <&apmixedsys CLK_APMIXED_VCODECPLL>,
1362                                           <&apmixedsys CLK_APMIXED_VENCPLL>;
1363                         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1364                                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1365                                                  <&topckgen CLK_TOP_VCODECPLL>;
1366                         assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1367                 };
1368
1369                 larb1: larb@16010000 {
1370                         compatible = "mediatek,mt8173-smi-larb";
1371                         reg = <0 0x16010000 0 0x1000>;
1372                         mediatek,smi = <&smi_common>;
1373                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1374                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1375                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1376                         clock-names = "apb", "smi";
1377                 };
1378
1379                 vencsys: clock-controller@18000000 {
1380                         compatible = "mediatek,mt8173-vencsys", "syscon";
1381                         reg = <0 0x18000000 0 0x1000>;
1382                         #clock-cells = <1>;
1383                 };
1384
1385                 larb3: larb@18001000 {
1386                         compatible = "mediatek,mt8173-smi-larb";
1387                         reg = <0 0x18001000 0 0x1000>;
1388                         mediatek,smi = <&smi_common>;
1389                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1390                         clocks = <&vencsys CLK_VENC_CKE1>,
1391                                  <&vencsys CLK_VENC_CKE0>;
1392                         clock-names = "apb", "smi";
1393                 };
1394
1395                 vcodec_enc: vcodec@18002000 {
1396                         compatible = "mediatek,mt8173-vcodec-enc";
1397                         reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
1398                               <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
1399                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1400                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1401                         mediatek,larb = <&larb3>,
1402                                         <&larb5>;
1403                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1404                                  <&iommu M4U_PORT_VENC_REC>,
1405                                  <&iommu M4U_PORT_VENC_BSDMA>,
1406                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1407                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1408                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1409                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1410                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1411                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1412                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1413                                  <&iommu M4U_PORT_VENC_NBM_WDMA>,
1414                                  <&iommu M4U_PORT_VENC_RCPU_SET2>,
1415                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1416                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1417                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1418                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1419                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1420                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1421                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1422                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1423                         mediatek,vpu = <&vpu>;
1424                         clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1425                                  <&topckgen CLK_TOP_VENC_SEL>,
1426                                  <&topckgen CLK_TOP_UNIVPLL1_D2>,
1427                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
1428                         clock-names = "venc_sel_src",
1429                                       "venc_sel",
1430                                       "venc_lt_sel_src",
1431                                       "venc_lt_sel";
1432                         assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
1433                                           <&topckgen CLK_TOP_VENC_LT_SEL>;
1434                         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
1435                                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1436                 };
1437
1438                 jpegdec: jpegdec@18004000 {
1439                         compatible = "mediatek,mt8173-jpgdec";
1440                         reg = <0 0x18004000 0 0x1000>;
1441                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1442                         clocks = <&vencsys CLK_VENC_CKE0>,
1443                                  <&vencsys CLK_VENC_CKE3>;
1444                         clock-names = "jpgdec-smi",
1445                                       "jpgdec";
1446                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1447                         mediatek,larb = <&larb3>;
1448                         iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1449                                  <&iommu M4U_PORT_JPGDEC_BSDMA>;
1450                 };
1451
1452                 vencltsys: clock-controller@19000000 {
1453                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1454                         reg = <0 0x19000000 0 0x1000>;
1455                         #clock-cells = <1>;
1456                 };
1457
1458                 larb5: larb@19001000 {
1459                         compatible = "mediatek,mt8173-smi-larb";
1460                         reg = <0 0x19001000 0 0x1000>;
1461                         mediatek,smi = <&smi_common>;
1462                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1463                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1464                                  <&vencltsys CLK_VENCLT_CKE0>;
1465                         clock-names = "apb", "smi";
1466                 };
1467         };
1468 };