2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
73 compatible = "arm,cortex-a53";
75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L2>;
88 compatible = "arm,cortex-a53";
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92 clock-names = "cpu", "intermediate";
93 operating-points-v2 = <&cpu_opp_table>;
95 enable-method = "psci";
96 clock-frequency = <1300000000>;
97 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L2>;
102 compatible = "cache";
107 pwrap_clk: dummy40m {
108 compatible = "fixed-clock";
109 clock-frequency = <40000000>;
114 compatible = "fixed-clock";
116 clock-frequency = <25000000>;
117 clock-output-names = "clkxtal";
121 compatible = "arm,psci-0.2";
126 compatible = "arm,cortex-a53-pmu";
127 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
129 interrupt-affinity = <&cpu0>, <&cpu1>;
133 #address-cells = <2>;
137 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
138 secmon_reserved: secmon@43000000 {
139 reg = <0 0x43000000 0 0x30000>;
145 cpu_thermal: cpu-thermal {
146 polling-delay-passive = <1000>;
147 polling-delay = <1000>;
149 thermal-sensors = <&thermal 0>;
152 cpu_passive: cpu-passive {
153 temperature = <47000>;
158 cpu_active: cpu-active {
159 temperature = <67000>;
165 temperature = <87000>;
171 temperature = <107000>;
179 trip = <&cpu_passive>;
180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
181 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185 trip = <&cpu_active>;
186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
192 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
200 compatible = "arm,armv8-timer";
201 interrupt-parent = <&gic>;
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
203 IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
205 IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
207 IRQ_TYPE_LEVEL_HIGH)>,
208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
209 IRQ_TYPE_LEVEL_HIGH)>;
212 infracfg: infracfg@10000000 {
213 compatible = "mediatek,mt7622-infracfg",
215 reg = <0 0x10000000 0 0x1000>;
220 pwrap: pwrap@10001000 {
221 compatible = "mediatek,mt7622-pwrap";
222 reg = <0 0x10001000 0 0x250>;
224 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
225 clock-names = "spi", "wrap";
226 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
227 reset-names = "pwrap";
228 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
232 pericfg: pericfg@10002000 {
233 compatible = "mediatek,mt7622-pericfg",
235 reg = <0 0x10002000 0 0x1000>;
240 scpsys: power-controller@10006000 {
241 compatible = "mediatek,mt7622-scpsys",
243 #power-domain-cells = <1>;
244 reg = <0 0x10006000 0 0x1000>;
245 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
249 infracfg = <&infracfg>;
250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
251 clock-names = "hif_sel";
255 compatible = "mediatek,mt7622-cir";
256 reg = <0 0x10009000 0 0x1000>;
257 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
258 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
259 <&topckgen CLK_TOP_AXI_SEL>;
260 clock-names = "clk", "bus";
264 sysirq: interrupt-controller@10200620 {
265 compatible = "mediatek,mt7622-sysirq",
266 "mediatek,mt6577-sysirq";
267 interrupt-controller;
268 #interrupt-cells = <3>;
269 interrupt-parent = <&gic>;
270 reg = <0 0x10200620 0 0x20>;
273 efuse: efuse@10206000 {
274 compatible = "mediatek,mt7622-efuse",
276 reg = <0 0x10206000 0 0x1000>;
277 #address-cells = <1>;
280 thermal_calibration: calib@198 {
285 apmixedsys: apmixedsys@10209000 {
286 compatible = "mediatek,mt7622-apmixedsys",
288 reg = <0 0x10209000 0 0x1000>;
292 topckgen: topckgen@10210000 {
293 compatible = "mediatek,mt7622-topckgen",
295 reg = <0 0x10210000 0 0x1000>;
300 compatible = "mediatek,mt7622-rng",
301 "mediatek,mt7623-rng";
302 reg = <0 0x1020f000 0 0x1000>;
303 clocks = <&infracfg CLK_INFRA_TRNG>;
307 pio: pinctrl@10211000 {
308 compatible = "mediatek,mt7622-pinctrl";
309 reg = <0 0x10211000 0 0x1000>,
310 <0 0x10005000 0 0x1000>;
311 reg-names = "base", "eint";
314 gpio-ranges = <&pio 0 0 103>;
315 interrupt-controller;
316 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
317 interrupt-parent = <&gic>;
318 #interrupt-cells = <2>;
321 watchdog: watchdog@10212000 {
322 compatible = "mediatek,mt7622-wdt",
323 "mediatek,mt6589-wdt";
324 reg = <0 0x10212000 0 0x800>;
328 compatible = "mediatek,mt7622-rtc",
330 reg = <0 0x10212800 0 0x200>;
331 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
332 clocks = <&topckgen CLK_TOP_RTC>;
336 gic: interrupt-controller@10300000 {
337 compatible = "arm,gic-400";
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 interrupt-parent = <&gic>;
341 reg = <0 0x10310000 0 0x1000>,
342 <0 0x10320000 0 0x1000>,
343 <0 0x10340000 0 0x2000>,
344 <0 0x10360000 0 0x2000>;
348 compatible = "arm,cci-400";
349 #address-cells = <1>;
351 reg = <0 0x10390000 0 0x1000>;
352 ranges = <0 0 0x10390000 0x10000>;
354 cci_control0: slave-if@1000 {
355 compatible = "arm,cci-400-ctrl-if";
356 interface-type = "ace-lite";
357 reg = <0x1000 0x1000>;
360 cci_control1: slave-if@4000 {
361 compatible = "arm,cci-400-ctrl-if";
362 interface-type = "ace";
363 reg = <0x4000 0x1000>;
366 cci_control2: slave-if@5000 {
367 compatible = "arm,cci-400-ctrl-if", "syscon";
368 interface-type = "ace";
369 reg = <0x5000 0x1000>;
373 compatible = "arm,cci-400-pmu,r1";
374 reg = <0x9000 0x5000>;
375 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
383 auxadc: adc@11001000 {
384 compatible = "mediatek,mt7622-auxadc";
385 reg = <0 0x11001000 0 0x1000>;
386 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
387 clock-names = "main";
388 #io-channel-cells = <1>;
391 uart0: serial@11002000 {
392 compatible = "mediatek,mt7622-uart",
393 "mediatek,mt6577-uart";
394 reg = <0 0x11002000 0 0x400>;
395 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
396 clocks = <&topckgen CLK_TOP_UART_SEL>,
397 <&pericfg CLK_PERI_UART0_PD>;
398 clock-names = "baud", "bus";
402 uart1: serial@11003000 {
403 compatible = "mediatek,mt7622-uart",
404 "mediatek,mt6577-uart";
405 reg = <0 0x11003000 0 0x400>;
406 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
408 <&pericfg CLK_PERI_UART1_PD>;
409 clock-names = "baud", "bus";
413 uart2: serial@11004000 {
414 compatible = "mediatek,mt7622-uart",
415 "mediatek,mt6577-uart";
416 reg = <0 0x11004000 0 0x400>;
417 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
419 <&pericfg CLK_PERI_UART2_PD>;
420 clock-names = "baud", "bus";
424 uart3: serial@11005000 {
425 compatible = "mediatek,mt7622-uart",
426 "mediatek,mt6577-uart";
427 reg = <0 0x11005000 0 0x400>;
428 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
430 <&pericfg CLK_PERI_UART3_PD>;
431 clock-names = "baud", "bus";
436 compatible = "mediatek,mt7622-pwm";
437 reg = <0 0x11006000 0 0x1000>;
438 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
440 <&pericfg CLK_PERI_PWM_PD>,
441 <&pericfg CLK_PERI_PWM1_PD>,
442 <&pericfg CLK_PERI_PWM2_PD>,
443 <&pericfg CLK_PERI_PWM3_PD>,
444 <&pericfg CLK_PERI_PWM4_PD>,
445 <&pericfg CLK_PERI_PWM5_PD>,
446 <&pericfg CLK_PERI_PWM6_PD>;
447 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
453 compatible = "mediatek,mt7622-i2c";
454 reg = <0 0x11007000 0 0x90>,
455 <0 0x11000100 0 0x80>;
456 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
458 clocks = <&pericfg CLK_PERI_I2C0_PD>,
459 <&pericfg CLK_PERI_AP_DMA_PD>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
467 compatible = "mediatek,mt7622-i2c";
468 reg = <0 0x11008000 0 0x90>,
469 <0 0x11000180 0 0x80>;
470 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
472 clocks = <&pericfg CLK_PERI_I2C1_PD>,
473 <&pericfg CLK_PERI_AP_DMA_PD>;
474 clock-names = "main", "dma";
475 #address-cells = <1>;
481 compatible = "mediatek,mt7622-i2c";
482 reg = <0 0x11009000 0 0x90>,
483 <0 0x11000200 0 0x80>;
484 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
486 clocks = <&pericfg CLK_PERI_I2C2_PD>,
487 <&pericfg CLK_PERI_AP_DMA_PD>;
488 clock-names = "main", "dma";
489 #address-cells = <1>;
495 compatible = "mediatek,mt7622-spi";
496 reg = <0 0x1100a000 0 0x100>;
497 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
498 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
499 <&topckgen CLK_TOP_SPI0_SEL>,
500 <&pericfg CLK_PERI_SPI0_PD>;
501 clock-names = "parent-clk", "sel-clk", "spi-clk";
502 #address-cells = <1>;
507 thermal: thermal@1100b000 {
508 #thermal-sensor-cells = <1>;
509 compatible = "mediatek,mt7622-thermal";
510 reg = <0 0x1100b000 0 0x1000>;
511 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
512 clocks = <&pericfg CLK_PERI_THERM_PD>,
513 <&pericfg CLK_PERI_AUXADC_PD>;
514 clock-names = "therm", "auxadc";
515 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
516 reset-names = "therm";
517 mediatek,auxadc = <&auxadc>;
518 mediatek,apmixedsys = <&apmixedsys>;
519 nvmem-cells = <&thermal_calibration>;
520 nvmem-cell-names = "calibration-data";
523 btif: serial@1100c000 {
524 compatible = "mediatek,mt7622-btif",
526 reg = <0 0x1100c000 0 0x1000>;
527 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
528 clocks = <&pericfg CLK_PERI_BTIF_PD>;
529 clock-names = "main";
535 compatible = "mediatek,mt7622-bluetooth";
536 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
542 nandc: nfi@1100d000 {
543 compatible = "mediatek,mt7622-nfc";
544 reg = <0 0x1100D000 0 0x1000>;
545 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
546 clocks = <&pericfg CLK_PERI_NFI_PD>,
547 <&pericfg CLK_PERI_SNFI_PD>;
548 clock-names = "nfi_clk", "pad_clk";
550 #address-cells = <1>;
556 compatible = "mediatek,mt7622-snand";
557 reg = <0 0x1100d000 0 0x1000>;
558 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
559 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
560 clock-names = "nfi_clk", "pad_clk";
561 nand-ecc-engine = <&bch>;
562 #address-cells = <1>;
568 compatible = "mediatek,mt7622-ecc";
569 reg = <0 0x1100e000 0 0x1000>;
570 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
571 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
572 clock-names = "nfiecc_clk";
576 nor_flash: spi@11014000 {
577 compatible = "mediatek,mt7622-nor",
578 "mediatek,mt8173-nor";
579 reg = <0 0x11014000 0 0xe0>;
580 clocks = <&pericfg CLK_PERI_FLASH_PD>,
581 <&topckgen CLK_TOP_FLASH_SEL>;
582 clock-names = "spi", "sf";
583 #address-cells = <1>;
589 compatible = "mediatek,mt7622-spi";
590 reg = <0 0x11016000 0 0x100>;
591 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
592 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
593 <&topckgen CLK_TOP_SPI1_SEL>,
594 <&pericfg CLK_PERI_SPI1_PD>;
595 clock-names = "parent-clk", "sel-clk", "spi-clk";
596 #address-cells = <1>;
601 uart4: serial@11019000 {
602 compatible = "mediatek,mt7622-uart",
603 "mediatek,mt6577-uart";
604 reg = <0 0x11019000 0 0x400>;
605 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
606 clocks = <&topckgen CLK_TOP_UART_SEL>,
607 <&pericfg CLK_PERI_UART4_PD>;
608 clock-names = "baud", "bus";
612 audsys: clock-controller@11220000 {
613 compatible = "mediatek,mt7622-audsys", "syscon";
614 reg = <0 0x11220000 0 0x2000>;
617 afe: audio-controller {
618 compatible = "mediatek,mt7622-audio";
619 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
620 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
621 interrupt-names = "afe", "asys";
623 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
624 <&topckgen CLK_TOP_AUD1_SEL>,
625 <&topckgen CLK_TOP_AUD2_SEL>,
626 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
627 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
628 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
629 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
630 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
631 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
632 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
633 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
634 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
635 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
636 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
637 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
638 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
639 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
640 <&audsys CLK_AUDIO_I2SO1>,
641 <&audsys CLK_AUDIO_I2SO2>,
642 <&audsys CLK_AUDIO_I2SO3>,
643 <&audsys CLK_AUDIO_I2SO4>,
644 <&audsys CLK_AUDIO_I2SIN1>,
645 <&audsys CLK_AUDIO_I2SIN2>,
646 <&audsys CLK_AUDIO_I2SIN3>,
647 <&audsys CLK_AUDIO_I2SIN4>,
648 <&audsys CLK_AUDIO_ASRCO1>,
649 <&audsys CLK_AUDIO_ASRCO2>,
650 <&audsys CLK_AUDIO_ASRCO3>,
651 <&audsys CLK_AUDIO_ASRCO4>,
652 <&audsys CLK_AUDIO_AFE>,
653 <&audsys CLK_AUDIO_AFE_CONN>,
654 <&audsys CLK_AUDIO_A1SYS>,
655 <&audsys CLK_AUDIO_A2SYS>;
657 clock-names = "infra_sys_audio_clk",
658 "top_audio_mux1_sel",
659 "top_audio_mux2_sel",
660 "top_audio_a1sys_hp",
661 "top_audio_a2sys_hp",
691 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
692 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
693 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
694 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
695 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
696 <&topckgen CLK_TOP_AUD2PLL>;
697 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
702 compatible = "mediatek,mt7622-mmc";
703 reg = <0 0x11230000 0 0x1000>;
704 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
705 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
706 <&topckgen CLK_TOP_MSDC50_0_SEL>;
707 clock-names = "source", "hclk";
708 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
709 reset-names = "hrst";
714 compatible = "mediatek,mt7622-mmc";
715 reg = <0 0x11240000 0 0x1000>;
716 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
717 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
718 <&topckgen CLK_TOP_AXI_SEL>;
719 clock-names = "source", "hclk";
720 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
721 reset-names = "hrst";
725 wmac: wmac@18000000 {
726 compatible = "mediatek,mt7622-wmac";
727 reg = <0 0x18000000 0 0x100000>;
728 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
730 mediatek,infracfg = <&infracfg>;
733 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
736 ssusbsys: ssusbsys@1a000000 {
737 compatible = "mediatek,mt7622-ssusbsys",
739 reg = <0 0x1a000000 0 0x1000>;
744 ssusb: usb@1a0c0000 {
745 compatible = "mediatek,mt7622-xhci",
747 reg = <0 0x1a0c0000 0 0x01000>,
748 <0 0x1a0c4700 0 0x0100>;
749 reg-names = "mac", "ippc";
750 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
751 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
752 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
753 <&ssusbsys CLK_SSUSB_REF_EN>,
754 <&ssusbsys CLK_SSUSB_MCU_EN>,
755 <&ssusbsys CLK_SSUSB_DMA_EN>;
756 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
757 phys = <&u2port0 PHY_TYPE_USB2>,
758 <&u3port0 PHY_TYPE_USB3>,
759 <&u2port1 PHY_TYPE_USB2>;
764 u3phy: t-phy@1a0c4000 {
765 compatible = "mediatek,mt7622-tphy",
766 "mediatek,generic-tphy-v1";
767 reg = <0 0x1a0c4000 0 0x700>;
768 #address-cells = <2>;
773 u2port0: usb-phy@1a0c4800 {
774 reg = <0 0x1a0c4800 0 0x0100>;
776 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
780 u3port0: usb-phy@1a0c4900 {
781 reg = <0 0x1a0c4900 0 0x0700>;
787 u2port1: usb-phy@1a0c5000 {
788 reg = <0 0x1a0c5000 0 0x0100>;
790 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
795 pciesys: pciesys@1a100800 {
796 compatible = "mediatek,mt7622-pciesys",
798 reg = <0 0x1a100800 0 0x1000>;
803 pciecfg: pciecfg@1a140000 {
804 compatible = "mediatek,generic-pciecfg", "syscon";
805 reg = <0 0x1a140000 0 0x1000>;
808 pcie0: pcie@1a143000 {
809 compatible = "mediatek,mt7622-pcie";
811 reg = <0 0x1a143000 0 0x1000>;
813 linux,pci-domain = <0>;
814 #address-cells = <3>;
816 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
817 interrupt-names = "pcie_irq";
818 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
819 <&pciesys CLK_PCIE_P0_AHB_EN>,
820 <&pciesys CLK_PCIE_P0_AUX_EN>,
821 <&pciesys CLK_PCIE_P0_AXI_EN>,
822 <&pciesys CLK_PCIE_P0_OBFF_EN>,
823 <&pciesys CLK_PCIE_P0_PIPE_EN>;
824 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
825 "axi_ck0", "obff_ck0", "pipe_ck0";
827 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
828 bus-range = <0x00 0xff>;
829 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
832 #interrupt-cells = <1>;
833 interrupt-map-mask = <0 0 0 7>;
834 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
835 <0 0 0 2 &pcie_intc0 1>,
836 <0 0 0 3 &pcie_intc0 2>,
837 <0 0 0 4 &pcie_intc0 3>;
838 pcie_intc0: interrupt-controller {
839 interrupt-controller;
840 #address-cells = <0>;
841 #interrupt-cells = <1>;
845 pcie1: pcie@1a145000 {
846 compatible = "mediatek,mt7622-pcie";
848 reg = <0 0x1a145000 0 0x1000>;
850 linux,pci-domain = <1>;
851 #address-cells = <3>;
853 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
854 interrupt-names = "pcie_irq";
855 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
856 /* designer has connect RC1 with p0_ahb clock */
857 <&pciesys CLK_PCIE_P0_AHB_EN>,
858 <&pciesys CLK_PCIE_P1_AUX_EN>,
859 <&pciesys CLK_PCIE_P1_AXI_EN>,
860 <&pciesys CLK_PCIE_P1_OBFF_EN>,
861 <&pciesys CLK_PCIE_P1_PIPE_EN>;
862 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
863 "axi_ck1", "obff_ck1", "pipe_ck1";
865 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
866 bus-range = <0x00 0xff>;
867 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
870 #interrupt-cells = <1>;
871 interrupt-map-mask = <0 0 0 7>;
872 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
873 <0 0 0 2 &pcie_intc1 1>,
874 <0 0 0 3 &pcie_intc1 2>,
875 <0 0 0 4 &pcie_intc1 3>;
876 pcie_intc1: interrupt-controller {
877 interrupt-controller;
878 #address-cells = <0>;
879 #interrupt-cells = <1>;
883 sata: sata@1a200000 {
884 compatible = "mediatek,mt7622-ahci",
886 reg = <0 0x1a200000 0 0x1100>;
887 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
888 interrupt-names = "hostc";
889 clocks = <&pciesys CLK_SATA_AHB_EN>,
890 <&pciesys CLK_SATA_AXI_EN>,
891 <&pciesys CLK_SATA_ASIC_EN>,
892 <&pciesys CLK_SATA_RBC_EN>,
893 <&pciesys CLK_SATA_PM_EN>;
894 clock-names = "ahb", "axi", "asic", "rbc", "pm";
895 phys = <&sata_port PHY_TYPE_SATA>;
896 phy-names = "sata-phy";
897 ports-implemented = <0x1>;
898 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
899 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
900 <&pciesys MT7622_SATA_PHY_SW_RST>,
901 <&pciesys MT7622_SATA_PHY_REG_RST>;
902 reset-names = "axi", "sw", "reg";
903 mediatek,phy-mode = <&pciesys>;
907 sata_phy: t-phy@1a243000 {
908 compatible = "mediatek,mt7622-tphy",
909 "mediatek,generic-tphy-v1";
910 #address-cells = <2>;
915 sata_port: sata-phy@1a243000 {
916 reg = <0 0x1a243000 0 0x0100>;
917 clocks = <&topckgen CLK_TOP_ETH_500M>;
923 hifsys: syscon@1af00000 {
924 compatible = "mediatek,mt7622-hifsys", "syscon";
925 reg = <0 0x1af00000 0 0x70>;
928 ethsys: syscon@1b000000 {
929 compatible = "mediatek,mt7622-ethsys",
931 reg = <0 0x1b000000 0 0x1000>;
936 hsdma: dma-controller@1b007000 {
937 compatible = "mediatek,mt7622-hsdma";
938 reg = <0 0x1b007000 0 0x1000>;
939 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
940 clocks = <ðsys CLK_ETH_HSDMA_EN>;
941 clock-names = "hsdma";
942 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
947 pcie_mirror: pcie-mirror@10000400 {
948 compatible = "mediatek,mt7622-pcie-mirror",
950 reg = <0 0x10000400 0 0x10>;
954 compatible = "mediatek,mt7622-wed",
956 reg = <0 0x1020a000 0 0x1000>;
957 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
961 compatible = "mediatek,mt7622-wed",
963 reg = <0 0x1020b000 0 0x1000>;
964 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
967 eth: ethernet@1b100000 {
968 compatible = "mediatek,mt7622-eth",
969 "mediatek,mt2701-eth",
971 reg = <0 0x1b100000 0 0x20000>;
972 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
973 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
974 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
975 clocks = <&topckgen CLK_TOP_ETH_SEL>,
976 <ðsys CLK_ETH_ESW_EN>,
977 <ðsys CLK_ETH_GP0_EN>,
978 <ðsys CLK_ETH_GP1_EN>,
979 <ðsys CLK_ETH_GP2_EN>,
980 <&sgmiisys CLK_SGMII_TX250M_EN>,
981 <&sgmiisys CLK_SGMII_RX250M_EN>,
982 <&sgmiisys CLK_SGMII_CDR_REF>,
983 <&sgmiisys CLK_SGMII_CDR_FB>,
984 <&topckgen CLK_TOP_SGMIIPLL>,
985 <&apmixedsys CLK_APMIXED_ETH2PLL>;
986 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
987 "sgmii_tx250m", "sgmii_rx250m",
988 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
990 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
991 mediatek,ethsys = <ðsys>;
992 mediatek,sgmiisys = <&sgmiisys>;
993 cci-control-port = <&cci_control2>;
994 mediatek,wed = <&wed0>, <&wed1>;
995 mediatek,pcie-mirror = <&pcie_mirror>;
996 mediatek,hifsys = <&hifsys>;
998 #address-cells = <1>;
1000 status = "disabled";
1003 sgmiisys: sgmiisys@1b128000 {
1004 compatible = "mediatek,mt7622-sgmiisys",
1006 reg = <0 0x1b128000 0 0x3000>;