2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: YT Shen <yt.shen@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "mediatek,mt2712";
13 interrupt-parent = <&sysirq>;
40 compatible = "arm,cortex-a35";
42 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
47 compatible = "arm,cortex-a35";
49 enable-method = "psci";
50 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
55 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
62 entry-method = "arm,psci";
64 CPU_SLEEP_0: cpu-sleep-0 {
65 compatible = "arm,idle-state";
67 entry-latency-us = <100>;
68 exit-latency-us = <80>;
69 min-residency-us = <2000>;
70 arm,psci-suspend-param = <0x0010000>;
73 CLUSTER_SLEEP_0: cluster-sleep-0 {
74 compatible = "arm,idle-state";
76 entry-latency-us = <350>;
77 exit-latency-us = <80>;
78 min-residency-us = <3000>;
79 arm,psci-suspend-param = <0x1010000>;
85 compatible = "arm,psci-0.2";
90 compatible = "fixed-clock";
91 clock-frequency = <26000000>;
96 compatible = "fixed-clock";
97 clock-frequency = <26000000>;
102 compatible = "arm,armv8-timer";
103 interrupt-parent = <&gic>;
104 interrupts = <GIC_PPI 13
105 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
107 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
109 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
111 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
114 uart5: serial@1000f000 {
115 compatible = "mediatek,mt2712-uart",
116 "mediatek,mt6577-uart";
117 reg = <0 0x1000f000 0 0x400>;
118 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
119 clocks = <&baud_clk>, <&sys_clk>;
120 clock-names = "baud", "bus";
124 sysirq: interrupt-controller@10220a80 {
125 compatible = "mediatek,mt2712-sysirq",
126 "mediatek,mt6577-sysirq";
127 interrupt-controller;
128 #interrupt-cells = <3>;
129 interrupt-parent = <&gic>;
130 reg = <0 0x10220a80 0 0x40>;
133 gic: interrupt-controller@10510000 {
134 compatible = "arm,gic-400";
135 #interrupt-cells = <3>;
136 interrupt-parent = <&gic>;
137 interrupt-controller;
138 reg = <0 0x10510000 0 0x10000>,
139 <0 0x10520000 0 0x20000>,
140 <0 0x10540000 0 0x20000>,
141 <0 0x10560000 0 0x20000>;
142 interrupts = <GIC_PPI 9
143 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
146 uart0: serial@11002000 {
147 compatible = "mediatek,mt2712-uart",
148 "mediatek,mt6577-uart";
149 reg = <0 0x11002000 0 0x400>;
150 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
151 clocks = <&baud_clk>, <&sys_clk>;
152 clock-names = "baud", "bus";
156 uart1: serial@11003000 {
157 compatible = "mediatek,mt2712-uart",
158 "mediatek,mt6577-uart";
159 reg = <0 0x11003000 0 0x400>;
160 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
161 clocks = <&baud_clk>, <&sys_clk>;
162 clock-names = "baud", "bus";
166 uart2: serial@11004000 {
167 compatible = "mediatek,mt2712-uart",
168 "mediatek,mt6577-uart";
169 reg = <0 0x11004000 0 0x400>;
170 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
171 clocks = <&baud_clk>, <&sys_clk>;
172 clock-names = "baud", "bus";
176 uart3: serial@11005000 {
177 compatible = "mediatek,mt2712-uart",
178 "mediatek,mt6577-uart";
179 reg = <0 0x11005000 0 0x400>;
180 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
181 clocks = <&baud_clk>, <&sys_clk>;
182 clock-names = "baud", "bus";
186 uart4: serial@11019000 {
187 compatible = "mediatek,mt2712-uart",
188 "mediatek,mt6577-uart";
189 reg = <0 0x11019000 0 0x400>;
190 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
191 clocks = <&baud_clk>, <&sys_clk>;
192 clock-names = "baud", "bus";