1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9130-DB board.
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Marvell Armada CN9130-DB";
16 stdout-path = "serial0:115200n8";
23 ethernet0 = &cp0_eth0;
24 ethernet1 = &cp0_eth1;
25 ethernet2 = &cp0_eth2;
31 device_type = "memory";
32 reg = <0x0 0x0 0x0 0x80000000>;
35 ap0_reg_sd_vccq: ap0_sd_vccq@0 {
36 compatible = "regulator-gpio";
37 regulator-name = "ap0_sd_vccq";
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <3300000>;
40 gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
41 states = <1800000 0x1 3300000 0x0>;
44 cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
45 compatible = "regulator-fixed";
46 regulator-name = "cp0-xhci0-vbus";
47 regulator-min-microvolt = <5000000>;
48 regulator-max-microvolt = <5000000>;
50 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
53 cp0_usb3_0_phy0: cp0_usb3_phy@0 {
54 compatible = "usb-nop-xceiv";
55 vcc-supply = <&cp0_reg_usb3_vbus0>;
58 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
59 compatible = "regulator-fixed";
60 regulator-name = "cp0-xhci1-vbus";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
64 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
67 cp0_usb3_0_phy1: cp0_usb3_phy@1 {
68 compatible = "usb-nop-xceiv";
69 vcc-supply = <&cp0_reg_usb3_vbus1>;
72 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
73 compatible = "regulator-gpio";
74 regulator-name = "cp0_sd_vccq";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <3300000>;
77 gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
82 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
83 compatible = "regulator-fixed";
84 regulator-name = "cp0_sd_vcc";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
92 cp0_sfp_eth0: sfp-eth@0 {
93 compatible = "sff,sfp";
94 i2c-bus = <&cp0_sfpp0_i2c>;
95 los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
96 mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
97 tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
98 tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
100 * SFP cages are unconnected on early PCBs because of an the I2C
101 * lanes not being connected. Prevent the port for being
102 * unusable by disabling the SFP node.
112 /* on-board eMMC - U9 */
114 pinctrl-names = "default";
118 vqmmc-supply = <&ap0_reg_sd_vccq>;
130 /* SLM-1521-V2, CON9 */
133 phy-mode = "10gbase-kr";
134 /* Generic PHY, providing serdes lanes */
135 phys = <&cp0_comphy4 0>;
136 managed = "in-band-status";
137 sfp = <&cp0_sfp_eth0>;
144 phy-mode = "rgmii-id";
151 phy-mode = "rgmii-id";
164 pinctrl-names = "default";
165 pinctrl-0 = <&cp0_i2c0_pins>;
166 clock-frequency = <100000>;
169 expander0: pca953x@21 {
170 compatible = "nxp,pca9555";
171 pinctrl-names = "default";
180 compatible = "atmel,24c64";
187 compatible = "atmel,24c64";
195 clock-frequency = <100000>;
197 /* SLM-1521-V2 - U3 */
198 i2c-mux@72 { /* verify address - depends on dpr */
199 compatible = "nxp,pca9544";
200 #address-cells = <1>;
203 cp0_sfpp0_i2c: i2c@0 {
204 #address-cells = <1>;
210 #address-cells = <1>;
214 cp0_module_expander1: pca9555@21 {
215 compatible = "nxp,pca9555";
216 pinctrl-names = "default";
229 phy0: ethernet-phy@0 {
233 phy1: ethernet-phy@1 {
239 &cp0_nand_controller {
240 pinctrl-names = "default";
241 pinctrl-0 = <&nand_pins &nand_rb>;
245 label = "main-storage";
247 nand-ecc-mode = "hw";
249 nand-ecc-strength = <8>;
250 nand-ecc-step-size = <512>;
253 compatible = "fixed-partitions";
254 #address-cells = <1>;
263 reg = <0x200000 0xd00000>;
266 label = "Filesystem";
267 reg = <0x1000000 0x3f000000>;
273 /* SLM-1521-V2, CON6 */
278 /* Generic PHY, providing serdes lanes */
279 phys = <&cp0_comphy0 0
288 /* SLM-1521-V2, CON2 */
291 /* Generic PHY, providing serdes lanes */
292 phys = <&cp0_comphy5 1>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&cp0_sdhci_pins
303 cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
305 vqmmc-supply = <&cp0_reg_sd_vccq>;
306 vmmc-supply = <&cp0_reg_sd_vcc>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&cp0_spi0_pins>;
314 reg = <0x700680 0x50>;
317 #address-cells = <0x1>;
319 compatible = "jedec,spi-nor";
321 /* On-board MUX does not allow higher frequencies */
322 spi-max-frequency = <40000000>;
325 compatible = "fixed-partitions";
326 #address-cells = <1>;
331 reg = <0x0 0x200000>;
335 label = "Filesystem-0";
336 reg = <0x200000 0xe00000>;
343 cp0_pinctrl: pinctrl {
344 compatible = "marvell,cp115-standalone-pinctrl";
346 cp0_i2c0_pins: cp0-i2c-pins-0 {
347 marvell,pins = "mpp37", "mpp38";
348 marvell,function = "i2c0";
350 cp0_i2c1_pins: cp0-i2c-pins-1 {
351 marvell,pins = "mpp35", "mpp36";
352 marvell,function = "i2c1";
354 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
355 marvell,pins = "mpp0", "mpp1", "mpp2",
356 "mpp3", "mpp4", "mpp5",
357 "mpp6", "mpp7", "mpp8",
358 "mpp9", "mpp10", "mpp11";
359 marvell,function = "ge0";
361 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
362 marvell,pins = "mpp44", "mpp45", "mpp46",
363 "mpp47", "mpp48", "mpp49",
364 "mpp50", "mpp51", "mpp52",
365 "mpp53", "mpp54", "mpp55";
366 marvell,function = "ge1";
368 cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
369 marvell,pins = "mpp43";
370 marvell,function = "gpio";
372 cp0_sdhci_pins: cp0-sdhi-pins-0 {
373 marvell,pins = "mpp56", "mpp57", "mpp58",
374 "mpp59", "mpp60", "mpp61";
375 marvell,function = "sdio";
377 cp0_spi0_pins: cp0-spi-pins-0 {
378 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
379 marvell,function = "spi1";
381 nand_pins: nand-pins {
382 marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
383 "mpp19", "mpp20", "mpp21", "mpp22",
384 "mpp23", "mpp24", "mpp25", "mpp26",
386 marvell,function = "dev";
389 marvell,pins = "mpp13";
390 marvell,function = "nf";
401 usb-phy = <&cp0_usb3_0_phy0>;
409 usb-phy = <&cp0_usb3_0_phy1>;