1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
13 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
17 * The contents of the node are defined below, in order to
18 * save one indentation level
20 CP11X_NAME: CP11X_NAME { };
23 * CPs only have one sensor in the thermal IC.
25 * The cooling maps are empty as there are no cooling devices.
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
35 CP11X_LABEL(crit): crit {
36 temperature = <100000>; /* mC degrees */
37 hysteresis = <2000>; /* mC degrees */
50 compatible = "simple-bus";
51 interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
54 config-space@CP11X_BASE {
57 compatible = "simple-bus";
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
61 compatible = "marvell,armada-7k-pp22";
62 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
63 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
64 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
65 <&CP11X_LABEL(clk) 1 18>;
66 clock-names = "pp_clk", "gop_clk",
67 "mg_clk", "mg_core_clk", "axi_clk";
68 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
72 CP11X_LABEL(eth0): eth0 {
73 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
74 <43 IRQ_TYPE_LEVEL_HIGH>,
75 <47 IRQ_TYPE_LEVEL_HIGH>,
76 <51 IRQ_TYPE_LEVEL_HIGH>,
77 <55 IRQ_TYPE_LEVEL_HIGH>,
78 <59 IRQ_TYPE_LEVEL_HIGH>,
79 <63 IRQ_TYPE_LEVEL_HIGH>,
80 <67 IRQ_TYPE_LEVEL_HIGH>,
81 <71 IRQ_TYPE_LEVEL_HIGH>,
82 <129 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-names = "hif0", "hif1", "hif2",
84 "hif3", "hif4", "hif5", "hif6", "hif7",
91 CP11X_LABEL(eth1): eth1 {
92 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
93 <44 IRQ_TYPE_LEVEL_HIGH>,
94 <48 IRQ_TYPE_LEVEL_HIGH>,
95 <52 IRQ_TYPE_LEVEL_HIGH>,
96 <56 IRQ_TYPE_LEVEL_HIGH>,
97 <60 IRQ_TYPE_LEVEL_HIGH>,
98 <64 IRQ_TYPE_LEVEL_HIGH>,
99 <68 IRQ_TYPE_LEVEL_HIGH>,
100 <72 IRQ_TYPE_LEVEL_HIGH>,
101 <128 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "hif0", "hif1", "hif2",
103 "hif3", "hif4", "hif5", "hif6", "hif7",
110 CP11X_LABEL(eth2): eth2 {
111 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
112 <45 IRQ_TYPE_LEVEL_HIGH>,
113 <49 IRQ_TYPE_LEVEL_HIGH>,
114 <53 IRQ_TYPE_LEVEL_HIGH>,
115 <57 IRQ_TYPE_LEVEL_HIGH>,
116 <61 IRQ_TYPE_LEVEL_HIGH>,
117 <65 IRQ_TYPE_LEVEL_HIGH>,
118 <69 IRQ_TYPE_LEVEL_HIGH>,
119 <73 IRQ_TYPE_LEVEL_HIGH>,
120 <127 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-names = "hif0", "hif1", "hif2",
122 "hif3", "hif4", "hif5", "hif6", "hif7",
130 CP11X_LABEL(comphy): phy@120000 {
131 compatible = "marvell,comphy-cp110";
132 reg = <0x120000 0x6000>;
133 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
134 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
135 <&CP11X_LABEL(clk) 1 18>;
136 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
137 #address-cells = <1>;
140 CP11X_LABEL(comphy0): phy@0 {
145 CP11X_LABEL(comphy1): phy@1 {
150 CP11X_LABEL(comphy2): phy@2 {
155 CP11X_LABEL(comphy3): phy@3 {
160 CP11X_LABEL(comphy4): phy@4 {
165 CP11X_LABEL(comphy5): phy@5 {
171 CP11X_LABEL(mdio): mdio@12a200 {
172 #address-cells = <1>;
174 compatible = "marvell,orion-mdio";
175 reg = <0x12a200 0x10>;
176 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
177 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
181 CP11X_LABEL(xmdio): mdio@12a600 {
182 #address-cells = <1>;
184 compatible = "marvell,xmdio";
185 reg = <0x12a600 0x10>;
186 clocks = <&CP11X_LABEL(clk) 1 5>,
187 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
191 CP11X_LABEL(icu): interrupt-controller@1e0000 {
192 compatible = "marvell,cp110-icu";
193 reg = <0x1e0000 0x440>;
194 #address-cells = <1>;
197 CP11X_LABEL(icu_nsr): interrupt-controller@10 {
198 compatible = "marvell,cp110-icu-nsr";
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 msi-parent = <&gicp>;
205 CP11X_LABEL(icu_sei): interrupt-controller@50 {
206 compatible = "marvell,cp110-icu-sei";
208 #interrupt-cells = <2>;
209 interrupt-controller;
214 CP11X_LABEL(rtc): rtc@284000 {
215 compatible = "marvell,armada-8k-rtc";
216 reg = <0x284000 0x20>, <0x284080 0x24>;
217 reg-names = "rtc", "rtc-soc";
218 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
221 CP11X_LABEL(syscon0): system-controller@440000 {
222 compatible = "syscon", "simple-mfd";
223 reg = <0x440000 0x2000>;
225 CP11X_LABEL(clk): clock {
226 compatible = "marvell,cp110-clock";
230 CP11X_LABEL(gpio1): gpio@100 {
231 compatible = "marvell,armada-8k-gpio";
236 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
237 marvell,pwm-offset = <0x1f0>;
239 interrupt-controller;
240 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
241 <85 IRQ_TYPE_LEVEL_HIGH>,
242 <84 IRQ_TYPE_LEVEL_HIGH>,
243 <83 IRQ_TYPE_LEVEL_HIGH>;
244 #interrupt-cells = <2>;
245 clock-names = "core", "axi";
246 clocks = <&CP11X_LABEL(clk) 1 21>,
247 <&CP11X_LABEL(clk) 1 17>;
251 CP11X_LABEL(gpio2): gpio@140 {
252 compatible = "marvell,armada-8k-gpio";
257 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
258 marvell,pwm-offset = <0x1f0>;
260 interrupt-controller;
261 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
262 <81 IRQ_TYPE_LEVEL_HIGH>,
263 <80 IRQ_TYPE_LEVEL_HIGH>,
264 <79 IRQ_TYPE_LEVEL_HIGH>;
265 #interrupt-cells = <2>;
266 clock-names = "core", "axi";
267 clocks = <&CP11X_LABEL(clk) 1 21>,
268 <&CP11X_LABEL(clk) 1 17>;
273 CP11X_LABEL(syscon1): system-controller@400000 {
274 compatible = "syscon", "simple-mfd";
275 reg = <0x400000 0x1000>;
276 #address-cells = <1>;
279 CP11X_LABEL(thermal): thermal-sensor@70 {
280 compatible = "marvell,armada-cp110-thermal";
282 interrupts-extended =
283 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
284 #thermal-sensor-cells = <1>;
288 CP11X_LABEL(usb3_0): usb@500000 {
289 compatible = "marvell,armada-8k-xhci",
291 reg = <0x500000 0x4000>;
293 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
294 clock-names = "core", "reg";
295 clocks = <&CP11X_LABEL(clk) 1 22>,
296 <&CP11X_LABEL(clk) 1 16>;
300 CP11X_LABEL(usb3_1): usb@510000 {
301 compatible = "marvell,armada-8k-xhci",
303 reg = <0x510000 0x4000>;
305 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
306 clock-names = "core", "reg";
307 clocks = <&CP11X_LABEL(clk) 1 23>,
308 <&CP11X_LABEL(clk) 1 16>;
312 CP11X_LABEL(sata0): sata@540000 {
313 compatible = "marvell,armada-8k-ahci";
314 reg = <0x540000 0x30000>;
316 clocks = <&CP11X_LABEL(clk) 1 15>,
317 <&CP11X_LABEL(clk) 1 16>;
318 #address-cells = <1>;
323 interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
328 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
333 CP11X_LABEL(xor0): xor@6a0000 {
334 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
335 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
337 msi-parent = <&gic_v2m0>;
338 clock-names = "core", "reg";
339 clocks = <&CP11X_LABEL(clk) 1 8>,
340 <&CP11X_LABEL(clk) 1 14>;
343 CP11X_LABEL(xor1): xor@6c0000 {
344 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
345 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
347 msi-parent = <&gic_v2m0>;
348 clock-names = "core", "reg";
349 clocks = <&CP11X_LABEL(clk) 1 7>,
350 <&CP11X_LABEL(clk) 1 14>;
353 CP11X_LABEL(spi0): spi@700600 {
354 compatible = "marvell,armada-380-spi";
355 reg = <0x700600 0x50>;
356 #address-cells = <0x1>;
358 clock-names = "core", "axi";
359 clocks = <&CP11X_LABEL(clk) 1 21>,
360 <&CP11X_LABEL(clk) 1 17>;
364 CP11X_LABEL(spi1): spi@700680 {
365 compatible = "marvell,armada-380-spi";
366 reg = <0x700680 0x50>;
367 #address-cells = <1>;
369 clock-names = "core", "axi";
370 clocks = <&CP11X_LABEL(clk) 1 21>,
371 <&CP11X_LABEL(clk) 1 17>;
375 CP11X_LABEL(i2c0): i2c@701000 {
376 compatible = "marvell,mv78230-i2c";
377 reg = <0x701000 0x20>;
378 #address-cells = <1>;
380 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
381 clock-names = "core", "reg";
382 clocks = <&CP11X_LABEL(clk) 1 21>,
383 <&CP11X_LABEL(clk) 1 17>;
387 CP11X_LABEL(i2c1): i2c@701100 {
388 compatible = "marvell,mv78230-i2c";
389 reg = <0x701100 0x20>;
390 #address-cells = <1>;
392 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
393 clock-names = "core", "reg";
394 clocks = <&CP11X_LABEL(clk) 1 21>,
395 <&CP11X_LABEL(clk) 1 17>;
399 CP11X_LABEL(uart0): serial@702000 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0x702000 0x100>;
403 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
405 clock-names = "baudclk", "apb_pclk";
406 clocks = <&CP11X_LABEL(clk) 1 21>,
407 <&CP11X_LABEL(clk) 1 17>;
411 CP11X_LABEL(uart1): serial@702100 {
412 compatible = "snps,dw-apb-uart";
413 reg = <0x702100 0x100>;
415 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
417 clock-names = "baudclk", "apb_pclk";
418 clocks = <&CP11X_LABEL(clk) 1 21>,
419 <&CP11X_LABEL(clk) 1 17>;
423 CP11X_LABEL(uart2): serial@702200 {
424 compatible = "snps,dw-apb-uart";
425 reg = <0x702200 0x100>;
427 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
429 clock-names = "baudclk", "apb_pclk";
430 clocks = <&CP11X_LABEL(clk) 1 21>,
431 <&CP11X_LABEL(clk) 1 17>;
435 CP11X_LABEL(uart3): serial@702300 {
436 compatible = "snps,dw-apb-uart";
437 reg = <0x702300 0x100>;
439 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
441 clock-names = "baudclk", "apb_pclk";
442 clocks = <&CP11X_LABEL(clk) 1 21>,
443 <&CP11X_LABEL(clk) 1 17>;
447 CP11X_LABEL(nand_controller): nand@720000 {
449 * Due to the limitation of the pins available
450 * this controller is only usable on the CPM
451 * for A7K and on the CPS for A8K.
453 compatible = "marvell,armada-8k-nand-controller",
454 "marvell,armada370-nand-controller";
455 reg = <0x720000 0x54>;
456 #address-cells = <1>;
458 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
459 clock-names = "core", "reg";
460 clocks = <&CP11X_LABEL(clk) 1 2>,
461 <&CP11X_LABEL(clk) 1 17>;
462 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
466 CP11X_LABEL(trng): trng@760000 {
467 compatible = "marvell,armada-8k-rng",
468 "inside-secure,safexcel-eip76";
469 reg = <0x760000 0x7d>;
470 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
471 clock-names = "core", "reg";
472 clocks = <&CP11X_LABEL(clk) 1 25>,
473 <&CP11X_LABEL(clk) 1 17>;
477 CP11X_LABEL(sdhci0): sdhci@780000 {
478 compatible = "marvell,armada-cp110-sdhci";
479 reg = <0x780000 0x300>;
480 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
481 clock-names = "core", "axi";
482 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
487 CP11X_LABEL(crypto): crypto@800000 {
488 compatible = "inside-secure,safexcel-eip197b";
489 reg = <0x800000 0x200000>;
490 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
491 <88 IRQ_TYPE_LEVEL_HIGH>,
492 <89 IRQ_TYPE_LEVEL_HIGH>,
493 <90 IRQ_TYPE_LEVEL_HIGH>,
494 <91 IRQ_TYPE_LEVEL_HIGH>,
495 <92 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-names = "mem", "ring0", "ring1",
497 "ring2", "ring3", "eip";
498 clock-names = "core", "reg";
499 clocks = <&CP11X_LABEL(clk) 1 26>,
500 <&CP11X_LABEL(clk) 1 17>;
505 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
506 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
507 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
508 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
509 reg-names = "ctrl", "config";
510 #address-cells = <3>;
512 #interrupt-cells = <1>;
515 msi-parent = <&gic_v2m0>;
517 bus-range = <0 0xff>;
518 /* non-prefetchable memory */
519 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
520 interrupt-map-mask = <0 0 0 0>;
521 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
522 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
524 clock-names = "core", "reg";
525 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
529 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
530 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
531 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
532 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
533 reg-names = "ctrl", "config";
534 #address-cells = <3>;
536 #interrupt-cells = <1>;
539 msi-parent = <&gic_v2m0>;
541 bus-range = <0 0xff>;
542 /* non-prefetchable memory */
543 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
544 interrupt-map-mask = <0 0 0 0>;
545 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
546 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
549 clock-names = "core", "reg";
550 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
554 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
555 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
556 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
557 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
558 reg-names = "ctrl", "config";
559 #address-cells = <3>;
561 #interrupt-cells = <1>;
564 msi-parent = <&gic_v2m0>;
566 bus-range = <0 0xff>;
567 /* non-prefetchable memory */
568 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
569 interrupt-map-mask = <0 0 0 0>;
570 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
571 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
574 clock-names = "core", "reg";
575 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;