1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
13 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
17 * The contents of the node are defined below, in order to
18 * save one indentation level
20 CP11X_NAME: CP11X_NAME { };
23 * CPs only have one sensor in the thermal IC.
25 * The cooling maps are empty as there are no cooling devices.
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
35 CP11X_LABEL(crit): crit {
36 temperature = <100000>; /* mC degrees */
37 hysteresis = <2000>; /* mC degrees */
50 compatible = "simple-bus";
51 interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
54 config-space@CP11X_BASE {
57 compatible = "simple-bus";
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
61 compatible = "marvell,armada-7k-pp22";
62 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
63 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
64 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
65 <&CP11X_LABEL(clk) 1 18>;
66 clock-names = "pp_clk", "gop_clk",
67 "mg_clk", "mg_core_clk", "axi_clk";
68 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
72 CP11X_LABEL(eth0): eth0 {
73 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
74 <43 IRQ_TYPE_LEVEL_HIGH>,
75 <47 IRQ_TYPE_LEVEL_HIGH>,
76 <51 IRQ_TYPE_LEVEL_HIGH>,
77 <55 IRQ_TYPE_LEVEL_HIGH>,
78 <59 IRQ_TYPE_LEVEL_HIGH>,
79 <63 IRQ_TYPE_LEVEL_HIGH>,
80 <67 IRQ_TYPE_LEVEL_HIGH>,
81 <71 IRQ_TYPE_LEVEL_HIGH>,
82 <129 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-names = "hif0", "hif1", "hif2",
84 "hif3", "hif4", "hif5", "hif6", "hif7",
91 CP11X_LABEL(eth1): eth1 {
92 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
93 <44 IRQ_TYPE_LEVEL_HIGH>,
94 <48 IRQ_TYPE_LEVEL_HIGH>,
95 <52 IRQ_TYPE_LEVEL_HIGH>,
96 <56 IRQ_TYPE_LEVEL_HIGH>,
97 <60 IRQ_TYPE_LEVEL_HIGH>,
98 <64 IRQ_TYPE_LEVEL_HIGH>,
99 <68 IRQ_TYPE_LEVEL_HIGH>,
100 <72 IRQ_TYPE_LEVEL_HIGH>,
101 <128 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "hif0", "hif1", "hif2",
103 "hif3", "hif4", "hif5", "hif6", "hif7",
110 CP11X_LABEL(eth2): eth2 {
111 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
112 <45 IRQ_TYPE_LEVEL_HIGH>,
113 <49 IRQ_TYPE_LEVEL_HIGH>,
114 <53 IRQ_TYPE_LEVEL_HIGH>,
115 <57 IRQ_TYPE_LEVEL_HIGH>,
116 <61 IRQ_TYPE_LEVEL_HIGH>,
117 <65 IRQ_TYPE_LEVEL_HIGH>,
118 <69 IRQ_TYPE_LEVEL_HIGH>,
119 <73 IRQ_TYPE_LEVEL_HIGH>,
120 <127 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-names = "hif0", "hif1", "hif2",
122 "hif3", "hif4", "hif5", "hif6", "hif7",
130 CP11X_LABEL(comphy): phy@120000 {
131 compatible = "marvell,comphy-cp110";
132 reg = <0x120000 0x6000>;
133 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
134 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
135 <&CP11X_LABEL(clk) 1 18>;
136 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
137 #address-cells = <1>;
140 CP11X_LABEL(comphy0): phy@0 {
145 CP11X_LABEL(comphy1): phy@1 {
150 CP11X_LABEL(comphy2): phy@2 {
155 CP11X_LABEL(comphy3): phy@3 {
160 CP11X_LABEL(comphy4): phy@4 {
165 CP11X_LABEL(comphy5): phy@5 {
171 CP11X_LABEL(mdio): mdio@12a200 {
172 #address-cells = <1>;
174 compatible = "marvell,orion-mdio";
175 reg = <0x12a200 0x10>;
176 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
177 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
181 CP11X_LABEL(xmdio): mdio@12a600 {
182 #address-cells = <1>;
184 compatible = "marvell,xmdio";
185 reg = <0x12a600 0x10>;
186 clocks = <&CP11X_LABEL(clk) 1 5>,
187 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
191 CP11X_LABEL(icu): interrupt-controller@1e0000 {
192 compatible = "marvell,cp110-icu";
193 reg = <0x1e0000 0x440>;
194 #address-cells = <1>;
197 CP11X_LABEL(icu_nsr): interrupt-controller@10 {
198 compatible = "marvell,cp110-icu-nsr";
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 msi-parent = <&gicp>;
205 CP11X_LABEL(icu_sei): interrupt-controller@50 {
206 compatible = "marvell,cp110-icu-sei";
208 #interrupt-cells = <2>;
209 interrupt-controller;
214 CP11X_LABEL(rtc): rtc@284000 {
215 compatible = "marvell,armada-8k-rtc";
216 reg = <0x284000 0x20>, <0x284080 0x24>;
217 reg-names = "rtc", "rtc-soc";
218 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
221 CP11X_LABEL(syscon0): system-controller@440000 {
222 compatible = "syscon", "simple-mfd";
223 reg = <0x440000 0x2000>;
225 CP11X_LABEL(clk): clock {
226 compatible = "marvell,cp110-clock";
230 CP11X_LABEL(gpio1): gpio@100 {
231 compatible = "marvell,armada-8k-gpio";
236 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
237 marvell,pwm-offset = <0x1f0>;
239 interrupt-controller;
240 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
241 <85 IRQ_TYPE_LEVEL_HIGH>,
242 <84 IRQ_TYPE_LEVEL_HIGH>,
243 <83 IRQ_TYPE_LEVEL_HIGH>;
244 #interrupt-cells = <2>;
245 clock-names = "core", "axi";
246 clocks = <&CP11X_LABEL(clk) 1 21>,
247 <&CP11X_LABEL(clk) 1 17>;
251 CP11X_LABEL(gpio2): gpio@140 {
252 compatible = "marvell,armada-8k-gpio";
257 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
258 marvell,pwm-offset = <0x1f0>;
260 interrupt-controller;
261 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
262 <81 IRQ_TYPE_LEVEL_HIGH>,
263 <80 IRQ_TYPE_LEVEL_HIGH>,
264 <79 IRQ_TYPE_LEVEL_HIGH>;
265 #interrupt-cells = <2>;
266 clock-names = "core", "axi";
267 clocks = <&CP11X_LABEL(clk) 1 21>,
268 <&CP11X_LABEL(clk) 1 17>;
273 CP11X_LABEL(syscon1): system-controller@400000 {
274 compatible = "syscon", "simple-mfd";
275 reg = <0x400000 0x1000>;
276 #address-cells = <1>;
279 CP11X_LABEL(thermal): thermal-sensor@70 {
280 compatible = "marvell,armada-cp110-thermal";
282 interrupts-extended =
283 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
284 #thermal-sensor-cells = <1>;
288 CP11X_LABEL(utmi): utmi@580000 {
289 compatible = "marvell,cp110-utmi-phy";
290 reg = <0x580000 0x2000>;
291 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
292 #address-cells = <1>;
296 CP11X_LABEL(utmi0): usb-phy@0 {
301 CP11X_LABEL(utmi1): usb-phy@1 {
307 CP11X_LABEL(usb3_0): usb@500000 {
308 compatible = "marvell,armada-8k-xhci",
310 reg = <0x500000 0x4000>;
312 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
313 clock-names = "core", "reg";
314 clocks = <&CP11X_LABEL(clk) 1 22>,
315 <&CP11X_LABEL(clk) 1 16>;
319 CP11X_LABEL(usb3_1): usb@510000 {
320 compatible = "marvell,armada-8k-xhci",
322 reg = <0x510000 0x4000>;
324 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
325 clock-names = "core", "reg";
326 clocks = <&CP11X_LABEL(clk) 1 23>,
327 <&CP11X_LABEL(clk) 1 16>;
331 CP11X_LABEL(sata0): sata@540000 {
332 compatible = "marvell,armada-8k-ahci",
334 reg = <0x540000 0x30000>;
336 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&CP11X_LABEL(clk) 1 15>,
338 <&CP11X_LABEL(clk) 1 16>;
339 #address-cells = <1>;
352 CP11X_LABEL(xor0): xor@6a0000 {
353 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
354 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
356 msi-parent = <&gic_v2m0>;
357 clock-names = "core", "reg";
358 clocks = <&CP11X_LABEL(clk) 1 8>,
359 <&CP11X_LABEL(clk) 1 14>;
362 CP11X_LABEL(xor1): xor@6c0000 {
363 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
364 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
366 msi-parent = <&gic_v2m0>;
367 clock-names = "core", "reg";
368 clocks = <&CP11X_LABEL(clk) 1 7>,
369 <&CP11X_LABEL(clk) 1 14>;
372 CP11X_LABEL(spi0): spi@700600 {
373 compatible = "marvell,armada-380-spi";
374 reg = <0x700600 0x50>;
375 #address-cells = <0x1>;
377 clock-names = "core", "axi";
378 clocks = <&CP11X_LABEL(clk) 1 21>,
379 <&CP11X_LABEL(clk) 1 17>;
383 CP11X_LABEL(spi1): spi@700680 {
384 compatible = "marvell,armada-380-spi";
385 reg = <0x700680 0x50>;
386 #address-cells = <1>;
388 clock-names = "core", "axi";
389 clocks = <&CP11X_LABEL(clk) 1 21>,
390 <&CP11X_LABEL(clk) 1 17>;
394 CP11X_LABEL(i2c0): i2c@701000 {
395 compatible = "marvell,mv78230-i2c";
396 reg = <0x701000 0x20>;
397 #address-cells = <1>;
399 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
400 clock-names = "core", "reg";
401 clocks = <&CP11X_LABEL(clk) 1 21>,
402 <&CP11X_LABEL(clk) 1 17>;
406 CP11X_LABEL(i2c1): i2c@701100 {
407 compatible = "marvell,mv78230-i2c";
408 reg = <0x701100 0x20>;
409 #address-cells = <1>;
411 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
412 clock-names = "core", "reg";
413 clocks = <&CP11X_LABEL(clk) 1 21>,
414 <&CP11X_LABEL(clk) 1 17>;
418 CP11X_LABEL(uart0): serial@702000 {
419 compatible = "snps,dw-apb-uart";
420 reg = <0x702000 0x100>;
422 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
424 clock-names = "baudclk", "apb_pclk";
425 clocks = <&CP11X_LABEL(clk) 1 21>,
426 <&CP11X_LABEL(clk) 1 17>;
430 CP11X_LABEL(uart1): serial@702100 {
431 compatible = "snps,dw-apb-uart";
432 reg = <0x702100 0x100>;
434 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
436 clock-names = "baudclk", "apb_pclk";
437 clocks = <&CP11X_LABEL(clk) 1 21>,
438 <&CP11X_LABEL(clk) 1 17>;
442 CP11X_LABEL(uart2): serial@702200 {
443 compatible = "snps,dw-apb-uart";
444 reg = <0x702200 0x100>;
446 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
448 clock-names = "baudclk", "apb_pclk";
449 clocks = <&CP11X_LABEL(clk) 1 21>,
450 <&CP11X_LABEL(clk) 1 17>;
454 CP11X_LABEL(uart3): serial@702300 {
455 compatible = "snps,dw-apb-uart";
456 reg = <0x702300 0x100>;
458 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
460 clock-names = "baudclk", "apb_pclk";
461 clocks = <&CP11X_LABEL(clk) 1 21>,
462 <&CP11X_LABEL(clk) 1 17>;
466 CP11X_LABEL(nand_controller): nand@720000 {
468 * Due to the limitation of the pins available
469 * this controller is only usable on the CPM
470 * for A7K and on the CPS for A8K.
472 compatible = "marvell,armada-8k-nand-controller",
473 "marvell,armada370-nand-controller";
474 reg = <0x720000 0x54>;
475 #address-cells = <1>;
477 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
478 clock-names = "core", "reg";
479 clocks = <&CP11X_LABEL(clk) 1 2>,
480 <&CP11X_LABEL(clk) 1 17>;
481 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
485 CP11X_LABEL(trng): trng@760000 {
486 compatible = "marvell,armada-8k-rng",
487 "inside-secure,safexcel-eip76";
488 reg = <0x760000 0x7d>;
489 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
490 clock-names = "core", "reg";
491 clocks = <&CP11X_LABEL(clk) 1 25>,
492 <&CP11X_LABEL(clk) 1 17>;
496 CP11X_LABEL(sdhci0): sdhci@780000 {
497 compatible = "marvell,armada-cp110-sdhci";
498 reg = <0x780000 0x300>;
499 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
500 clock-names = "core", "axi";
501 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
506 CP11X_LABEL(crypto): crypto@800000 {
507 compatible = "inside-secure,safexcel-eip197b";
508 reg = <0x800000 0x200000>;
509 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
510 <88 IRQ_TYPE_LEVEL_HIGH>,
511 <89 IRQ_TYPE_LEVEL_HIGH>,
512 <90 IRQ_TYPE_LEVEL_HIGH>,
513 <91 IRQ_TYPE_LEVEL_HIGH>,
514 <92 IRQ_TYPE_LEVEL_HIGH>;
515 interrupt-names = "mem", "ring0", "ring1",
516 "ring2", "ring3", "eip";
517 clock-names = "core", "reg";
518 clocks = <&CP11X_LABEL(clk) 1 26>,
519 <&CP11X_LABEL(clk) 1 17>;
524 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
525 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
526 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
527 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
528 reg-names = "ctrl", "config";
529 #address-cells = <3>;
531 #interrupt-cells = <1>;
534 msi-parent = <&gic_v2m0>;
536 bus-range = <0 0xff>;
537 /* non-prefetchable memory */
538 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
539 interrupt-map-mask = <0 0 0 0>;
540 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
541 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
543 clock-names = "core", "reg";
544 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
548 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
549 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
550 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
551 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
552 reg-names = "ctrl", "config";
553 #address-cells = <3>;
555 #interrupt-cells = <1>;
558 msi-parent = <&gic_v2m0>;
560 bus-range = <0 0xff>;
561 /* non-prefetchable memory */
562 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
563 interrupt-map-mask = <0 0 0 0>;
564 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
565 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
568 clock-names = "core", "reg";
569 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
573 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
574 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
575 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
576 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
577 reg-names = "ctrl", "config";
578 #address-cells = <3>;
580 #interrupt-cells = <1>;
583 msi-parent = <&gic_v2m0>;
585 bus-range = <0 0xff>;
586 /* non-prefetchable memory */
587 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
588 interrupt-map-mask = <0 0 0 0>;
589 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
590 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
593 clock-names = "core", "reg";
594 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;