2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
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30 * The above copyright notice and this permission notice shall be
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44 * Device Tree file for Marvell Armada CP110 Slave.
47 #define ICU_GRP_NSR 0x0
53 compatible = "simple-bus";
54 interrupt-parent = <&cps_icu>;
57 config-space@f4000000 {
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf4000000 0x2000000>;
63 cps_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
67 clock-names = "pp_clk", "gop_clk", "mg_clk";
68 marvell,system-controller = <&cps_syscon0>;
73 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
74 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
75 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
76 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
77 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
78 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
80 "tx-cpu3", "rx-shared", "link";
87 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
88 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
89 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
90 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
91 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
92 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
94 "tx-cpu3", "rx-shared", "link";
101 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
102 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
103 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
104 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
105 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
106 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
108 "tx-cpu3", "rx-shared", "link";
115 cps_comphy: phy@120000 {
116 compatible = "marvell,comphy-cp110";
117 reg = <0x120000 0x6000>;
118 marvell,system-controller = <&cps_syscon0>;
119 #address-cells = <1>;
153 cps_mdio: mdio@12a200 {
154 #address-cells = <1>;
156 compatible = "marvell,orion-mdio";
157 reg = <0x12a200 0x10>;
158 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
162 cps_xmdio: mdio@12a600 {
163 #address-cells = <1>;
165 compatible = "marvell,xmdio";
166 reg = <0x12a600 0x10>;
170 cps_icu: interrupt-controller@1e0000 {
171 compatible = "marvell,cp110-icu";
172 reg = <0x1e0000 0x10>;
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 msi-parent = <&gicp>;
178 cps_rtc: rtc@284000 {
179 compatible = "marvell,armada-8k-rtc";
180 reg = <0x284000 0x20>, <0x284080 0x24>;
181 reg-names = "rtc", "rtc-soc";
182 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
185 cps_syscon0: system-controller@440000 {
186 compatible = "syscon", "simple-mfd";
187 reg = <0x440000 0x2000>;
190 compatible = "marvell,cp110-clock";
194 cps_gpio1: gpio@100 {
195 compatible = "marvell,armada-8k-gpio";
200 gpio-ranges = <&cps_pinctrl 0 0 32>;
201 interrupt-controller;
202 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
203 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
204 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
205 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
209 cps_gpio2: gpio@140 {
210 compatible = "marvell,armada-8k-gpio";
215 gpio-ranges = <&cps_pinctrl 0 32 31>;
216 interrupt-controller;
217 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
218 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
219 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
220 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
226 cps_usb3_0: usb3@500000 {
227 compatible = "marvell,armada-8k-xhci",
229 reg = <0x500000 0x4000>;
231 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cps_clk 1 22>;
236 cps_usb3_1: usb3@510000 {
237 compatible = "marvell,armada-8k-xhci",
239 reg = <0x510000 0x4000>;
241 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&cps_clk 1 23>;
246 cps_sata0: sata@540000 {
247 compatible = "marvell,armada-8k-ahci",
249 reg = <0x540000 0x30000>;
250 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&cps_clk 1 15>;
255 cps_xor0: xor@6a0000 {
256 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
257 reg = <0x6a0000 0x1000>,
260 msi-parent = <&gic_v2m0>;
261 clocks = <&cps_clk 1 8>;
264 cps_xor1: xor@6c0000 {
265 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
266 reg = <0x6c0000 0x1000>,
269 msi-parent = <&gic_v2m0>;
270 clocks = <&cps_clk 1 7>;
273 cps_spi0: spi@700600 {
274 compatible = "marvell,armada-380-spi";
275 reg = <0x700600 0x50>;
276 #address-cells = <0x1>;
279 clocks = <&cps_clk 1 21>;
283 cps_spi1: spi@700680 {
284 compatible = "marvell,armada-380-spi";
285 reg = <0x700680 0x50>;
286 #address-cells = <1>;
289 clocks = <&cps_clk 1 21>;
293 cps_i2c0: i2c@701000 {
294 compatible = "marvell,mv78230-i2c";
295 reg = <0x701000 0x20>;
296 #address-cells = <1>;
298 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cps_clk 1 21>;
303 cps_i2c1: i2c@701100 {
304 compatible = "marvell,mv78230-i2c";
305 reg = <0x701100 0x20>;
306 #address-cells = <1>;
308 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cps_clk 1 21>;
313 cps_nand: nand@720000 {
315 * Due to the limiation of the pin available
316 * this controller is only usable on the CPM
317 * for A7K and on the CPS for A8K.
319 compatible = "marvell,armada370-nand",
320 "marvell,armada370-nand";
321 reg = <0x720000 0x54>;
322 #address-cells = <1>;
324 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cps_clk 1 2>;
329 cps_trng: trng@760000 {
330 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
331 reg = <0x760000 0x7d>;
332 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cps_clk 1 25>;
337 cps_crypto: crypto@800000 {
338 compatible = "inside-secure,safexcel-eip197";
339 reg = <0x800000 0x200000>;
340 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
341 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
342 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
343 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
344 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
345 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "mem", "ring0", "ring1",
347 "ring2", "ring3", "eip";
348 clocks = <&cps_clk 1 26>;
351 * The cryptographic engine found on the cp110
352 * master is enabled by default at the SoC
353 * level. Because it is not possible as of now
354 * to enable two cryptographic engines in
355 * parallel, disable this one by default.
361 cps_pcie0: pcie@f4600000 {
362 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
363 reg = <0 0xf4600000 0 0x10000>,
364 <0 0xfaf00000 0 0x80000>;
365 reg-names = "ctrl", "config";
366 #address-cells = <3>;
368 #interrupt-cells = <1>;
371 msi-parent = <&gic_v2m0>;
373 bus-range = <0 0xff>;
376 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
377 /* non-prefetchable memory */
378 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
379 interrupt-map-mask = <0 0 0 0>;
380 interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
381 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cps_clk 1 13>;
387 cps_pcie1: pcie@f4620000 {
388 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
389 reg = <0 0xf4620000 0 0x10000>,
390 <0 0xfbf00000 0 0x80000>;
391 reg-names = "ctrl", "config";
392 #address-cells = <3>;
394 #interrupt-cells = <1>;
397 msi-parent = <&gic_v2m0>;
399 bus-range = <0 0xff>;
402 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
403 /* non-prefetchable memory */
404 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
405 interrupt-map-mask = <0 0 0 0>;
406 interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
407 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cps_clk 1 11>;
414 cps_pcie2: pcie@f4640000 {
415 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
416 reg = <0 0xf4640000 0 0x10000>,
417 <0 0xfcf00000 0 0x80000>;
418 reg-names = "ctrl", "config";
419 #address-cells = <3>;
421 #interrupt-cells = <1>;
424 msi-parent = <&gic_v2m0>;
426 bus-range = <0 0xff>;
429 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
430 /* non-prefetchable memory */
431 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
432 interrupt-map-mask = <0 0 0 0>;
433 interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
434 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&cps_clk 1 12>;