1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada 8040 Development board platform
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi"
12 model = "Marvell Armada 8040 DB board";
13 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000>;
26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth2;
28 ethernet2 = &cp1_eth0;
29 ethernet3 = &cp1_eth1;
32 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
33 compatible = "regulator-fixed";
34 regulator-name = "cp0-usb3h0-vbus";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
38 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
42 compatible = "regulator-fixed";
43 regulator-name = "cp0-usb3h1-vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
47 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50 cp0_usb3_0_phy: cp0-usb3-0-phy {
51 compatible = "usb-nop-xceiv";
52 vcc-supply = <&cp0_reg_usb3_0_vbus>;
55 cp0_usb3_1_phy: cp0-usb3-1-phy {
56 compatible = "usb-nop-xceiv";
57 vcc-supply = <&cp0_reg_usb3_1_vbus>;
60 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
61 compatible = "regulator-fixed";
62 regulator-name = "cp1-usb3h0-vbus";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
66 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
69 cp1_usb3_0_phy: cp1-usb3-0-phy {
70 compatible = "usb-nop-xceiv";
71 vcc-supply = <&cp1_reg_usb3_0_vbus>;
77 clock-frequency = <100000>;
84 compatible = "jedec,spi-nor";
86 spi-max-frequency = <10000000>;
89 compatible = "fixed-partitions";
99 reg = <0x200000 0xce0000>;
105 /* Accessible over the mini-USB CON9 connector on the main board */
108 pinctrl-0 = <&uart0_pins>;
109 pinctrl-names = "default";
112 /* CON6 on CP0 expansion */
117 /* CON5 on CP0 expansion */
124 clock-frequency = <100000>;
127 expander0: pca9555@21 {
128 compatible = "nxp,pca9555";
129 pinctrl-names = "default";
136 expander1: pca9555@25 {
137 compatible = "nxp,pca9555";
138 pinctrl-names = "default";
146 /* CON4 on CP0 expansion */
151 /* CON9 on CP0 expansion */
153 usb-phy = <&cp0_usb3_0_phy>;
157 /* CON10 on CP0 expansion */
159 usb-phy = <&cp0_usb3_1_phy>;
166 phy1: ethernet-phy@1 {
177 phy-mode = "10gbase-kr";
188 phy-mode = "rgmii-id";
191 /* CON6 on CP1 expansion */
196 /* CON7 on CP1 expansion */
201 /* CON5 on CP1 expansion */
208 clock-frequency = <100000>;
215 compatible = "jedec,spi-nor";
217 spi-max-frequency = <20000000>;
220 compatible = "fixed-partitions";
221 #address-cells = <1>;
226 reg = <0x0 0x200000>;
229 label = "Filesystem";
230 reg = <0x200000 0xd00000>;
234 reg = <0xf00000 0x100000>;
241 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
242 * MDIO signal of CP1.
244 &cp1_nand_controller {
245 pinctrl-0 = <&nand_pins>, <&nand_rb>;
246 pinctrl-names = "default";
252 nand-ecc-strength = <4>;
253 nand-ecc-step-size = <512>;
256 compatible = "fixed-partitions";
257 #address-cells = <1>;
266 reg = <0x200000 0xe00000>;
269 label = "Filesystem";
270 reg = <0x1000000 0x3f000000>;
276 /* CON4 on CP1 expansion */
281 /* CON9 on CP1 expansion */
283 usb-phy = <&cp1_usb3_0_phy>;
287 /* CON10 on CP1 expansion */
295 phy0: ethernet-phy@0 {
306 phy-mode = "10gbase-kr";
317 phy-mode = "rgmii-id";